diff options
| author | tameraw <[email protected]> | 2020-07-16 14:32:40 -0700 |
|---|---|---|
| committer | tameraw <[email protected]> | 2020-07-16 14:32:40 -0700 |
| commit | 2c35570dc9ced8690ea269d1efab201c361fea98 (patch) | |
| tree | a950c056346ab9a2260ba92a6be8ee3dd91ab7b6 /ports/cortex_a9/iar | |
| parent | f8e91d47625881614fe28efbcd43470922590d42 (diff) | |
updated to 6.0.1 and added additional processors/toolchains
Diffstat (limited to 'ports/cortex_a9/iar')
47 files changed, 34535 insertions, 0 deletions
diff --git a/ports/cortex_a9/iar/example_build/azure_rtos.eww b/ports/cortex_a9/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="iso-8859-1"?> + +<workspace> + <project> + <path>$WS_DIR$\sample_threadx.ewp</path> + </project> + <project> + <path>$WS_DIR$\tx.ewp</path> + </project> + <batchBuild/> +</workspace> + + diff --git a/ports/cortex_a9/iar/example_build/cstartup.s b/ports/cortex_a9/iar/example_build/cstartup.s new file mode 100644 index 00000000..647de2e8 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.c b/ports/cortex_a9/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c7c300cb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.dep b/ports/cortex_a9/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..714728f2 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.dep @@ -0,0 +1,220 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>4</fileVersion> + <fileChecksum>512928594</fileChecksum> + <configuration> + <name>Debug</name> + <outputs> + <file>$PROJ_DIR$\tx_api.h</file> + <file>$PROJ_DIR$\tx_port.h</file> + <file>$PROJ_DIR$\Debug\Obj\TX_ILL.r79</file> + <file>$PROJ_DIR$\tx_initialize_low_level.s</file> + <file>$PROJ_DIR$\sample_threadx.c</file> + <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file> + <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file> + <file>$PROJ_DIR$\TX_ILL.s79</file> + <file>$TOOLKIT_DIR$\inc\string.h</file> + <file>$PROJ_DIR$\DEMO.C</file> + <file>$PROJ_DIR$\cstartup.s</file> + <file>$PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o</file> + <file>$PROJ_DIR$\Debug\Exe\tx.a</file> + <file>$PROJ_DIR$\Debug\Obj\sample_threadx.pbd</file> + <file>$TOOLKIT_DIR$\inc\stdlib.h</file> + <file>$PROJ_DIR$\Debug\Exe\sample_threadx.out</file> + <file>$PROJ_DIR$\Debug\List\cstartup.lst</file> + <file>$PROJ_DIR$\Debug\Obj\tx_cstartup.r79</file> + <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file> + <file>$PROJ_DIR$\Debug\List\tx_initialize_low_level.lst</file> + <file>$TOOLKIT_DIR$\inc\c\string.h</file> + <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file> + <file>$TOOLKIT_DIR$\inc\DLib_Product_string.h</file> + <file>$TOOLKIT_DIR$\lib\m7Sx_tlv.a</file> + <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file> + <file>$TOOLKIT_DIR$\inc\DLib_Config_Normal.h</file> + <file>$TOOLKIT_DIR$\inc\ysizet.h</file> + <file>$PROJ_DIR$\sample_threadx.icf</file> + <file>$PROJ_DIR$\tx_initialize_low_level.s79</file> + <file>$PROJ_DIR$\Debug\Obj\demo.r79</file> + <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file> + <file>$TOOLKIT_DIR$\lib\dl7Sx_tln.a</file> + <file>$TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h</file> + <file>$TOOLKIT_DIR$\inc\yvals.h</file> + <file>$PROJ_DIR$\tx_execution_profile.c</file> + <file>$TOOLKIT_DIR$\inc\c\yvals.h</file> + <file>$TOOLKIT_DIR$\lib\rt7Sx_tl.a</file> + <file>$TOOLKIT_DIR$\lib\sh7Sxs_l.a</file> + <file>$TOOLKIT_DIR$\inc\ycheck.h</file> + <file>$PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi</file> + <file>$PROJ_DIR$\Debug\List\sample_threadx.map</file> + <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file> + <file>$PROJ_DIR$\Debug\Obj\cstartup.o</file> + <file>$PROJ_DIR$\Debug\Obj\sample_threadx.o</file> + <file>$PROJ_DIR$\tx_cstartup.s79</file> + <file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file> + <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file> + <file>$PROJ_DIR$\Debug\Obj\tx_execution_profile.o</file> + <file>$TOOLKIT_DIR$\inc\intrinsics.h</file> + <file>$TOOLKIT_DIR$\inc\c\intrinsics.h</file> + <file>$PROJ_DIR$\Debug\Obj\sample_threadx.xcl</file> + <file>$TOOLKIT_DIR$\inc\c\DLib_Product_string.h</file> + <file>$PROJ_DIR$\cstartup.s79</file> + <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file> + <file>$PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c</file> + <file>$PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et</file> + <file>$PROJ_DIR$\..\inc\tx_port.h</file> + <file>$PROJ_DIR$\..\..\..\..\common\inc\tx_api.h</file> + <file>$TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h</file> + <file>$TOOLKIT_DIR$\inc\c\iccarm_builtin.h</file> + </outputs> + <file> + <name>[ROOT_NODE]</name> + <outputs> + <tool> + <name>ILINK</name> + <file> 15 40</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s</name> + <outputs> + <tool> + <name>AARM</name> + <file> 11 19</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\sample_threadx.c</name> + <outputs> + <tool> + <name>ICCARM</name> + <file> 43</file> + </tool> + <tool> + <name>__cstat</name> + <file> 55</file> + </tool> + <tool> + <name>BICOMP</name> + <file> 50</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ICCARM</name> + <file> 57 56 21 5 35 53 45 46 41 32 20 51 49 59 58</file> + </tool> + </inputs> + </file> + <file> + <name>$PROJ_DIR$\TX_ILL.s79</name> + <outputs> + <tool> + <name>AARM</name> + <file> 2</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\DEMO.C</name> + <outputs> + <tool> + <name>ICCARM</name> + <file> 29</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ICCARM</name> + <file> 0 1</file> + </tool> + </inputs> + </file> + <file> + <name>$PROJ_DIR$\cstartup.s</name> + <outputs> + <tool> + <name>AARM</name> + <file> 42 16</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\sample_threadx.out</name> + <outputs> + <tool> + <name>ILINK</name> + <file> 40</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ILINK</name> + <file> 27 42 43 12 11 37 36 23 31</file> + </tool> + </inputs> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s79</name> + <outputs> + <tool> + <name>AARM</name> + <file> 11 19</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\tx_execution_profile.c</name> + <outputs> + <tool> + <name>ICCARM</name> + <file> 47</file> + </tool> + <tool> + <name>BICOMP</name> + <file> 39</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ICCARM</name> + <file> 0 1 14 38 33 18 25 30 6 24 26 8 22 48</file> + </tool> + <tool> + <name>BICOMP</name> + <file> 0 1 14 38 33 18 30 6 24 26 8 22 48</file> + </tool> + </inputs> + </file> + <file> + <name>$PROJ_DIR$\tx_cstartup.s79</name> + <outputs> + <tool> + <name>AARM</name> + <file> 17</file> + </tool> + </outputs> + </file> + <file> + <name>$PROJ_DIR$\cstartup.s79</name> + <outputs> + <tool> + <name>AARM</name> + <file> 42</file> + </tool> + </outputs> + </file> + </configuration> + <configuration> + <name>Release</name> + <outputs /> + <forcedrebuild> + <name>[MULTI_TOOL]</name> + <tool>ILINK</tool> + </forcedrebuild> + <forcedrebuild> + <name>[REBUILD_ALL]</name> + </forcedrebuild> + </configuration> +</project> diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.ewd b/ports/cortex_a9/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..9cfde331 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state></state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.50.1.24770</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>0</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>CMSISDAPProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>8</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>1</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + 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<file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.ewp b/ports/cortex_a9/iar/example_build/sample_threadx.ewp new file mode 100644 index 00000000..cdcbc403 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.ewp @@ -0,0 +1,2136 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>31</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.50.1.24770</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>Default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>Default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>NEON</name> + <state>1</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>0</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>36</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>1</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common\inc</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>0</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>1</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>1</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>1</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state>sample_threadx.srec</state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>23</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>sample_threadx.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>1</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + 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<name>$PROJ_DIR$\cstartup.s</name> + </file> + <file> + <name>$PROJ_DIR$\sample_threadx.c</name> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\tx.a</name> + </file> + <file> + <name>$PROJ_DIR$\tx_api.h</name> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s</name> + </file> + <file> + <name>$PROJ_DIR$\tx_port.h</name> + </file> + </group> +</project> diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.ewt b/ports/cortex_a9/iar/example_build/sample_threadx.ewt new file mode 100644 index 00000000..a30fa4d3 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.ewt @@ -0,0 +1,2797 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-STAT</name> + <archiveVersion>263</archiveVersion> + <data> + <version>263</version> + <cstatargs> + <useExtraArgs>0</useExtraArgs> + <extraArgs></extraArgs> + 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<state>0</state> + </option> + <option> + <name>GenRtcEnable</name> + <state>0</state> + </option> + <option> + <name>GenRtcCheckPtrsNonInstrFunc</name> + <state>1</state> + </option> + </data> + </settings> + </configuration> + <group> + <name>Common sources</name> + <file> + <name>$PROJ_DIR$\cstartup.s</name> + </file> + <file> + <name>$PROJ_DIR$\sample_threadx.c</name> + </file> + <file> + <name>$PROJ_DIR$\Debug\Exe\tx.a</name> + </file> + <file> + <name>$PROJ_DIR$\tx_api.h</name> + </file> + <file> + <name>$PROJ_DIR$\tx_initialize_low_level.s</name> + </file> + <file> + <name>$PROJ_DIR$\tx_port.h</name> + </file> + </group> +</project> diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.icf b/ports/cortex_a9/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM};
\ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..b0ed62eb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ +<?xml version="1.0" encoding="UTF-8"?> +<Workspace> + <ConfigDictionary> + <CurrentConfigs> + <Project>sample_threadx/Debug</Project> + <Project>tx/Debug</Project> + </CurrentConfigs> + <CurrentProj>sample_threadx</CurrentProj> + <OverviewSelected>1</OverviewSelected> + </ConfigDictionary> + <WindowStorage> + <Desktop> + <IarPane-34048> + <ColumnWidth0>21</ColumnWidth0> + <ColumnWidth1>2518</ColumnWidth1> + <FilterLevel>2</FilterLevel> + <LiveFile></LiveFile> + <LiveLogEnabled>0</LiveLogEnabled> + <LiveFilterLevel>-1</LiveFilterLevel> + </IarPane-34048> + <IarPane-34049> + <ToolBarCmdIds> + <item>34001</item> + <item>0</item> + </ToolBarCmdIds> + </IarPane-34049> + <IarPane-34050> + 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+ </MFCToolBar-34050> + <Pane-34050> + <ID>34050</ID> + <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat> + <RectRecentDocked>0000000000000000FE0200001A000000</RectRecentDocked> + <RecentFrameAlignment>8192</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <IsFloating>0</IsFloating> + <MRUWidth>744</MRUWidth> + <PinState>0</PinState> + </Pane-34050> + <BasePane-34050> + <IsVisible>1</IsVisible> + </BasePane-34050> + </Desktop> + <ChildIdMap> + <WIN_DEBUG_LOG>34048</WIN_DEBUG_LOG> + <TB_CMSISPACK>34049</TB_CMSISPACK> + <TB_MAIN2>34050</TB_MAIN2> + <WIN_BREAKPOINTS>34051</WIN_BREAKPOINTS> + <WIN_BUILD>34052</WIN_BUILD> + <WIN_CALL_GRAPH>34053</WIN_CALL_GRAPH> + <WIN_CUSTOM_SFR>34054</WIN_CUSTOM_SFR> + <WIN_C_STAT>34055</WIN_C_STAT> + <WIN_FIND_ALL_DECLARATIONS>34056</WIN_FIND_ALL_DECLARATIONS> + <WIN_FIND_ALL_REFERENCES>34057</WIN_FIND_ALL_REFERENCES> + <WIN_FIND_IN_FILES>34058</WIN_FIND_IN_FILES> + <WIN_SELECT_AMBIGUOUS_DEFINITIONS>34059</WIN_SELECT_AMBIGUOUS_DEFINITIONS> + <WIN_SOURCEBROWSE_LOG>34060</WIN_SOURCEBROWSE_LOG> + <WIN_SOURCE_BROWSE2>34061</WIN_SOURCE_BROWSE2> + <WIN_TOOL_OUTPUT>34062</WIN_TOOL_OUTPUT> + <WIN_TS_INTERRUPT_AVAILABLE>34063</WIN_TS_INTERRUPT_AVAILABLE> + <WIN_TS_INTERRUPT_CONFIG>34064</WIN_TS_INTERRUPT_CONFIG> + <WIN_WORKSPACE>34065</WIN_WORKSPACE> + </ChildIdMap> + <MDIWindows> + <MDIClientArea-0> + <MDITabsState>01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000</MDITabsState> + </MDIClientArea-0> + </MDIWindows> + </WindowStorage> +</Workspace> diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..94aadadb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end
\ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..63278961 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..a969962f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A9" + +"--fpu=VFPv3Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..1f2b1698 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun b/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8"?> +<crun> + <version>1</version> + <filter_entries> + <filter index="0" type="default"> + <type>*</type> + <start_file>*</start_file> + <end_file>*</end_file> + <action_debugger>0</action_debugger> + <action_log>1</action_log> + </filter> + </filter_entries> +</crun> diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..cd1843d2 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1397 @@ +<?xml version="1.0"?> +<Project> + <WindowStorage> + <ChildIdMap> + <TB_CMSISPACK>34048</TB_CMSISPACK> + <TB_DEBUG>34049</TB_DEBUG> + <TB_MAIN>34050</TB_MAIN> + <WIN_AUTO>34051</WIN_AUTO> + <WIN_BREAKPOINTS>34052</WIN_BREAKPOINTS> + <WIN_BUILD>34053</WIN_BUILD> + <WIN_CALL_GRAPH>34054</WIN_CALL_GRAPH> + <WIN_CALL_STACK>34055</WIN_CALL_STACK> + <WIN_CMSISPACK_AGENT_LOG>34056</WIN_CMSISPACK_AGENT_LOG> + <WIN_CODE_COVERAGE>34057</WIN_CODE_COVERAGE> + <WIN_CORES>34058</WIN_CORES> + <WIN_CUSTOM_SFR>34059</WIN_CUSTOM_SFR> + <WIN_C_STAT>34060</WIN_C_STAT> + <WIN_DATA_LOG>34061</WIN_DATA_LOG> + <WIN_DATA_STAT>34062</WIN_DATA_STAT> + <WIN_DEBUGGER_MACROS>34063</WIN_DEBUGGER_MACROS> + <WIN_DEBUG_LOG>34064</WIN_DEBUG_LOG> + <WIN_DISASSEMBLY>34065</WIN_DISASSEMBLY> + <WIN_FIND_ALL_DECLARATIONS>34066</WIN_FIND_ALL_DECLARATIONS> + <WIN_FIND_ALL_REFERENCES>34067</WIN_FIND_ALL_REFERENCES> + <WIN_FIND_IN_FILES>34068</WIN_FIND_IN_FILES> + <WIN_FIND_IN_SLIDING_TRACE>34069</WIN_FIND_IN_SLIDING_TRACE> + <WIN_IMAGES>34070</WIN_IMAGES> + <WIN_INTERRUPT_LOG>34071</WIN_INTERRUPT_LOG> + <WIN_INTERRUPT_STAT>34072</WIN_INTERRUPT_STAT> + <WIN_LOCALS>34073</WIN_LOCALS> + <WIN_MACRO_EVAL>34074</WIN_MACRO_EVAL> + <WIN_MACRO_REGISTRATION>34075</WIN_MACRO_REGISTRATION> + <WIN_MEMORY_1>34076</WIN_MEMORY_1> + <WIN_MEMORY_2>34077</WIN_MEMORY_2> + <WIN_MEMORY_3>34078</WIN_MEMORY_3> + <WIN_MEMORY_4>34079</WIN_MEMORY_4> + <WIN_PHYSICAL_BREAKPOINTS>34080</WIN_PHYSICAL_BREAKPOINTS> + <WIN_PROFILING2>34081</WIN_PROFILING2> + <WIN_QUICK_WATCH>34082</WIN_QUICK_WATCH> + <WIN_REGISTER_1>34083</WIN_REGISTER_1> + <WIN_REGISTER_2>34084</WIN_REGISTER_2> + <WIN_REGISTER_3>34085</WIN_REGISTER_3> + <WIN_REGISTER_4>34086</WIN_REGISTER_4> + <WIN_REGISTER_GROUPS>34087</WIN_REGISTER_GROUPS> + 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<IarPane-34048> + <ToolBarCmdIds> + <item>34000</item> + <item>34001</item> + <item>0</item> + </ToolBarCmdIds> + </IarPane-34048> + <IarPane-34049> + <ToolBarCmdIds> + <item>34390</item> + <item>34323</item> + <item>34398</item> + <item>34400</item> + <item>34397</item> + <item>34320</item> + <item>34321</item> + <item>34324</item> + <item>0</item> + </ToolBarCmdIds> + </IarPane-34049> + <IarPane-34050> + <ToolBarCmdIds> + <item>57600</item> + <item>57601</item> + <item>57603</item> + <item>33024</item> + <item>0</item> + <item>57607</item> + <item>0</item> + <item>57635</item> + <item>57634</item> + <item>57637</item> + <item>0</item> + <item>57643</item> + <item>57644</item> + <item>0</item> + <item>33090</item> + <item>33057</item> + <item>57636</item> + <item>57640</item> + <item>57641</item> + <item>33026</item> + <item>33065</item> + <item>33063</item> + <item>33064</item> + <item>33053</item> + <item>33054</item> + <item>0</item> + <item>33035</item> + <item>33036</item> + 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<PinState>0</PinState> + </Pane-34126> + <BasePane-34126> + <IsVisible>0</IsVisible> + </BasePane-34126> + <IarPane-34126 /> + <Pane-34127> + <ID>34127</ID> + <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat> + <RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked> + <RecentFrameAlignment>32768</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <IsFloating>0</IsFloating> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + </Pane-34127> + <BasePane-34127> + <IsVisible>0</IsVisible> + </BasePane-34127> + <Pane-34128> + <ID>34128</ID> + <RectRecentFloat>000000001700000080020000A8000000</RectRecentFloat> + <RectRecentDocked>00000000000000008002000091000000</RectRecentDocked> + <RecentFrameAlignment>32768</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <IsFloating>0</IsFloating> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + </Pane-34128> + <BasePane-34128> + <IsVisible>0</IsVisible> + </BasePane-34128> + <MFCToolBar-34124> + <Name>Main</Name> + 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+ </MFCToolBar-34124> + <Pane-34124> + <ID>34124</ID> + <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat> + <RectRecentDocked>0000000000000000150300001A000000</RectRecentDocked> + <RecentFrameAlignment>8192</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <IsFloating>0</IsFloating> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + </Pane-34124> + <BasePane-34124> + <IsVisible>1</IsVisible> + </BasePane-34124> + </Desktop> + </WindowStorage> +</Project> diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..f612528c --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,100 @@ +<?xml version="1.0"?> +<settings> + <Stack> + <FillEnabled>0</FillEnabled> + <OverflowWarningsEnabled>1</OverflowWarningsEnabled> + <WarningThreshold>90</WarningThreshold> + <SpWarningsEnabled>1</SpWarningsEnabled> + <WarnLogOnly>1</WarnLogOnly> + <UseTrigger>1</UseTrigger> + <TriggerName>main</TriggerName> + <LimitSize>0</LimitSize> + <ByteLimit>50</ByteLimit> + </Stack> + <Trace1> + <Enabled>0</Enabled> + <ShowSource>1</ShowSource> + </Trace1> + <DebugChecksum> + <Checksum>79500869</Checksum> + </DebugChecksum> + <CodeCoverage> + <Enabled>0</Enabled> + <ShowSource>0</ShowSource> + <HideCovered>0</HideCovered> + </CodeCoverage> + <Disassembly> + <MixedMode>1</MixedMode> + <InstrCount>0</InstrCount> + </Disassembly> + <Exceptions> + <StopOnUncaught>_ 0</StopOnUncaught> + <StopOnThrow>_ 0</StopOnThrow> + </Exceptions> + <CallStack> + <ShowArgs>0</ShowArgs> + </CallStack> + <DriverProfiling> + <Enabled>0</Enabled> + <Mode>1</Mode> + <Graph>0</Graph> + <Symbiont>0</Symbiont> + </DriverProfiling> + <CallStackLog> + <Enabled>0</Enabled> + </CallStackLog> + <CallStackStripe> + <ShowTiming>1</ShowTiming> + </CallStackStripe> + <TermIOLog> + <LoggingEnabled>_ 0</LoggingEnabled> + <LogFile>_ ""</LogFile> + </TermIOLog> + <LogFile> + <LoggingEnabled>_ 0</LoggingEnabled> + <LogFile>_ ""</LogFile> + <Category>_ 0</Category> + </LogFile> + <InterruptLog> + <LogEnabled>0</LogEnabled> + <GraphEnabled>0</GraphEnabled> + <ShowTimeLog>1</ShowTimeLog> + <SumEnabled>0</SumEnabled> + <ShowTimeSum>1</ShowTimeSum> + <SumSortOrder>0</SumSortOrder> + </InterruptLog> + <DataLog> + <LogEnabled>0</LogEnabled> + <GraphEnabled>0</GraphEnabled> + <ShowTimeLog>1</ShowTimeLog> + <SumEnabled>0</SumEnabled> + <ShowTimeSum>1</ShowTimeSum> + </DataLog> + <DisassembleMode> + <mode>0</mode> + </DisassembleMode> + <Breakpoints2> + <Count>0</Count> + </Breakpoints2> + <Interrupts> + <Enabled>1</Enabled> + <Irq0>_ 0 9999 0 9999 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I"</Irq0> + <Count>1</Count> + </Interrupts> + <MemConfig> + <Base>1</Base> + <Manual>0</Manual> + <Ddf>1</Ddf> + <TypeViol>0</TypeViol> + <Stop>1</Stop> + </MemConfig> + <Aliases> + <Count>0</Count> + <SuppressDialog>0</SuppressDialog> + </Aliases> + <Simulator> + <Freq>10000000</Freq> + <FreqHi>0</FreqHi> + <MultiCoreRunAll>1</MultiCoreRunAll> + </Simulator> +</settings> diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..256ebf4d --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end
\ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..a969962f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A9" + +"--fpu=VFPv3Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.crun b/ports/cortex_a9/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ +<?xml version="1.0" encoding="UTF-8"?> +<crun> + <version>1</version> + <filter_entries> + <filter index="0" type="default"> + <type>*</type> + <start_file>*</start_file> + <end_file>*</end_file> + <action_debugger>0</action_debugger> + <action_log>1</action_log> + </filter> + </filter_entries> +</crun> diff --git a/ports/cortex_a9/iar/example_build/settings/tx.dbgdt b/ports/cortex_a9/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ +<?xml version="1.0" encoding="UTF-8"?> +<Project> + <WindowStorage /> +</Project> diff --git a/ports/cortex_a9/iar/example_build/settings/tx.dnx b/ports/cortex_a9/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ +<?xml version="1.0"?> +<settings> + <InterruptLog> + <LogEnabled>0</LogEnabled> + <GraphEnabled>0</GraphEnabled> + <ShowTimeLog>1</ShowTimeLog> + <SumEnabled>0</SumEnabled> + <ShowTimeSum>1</ShowTimeSum> + <SumSortOrder>0</SumSortOrder> + </InterruptLog> + <DataLog> + <LogEnabled>0</LogEnabled> + <GraphEnabled>0</GraphEnabled> + <ShowTimeLog>1</ShowTimeLog> + <SumEnabled>0</SumEnabled> + <ShowTimeSum>1</ShowTimeSum> + </DataLog> + <Stack> + <FillEnabled>0</FillEnabled> + <OverflowWarningsEnabled>1</OverflowWarningsEnabled> + <WarningThreshold>90</WarningThreshold> + <SpWarningsEnabled>1</SpWarningsEnabled> + <WarnLogOnly>1</WarnLogOnly> + <UseTrigger>1</UseTrigger> + <TriggerName>main</TriggerName> + <LimitSize>0</LimitSize> + <ByteLimit>50</ByteLimit> + </Stack> + <DisassembleMode> + <mode>0</mode> + </DisassembleMode> + <Breakpoints2> + <Count>0</Count> + </Breakpoints2> + <Interrupts> + <Enabled>1</Enabled> + </Interrupts> + <MemConfig> + <Base>1</Base> + <Manual>0</Manual> + <Ddf>1</Ddf> + <TypeViol>0</TypeViol> + <Stop>1</Stop> + </MemConfig> + <Trace1> + <Enabled>0</Enabled> + <ShowSource>1</ShowSource> + </Trace1> + <Aliases> + <Count>0</Count> + <SuppressDialog>0</SuppressDialog> + </Aliases> + <Simulator> + <Freq>10000000</Freq> + <FreqHi>0</FreqHi> + <MultiCoreRunAll>1</MultiCoreRunAll> + </Simulator> +</settings> diff --git a/ports/cortex_a9/iar/example_build/tx.dep b/ports/cortex_a9/iar/example_build/tx.dep new file mode 100644 index 00000000..a1dc2578 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/tx.dep @@ -0,0 +1,9593 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>4</fileVersion> + <fileChecksum>607583892</fileChecksum> + <configuration> + <name>Debug</name> + <outputs> + <file>$PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c</file> + <file>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c</file> + <file>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c</file> + <file>$PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c</file> + 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<name>$PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_system_info_get.c</name> + <outputs> + <tool> + <name>ICCARM</name> + <file> 144</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ICCARM</name> + <file> 897 855 456 529 524 440 410 507 726 521 735 567 720 853 854 898</file> + </tool> + </inputs> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c</name> + <outputs> + <tool> + <name>ICCARM</name> + <file> 324</file> + </tool> + </outputs> + <inputs> + <tool> + <name>ICCARM</name> + <file> 897 855 456 529 524 440 410 507 726 521 735 567 720 853 854 902 898 914</file> + </tool> + </inputs> + </file> + </configuration> + <configuration> + <name>Release</name> + <outputs /> + <forcedrebuild> + <name>[MULTI_TOOL]</name> + <tool>IARCHIVE</tool> + </forcedrebuild> + <forcedrebuild> + <name>[REBUILD_ALL]</name> + </forcedrebuild> + </configuration> +</project> diff --git a/ports/cortex_a9/iar/example_build/tx.ewd b/ports/cortex_a9/iar/example_build/tx.ewd new file mode 100644 index 00000000..897111f4 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/tx.ewd @@ -0,0 +1,2974 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>C-SPY</name> + <archiveVersion>2</archiveVersion> + <data> + <version>32</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CInput</name> + <state>1</state> + </option> + <option> + <name>CEndian</name> + <state>1</state> + </option> + <option> + <name>CProcessor</name> + <state>1</state> + </option> + <option> + <name>OCVariant</name> + <state>0</state> + </option> + <option> + <name>MacOverride</name> + <state>0</state> + </option> + <option> + <name>MacFile</name> + <state></state> + </option> + <option> + <name>MemOverride</name> + <state>0</state> + </option> + <option> + <name>MemFile</name> + <state></state> + </option> + <option> + <name>RunToEnable</name> + <state>1</state> + </option> + <option> + <name>RunToName</name> + <state>main</state> + </option> + <option> + <name>CExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>CExtraOptions</name> + <state></state> + </option> + <option> + <name>CFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OCDDFArgumentProducer</name> + <state></state> + </option> + <option> + <name>OCDownloadSuppressDownload</name> + <state>0</state> + </option> + <option> + <name>OCDownloadVerifyAll</name> + <state>0</state> + </option> + <option> + <name>OCProductVersion</name> + <state>4.11A</state> + </option> + <option> + <name>OCDynDriverList</name> + <state>ARMSIM_ID</state> + </option> + <option> + <name>OCLastSavedByProductVersion</name> + <state>8.11.2.13604</state> + </option> + <option> + <name>UseFlashLoader</name> + <state>0</state> + </option> + <option> + <name>CLowLevel</name> + <state>1</state> + </option> + <option> + <name>OCBE8Slave</name> + <state>1</state> + </option> + <option> + <name>MacFile2</name> + <state></state> + </option> + <option> + <name>CDevice</name> + <state>1</state> + </option> + <option> + <name>FlashLoadersV3</name> + <state>$TOOLKIT_DIR$\config\flashloader\</state> + </option> + <option> + <name>OCImagesSuppressCheck1</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath1</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck2</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath2</name> + <state></state> + </option> + <option> + <name>OCImagesSuppressCheck3</name> + <state>0</state> + </option> + <option> + <name>OCImagesPath3</name> + <state></state> + </option> + <option> + <name>OverrideDefFlashBoard</name> + <state>0</state> + </option> + <option> + <name>OCImagesOffset1</name> + <state></state> + </option> + <option> + <name>OCImagesOffset2</name> + <state></state> + </option> + <option> + <name>OCImagesOffset3</name> + <state></state> + </option> + <option> + <name>OCImagesUse1</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse2</name> + <state>0</state> + </option> + <option> + <name>OCImagesUse3</name> + <state>0</state> + </option> + <option> + <name>OCDeviceConfigMacroFile</name> + <state>1</state> + </option> + <option> + <name>OCDebuggerExtraOption</name> + <state>1</state> + </option> + <option> + <name>OCAllMTBOptions</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreNrOfCores</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreWorkspace</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveProject</name> + <state></state> + </option> + <option> + <name>OCMulticoreSlaveConfiguration</name> + <state></state> + </option> + <option> + <name>OCDownloadExtraImage</name> + <state>1</state> + </option> + <option> + <name>OCAttachSlave</name> + <state>0</state> + </option> + <option> + <name>MassEraseBeforeFlashing</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreNrOfCoresSlave</name> + <state>1</state> + </option> + <option> + <name>OCMulticoreAMPConfigType</name> + <state>0</state> + </option> + <option> + <name>OCMulticoreSessionFile</name> + <state></state> + </option> + <option> + <name>OCTpiuBaseOption</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ARMSIM_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCSimDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCSimEnablePSP</name> + <state>0</state> + </option> + <option> + <name>OCSimPspOverrideConfig</name> + <state>0</state> + </option> + <option> + <name>OCSimPspConfigFile</name> + <state></state> + </option> + </data> + </settings> + <settings> + <name>CADI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCadiMemory</name> + <state>1</state> + </option> + <option> + <name>Fast Model</name> + <state></state> + </option> + <option> + <name>CCADILogFileCheck</name> + <state>0</state> + </option> + <option> + <name>CCADILogFileEditB</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CMSISDAP_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>4</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>CMSISDAPResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>CMSISDAPHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>CMSISDAPHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>CMSISDAPDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>CMSISDAPInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CMSISDAPBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>1</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>1</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>1</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>1</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>1</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>1</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>1</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>1</state> + </option> + <option> + <name>CatchINTERR</name> + <state>1</state> + </option> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>1</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>CMSISDAPProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>CMSISDAPSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCCMSISDAPUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>GDBSERVER_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>TCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJTagBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJTagDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJTagUpdateBreakpoints</name> + <state>main</state> + </option> + </data> + </settings> + <settings> + <name>IJET_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>8</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CatchSFERR</name> + <state>1</state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>OCIarProbeScriptFile</name> + <state>1</state> + </option> + <option> + <name>IjetResetList</name> + <version>1</version> + <state>10</state> + </option> + <option> + <name>IjetHWResetDuration</name> + <state>300</state> + </option> + <option> + <name>IjetHWResetDelay</name> + <state>200</state> + </option> + <option> + <name>IjetPowerFromProbe</name> + <state>1</state> + </option> + <option> + <name>IjetPowerRadio</name> + <state>1</state> + </option> + <option> + <name>IjetDoLogfile</name> + <state>0</state> + </option> + <option> + <name>IjetLogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + <option> + <name>IjetInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>IjetInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTargetEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiTarget</name> + <state>0</state> + </option> + <option> + <name>IjetScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>IjetIRLength</name> + <state>0</state> + </option> + <option> + <name>IjetJtagSpeedList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetProtocolRadio</name> + <state>0</state> + </option> + <option> + <name>IjetSwoPin</name> + <state>0</state> + </option> + <option> + <name>IjetCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>IjetSwoPrescalerList</name> + <version>1</version> + <state>0</state> + </option> + <option> + <name>IjetBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>IjetRestoreBreakpointsCheck</name> + <state>0</state> + </option> + <option> + <name>IjetUpdateBreakpointsEdit</name> + <state>_call_main</state> + </option> + <option> + <name>RDICatchReset</name> + <state>0</state> + </option> + <option> + <name>RDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>RDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>RDICatchData</name> + <state>0</state> + </option> + <option> + <name>RDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>RDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>RDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CatchCHKERR</name> + <state>0</state> + </option> + <option> + <name>CatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCProbeCfgOverride</name> + <state>0</state> + </option> + <option> + <name>OCProbeConfig</name> + <state></state> + </option> + <option> + <name>IjetProbeConfigRadio</name> + <state>0</state> + </option> + <option> + <name>IjetMultiCPUEnable</name> + <state>0</state> + </option> + <option> + <name>IjetMultiCPUNumber</name> + <state>0</state> + </option> + <option> + <name>IjetSelectedCPUBehaviour</name> + <state>0</state> + </option> + <option> + <name>ICpuName</name> + <state></state> + </option> + <option> + <name>OCJetEmuParams</name> + <state>1</state> + </option> + <option> + <name>IjetPreferETB</name> + <state>1</state> + </option> + <option> + <name>IjetTraceSettingsList</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IjetTraceSizeList</name> + <version>0</version> + <state>4</state> + </option> + <option> + <name>FlashBoardPathSlave</name> + <state>0</state> + </option> + <option> + <name>CCIjetUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCIjetUsbSerialNoSelect</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>JLINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>16</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCCatchSFERR</name> + <state>0</state> + </option> + <option> + <name>JLinkSpeed</name> + <state></state> + </option> + <option> + <name>CCJLinkDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCJLinkLogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCJLinkHWResetDelay</name> + <state></state> + </option> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>JLinkInitialSpeed</name> + <state>32</state> + </option> + <option> + <name>CCDoJlinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCScanChainNonARMDevices</name> + <state>0</state> + </option> + <option> + <name>CCJLinkMultiTarget</name> + <state>0</state> + </option> + <option> + <name>CCJLinkIRLength</name> + <state>0</state> + </option> + <option> + <name>CCJLinkCommRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkTCPIP</name> + <state>aaa.bbb.ccc.ddd</state> + </option> + <option> + <name>CCJLinkSpeedRadioV2</name> + <state>0</state> + </option> + <option> + <name>CCUSBDevice</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CCRDICatchReset</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchUndef</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchSWI</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchData</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchPrefetch</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchIRQ</name> + <state>0</state> + </option> + <option> + <name>CCRDICatchFIQ</name> + <state>0</state> + </option> + <option> + <name>CCJLinkBreakpointRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkDoUpdateBreakpoints</name> + <state>0</state> + </option> + <option> + <name>CCJLinkUpdateBreakpoints</name> + <state>main</state> + </option> + <option> + <name>CCJLinkInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCJLinkResetList</name> + <version>6</version> + <state>5</state> + </option> + <option> + <name>CCJLinkInterfaceCmdLine</name> + <state>0</state> + </option> + <option> + <name>CCCatchCORERESET</name> + <state>0</state> + </option> + <option> + <name>CCCatchMMERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchNOCPERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchCHRERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchSTATERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchBUSERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchINTERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchHARDERR</name> + <state>0</state> + </option> + <option> + <name>CCCatchDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkScriptFile</name> + <state>1</state> + </option> + <option> + <name>CCJLinkUsbSerialNo</name> + <state></state> + </option> + <option> + <name>CCTcpIpAlt</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCJLinkTcpIpSerialNo</name> + <state></state> + </option> + <option> + <name>CCCpuClockEdit</name> + <state>72.0</state> + </option> + <option> + <name>CCSwoClockAuto</name> + <state>0</state> + </option> + <option> + <name>CCSwoClockEdit</name> + <state>2000</state> + </option> + <option> + <name>OCJLinkTraceSource</name> + <state>0</state> + </option> + <option> + <name>OCJLinkTraceSourceDummy</name> + <state>0</state> + </option> + <option> + <name>OCJLinkDeviceName</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>LMIFTDI_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>2</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>LmiftdiSpeed</name> + <state>500</state> + </option> + <option> + <name>CCLmiftdiDoLogfile</name> + <state>0</state> + </option> + <option> + <name>CCLmiftdiLogFile</name> + <state>$TOOLKIT_DIR$\cspycomm.log</state> + </option> + <option> + <name>CCLmiFtdiInterfaceRadio</name> + <state>0</state> + </option> + <option> + <name>CCLmiFtdiInterfaceCmdLine</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>NULINK_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OCDriverInfo</name> + <state>1</state> + </option> + <option> + <name>DoLogfile</name> + <state>0</state> + </option> + <option> + <name>LogFile</name> + <state>$PROJ_DIR$\cspycomm.log</state> + </option> + </data> + </settings> + <settings> + <name>PEMICRO_ID</name> + <archiveVersion>2</archiveVersion> + <data> + <version>3</version> + <wantNonLocal>1</wantNonLocal> + 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<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + <plugin> + <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file> + <loadFlag>0</loadFlag> + </plugin> + </debuggerPlugins> + </configuration> +</project> diff --git a/ports/cortex_a9/iar/example_build/tx.ewp b/ports/cortex_a9/iar/example_build/tx.ewp new file mode 100644 index 00000000..c5732045 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/tx.ewp @@ -0,0 +1,2766 @@ +<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>Debug</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>31</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>Debug\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Debug\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Debug\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Full formatting, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>1</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>4.30A</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.50.1.24770</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>3</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>2</state> + </option> + <option> + <name>NEON</name> + <state>1</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>28</version> + <state>54</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + <option> + <name>TrustZone</name> + <state>1</state> + </option> + <option> + <name>TrustZoneModes</name> + <version>0</version> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>36</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state>$PROJ_DIR$\..\inc</state> + <state>$PROJ_DIR$\..\..\..\..\common\inc</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>0</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>1</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + <option> + <name>OICompilerExtraOption</name> + <state>1</state> + </option> + <option> + <name>CCStackProtection</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + 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<settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>23</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>tx.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + 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+ <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c</name> + </file> + </group> +</project> diff --git a/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..e9a16771 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,327 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h new file mode 100644 index 00000000..4d6d1537 --- /dev/null +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -0,0 +1,398 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include <stdlib.h> +#include <string.h> +#include <intrinsics.h> +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_a9/iar/readme_threadx.txt b/ports/cortex_a9/iar/readme_threadx.txt new file mode 100644 index 00000000..f2221ee0 --- /dev/null +++ b/ports/cortex_a9/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A9 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A9 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A9 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A9 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/iar/src/tx_iar.c b/ports/cortex_a9/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and <yvals.h> is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include <yvals.h> + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and <yvals.h> is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include <yvals.h> +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include <DLib_threads.h> + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include <stdio.h> /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a9/iar/src/tx_thread_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..fbdffc78 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_context_save.s b/ports/cortex_a9/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..63f4792a --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_context_save.s @@ -0,0 +1,210 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..566dcd15 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,270 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..c60ea9a4 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..15350c38 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..75cb6a98 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..4ad92728 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..31680cbb --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..78eeeb68 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..cb0976d2 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..512ef7f2 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_schedule.s b/ports/cortex_a9/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..4c8eabbf --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_schedule.s @@ -0,0 +1,240 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MOV r0, r5 ; Move CPSR to scratch register + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + MSR CPSR_cxsf, r0 ; Recover CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_stack_build.s b/ports/cortex_a9/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..04876d27 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_system_return.s b/ports/cortex_a9/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..2e4e661d --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_system_return.s @@ -0,0 +1,166 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Lockout interrupts. */ +; + MRS r1, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..54bf3ea3 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_timer_interrupt.s b/ports/cortex_a9/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..629a76c5 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + |