summaryrefslogtreecommitdiff
path: root/ports/xtensa
diff options
context:
space:
mode:
authorScott Larson <[email protected]>2022-12-16 08:16:32 +0000
committerScott Larson <[email protected]>2022-12-16 08:16:32 +0000
commit4e62226eeaf870827facbeef40bd1767db5cf9f0 (patch)
treebdd7b3bd4fa13b00529d00c240e949ba9c8d537f /ports/xtensa
parentb42c5acd8b9b1eb156c25e0b18c82beecfc033a1 (diff)
Update on 16 Dec 2022. Expand to see details.
b5d5df511 #include tx_user.h in assembly files for cortex-m ports 33e04e3d5 initial port of MIPS SMP for GHS and GNU 2eda2c17d capitalize extensions for M23 asm files 21c354ccb Fix armv7-m MPU settings for corner case, unify txm_module_port.h files 4a1ff93f9 remove uneeded include for ac6 c823e91ff update riscv iar example for latest iar tools 5559d185d check module stack for overlap (not kernel stack) efa9ce7b7 apply patch from mobileye to fix time slice processing 75fdcb722 Updated copy_armv7_cm.yml de04b9904 initialize unused MPU settings so that aliasing will work 79b317b60 add config directory to IAR RISC-V port in order to use simulator
Diffstat (limited to 'ports/xtensa')
-rw-r--r--ports/xtensa/xcc/inc/xtensa_context.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/ports/xtensa/xcc/inc/xtensa_context.h b/ports/xtensa/xcc/inc/xtensa_context.h
index c2f76afa..2ec96ecf 100644
--- a/ports/xtensa/xcc/inc/xtensa_context.h
+++ b/ports/xtensa/xcc/inc/xtensa_context.h
@@ -427,9 +427,11 @@ XSTRUCT_END(XtExcFrame)
addi a10, a1, -XT_STK_FRMSZ
s32i a10, a11, tx_thread_stack_ptr // save outgoing thread stack pointer
l32i a10, a12, 0 // a10 <- _tx_timer_time_slice
+ beqz a10, .Ldont_save_ts
s32i a10, a11, tx_thread_time_slice // save outgoing time slice value
movi a10, 0
s32i a10, a12, 0 // disable time slice
+.Ldont_save_ts:
s32i a10, a11, tx_thread_solicited // mark as preempted
s32i a10, a8, 0 // Clear _tx_thread_current_ptr
#if XCHAL_CP_NUM > 0