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2026-06-08Release 6.5.1.202602a preparation (#547)Frédéric Desbiens
* Updated version number constants * Updated port version strings --------- Co-authored-by: Copilot <[email protected]>
2026-06-03Release 6.5.1.202602 preparation (#543)Frédéric Desbiens
* Updated version number constants * Updated port version strings --------- Co-authored-by: Copilot <[email protected]>
2026-05-26Added win64 ports of ThreadX and ThreadX SMP (#529)Frédéric Desbiens
Windows x64 port and regression suite This PR adds the Windows x64 (Win64) simulation port for both the standalone and SMP variants of ThreadX, along with the full CMake build and test infrastructure needed to run the regression suite on Windows. New ports Win64 standalone (ports/win64/vs_2022): self-contained Windows simulation port using Win32 threading primitives as virtual cores. Includes CMake integration, build/test scripts, and MSVC project files. Win64 SMP (ports/win64_smp/vs_2022): multi-core Windows simulation port. Supports up to 4 virtual cores backed by Windows host threads. Scheduler and timer improvements The initial port used coarse polling and synchronous SuspendThread/ResumeThread pairs throughout the scheduler hot path. Several rounds of optimization reduced the SMP regression suite runtime from ~150 s to ~78 s (-48%), with no regressions: - Replaced scheduler polling with an event-driven wake path; switched the simulated timer to one-shot rearming to eliminate catch-up ticks. - Skip SuspendThread when _tx_thread_preempt_disable != 0 (new suspension type 3) -- the primary optimization, yielding up to 7.9x speedup on preemption-heavy tests. - Skip SuspendThread when a thread is spinning on the Win32 critical section (suspension type 4), and fix a stale-TLS bug in _tx_win32_critical_section_obtain that could stamp mutex_access on the wrong virtual core. - Added a 2 ms scheduler event timeout (matching the Linux SMP port) to prevent stalls on any missed SetEvent. - Enabled high-resolution waitable timers (SetWaitableTimerEx) for accurate 100 Hz tick cadence. - Increased TX_WIN32_CONTENTION_PAUSE_COUNT from 64 to 256 to reduce SwitchToThread overhead under heavy CS contention. Build and test infrastructure - Hardened the Windows build wrapper (scripts/build_tx.ps1): invoke Ninja directly for Ninja build trees, fix timeout detection, add a default build timeout, and limit fallback replay to real timeout cases. - Added -Clean support to Windows test scripts to remove stale CTest state before each run. - Skip Visual Studio DevShell re-entry when the active MSVC environment already matches the requested architecture. - Fixed scripts/build_tx.sh (Linux) regression source generation: replaced brittle exact-string insertion with line-based matching so the interrupt dispatcher hook is inserted reliably for both simulator ports. Test suite updates - Introduced test/tx/regression/threadx_test_port.h with portable macros (TX_TEST_POINTER_WORD, TX_TEST_STORE_POINTER) for storing pointers in test arrays on 64-bit targets where ULONG remains 32-bit. - Adjusted pool-capacity and pointer-storage patterns in regression tests to use ALIGN_TYPE-sized slots, making the suite correct on 64-bit hosts. - Restored stricter event flag, sleep, and timer expectations now that port-level fixes make prior Windows accommodations unnecessary. - Tightened SMP watchdog and clean-build timeout defaults. Version metadata Updated Win32, Win64, and Win64 SMP port version strings to 6.5.1.202602. Co-authored-by: Copilot <[email protected]> Co-authored-by: Codex (gpt 5.5) <[email protected]>
2026-05-19Add QEMU based CI regression test infra for RV32 and RV64 (#526)Akif Ejaz
Added a QEMU virt-machine BSP and CTest infrastructure to run the ThreadX regression suite on both RISC-V 32-bit and 64-bit targets in CI. New components: - BSP (entry, trap, PLIC, CLINT timer, UART, linker script) targeting QEMU virt machine for RV32 and RV64 - CMake build system with Ninja, supporting multiple build configs - CI scripts: install_riscv.sh (toolchain + QEMU), build_tx_riscv.sh, test_tx_riscv.sh - GitHub Actions workflow job for RISC-V regression gating Port fixes: - RV32 tx_thread_context_restore.S: set MPIE alongside MPP (0x1800 → 0x1880) so mret re-enables interrupts - RV32/RV64 tx_port.h: add TX_REGRESSION_TEST extension macros needed by the test harness - RV32/RV64 example_build scripts: add compile and QEMU launch steps Regression test portability fixes: - Block memory tests: increase pool sizes (320 → 340) to accommodate larger RISC-V block-header alignment - Byte memory test: replace hardcoded offsets with BYTE_POOL_OVERHEAD macro for portable pool-size computation - Event flag timeout test: make counter tolerance unconditional, removing linux-only guard Signed-off-by: Akif Ejaz <[email protected]>
2026-04-29Fixed race condition and message loss in Cortex-M ports (#523)Frédéric Desbiens
* Fixed race condition and message loss in Cortex-M GNU, AC6, and IAR ports (#516) - Added compiler memory barriers to BASEPRI management functions in tx_port.h. - Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.S to prevent fall-through before context switch. - These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled. - These changes ensure that pending interrupts (specifically PendSV) are recognised before subsequent instructions are executed, following Kairalite's feedback and ARM architectural guidelines. Assisted-by: Gemini (Gemini 2.0 Flash) ----- * Added a comment in common/tx_queue_cleanup to document why the NI path omits revalidation guards - In `TX_NOT_INTERRUPTABLE` mode, the caller keeps interrupts disabled across the entire cleanup call, so the race window that makes the guards necessary in the interruptable path cannot occur. Add a comment explaining this, and noting that all paths that resume a suspended thread clear tx_thread_suspend_cleanup before calling _tx_thread_system_ni_resume, making double-cleanup impossible. This prevents future false-positive suggestions (e.g. from AI tools) to add redundant checks to the NI path. Relates to: eclipse-threadx/threadx#516 Co-authored-by: Copilot <[email protected]>
2026-04-12Fix default TX_TIMER_TICKS_PER_SECOND default value in tx_user_sample.hJonathan Blanchard
Changed default value to TX_16_ULONG.
2026-03-05Updated copyright headers and version number constants (#509)Frédéric Desbiens
* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header
2026-01-09Updated the version numberFrédéric Desbiens
2025-09-28Updated version number and added build and hotfix.Frédéric Desbiens
2025-09-16Merge pull request #464 from gzzi/avoid-hang-check-stackFrédéric Desbiens
Do not analyze when stack overflow has occured.
2025-09-01Do not analyze when stack overflow has occuredGuillaume Galeazzi
2025-04-02Make queue max message size configurableHaithem Rahmani
Summary ------- This commit fixes the issue #424 Details -------- - Add a the configuration option TX_QUEUE_MESSAGE_MAX_SIZE in the tx_api.h with default value set to TX_ULONG_16 to keep backword compatibility. - Update the txe_queue_create() to check on TX_QUEUE_MESSAGE_MAX_SIZE rather than TX_ULONG_16 as max message size. - Add a new unitary test to cover the new change.
2025-02-24Updated version number to 6.4.2.Frédéric Desbiens
2024-02-27Update version number to 6.4.1TiejunZhou
2024-01-30Update version id string.Bo Chen (from Dev Box)
2024-01-29Update copyright.Bo Chen (from Dev Box)
2023-12-28Update release date and version (#338)TiejunZhou
* Update version number in API header * Update release date and version
2023-10-23Update release version to 6.3.0 and date to 10-31-2023 (#308)v6.3.0_relTiejunZhou
2023-05-12Add random number stack filling option. (#257)Xiuwen Cai
Co-authored-by: TiejunZhou <[email protected]>
2023-03-08Release 6.2.1 on 08 Mar 2023. Expand to see details.v6.2.1_relTiejun Zhou
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
2022-10-26Release 6.2.0v6.2.0_relTiejun Zhou
2022-07-26Release 6.1.12v6.1.12_relYuxin Zhou
2022-04-20Release 6.1.11Yuxin Zhou
2022-01-29Release 6.1.10Yuxin Zhou
2021-10-14Release 6.1.9Yuxin Zhou
2021-07-28Release 6.1.8v6.1.8_relYuxin Zhou
2021-06-02Release 6.1.7Bo Chen
2021-04-03Release 6.1.6v6.1.6_relYuxin Zhou
2021-03-05Release 6.1.5v6.1.5_relYuxin Zhou
2021-01-08update to v6.1.3Scott Larson
2020-11-10patch release 6.1.2v6.1.2_relScott Larson
2020-10-166.1.1 patch: add stack sealing to armv8-m, fix misra warning, fix stack ↵v6.1.1_relScott Larson
check link error
2020-09-306.1 minor releaseScott Larson
2020-08-14apply 6.0.2 patchScott Larson
2020-07-16updated to 6.0.1 and added additional processors/toolchainstameraw
2020-05-15Updated code for RC5PProvost
2020-05-15Unneeded output messagePProvost
2020-05-11Initial commitPProvost