/***************************************************************************
 * Copyright (c) 2026 Eclipse ThreadX contributors
 *
 * This program and the accompanying materials are made available under the
 * terms of the MIT License which is available at
 * https://opensource.org/licenses/MIT.
 *
 * AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
 * The AI-generated portions may be considered public domain (CC0-1.0)
 * and not subject to the project's licence. The human contributor has
 * reviewed and verified that the code is correct.
 *
 * SPDX-License-Identifier: MIT and CC0-1.0
 **************************************************************************/

/* Machine-mode CSR definitions and helpers for the Erbium example.  */

#ifndef RISCV_CSR_H
#define RISCV_CSR_H

/* The Erbium FPU implements only part of the F extension: single-precision
   divide, square root and conversions to and from 64-bit integers raise an
   emulation exception that this example does not handle.  Build for the
   integer ISA with the soft-float lp64 ABI.  */
#ifdef __riscv_flen
#error "The Erbium example requires a soft-float build: use -march=rv64imc_zicsr_zifencei -mabi=lp64."
#endif

/* Machine Status Register, mstatus  */
#define MSTATUS_MIE         (1L << 3)    /* machine-mode interrupt enable  */
#define MSTATUS_MPIE        (1L << 7)    /* previous MIE  */
#define MSTATUS_MPP_M       (3L << 11)   /* previous mode: machine  */

/* Machine Interrupt Enable, mie  */
#define MIE_MTIE            (1L << 7)    /* machine timer  */
#define MIE_MEIE            (1L << 11)   /* machine external  */

#ifndef __ASSEMBLER__

#include <stdint.h>

static inline uintptr_t riscv_get_core(void)
{
    uintptr_t x;
    __asm__ volatile("csrr %0, mhartid" : "=r" (x));
    return x;
}

/* Clear mstatus.MIE and return whether it was set.  */
static inline int riscv_mintr_save(void)
{
    uintptr_t x;
    __asm__ volatile("csrrci %0, mstatus, %1" : "=r" (x) : "i" (MSTATUS_MIE) : "memory");
    return (x & MSTATUS_MIE) != 0;
}

/* Set mstatus.MIE again if riscv_mintr_save found it set.  */
static inline void riscv_mintr_restore(int enabled)
{
    if (enabled)
        __asm__ volatile("csrsi mstatus, %0" : : "i" (MSTATUS_MIE) : "memory");
}

#endif /* __ASSEMBLER__ */

#endif /* RISCV_CSR_H */