Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/tinyusb.git/atom/.claude?h=codex%2Fclass-reference-docs 2026-07-29T19:29:32Z 2026-07-29T19:29:32Z Ha Thach thach@tinyusb.org 2026-07-29T19:29:32Z urn:sha1:eef5af86aa26fe3d72e41156a586a6ed3ffce9f8 hil, ci: scope HIL builds and tests to the boards a PR affects Add test/hil/hil_select.py, a stdlib-only selector that maps a PR diff to the rig boards, tests and BSP families a change can affect, and wire it into CI so pull requests build and run only those. A port change picks its families' boards, a class change picks the examples enabling that class, and device/host changes prune the other role. Anything unclassified — infra, an unmapped port, a selector error — falls back to the full matrix, and push/schedule runs are untouched. Move the shared example lists to hil_examples.py; 54 hardware-free tests cover the rules. 2026-07-29T10:29:59Z Ha Thach thach@tinyusb.org 2026-07-29T10:29:59Z urn:sha1:e88fc441ddcaaa5abd4f4673ef2bf29499522dc0 test/hil: add board-pool health check, split hil_test into focused modules (#3794) Add test/hil/hil_pool_check.py: per-board rig health scan — probe presence, light-example flash (dfu_runtime; device_info + serial check for host-only boards), uid re-enumeration, safe recovery (probe authorized-toggle, board reset), verified board_test re-park, USB topology report, and a markdown summary table. Missing firmware is built on the spot (tools/build.py, idf.py for espressif, one get_deps retry); row statuses: ok, flash-failed, failed, locked. Board locks are always respected, never bypassed. Refactor hil_test.py into hil_lock.py (flock protocol, controller permits, hold/release/status CLI; replaces board_lock.py) and hil_flash.py (flashers, find_firmware, run_cmd). Update WCH probe uids and the board roster in tinyusb.json; add the hil-pool-check skill. 2026-07-27T17:17:14Z Ha Thach thach@tinyusb.org 2026-07-27T17:17:14Z urn:sha1:72f95d7d61a5a445be267eef2d677c33baa2fec2 test/hil: replace PCI reset with root-port VBUS cycle for D-state recovery pci-reset was documented as an FLR, but no controller on either rig has FLR, so it issued a PCIe secondary bus reset on a live, driver-bound xHCI -- halting the card until the PVE host was power-cycled, and returning success so the caller could not tell. It destroyed the ci controller twice. Replace it with root-cycle, which cuts VBUS at the xHCI root port and touches only the root hub, so it never takes the per-device lock the wedged ioctl holds. uhubctl needs -S, or its sysfs backend disconnects the child before cutting power and blocks on that same lock. Success is proven by the device's sysfs directory inode changing: node existence proves nothing, and devnum is reused once the per-bus map wraps. usbtest.py's hang path invokes it, then confirms via /proc that nothing still holds the device node. Skill scripts now run from the repo; the drifted /usr/local/sbin copies are deleted. 2026-07-24T15:40:52Z hathach thach@tinyusb.org 2026-07-24T15:40:52Z urn:sha1:10dd1e5b4d2db9a31cb8f08d3caf7635c3fa64fe Coverage rows now resolve the de-collided module-qualified key introduced for same-named statics. RA boards: document that --attach requires a debugger-booted target - the C_DEBUGEN gate exists because an unguarded TRCKCR write bricks standalone boots (hardware-proven), so the limitation is documented rather than the guard weakened; a debugger-side TRCKCR hook can lift it later once re-verified on hardware. The stm32n6 board-gating suggestion is not taken: N6 trace pins are AF0-fixed chip-level, the same family-wide pattern as stm32h7. 2026-07-24T14:30:42Z hathach thach@tinyusb.org 2026-07-24T14:30:42Z urn:sha1:f08c8211904ac9feb2598aa354b0b7bddc245bfe The board-specific PHY-reset nets move behind a board.h opt-in (TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other boards of those families cannot inherit a foreign GPIO write; the chip-level trace pin muxes stay family-wide by design (same pattern as stm32h7). same70 reference: width 1 is the validated default until the J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so --attach sessions decode ROM execution too. etm_capture rejects an unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB and a runtime switch would desync the stream); etm_profile keeps same-named statics from different modules as distinct rows. Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2. 2026-07-24T11:38:40Z hathach thach@tinyusb.org 2026-07-24T11:38:40Z urn:sha1:e65368ea16975710f029f7ff7e2089b9ea90186d Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70 ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the RA references, profile-script support for --no-timestamps itraces. Deep review (whole branch): same70_xplained board row + caveat restored, stale pico2 72 MHz claim corrected to the shipped 48, explicit SetTracePortWidth(4) in the three references that relied on Ozone's default, coverage-cell guard, median-based SysTick calibration, dead session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the validated chip max) and the debugger guard indented. EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified); RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB breaks the external probe even with JP4 shorted. 2026-07-24T09:20:13Z hathach thach@tinyusb.org 2026-07-24T09:20:13Z urn:sha1:d3eaeb06e04519b480637f6e7cb007a3de08d923 Fresh bring-up pass on mimxrt1170_evkb: holding the 100M RTL8201 in reset (ENET_RST_B = GPIO_LPSR_04) stops its RMII lines driving against the shared trace pads and doubles the clean trace-pin rate to 50 MHz (100 MHz CSTRACE root; 133 MHz root is marginal, stock 132 corrupts). Validated 3x 8 s TinyUSB captures at 11.46M fetches. D1-D3 remain silent in every configuration - the welded R1882-R1884 are electrically open; reflow is the remaining step to width 4. Board notes gain JP4 (must be shorted for an external probe on J58). 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:49:03Z urn:sha1:08c4c558a7542c0eb8995fe22602e129be526802 Fifth capture view alongside usbmon/kernel/target/wire: exact execution history via J-Trace, existing only where the trace header is wired - confirm with the user before reaching for it. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:45:16Z urn:sha1:d7f1bbb6e554820911c4a568e56b6f42f5b4931d Instruction-level trace outranks PC-sampling when samples cannot resolve a mechanism, but the J-Trace is exclusive per-board hardware: the agent uses it only when its prompt says the board is trace-wired or the user asked, and otherwise proposes it in notes - mirroring the lock-force consent rule. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:42:46Z urn:sha1:49d7ee6dbe839ae6fbcfd9cc69323c9e976d0faa target-debug replaced usb-target-debug in the debug-skill overhaul; update the cross-skill table and PC-sampling pointer. Add the consent gate: the J-Trace is a single probe moved between boards, so captures on a board the user did not just ask about need explicit confirmation that it is wired.