tinyusb.git/docs/reference/boards.rst, branch etmtrace-rp2350

pico2_etm_trace: point board metadata at the carrier's PCB repo

2026-08-26T10:06:07Z

rp2040: remove family_configure_sys_clock(), keep the pico-sdk clock

2026-08-26T09:58:24Z

With the 12 x n MHz rule gone (previous commit), nothing needs a non-stock clock: every board runs whatever pico-sdk's platform_defs.h selects (125 MHz rp2040, 150 MHz rp2350), set from crt0 by the SDK's own runtime_init_clocks(). The per-platform PLL table this file carried only existed to force other rates, so it goes too. Overriding is still possible the way the SDK documents it - pass SYS_CLK_KHZ together with PLL_SYS_VCO_FREQ_HZ / PLL_SYS_POSTDIV1 / PLL_SYS_POSTDIV2 from scripts/vcocalc.py - which is what the etm-trace notes now tell you to do for the higher trace rates. The removed function and its measured PLL values stay in git history if a board ever needs a pinned clock again.

rp2350: ETM trace on the pico2 trace carrier, at the pico-sdk stock clock

2026-08-26T09:58:24Z

Adds board pico2_etm_trace - a Pico 2 seated on the pico2 trace motherboard carrier (MIPI-20 Cortex Debug+ETM, 27 Ohm source-terminated, GND-guarded) - and the trace reference that goes with it. Firmware needs almost no trace support: J-Link's built-in RP2350 device script declares the off-ROM-table trace components (funnel/TPIU/ETM) and re-arms the whole chip-side path via OnTraceStart at every resume, so TRACE_ETM=1 does one thing only - keep the UART console TX-only when the console RX would sit on a trace pin. The carrier moves the console to GP12/13 (GP1 = TRACECLK), so it keeps a full-duplex console while tracing. Never set a custom JLinkScript here: it replaces the built-in one and pin trace stops working. Validated on the carrier at the rp2350 stock 150 MHz (75 MHz TRACECLK, width 4): cdc_msc enumeration burst 3/3, zero overflow, data sampling +1 ns (idle eye -1000..+2000 ps), 33M fetches per 10 s capture. Higher rates measured too: 180 MHz (90 MHz TRACECLK, +4..+5 ns) and 240 MHz (120 MHz TRACECLK, +3.5 ns) - the latter is the J-Trace PRO V2 ceiling, which is the probe at its documented limit rather than a board limit. board_init() no longer switches clk_sys on either chip, and boards run the pico-sdk default (125 MHz rp2040, 150 MHz rp2350). The 12 x n MHz PIO-USB rule that motivated the old forced clock is not real - it is the Pico-PIO-USB author's day-one design note (4d952cb, Dec 2021), never enforced by an assert, and contradicted by measurement: MSC dd over PIO-USB at ten clocks from 120 to 240 MHz on rp2350 gives 62 KB/s at every one; rp2040 CDC bulk loopback is byte-exact at 120/125/133/156/180 MHz; adafruit_fruit_jam passes 19/19 HIL at its stock 150 MHz including usbtest 30/30 and PIO-USB host+dual. CircuitPython ships PIO-USB at these same defaults. Two earlier fly-wire-era workarounds are dropped after A/B on the PCB: the TIMER0/1 DBGPAUSE clear (captures profile healthy firmware without it) and 12 mA fast-slew trace pads (default pads pass with a wider eye). A runtime clk_sys switch does still silently truncate a capture at the switch, which is why nothing sets the clock at runtime. Also included: docs/superpowers/followup/pr0000-msc-host-tur-retry.md - an unbounded Test Unit Ready / Request Sense retry in the MSC host driver, found while sweeping clocks and deferred to its own PR.

Update docs

2026-07-21T10:07:43Z

Bump version to 0.21.0; rework changelog, contributors, and docs

2026-06-29T16:38:01Z

Release: - Bump version to 0.21.0 and regenerate tusb_option.h, library.json, repository.yml, sonar-project.properties, boards.rst, dependencies.rst - Add 0.21.0 release notes and split the changelog into per-release files under docs/info/changelog/ (date out of title, driver/class groups as sub-headings, DCD & HCD section after Device/Host stacks) Contributors: - Credit each release's PR authors in a Contributors section - Drop the curated contributors page; add MAINTAINERS.rst Docs: - Update Code of Conduct to Contributor Covenant 3.0 (keep it in the repo, remove it from the built docs) - Sidebar: add a home entry, rename the group to "Documentation", move Changelog into it, add a GitHub Sponsor button, merge external links, rename FAQ; hide the inline toctree on the landing page - Add the make-release skill and update the AGENTS.md release process Co-Authored-By: Claude Opus 4.8 (1M context)

bsp/stm32h5: fix uart definition

2026-06-27T10:53:53Z

Signed-off-by: HiFiPhile

hw/bsp+wch: rename the CH58x family to ch583 and OPT_MCU_CH58X to OPT_MCU_CH583

2026-06-22T08:23:08Z

The BSP family and MCU option were named "ch58x"/"CH58X", but the supported part is the CH583/CH582 (and the SDK repo is openwch/ch583); CH585 is a separate MCU family, so the CH58x umbrella was misleading. Rename to the specific family: - hw/bsp/ch58x -> hw/bsp/ch583 (dir), and the BSP-local files ch58x_it.* -> ch583_it.*, system_ch58x.* -> system_ch583.* (include guards/refs updated). The vendor SDK files (CH58x_common.h, CH58x_*.c in hw/mcu/wch/ch583) keep their names. - OPT_MCU_CH58X -> OPT_MCU_CH583 in tusb_option.h, tusb_mcu.h, and the shared WCH USBFS driver (ch32_usbfs_reg.h, dcd_ch32_usbfs.c). OPT_MCU_CH582 is kept as an alias (same value), so either name selects the same code. - FAMILY_MCUS CH58X -> CH583, CFG_TUSB_MCU=OPT_MCU_CH583, mcu:CH58X -> mcu:CH583 in the example skip lists, the CI build matrix (ci_set_matrix.py), the get_deps family tag, and docs/reference/boards.rst. Board names (ch582m_evt, yd-ch582m) are unchanged. Verified: make + cmake build for ch582m_evt, and ci.lan HIL (all device examples pass). Co-Authored-By: Claude Opus 4.8 (1M context)

Merge remote-tracking branch 'origin/master' into add-ch58x-usbfs

2026-06-18T08:31:03Z

add stm32c5 support

2026-05-10T12:17:00Z

Signed-off-by: HiFiPHile

fix(docs): update URL for STM32C071 Nucleo board documentation

2026-04-16T08:40:42Z