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<title>tinyusb.git/docs, branch worktree-ch569-hydrausb3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/tinyusb.git/atom/docs?h=worktree-ch569-hydrausb3</id>
<link rel='self' href='http://cgit.235523.xyz/tinyusb.git/atom/docs?h=worktree-ch569-hydrausb3'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/'/>
<updated>2026-07-11T22:02:59Z</updated>
<entry>
<title>ch32h417: register in CI matrix, lwIP throughput, docs and presets</title>
<updated>2026-07-11T22:02:59Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-07-11T22:02:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=741776311b8f6e0c3fdbf4e00a9c3aff7cd577b2'/>
<id>urn:sha1:741776311b8f6e0c3fdbf4e00a9c3aff7cd577b2</id>
<content type='text'>
Final integration for the CH32H417 port.

- .github/workflows/ci_set_matrix.py: add ch32h417 (riscv-gcc) so CI builds it.
- examples/device/net_lwip_webserver: enable LWIP_HIGH_THROUGHPUT for the H417
  (SuperSpeed iperf).
- docs/reference/{boards,dependencies}.rst + hw/bsp/BoardPresets.json: regenerated
  for the new board and dependency.

usbtest quirks intentionally left at 0 for the H417: its endpoint engine fixes the
two CH569 5 Gbps silicon limitations (RB_EP_TX/RX_HALT gives a repeatable STALL for
case 13; the reworked EP0/chain path is expected free of the wLength%4==1 ctrl_out
drop), so the H417 targets a full 30/30 at SuperSpeed rather than 27/27.

The HIL entry (test/hil/tinyusb.json) is deliberately deferred: it needs the chip's
ESIG unique id read from the board on first flash, which is pending hardware access.

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm
</content>
</entry>
<entry>
<title>Switch CH569 port to the official openwch/ch569 SDK</title>
<updated>2026-07-07T16:08:19Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-07-07T16:08:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=206e63349199e34047486d3dba3f2c8972aae5f2'/>
<id>urn:sha1:206e63349199e34047486d3dba3f2c8972aae5f2</id>
<content type='text'>
Replace the hydrausb3/wch-ch56x-bsp dependency with WCH's official EVT
(openwch/ch569 @0424d2968); rename the family hw/bsp/ch56x -&gt; hw/bsp/ch569
to match. Adaptations for the EVT layout and API:
- family.cmake/mk: EVT/EXAM/SRC paths (Peripheral/src|inc, RVMSIS, Startup)
- CH56xSFR.H case-wrapper (EVT includes the uppercase name, which breaks
  case-sensitive filesystems)
- debug_uart: official UART1_BaudRateCfg + explicit TXD1/RXD1 pin setup
  (the EVT has no pin-configuring UART init)
- family.c: .dmadata (RAMX) zeroing moved into board_init (EVT startup
  only clears .bss) and a self-contained SPI-ROM reader for the factory
  unique ID (the EVT flash API is a binary blob, not linked)
- dcd_ch56x_usbhs.c: plain volatile casts instead of hydrausb3-only
  pointer typedefs
- -Wno-comment for the EVT's nested header comments

Validated: full 19-example CMake sweep + Make build green, 65/65 unit
tests, pre-commit clean; on HydraUSB3 hardware cdc_msc_throughput
enumerates at SuperSpeed 5000M with MSC 124/110 MB/s read/write
(direct-IO dd).

Co-Authored-By: Claude Fable 5 &lt;noreply@anthropic.com&gt;
Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE
</content>
</entry>
<entry>
<title>Add CH569 runtime USB2 fallback, HIL board entry and docs</title>
<updated>2026-07-07T04:35:06Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-07-07T04:35:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=1f48e279c0c8b56b21385870e218242058f86edb'/>
<id>urn:sha1:1f48e279c0c8b56b21385870e218242058f86edb</id>
<content type='text'>
- CFG_TUD_WCH_USB30_FALLBACK (on by default for SPEED=super): the USB3
  dcd owns both controllers on rhport 0. TMR0 times out SuperSpeed link
  training (2x 0.5 s: shut USB3 down, then bring USB2 up); an LTSSM
  disabled event (SS rejected by the port) switches immediately. The
  active controller is dispatched at each dcd entry point; IRQ pendings
  are cleared on switch and dcd_int_enable is mode-aware (a stale LINK
  pending otherwise refires on every usbd queue unlock)
- Bounded link busy-waits (LINK_STATUS busy can stick once the link is
  torn down)
- board_get_unique_id from the factory ID in read-only info flash
  (0x77FE4), so the USB serial identifies the chip (HIL requirement)
- HIL: replace ch582m_evt (probe moved) with hydrausb3_v1
- Regenerate boards.rst, dependencies.rst, BoardPresets.json

Verified on HydraUSB3 v1 (ci rig): SuperSpeed still trains at 5000M
with fallback armed (3x replug); with SS terminations disabled the
device falls back and enumerates fully at 480M. Full HIL run passes
10/10 device tests including cdc_msc at SuperSpeed and
cdc_msc_throughput (MSC 22.1/14.1 MBps read/write at NUMP=1);
non-SuperSpeed-aware examples recover onto USB2 via the fallback.

Co-Authored-By: Claude Fable 5 &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>docs: convert changelog release notes from RST to Markdown (#3746)</title>
<updated>2026-06-30T15:27:27Z</updated>
<author>
<name>Ha Thach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T15:27:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=dae3f9a366bfcddbf9dcf1b48d7500286a849539'/>
<id>urn:sha1:dae3f9a366bfcddbf9dcf1b48d7500286a849539</id>
<content type='text'>
* docs: convert changelog release notes from RST to Markdown</content>
</entry>
<entry>
<title>docs: move changelog to docs/changelog, drop the docs/info folder</title>
<updated>2026-06-30T07:39:57Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T07:39:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=20200b35202e5dd0a1a5e8be1db081dc57f6ae8e'/>
<id>urn:sha1:20200b35202e5dd0a1a5e8be1db081dc57f6ae8e</id>
<content type='text'>
Relocate docs/info/changelog/ -&gt; docs/changelog/ (docs/info held only the
changelog) and update all references: the toctree, README + MAINTAINERS links,
make_release.py, and the make-release skill.

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>docs: keep the changelog page last in the toctree (maintainers before it)</title>
<updated>2026-06-30T07:36:48Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T07:36:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=0849a5c1722dfeaa1e576aa11259bd6274afe73c'/>
<id>urn:sha1:0849a5c1722dfeaa1e576aa11259bd6274afe73c</id>
<content type='text'>
Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>Revert MAINTAINERS to .rst and add it to the docs build</title>
<updated>2026-06-30T07:33:15Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T07:33:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=ae87287f5b79fe8242ecd2d70711a1820bf429ee'/>
<id>urn:sha1:ae87287f5b79fe8242ecd2d70711a1820bf429ee</id>
<content type='text'>
- restore MAINTAINERS.rst (drop the .md); make the changelog link absolute so it
  resolves both on GitHub and in the rendered docs
- docs/maintainers.rst includes the root file (same pattern as README) and is
  wired into the Documentation toctree

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>Fix code-review findings (changelog rendering, release skill, sidebar)</title>
<updated>2026-06-30T03:57:26Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T03:57:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=461dff59119addc8df38fca6189a2b691c77dedc'/>
<id>urn:sha1:461dff59119addc8df38fca6189a2b691c77dedc</id>
<content type='text'>
- changelog: fix 3 silent RST mis-renders carried over from the old monolith
  — Markdown link in 0.7.0, mismatched/single backticks in 0.18.0 / 0.20.0
- make-release skill contributors one-liner: parallelize the gh fetch, anchor
  the bot filter (was a substring that dropped handles like "abbott"), and join
  with ", " (paste -sd cycles the delimiter -&gt; "@a,@b @c"); finalize now stages
  only the reviewed set (git add -A -- ':!.idea'); drop the obsolete CRLF gotcha
- make_release.py: emit LF not CRLF in the repository.yml insertion (fixes the
  gotcha at the source)
- docs sidebar: drop the hardcoded furo component list; override brand.html to
  include furo's own template + the sponsor button (decoupled from furo
  internals, no upper-bound pin needed); move sponsor styles into custom.css
- .pre-commit-config.yaml: drop stale end-of-file-fixer excludes for the
  deleted contributors/CoC include shims

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>Address Codex review: release skill + furo requirement</title>
<updated>2026-06-30T03:23:36Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T03:23:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=0657ecf72839dbed263624af524d10d77d9c2b06'/>
<id>urn:sha1:0657ecf72839dbed263624af524d10d77d9c2b06</id>
<content type='text'>
- make-release skill: stage new files with git add -A in finalize, use
  unprefixed release tags (X.Y.Z), and run validate build steps in subshells
  so the cwd doesn't leak between commands
- docs/requirements.txt: require furo&gt;=2025.12.19 so the sidebar component
  list in conf.py (incl. variant-selector.html) is always available

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>Address Copilot review; move release process into the make-release skill</title>
<updated>2026-06-30T02:10:50Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-06-30T02:10:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/tinyusb.git/commit/?id=ce23b8d72e18398873d4e5deb8e38206218aea3d'/>
<id>urn:sha1:ce23b8d72e18398873d4e5deb8e38206218aea3d</id>
<content type='text'>
- README: restore the separate CH32V103 / CH583,CH582 rows in the Supported
  CPUs table — the merged row wrongly applied "ISO data loss [2]" to CH583/2
- Fix typos in historical changelog entries (santiy, Venndor, dynamnic, bagde,
  masstorage, techinical, walkaround, "Update Update") flagged by Copilot
- Replace the AGENTS.md Release section with a pointer to the make-release
  skill; add a Finalize step (maintainer commit/tag/push + GitHub release) to
  the skill so nothing is lost

Co-Authored-By: Claude Opus 4.8 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
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