tinyusb.git/examples/device/net_lwip_webserver, branch worktree-ch569-hydrausb3

ch32h417: register in CI matrix, lwIP throughput, docs and presets

2026-07-11T22:02:59Z

Final integration for the CH32H417 port. - .github/workflows/ci_set_matrix.py: add ch32h417 (riscv-gcc) so CI builds it. - examples/device/net_lwip_webserver: enable LWIP_HIGH_THROUGHPUT for the H417 (SuperSpeed iperf). - docs/reference/{boards,dependencies}.rst + hw/bsp/BoardPresets.json: regenerated for the new board and dependency. usbtest quirks intentionally left at 0 for the H417: its endpoint engine fixes the two CH569 5 Gbps silicon limitations (RB_EP_TX/RX_HALT gives a repeatable STALL for case 13; the reworked EP0/chain path is expected free of the wLength%4==1 ctrl_out drop), so the H417 targets a full 30/30 at SuperSpeed rather than 27/27. The HIL entry (test/hil/tinyusb.json) is deliberately deferred: it needs the chip's ESIG unique id read from the board on first flash, which is pending hardware access. Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

Reach SuperSpeed-class iperf on CH569 net_lwip_webserver

2026-07-08T01:49:16Z

Measurements with the 9*MSS window showed iperf pinned at 51 Mbit/s with the in-flight data exactly tracking the advertised window: the 120 MHz core's TCP receive path is the bottleneck, not the window or the USB link. Recover the software-checksum cost: inbound IP/UDP/TCP checksum VERIFICATION is skipped on the SuperSpeed build (USB already CRC32 protects every payload; outbound generation stays on). iperf over SuperSpeed improves 51 -> 74.5 Mbit/s (device RX, lwiperf). Also from bringing this up on a marginal SS lane that takes seconds to train (normal lanes train in <100 ms): - CFG_TUD_WCH_USB30_FALLBACK is now overridable from the build line; =0 builds SuperSpeed-only, which retries training indefinitely instead of settling for high speed - the fallback keeps retrying twice as long (4.4 s) when far-end RX terminations were seen: terminations mean an SS-capable partner exists, while a USB2-only host (no terminations) still falls back after ~2 s Validated on HydraUSB3 behind a Renesas uPD720201 hub; 65/65 unit tests, full example sweep, pre-commit clean. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Tune net_lwip_webserver lwIP memory for SuperSpeed on CH569

2026-07-08T00:55:13Z

iperf on the SuperSpeed build is TCP-window-bound (51 Mbit/s with the 6*MSS window). Reclaim RAMX to widen it: - dcd_ch56x_usbhs: new CFG_TUD_WCH_USBHS_EP_MAX limits usable endpoint numbers and scales the static RAMX bounce buffers accordingly (default unchanged at 8 endpoints) - net_lwip_webserver: limit the (fallback) USB2 endpoints to 1-3, freeing 4 KB of RAMX; grow the SuperSpeed build to PBUF_POOL_SIZE 9 / TCP_WND 9*MSS (the high-speed build keeps 6/6). RAMX 94% of 32 KB. High-speed fallback verified unchanged on HydraUSB3 (33 Mbit/s, full enumeration); the SuperSpeed window measurement is pending the rig's SS lane, which trains only intermittently (analog-marginal path - same binaries trained and ran 51 Mbit/s earlier the same day). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Retry CH569 SuperSpeed training and fix net_lwip_webserver EP0 size

2026-07-08T00:32:49Z

Two fixes found bringing up SuperSpeed on a Renesas uPD720201-based hub: - dcd_ch56x_usb30: retry link training with a fresh detect cycle every second fallback-timer tick (4 ticks total) before switching to the USB2 fallback. Some hubs only complete Polling on a re-attempt; with a single continuous attempt the link reached U0 rarely and the port fell back to high speed almost every boot. - net_lwip_webserver: CFG_TUD_ENDPOINT0_SIZE was left at plain 64, so usbd chunked EP0 data at 64 bytes; on a 512-mps SuperSpeed control endpoint the first chunk is a short packet, the host ends the data stage early and the status stage deadlocks until timeout ("can't read configurations, error -110"). Use the SuperSpeed-aware size and clamp the device-qualifier bMaxPacketSize0 like the other examples. Validated on HydraUSB3: NCM enumerates at 5000M reliably across warm reboots; lwiperf over SuperSpeed measures 51 Mbit/s device RX (TCP window bound; 33 Mbit/s on the high-speed fallback), MSC 169/136 MB/s. Full example sweep, 65/65 unit tests, pre-commit clean. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Add SuperSpeed support to CDC-NCM and enable iperf on CH569

2026-07-07T06:03:25Z

- TUD_CDC_NCM_SS_DESCRIPTOR template (bulk 1024 + endpoint companions) and companion handling in netd_open (notification endpoint skip, bulk pair drv_len) - net_lwip_webserver: SS device/config/BOS descriptors for the NCM build, CH569 added to the LWIP_HIGH_THROUGHPUT tier (builds lwiperf). The 16 KB RAMS cannot hold lwIP: heap and pools go to the 32 KB RAMX via LWIP_DECLARE_MEMORY_ALIGNED (arch/cc.h), with a 6-pbuf pool / 6*MSS window and a 3 KB dcd bounce pool to fit (RAMX 92%) - CH569 dcd fixes found while bringing this up: TMR0 counts only 26 bits, so the previous 1 s fallback CNT_END (120e6 > 2^26) silently never expired - use 0.55 s per phase; make link busy-waits in usb30_hw_init best-effort so a stuck-BUSY teardown state cannot abort re-initialization half way Builds clean (full ch56x example sweep); NOT yet hardware-validated: the rig's WCH-LinkE stopped completing flash writes mid-session (reads and erases fine), leaving the board without firmware - iperf numbers pending physical probe/board recovery. Co-Authored-By: Claude Fable 5

Add CH569 USB3.0 SuperSpeed device driver - TinyUSB's first SuperSpeed port

2026-07-07T04:11:41Z

New dcd_ch56x_usb30.c + ch56x_usb30_reg.h (both MIT, written fresh): - Register model from the hydrausb3 project's reverse engineering (wch-ch56x-lib, Apache-2.0) and TeenyUSB's CH56x port (MIT), with LINK-layer bit names per the officially documented CH32H417 (same IP, CH32H417RM chapter 27); TU_VERIFY_STATIC offset asserts guard the vendor header layout - Software-assisted LTSSM in the LINK interrupt: polling/TXEQ/ready sequencing, LMP PORT_CAPABILITY + PORT_CONFIGURATION exchange, warm and hot reset handling. Link-up (ready after TXEQ) is reported as dcd_event_bus_reset with TUSB_SPEED_SUPER - EP0 with fixed 512-byte mps: SETUP via RX flag bit30, unified status stage via bit29 (SET_ADDRESS applied there), manual IN packet sequence - Data endpoints with per-burst DMA re-arm, partial burst-drain accounting, ERDY flow control and NUMP=1 default (multi-packet burst silicon quirk); RAMX bounce slots from a small pool for transfer buffers outside RAMX; isochronous not supported - Board vector forwarders unified into one handler + symbol aliases: gcc identical-code-folding otherwise rewrites one interrupt handler as a call into another whose mret skips the caller's epilogue, leaking a stack frame per interrupt (found the hard way) - hydrausb3_v1 default SPEED flipped to super; skip net_lwip_webserver (16 KB RAMS, same as other small-RAM parts) Verified on HydraUSB3 v1 hardware (ci rig, USB3 host port): - cdc_msc enumerates at 5000M: bcdUSB 3.20, EP0 mps 2^9, endpoint companion descriptors, BOS with USB2-ext + SuperSpeed capability - CDC echo and MSC FAT12 reads functional at SuperSpeed; 30x sustained read stress and 5x replug/reset cycles all re-enumerate at 5000M - SPEED=high regression: still enumerates at 480M - Full example sweep builds for both controllers Co-Authored-By: Claude Fable 5

docs: add build-doc tooling and a README for every example

2026-06-29T03:16:25Z

Documentation tooling: - Add the `build-doc` skill and `tools/build_doc.py` wrapper for local Sphinx builds (clean / -W / open). - Enable Markdown (MyST) in conf.py and auto-collect examples/{device,host,dual}/*/README.md into a 3-level Examples nav (Examples > Device/Host/Dual > example), noting each page's source location and normalizing headings to a single H1. - Remove the stale `.claude/commands/build-doc.md`; point the AGENTS.md Documentation section at the skill. Example docs: - Add a README.md for every device/host/dual example: what it does, USB interface table, notable tusb_config.h settings, generic CMake + Make build steps, and how to try it. - Fold each *_freertos variant into its base README, noting the FreeRTOS source path and any RTOS-specific behavior. Generated docs/examples/ output is git-ignored. Builds clean with `sphinx-build -W`. Co-Authored-By: Claude Opus 4.8 (1M context)

Merge remote-tracking branch 'tinyusb/master' into stm32c5

2026-05-24T16:46:26Z

Signed-off-by: HiFiPhile

tweak examples

2026-05-23T17:37:47Z

Signed-off-by: HiFiPhile

enable iperf

2026-05-14T12:09:06Z

Signed-off-by: HiFiPhile