tinyusb.git/examples/device, branch worktree-ch569-hydrausb3

ch32h417: register in CI matrix, lwIP throughput, docs and presets

2026-07-11T22:02:59Z

Final integration for the CH32H417 port. - .github/workflows/ci_set_matrix.py: add ch32h417 (riscv-gcc) so CI builds it. - examples/device/net_lwip_webserver: enable LWIP_HIGH_THROUGHPUT for the H417 (SuperSpeed iperf). - docs/reference/{boards,dependencies}.rst + hw/bsp/BoardPresets.json: regenerated for the new board and dependency. usbtest quirks intentionally left at 0 for the H417: its endpoint engine fixes the two CH569 5 Gbps silicon limitations (RB_EP_TX/RX_HALT gives a repeatable STALL for case 13; the reworked EP0/chain path is expected free of the wLength%4==1 ctrl_out drop), so the H417 targets a full 30/30 at SuperSpeed rather than 27/27. The HIL entry (test/hil/tinyusb.json) is deliberately deferred: it needs the chip's ESIG unique id read from the board on first flash, which is pending hardware access. Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

ch32h417: add USB3 SuperSpeed dcd with runtime USB2 fallback

2026-07-11T21:59:21Z

Second stage: the USBSS SuperSpeed device driver (SPEED=super now links). The LINK layer is the same IP as the CH569 but the endpoint engine is the H417's reworked chain-DMA design (hardware SEQ_AUTO/ERDY_AUTO, persistent RB_EP_*_HALT, per-chain completion). The RCC/PHY/LINK bring-up and EP0 control sequences are transcribed from the WCH EVT USBSS device demo; data endpoints arm one chain per packet (burst 1) for correctness-first bring-up, matching the CH569 port's initial path - raise CFG_TUD_WCH_USB30_MAX_BURST once the hardware validates. Buffers may live anywhere in the shared SRAM (all DMA-reachable), so no bounce machinery is needed. - src/portable/wch/dcd_ch32h417_usb30.c (+ ch32h417_usb30_reg.h): full dcd with a STATE_CHG-driven LTSSM handler, LMP PORT_CAP/PORT_CFG exchange, EP0 DPH/ERDY flow with software sequence, chain-armed data endpoints, per-EP HALT stall, and a TIM12-backstopped runtime USB2 fallback that hands rhport 0 to ch32h417_usb2_* when SuperSpeed training fails (host has no SS port). - examples/device/*/skip.txt: add mcu:CH32H417 to the FreeRTOS + audio/video examples (no FreeRTOSConfig for this family yet), mirroring mcu:CH569. Build-verified: all 20 device examples build for SPEED=super, and cdc_msc for SPEED=high, clean under -Werror (riscv-none-elf-gcc 13.2). Hardware bring-up at 5 Gbps (usbtest battery, throughput) is pending rig availability. Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

usbtest: skip silicon-impossible cases via bcdDevice quirk flags

2026-07-09T07:34:13Z

The CH569 USBSS ctrl_out flakiness (cases 14/21, host -EPROTO) is a silicon erratum, not a driver bug: EP0 OUT data stages whose wLength % 4 == 1 are intermittently dropped at 5 Gbps. Proven by A/B against WCH's own binary USB3 stack (SimulateCDC EVT demo patched to accept the gadget-zero 0x5b/0x5c requests), which fails identically on the same board — independent of host LPM (persists with U1/U2 disabled) and sysclk (80 vs 120 MHz). Bulk OUT at the same lengths is clean. Document the erratum in the dcd and drop the ineffective zeroed-BOS workaround. Rather than letting known-impossible cases flake the battery, the firmware now advertises quirk flags in bcdDevice bits 4-7 (tier stays in bits 0-3): 0x10 skips ctrl_out 14/21, 0x20 skips ep-halt 13 (the previously proven single-STALL limitation). usbtest.py skips flagged cases visibly at SuperSpeed only (explicit --tests still runs them) and reports them in the summary/JSON. Also fix the CH56x USB3 dcd leaving an endpoint halted across reconfiguration: clear the stalled flag in dcd_edpt_open/close/ close_all (USB 2.0 9.4.5) so a SET_CONFIGURATION recovery of a halted-then-reopened endpoint does not STALL forever. Validated on hydrausb3_v1 at 5000M: tier-4 battery x3 = 27/27 passed + 3 skipped, full HIL device suite 12/12 green (MSC 160/134 MB/s). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Add SuperSpeed isochronous support to the CH56x USB3 dcd

2026-07-08T05:26:08Z

The register model comes from disassembling WCH's official USB30 device blob (libCH56x_USB30_device_lib.a): USB30_ISO_Setendp reveals per- endpoint isochronous mode bits in UEP_CFG (bit 16+ep for OUT, bit 24+ep for IN); arming and completion then use the normal endpoint flow. The usbtest example moves back to tier 4 at SuperSpeed with an iso pair in the SS descriptor set - all four kernel usbtest iso cases (15/16/22/23) pass on hardware at 5000M. The endpoint-halt latch from the previous commit is kept (it fixes usbtest case 29); case 13 is now documented as a silicon limitation after exhaustive on-hardware experiments: a halted endpoint answers exactly one probe with a STALL TP and no re-arm strategy (any NUMP, ERDY, 30 us timer re-assertion, endpoint enable bounce) revives it - no event fires per stall TP. The CH32H417's reworked endpoint engine adds a persistent RB_EP_TX_HALT mode, evidently addressing exactly this. Battery results: 30/30 at high speed, 28/30 at SuperSpeed (case 13 = silicon halt limitation; case 14 ctrl_out is intermittent - pre-existing EP0 OUT flakiness under investigation). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Pass the usbtest battery on CH569 at high and SuperSpeed

2026-07-08T05:26:08Z

Running the Linux kernel usbtest/testusb battery against the CH569 for the first time. Results: 30/30 at high speed (4 consecutive reflash cycles), 25/26 at SuperSpeed. DCD fixes found by the battery: - dcd_ch56x_usbhs: clear-halt on an armed bulk-OUT pipe reset the toggle but dropped the queued receive, NAKing forever (usbtest case 29 - the same defect previously found on rp2040/fsdev/ch32_usbhs/rusb2) - dcd_ch56x_usb30: endpoint halt is now latched; the endpoint event handler used to clear the response field on every completion, wiping a just-set STALL while the peer streamed, and clear-halt now re-arms a still-armed transfer with the fresh packet sequence (cases 13/29) usbtest example gains SuperSpeed support: tier 3 on SS builds, a 4-endpoint SS descriptor set with companions, EP0 512 config and 1024-byte receive buffers. test/hil/usbtest.py gains SuperSpeed-aware case parameters: bulk sizes and vary steps must be 1024-multiples at SS or the device's whole-packet source overruns the host request (case 4 EOVERFLOW). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Merge branch 'usbtest': Linux kernel usbtest battery support

2026-07-08T05:26:08Z

Brings the usbtest device example (gadget-zero source/sink peer for the kernel's usbtest.ko/testusb), the test/hil/usbtest.py battery runner and the extended vendor class driver (interrupt/isochronous endpoints, alt settings) into the CH569 SuperSpeed branch, enabling the battery to run against both CH56x dcds. Conflict resolution: test/hil/tinyusb.json keeps this branch's hydrausb3_v1 fixture entry and adds the usbtest branch's ch32v307v_r1_1v0 entry. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Reach SuperSpeed-class iperf on CH569 net_lwip_webserver

2026-07-08T01:49:16Z

Measurements with the 9*MSS window showed iperf pinned at 51 Mbit/s with the in-flight data exactly tracking the advertised window: the 120 MHz core's TCP receive path is the bottleneck, not the window or the USB link. Recover the software-checksum cost: inbound IP/UDP/TCP checksum VERIFICATION is skipped on the SuperSpeed build (USB already CRC32 protects every payload; outbound generation stays on). iperf over SuperSpeed improves 51 -> 74.5 Mbit/s (device RX, lwiperf). Also from bringing this up on a marginal SS lane that takes seconds to train (normal lanes train in <100 ms): - CFG_TUD_WCH_USB30_FALLBACK is now overridable from the build line; =0 builds SuperSpeed-only, which retries training indefinitely instead of settling for high speed - the fallback keeps retrying twice as long (4.4 s) when far-end RX terminations were seen: terminations mean an SS-capable partner exists, while a USB2-only host (no terminations) still falls back after ~2 s Validated on HydraUSB3 behind a Renesas uPD720201 hub; 65/65 unit tests, full example sweep, pre-commit clean. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Tune net_lwip_webserver lwIP memory for SuperSpeed on CH569

2026-07-08T00:55:13Z

iperf on the SuperSpeed build is TCP-window-bound (51 Mbit/s with the 6*MSS window). Reclaim RAMX to widen it: - dcd_ch56x_usbhs: new CFG_TUD_WCH_USBHS_EP_MAX limits usable endpoint numbers and scales the static RAMX bounce buffers accordingly (default unchanged at 8 endpoints) - net_lwip_webserver: limit the (fallback) USB2 endpoints to 1-3, freeing 4 KB of RAMX; grow the SuperSpeed build to PBUF_POOL_SIZE 9 / TCP_WND 9*MSS (the high-speed build keeps 6/6). RAMX 94% of 32 KB. High-speed fallback verified unchanged on HydraUSB3 (33 Mbit/s, full enumeration); the SuperSpeed window measurement is pending the rig's SS lane, which trains only intermittently (analog-marginal path - same binaries trained and ran 51 Mbit/s earlier the same day). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Retry CH569 SuperSpeed training and fix net_lwip_webserver EP0 size

2026-07-08T00:32:49Z

Two fixes found bringing up SuperSpeed on a Renesas uPD720201-based hub: - dcd_ch56x_usb30: retry link training with a fresh detect cycle every second fallback-timer tick (4 ticks total) before switching to the USB2 fallback. Some hubs only complete Polling on a re-attempt; with a single continuous attempt the link reached U0 rarely and the port fell back to high speed almost every boot. - net_lwip_webserver: CFG_TUD_ENDPOINT0_SIZE was left at plain 64, so usbd chunked EP0 data at 64 bytes; on a 512-mps SuperSpeed control endpoint the first chunk is a short packet, the host ends the data stage early and the status stage deadlocks until timeout ("can't read configurations, error -110"). Use the SuperSpeed-aware size and clamp the device-qualifier bMaxPacketSize0 like the other examples. Validated on HydraUSB3: NCM enumerates at 5000M reliably across warm reboots; lwiperf over SuperSpeed measures 51 Mbit/s device RX (TCP window bound; 33 Mbit/s on the high-speed fallback), MSC 169/136 MB/s. Full example sweep, 65/65 unit tests, pre-commit clean. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Add SuperSpeed descriptors to all bulk/interrupt class drivers and examples

2026-07-07T11:12:02Z

Class drivers: skip and account the SS endpoint companion descriptor in every descriptor walk (hid, midi, midi2, ecm_rndis, printer, mtp, usbtmc), via a shared usbd_skip_ss_ep_companion() helper in usbd_pvt.h (cdc/ncm already handled; vendor/dfu naturally tolerant). usbtmc buffer grows to 1024 at SS to satisfy its packet-multiple assert. bth/audio/video are left FS/HS-only (ISO-centric; ISO is unsupported on the CH569 dcd). usbd.h: new SS template macros TUD_HID_SS_DESCRIPTOR(+INOUT), TUD_MIDI_SS_DESCRIPTOR (+ DESC_EP_SS part), TUD_MIDI2_DESC_ALT1_EP_SS, TUD_PRINTER_SS_DESCRIPTOR, TUD_MTP_SS_DESCRIPTOR, TUD_USBTMC_BULK_SS_DESCRIPTORS/INT_SS_DESCRIPTOR, with _SS_DESC_LEN counterparts (bulk endpoints hardcode 1024, companion after every EP). Examples: 17 bulk/interrupt examples gain the full SS descriptor set (EP0 512/64 clamp, SS device descriptor bcdUSB 3.20 mps0=2^9, SS config with companions, BOS caps, speed-switched callbacks): cdc_dual_ports, cdc_msc_freertos, dfu, dfu_runtime, dynamic_configuration, hid_boot_interface, hid_composite(+freertos), hid_generic_inout, hid_multiple_interface, midi_test(+freertos), midi2_device, msc_dual_lun, mtp, printer_to_cdc, usbtmc, webusb_serial. msc_dual_lun is un-skipped for CH569 using read-only flash disks (16KB RAM can't hold two 8KB RAM disks, same as ch32v10x/v20x boards). Validation: full example sweep green for hydrausb3_v1 (SPEED=super, 19 device ELFs) and raspberry_pi_pico; wTotalLength == sizeof() verified for every SS configuration array in the built ELFs; ceedling 65/65; pre-commit clean; code-size delta +0.0% on rp2040 (SS code folds out on non-SS builds). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE