tinyusb.git/hw/bsp/ch32v10x, branch claude/add-systemview-debug

sysview: take the timestamp from a BSP hardware timer where the core has no DWT

2026-09-03T21:21:57Z

Cortex-M0/M0+, the WCH RISC-V parts and MAX3266x have no usable DWT cycle counter, so their family.c provides SEGGER_SYSVIEW_X_GetTimestamp() from a free-running hardware timer: a 32-bit general-purpose timer on ST parts (sysview_stm32_tim2.h), SysTick-extended sources on the M0 families, the core's SysTick-equivalent on WCH with the documented ordered read of the split count registers (sysview_wch_timestamp.h), and a TMR on MAX3266x (sysview_max32_tmr.h). max32666fthr's DWT implements only watchpoint comparators (DWT_CTRL.NOCYCCNT=1 read live; UG6971 documents no DWT/trace at all), so SystemView's ARMv7-M default read 0xE0001004 as a frozen 0 and every duration decoded as zero. The TMR runs at 48 MHz (f_PCLK = f_SYS_CLK/2; Continuous mode, CMP=0xFFFFFFFF, prescaler 1 - UG6971 15.2 guarantees TMRn_CNT readable while counting); TMR0 by default - present on every MAX32 part, unused by the examples, FreeRTOS ticks on SysTick - overridable with -DSYSVIEW_MAX32_TMR=n. The family builds SystemView with SEGGER_SYSVIEW_CORE_OTHER and sets CFG_TUSB_SYSVIEW_TIMESTAMP_BSP, a tusb_sysview.c opt-in for ARMv7-M parts without CYCCNT where the BSP also reports the rate via SEGGER_SYSVIEW_X_GetTimestampFreq(); the fixed-1MHz microsecond contract is unreachable on a powers-of-two-only prescaler. SEGGER_SYSVIEW_X_GetInterruptId() gains the ICSR.VECTACTIVE read for CORE_OTHER builds. MAX32650/32690 use different GCR clock-gate names and stay unported. Measured on the rig: seven host-timed 1.000 s gaps at 1.00044-1.00091 (median +0.05%). stm32f0 refuses to configure SYSVIEW for stm32f070xb at CMake time: that variant has no TIM2 at all, and the alternative was an undefined-reference link error with no hint. The shared hw/bsp/sysview_*.h join ci_select rule 16's hw/bsp file list (cross-family build files, compiled only under -DSYSVIEW which no CI leg enables), mirrored in the spec's rule table, so master's classification guard resolves them on both axes.

bsp, hil: flash WCH boards with the unified OpenOCD fork (#3791)

2026-07-28T05:50:28Z

bsp, hil: flash with the unified OpenOCD fork https://github.com/hathach/openocd (branch tinyusb) is mainline plus every config these boards need: RPi RP2350, ADI max32/max78, the MounRiver WCH configs, and the wlinke adapter on mainline's riscv target. It is a superset of the vendor forks, so one 'openocd' covers all boards; -DOPENOCD=/OPENOCD= still select another, msdk's when MAXIM_PATH is set. Drops family_flash_openocd_wch and the OPENOCD_WCH pair, dedups family_flash_openocd_adi, aligns ch583's work area, and points hil at the flasher's own config instead of generating one per probe. Verified: HIL green on all four WCH boards and max32666fthr.

dcd/ch32_usbfs: support CH32V103 combined endpoint control register

2026-06-18T03:58:58Z

CH32V103 uses the older USBFS IP: a single combined UEPn_CTRL register per endpoint (IN response in bits [1:0], OUT response in [3:2], shared auto-toggle, separate IN/OUT toggles) instead of the separate UEPn_TX_CTRL/UEPn_RX_CTRL bytes of the newer IP (CH32V20x/V307). The shared driver was written for the newer IP, so EP0 control transfers never worked on V103: the OUT response was written to a reserved byte and the IN write clobbered the OUT bits. - ch32_usbfs_reg.h: annotate the V103 register struct with byte offsets and add a union exposing the combined UEPn_CTRL at the UEPn_TX_CTRL offset; define CH32_USBFS_EP_CTRL_COMBINED and the combined-register bit positions. - dcd_ch32_usbfs.c: abstract EP control access behind ep_tx/rx_ctrl_set() (full write) and ep_tx/rx_set_response() (response-only RMW). The newer-IP path is unchanged; the combined path read-modify-writes the single register and arms the post-SETUP data stage at DATA1. - bsp/ch32v10x: implement board_get_unique_id() (real chip UID) and drop the CSR 0x800 writes that corrupted the QingKe V3 interrupt config and left all interrupts disabled (the USB ISR never ran). Verified on ch32v103r_r1_1v0: enumerates and passes HIL for cdc_msc, hid, msc, midi, mtp, dfu, etc. Co-Authored-By: Claude Opus 4.8 (1M context)

Merge pull request #3620 from UMRnInside/fix-ch32v103-hardfault

2026-05-30T15:05:01Z

Fix ch32v103 hardfault & Add CH32V103C8T6 Bluepill board

Enable GPIOC for CH32V103 bluepill boards

2026-05-26T14:52:30Z

Fix missing prototype in ch32v10x bsp

2026-05-24T02:21:41Z

use vendor-specific CSR 0x800 to toggle IRQ

2026-05-24T02:00:06Z

Fix typo found by Copilot

2026-05-24T01:27:32Z

chinese -> Chinese manufactors -> manufacturers Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>

bsp/ch32: fix linker report 100% RAM usage

2026-05-22T13:25:24Z

Signed-off-by: HiFiPhile

Add ch32v103c_bluepill board

2026-04-26T12:36:55Z