tinyusb.git/hw/bsp/imxrt/family.c, branch codex/class-reference-docs

address #3787 Codex round 2: board-gate PHY resets, session robustness

2026-07-24T14:30:42Z

The board-specific PHY-reset nets move behind a board.h opt-in (TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other boards of those families cannot inherit a foreign GPIO write; the chip-level trace pin muxes stay family-wide by design (same pattern as stm32h7). same70 reference: width 1 is the validated default until the J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so --attach sessions decode ROM execution too. etm_capture rejects an unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB and a runtime switch would desync the stream); etm_profile keeps same-named statics from different modules as distinct rows. Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2.

imxrt: hold EVKB Ethernet PHY in reset while tracing, 50 MHz trace pin

2026-07-24T09:20:13Z

Fresh bring-up pass on mimxrt1170_evkb: holding the 100M RTL8201 in reset (ENET_RST_B = GPIO_LPSR_04) stops its RMII lines driving against the shared trace pads and doubles the clean trace-pin rate to 50 MHz (100 MHz CSTRACE root; 133 MHz root is marginal, stock 132 corrupts). Validated 3x 8 s TinyUSB captures at 11.46M fetches. D1-D3 remain silent in every configuration - the welded R1882-R1884 are electrically open; reflow is the remaining step to width 4. Board notes gain JP4 (must be shorted for an external probe on J58).

imxrt: TRACE_ETM for RT1011 and RT1176, validate both boards

2026-07-24T08:56:14Z

metro_m7_1011 (custom ETM-header rework): 500 MHz core, 66 MHz TRACECLK width 4, +50 ps; trace_etm_init ungates the 132 MHz trace root that BOARD_BootClockRUN leaves gated. mimxrt1170_evkb: 996 MHz CM7 at width 1, CSTRACE pinned to 50 MHz (stock 132 corrupts - the Ethernet PHY loads the CLK net) and the CM7 platform trace-funnel port enabled in firmware: J-Link does not program that funnel and everything reads register-perfect yet silent without it. FlexSPI boot needs the committed SP/PC hooks; D1-D3 stay dead pending the R1882-R1884 continuity check (width-4 TODO).

fix hil host cdc echo test with imxrt and other fast mcu

2026-04-03T03:45:13Z

replace board_millis() with tusb_time_millis_api()

2026-02-27T17:01:40Z

SCB_EnableDCache() is required for rt1011

2025-12-20T16:08:40Z

bsp: Disable SysTick ISR if FreeRTOS is enabled

2025-11-25T15:30:32Z

fix build warning with clang

2025-10-15T08:27:48Z

fix imxrt build

2025-09-15T09:15:48Z

Move BOARD_ConfigMPU into board specific init

2025-09-12T12:06:57Z

Signed-off-by: HiFiPhile