tinyusb.git/hw/bsp/ra/boards/ra6m5_ek/ozone, branch codex/class-reference-docs Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp/ra/boards/ra6m5_ek/ozone?h=codex%2Fclass-reference-docs 2026-07-24T08:56:14Z ra: TRACE_ETM for ra6m5_ek and ra8m1_ek 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:53Z urn:sha1:4d9e4c9e3895b0c15a04763028d1becd27bbf89c Generic TRCKCR setup gated on DHCSR.C_DEBUGEN (a standalone-boot TRCKCR write wedges the chip un-attachable until power-cycle), two-step write per the hardware manual. ra6m5_ek: div-4 (25 MHz pin) - div-2 is dead on this board at every width/timing; J9 must be closed. ra8m1_ek: chip-max 120 MHz TRCLK / 60 MHz pin via the committed JLinkScript whose empty OnTraceStart defers the trace clock to firmware (J-Link's from-reset enable steps the clock mid-stream at the FSP MOCO-to-PLL switch); ReadIntoTraceCache covers runtime ROM execution. J9 closed on both EKs - open = SWD contention up to apparent bricks. update build for ra8m1: usbfs work, but usbhs not working just yet. Probably missing configuration or clock setup 2024-12-13T10:28:45Z hathach thach@tinyusb.org 2024-12-13T10:24:57Z urn:sha1:0785daecc1a3a11d5bacbd7c4cd7dc4a48b11b49 refactored multiple ports for hcd rusb2 2023-07-26T12:52:33Z hathach thach@tinyusb.org 2023-07-26T12:50:50Z urn:sha1:6b6dcc6c099eeafaa6d76bf6133181874beabc0d correct setting trace clock 2023-07-07T04:07:57Z hathach thach@tinyusb.org 2023-07-07T04:07:57Z urn:sha1:4bbacb10089856fd6cd6e4c54da8ab2dc8575c60 update fsp to version 4.5, correct RA BSP. Fix ETM Trace with 6m5 by lowering PLL to 128Mhz. 2023-07-04T12:27:37Z hathach thach@tinyusb.org 2023-07-04T12:27:37Z urn:sha1:071c30f381074c780bfb068cd31ed0801336bea6 add etm trace for 6m5 2023-07-02T16:39:43Z hathach thach@tinyusb.org 2023-07-02T16:39:43Z urn:sha1:787229a35e20e488b642e879e4f068571e9488df