tinyusb.git/hw/bsp/ra/boards, branch cdc_persistent

address #3787 Codex round 2: board-gate PHY resets, session robustness

2026-07-24T14:30:42Z

The board-specific PHY-reset nets move behind a board.h opt-in (TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other boards of those families cannot inherit a foreign GPIO write; the chip-level trace pin muxes stay family-wide by design (same pattern as stm32h7). same70 reference: width 1 is the validated default until the J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so --attach sessions decode ROM execution too. etm_capture rejects an unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB and a runtime switch would desync the stream); etm_profile keeps same-named statics from different modules as distinct rows. Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2.

address #3787 reviews: bsp fixes, script hardening, board-note accuracy

2026-07-24T11:38:40Z

Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70 ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the RA references, profile-script support for --no-timestamps itraces. Deep review (whole branch): same70_xplained board row + caveat restored, stale pico2 72 MHz claim corrected to the shipped 48, explicit SetTracePortWidth(4) in the three references that relied on Ozone's default, coverage-cell guard, median-based SysTick calibration, dead session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the validated chip max) and the debugger guard indented. EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified); RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB breaks the external probe even with JP4 shorted.

ra: TRACE_ETM for ra6m5_ek and ra8m1_ek

2026-07-24T08:56:14Z

Generic TRCKCR setup gated on DHCSR.C_DEBUGEN (a standalone-boot TRCKCR write wedges the chip un-attachable until power-cycle), two-step write per the hardware manual. ra6m5_ek: div-4 (25 MHz pin) - div-2 is dead on this board at every width/timing; J9 must be closed. ra8m1_ek: chip-max 120 MHz TRCLK / 60 MHz pin via the committed JLinkScript whose empty OnTraceStart defers the trace clock to firmware (J-Link's from-reset enable steps the clock mid-stream at the FSP MOCO-to-PLL switch); ReadIntoTraceCache covers runtime ROM execution. J9 closed on both EKs - open = SWD contention up to apparent bricks.

rusb2: EP0 OUT reliability, HS UTMI PHY power-up, FS-only build support

2026-07-13T08:30:44Z

- EP0 OUT: park a back-to-back data-stage packet the DCP accepted before PID could go NAK and deliver it into the next armed chunk; flow-control the single-buffer control pipe between chunks (usbtest ctrl_out corruption); discard a packet parked while an OUT pipe was halted so BOT reset recovery's fresh CBW read can't receive stale WRITE data - HS UTMI PHY power-up per the FSP sequence, shared by dcd/hcd: CLKSEL programmed from the board XTAL (EK-RA8M1 runs 20 MHz; the 24 MHz reset default never locks) while DIRPD holds the PHY down, then timed release - hw/bsp(ra8m1_ek): fix U60CK divider macro - BSP_CFG_U60CK_DIV used the generic USB_CLOCK_DIV_8 encoding (7), which USB60CKDIVCR rejects, leaving the USBHS link domain at 480 MHz; the USB60-specific BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) sticks and yields the required 60 MHz from PLL1P - support FS-only builds on the high-speed port: gate SYSCFG.HSE on TUD_OPT_HIGH_SPEED (RHPORT_DEVICE_SPEED=OPT_MODE_FULL_SPEED was a silent no-op) and always compile both hwfifo access widths - the FIFO width belongs to the module, not the link speed (FS builds corrupted odd-length tails: 16-bit access against MBW-32) - iso activate: reset stale pipe bookkeeping so a BRDY firing before the class re-arms can't replay a pre-SET_INTERFACE transfer; write PIPEBUF after PIPESEL selects the pipe (PIPESEL-windowed register) - clear-halt: re-assert BUF on a still-armed OUT pipe (usbtest case 29) - bound the D0FIFO ready spin so an undrained double-buffered IN pipe can't freeze the stack with the IRQ masked - usbtest example: cap interrupt mps at 64 on RUSB2 high speed (pipes 6-9 have a fixed 64-byte buffer, RA6M5 UM 29.1) Verified: usbtest 30/30 on ra6m5_ek (HS), ra4m1_ek (FS) and ra8m1_ek (FS-forced build on the HS port). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_01HeF2gZ1M7GWkz6Av4BpKPg

- change to use CMAKE_SYSTEM_CPU to prevent CMAKE_SYSTEM_PROCESSOR conflict with zephyr

2025-01-22T15:31:08Z

- change tinyusb CMakeLists.txt to function tinyusb_target_add() instead of defining tinyusb lib target

embed metadata to family.c and board.h to generate supported boards doc

2024-12-27T02:11:09Z

make sure g_bsp_rom_registers is not dropped by linker in cmake build.

2024-12-16T15:03:06Z

always reserve 0x100 for option setting in linker to prevent possible bricked mcu

fix portenta build, added core-m85.cmake/mk

2024-12-13T11:16:19Z

update build for ra8m1: usbfs work, but usbhs not working just yet. Probably missing configuration or clock setup

2024-12-13T10:28:45Z

ra8m1_ek led and button works

2024-12-13T05:50:51Z