Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp/rp2040?h=claude%2Fadd-systemview-debug 2026-09-03T21:21:57Z 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-08-11T10:07:44Z urn:sha1:d2de029fd9def460d66e87fd1088cc49ed0f4574 The dual-role dogfood measured the 4096 fallback losing 96.7% of ISR exit contexts on mimxrt1064_evk and 99.1% on metro_m4_express; a local-board run measured stm32u575nucleo losing ~19% of the whole stream under a 12 s cdc_msc workload. The default was too small for any real capture on fast parts and every user had to rediscover that per board. Families now declare SYSVIEW_BUFFER_SIZE_DEFAULT in family.cmake (the SYSVIEW_RAM_BASE_DEFAULT pattern): imxrt, nrf, rp2040, samd5x_e5x, stm32f4, stm32f7, stm32h7 and stm32u5 set 65536, the measured-safe value. -DSYSVIEW_BUFFER_SIZE still beats everything; small-RAM parts keep the 4096 fallback and their per-board overrides (stm32f072disco's 2048 verified still honoured). lpc55 measured 34 lost events on the same route, an order of magnitude lighter, so it keeps the fallback rather than inheriting a default on thin evidence. 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-09-03T10:14:28Z urn:sha1:5a0d707dd96ae7821d97793b441b86aabb684855 Cortex-M0/M0+, the WCH RISC-V parts and MAX3266x have no usable DWT cycle counter, so their family.c provides SEGGER_SYSVIEW_X_GetTimestamp() from a free-running hardware timer: a 32-bit general-purpose timer on ST parts (sysview_stm32_tim2.h), SysTick-extended sources on the M0 families, the core's SysTick-equivalent on WCH with the documented ordered read of the split count registers (sysview_wch_timestamp.h), and a TMR on MAX3266x (sysview_max32_tmr.h). max32666fthr's DWT implements only watchpoint comparators (DWT_CTRL.NOCYCCNT=1 read live; UG6971 documents no DWT/trace at all), so SystemView's ARMv7-M default read 0xE0001004 as a frozen 0 and every duration decoded as zero. The TMR runs at 48 MHz (f_PCLK = f_SYS_CLK/2; Continuous mode, CMP=0xFFFFFFFF, prescaler 1 - UG6971 15.2 guarantees TMRn_CNT readable while counting); TMR0 by default - present on every MAX32 part, unused by the examples, FreeRTOS ticks on SysTick - overridable with -DSYSVIEW_MAX32_TMR=n. The family builds SystemView with SEGGER_SYSVIEW_CORE_OTHER and sets CFG_TUSB_SYSVIEW_TIMESTAMP_BSP, a tusb_sysview.c opt-in for ARMv7-M parts without CYCCNT where the BSP also reports the rate via SEGGER_SYSVIEW_X_GetTimestampFreq(); the fixed-1MHz microsecond contract is unreachable on a powers-of-two-only prescaler. SEGGER_SYSVIEW_X_GetInterruptId() gains the ICSR.VECTACTIVE read for CORE_OTHER builds. MAX32650/32690 use different GCR clock-gate names and stay unported. Measured on the rig: seven host-timed 1.000 s gaps at 1.00044-1.00091 (median +0.05%). stm32f0 refuses to configure SYSVIEW for stm32f070xb at CMake time: that variant has no TIM2 at all, and the alternative was an undefined-reference link error with no hint. The shared hw/bsp/sysview_*.h join ci_select rule 16's hw/bsp file list (cross-family build files, compiled only under -DSYSVIEW which no CI leg enables), mirrored in the spec's rule table, so master's classification guard resolves them on both axes. 2026-09-03T02:55:54Z Zixun LI admin@hifiphile.com 2026-09-03T02:55:54Z urn:sha1:fe3074ede45c53acd66356b4568115410a0bfc0b rp2040: do not require PICO_DEFAULT_PIO_USB_DP_PIN to be set for pio_usb 2026-09-02T18:35:51Z graham sanderson graham.sanderson@raspberrypi.com 2026-09-02T18:35:51Z urn:sha1:5d71979f4ee629f5d811bd2e3f4d975f2a87f61a 2026-08-28T18:08:40Z hathach thach@tinyusb.org 2026-08-28T09:40:07Z urn:sha1:839c324458f6900a58182d9aa23d846e8ec55c94 Closes the sys-clock question. rp2350: the dynamic 156 MHz switch is removed - 150 MHz soak-tested clean (and a runtime switch truncates ETM capture on the trace carrier). rp2040 keeps its existing 120 MHz: soak sweeps show 120 = 8/8, stock 125 = 0/3 (bulk-OUT collapses, device NAKs ~600:1 with zero CRC errors on the wire), and 132 = 2/10 flaky despite an exact 12n/375k divider - no divider criterion predicts rp2040 PIO-USB health (the RX state machine samples at raw sysclk), so only soak-validated clocks ship. 2026-08-28T18:08:31Z hathach thach@tinyusb.org 2026-08-28T09:39:58Z urn:sha1:6e8e2caf7fc2dc5575f5e0c71e69c1b19b3f5699 Board files for the trace carrier (console GP12/13, LED GP10, I2C GP8/9, PIO-USB host on GP20, all retargeted in board.cmake so the SDK defaults cannot mux a trace pin), compile-time trace pin-conflict checks, the measured DBGPAUSE rationale, Ozone project, and skill/docs updates. Trace validated at the stock 150 MHz (75 MHz TRACECLK, +1 ns sampling): zero overflow through a 15 s throughput soak; V2 probe ceiling 120 MHz. 2026-08-21T04:06:14Z hathach thach@tinyusb.org 2026-08-21T04:06:14Z urn:sha1:a57f857f811e054e7a240fc55520648192349c2b vendor_host.c/.h implemented a CFG_TUH_VENDOR class driver that no example, board or test ever enabled: usbh's driver table entry was compiled out everywhere, and the six tusb_config.h files that mentioned the macro all set it to 0. Maintainer call - dead code, not a shrinking of supported classes. Removes the sources, the usbh driver-table entry, the CFG_TUH_VENDOR default in tusb_option.h, the tusb.h include, both build-system source lists, the rp2040 family.cmake entry and the IAR project template rows. 2026-07-28T05:50:28Z Ha Thach thach@tinyusb.org 2026-07-28T05:50:28Z urn:sha1:1d915b6b59cb88f14344521db1f9345d8c7dc9a7 bsp, hil: flash with the unified OpenOCD fork https://github.com/hathach/openocd (branch tinyusb) is mainline plus every config these boards need: RPi RP2350, ADI max32/max78, the MounRiver WCH configs, and the wlinke adapter on mainline's riscv target. It is a superset of the vendor forks, so one 'openocd' covers all boards; -DOPENOCD=/OPENOCD= still select another, msdk's when MAXIM_PATH is set. Drops family_flash_openocd_wch and the OPENOCD_WCH pair, dedups family_flash_openocd_adi, aligns ch583's work area, and points hil at the flasher's own config instead of generating one per probe. Verified: HIL green on all four WCH boards and max32666fthr. 2026-07-24T14:30:42Z hathach thach@tinyusb.org 2026-07-24T14:30:42Z urn:sha1:f08c8211904ac9feb2598aa354b0b7bddc245bfe The board-specific PHY-reset nets move behind a board.h opt-in (TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other boards of those families cannot inherit a foreign GPIO write; the chip-level trace pin muxes stay family-wide by design (same pattern as stm32h7). same70 reference: width 1 is the validated default until the J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so --attach sessions decode ROM execution too. etm_capture rejects an unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB and a runtime switch would desync the stream); etm_profile keeps same-named statics from different modules as distinct rows. Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:53Z urn:sha1:e90d232b7718656a627775e3ecde63c6fc7c2e84 J-Link's built-in RP2350 script owns the whole chip-side path (component map is not ROM-table-discoverable; a custom JLinkScript replaces the built-in one and kills pin trace), re-arming at every resume - firmware does no trace setup. TRACE_ETM builds pin clk_sys to 48 MHz from crt0 (fly-wire seating-proof; the port is DDR at clk_sys/2 and the J-Trace PRO V2 cliff sits just above 40 MHz TRACECLK - SEGGER requires V3.0+ for this chip), clear TIMER0/1 DBGPAUSE (default freezes the us-timer while any core is debug-halted and sleep_ms spins forever), and run the UART console TX-only (GPIO1 = default UART0 RX = TRACECLK).