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<title>tinyusb.git/hw/bsp/stm32g0, branch claude/add-systemview-debug</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp/stm32g0?h=claude%2Fadd-systemview-debug</id>
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<updated>2026-09-03T21:21:57Z</updated>
<entry>
<title>sysview: take the timestamp from a BSP hardware timer where the core has no DWT</title>
<updated>2026-09-03T21:21:57Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-09-03T10:14:28Z</published>
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<id>urn:sha1:5a0d707dd96ae7821d97793b441b86aabb684855</id>
<content type='text'>
Cortex-M0/M0+, the WCH RISC-V parts and MAX3266x have no usable DWT cycle
counter, so their family.c provides SEGGER_SYSVIEW_X_GetTimestamp() from a
free-running hardware timer: a 32-bit general-purpose timer on ST parts
(sysview_stm32_tim2.h), SysTick-extended sources on the M0 families, the
core's SysTick-equivalent on WCH with the documented ordered read of the
split count registers (sysview_wch_timestamp.h), and a TMR on MAX3266x
(sysview_max32_tmr.h).

max32666fthr's DWT implements only watchpoint comparators (DWT_CTRL.NOCYCCNT=1
read live; UG6971 documents no DWT/trace at all), so SystemView's ARMv7-M
default read 0xE0001004 as a frozen 0 and every duration decoded as zero. The
TMR runs at 48 MHz (f_PCLK = f_SYS_CLK/2; Continuous mode, CMP=0xFFFFFFFF,
prescaler 1 - UG6971 15.2 guarantees TMRn_CNT readable while counting); TMR0
by default - present on every MAX32 part, unused by the examples, FreeRTOS
ticks on SysTick - overridable with -DSYSVIEW_MAX32_TMR=n. The family builds
SystemView with SEGGER_SYSVIEW_CORE_OTHER and sets CFG_TUSB_SYSVIEW_TIMESTAMP_BSP,
a tusb_sysview.c opt-in for ARMv7-M parts without CYCCNT where the BSP also
reports the rate via SEGGER_SYSVIEW_X_GetTimestampFreq(); the fixed-1MHz
microsecond contract is unreachable on a powers-of-two-only prescaler.
SEGGER_SYSVIEW_X_GetInterruptId() gains the ICSR.VECTACTIVE read for
CORE_OTHER builds. MAX32650/32690 use different GCR clock-gate names and stay
unported. Measured on the rig: seven host-timed 1.000 s gaps at
1.00044-1.00091 (median +0.05%).

stm32f0 refuses to configure SYSVIEW for stm32f070xb at CMake time: that
variant has no TIM2 at all, and the alternative was an undefined-reference
link error with no hint.

The shared hw/bsp/sysview_*.h join ci_select rule 16's hw/bsp file list
(cross-family build files, compiled only under -DSYSVIEW which no CI leg
enables), mirrored in the spec's rule table, so master's classification
guard resolves them on both axes.
</content>
</entry>
<entry>
<title>ensure board_uart_write return -1 on default</title>
<updated>2026-04-29T20:00:05Z</updated>
<author>
<name>HiFiPhile</name>
<email>admin@hifiphile.com</email>
</author>
<published>2026-04-29T20:00:05Z</published>
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<id>urn:sha1:4722252558d4b2a5d77fff7a59ab9c9e51befe47</id>
<content type='text'>
Signed-off-by: HiFiPhile &lt;admin@hifiphile.com&gt;
</content>
</entry>
<entry>
<title>remove IAR toolchain support from make build system</title>
<updated>2026-04-06T04:17:34Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-03-19T15:23:47Z</published>
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<id>urn:sha1:4c7a9fed96e0a81cc640333c1c82fee54fa4be34</id>
<content type='text'>
IAR is only supported with CMake. Remove all IAR-specific references
from the Make build system including toolchain files, SRC_S_IAR,
LD_FILE_IAR variables, and IAR toolchain detection.

Also fix GET_SECTOR_COUNT truncation in msc_file_explorer and
broken formatting in stm32f7 board_uart_write.

Co-Authored-By: Claude Opus 4.6 (1M context) &lt;noreply@anthropic.com&gt;
</content>
</entry>
<entry>
<title>update stm32 to use better uart id</title>
<updated>2026-04-03T12:38:07Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-04-03T12:38:07Z</published>
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<id>urn:sha1:81efb78d1655dcab31da5e03fd7e22e91491d186</id>
<content type='text'>
</content>
</entry>
<entry>
<title>stm32 add uart hwfifo if supported, otherwise usb tu_fifo_t for receive uart in irq</title>
<updated>2026-04-03T09:33:03Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-04-03T05:51:06Z</published>
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<id>urn:sha1:e82df22375ac22ffddf86234a818bb7f4d66af7c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>replace board_millis() with tusb_time_millis_api()</title>
<updated>2026-02-27T17:01:40Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-02-27T16:51:36Z</published>
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<id>urn:sha1:8444c25ab6bc841bad81fd04afc1e66a9d57a115</id>
<content type='text'>
</content>
</entry>
<entry>
<title>bsp/stm32h5: support host mode</title>
<updated>2025-11-27T21:39:34Z</updated>
<author>
<name>HiFiPhile</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-11-27T21:09:29Z</published>
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<id>urn:sha1:2d3aaaf6e12ba62f73ca31d5d239ac4bbc70fde4</id>
<content type='text'>
Signed-off-by: HiFiPhile &lt;admin@hifiphile.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'tinyusb/master' into hcd_fsdev</title>
<updated>2025-11-26T10:10:34Z</updated>
<author>
<name>Zixun LI</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-11-26T10:10:34Z</published>
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<id>urn:sha1:37df71cae4c37faaffa1f8a6fc236ec763e4ec03</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fsdev: reorganize functions</title>
<updated>2025-11-25T21:45:40Z</updated>
<author>
<name>HiFiPhile</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-11-24T20:03:04Z</published>
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<id>urn:sha1:03bd8c26d6b72b5e53c0d4b9787a6396ee295927</id>
<content type='text'>
Signed-off-by: HiFiPhile &lt;admin@hifiphile.com&gt;
</content>
</entry>
<entry>
<title>bsp: Disable SysTick ISR if FreeRTOS is enabled</title>
<updated>2025-11-25T15:30:32Z</updated>
<author>
<name>Zixun LI</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-11-25T14:54:45Z</published>
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<id>urn:sha1:8221ea220bb523b3d8c6bab915a968477a228a16</id>
<content type='text'>
</content>
</entry>
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