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<title>tinyusb.git/hw/bsp/stm32h7rs/linker, branch codex/class-reference-docs</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp/stm32h7rs/linker?h=codex%2Fclass-reference-docs</id>
<link rel='self' href='http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp/stm32h7rs/linker?h=codex%2Fclass-reference-docs'/>
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<updated>2025-07-07T13:31:49Z</updated>
<entry>
<title>change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1</title>
<updated>2025-07-07T13:31:49Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2025-07-07T05:33:14Z</published>
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<id>urn:sha1:3eb04518796e81e41ff119dc5acf33bf5241fdec</id>
<content type='text'>
use stock iar linker
</content>
</entry>
<entry>
<title>Revise DCache with RTT section</title>
<updated>2025-07-04T10:10:56Z</updated>
<author>
<name>HiFiPhile</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-07-04T10:10:56Z</published>
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<id>urn:sha1:ffab23cf0f9e5422f55311e0b9f95d05e68082a6</id>
<content type='text'>
Signed-off-by: HiFiPhile &lt;admin@hifiphile.com&gt;
</content>
</entry>
<entry>
<title>fix build with clang</title>
<updated>2025-07-03T11:03:19Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2025-07-03T11:03:19Z</published>
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<id>urn:sha1:211c2e380fb5744bef484ad9b59b2579e91d30b4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>hw/h7rs: Update linker to put RTT in DTCM</title>
<updated>2025-06-13T20:49:06Z</updated>
<author>
<name>HiFiPhile</name>
<email>admin@hifiphile.com</email>
</author>
<published>2025-01-31T22:52:01Z</published>
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<id>urn:sha1:424d74373981a75d127889866848bb4aef7a46a6</id>
<content type='text'>
Signed-off-by: HiFiPhile &lt;admin@hifiphile.com&gt;
</content>
</entry>
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