Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/tinyusb.git/atom/hw/bsp?h=cdc_persistent 2026-07-24T14:30:42Z 2026-07-24T14:30:42Z hathach thach@tinyusb.org 2026-07-24T14:30:42Z urn:sha1:f08c8211904ac9feb2598aa354b0b7bddc245bfe The board-specific PHY-reset nets move behind a board.h opt-in (TRACE_ETM_QUIET_ENET_PHY on same70_xplained and mimxrt1170_evkb) so other boards of those families cannot inherit a foreign GPIO write; the chip-level trace pin muxes stay family-wide by design (same pattern as stm32h7). same70 reference: width 1 is the validated default until the J403.16 rework, and the hooks now wait (bounded) for PCKRDY3 before Ozone arms trace. ra8m1 reference caches the boot ROM in AfterTargetConnect so --attach sessions decode ROM execution too. etm_capture rejects an unexpanded CMake JLINK_DEVICE with a clear error; PIO-USB + TRACE_ETM on RP2350 is now a compile error (48 MHz trace clock is too slow for PIO-USB and a runtime switch would desync the stream); etm_profile keeps same-named statics from different modules as distinct rows. Build-verified: same70_xplained, mimxrt1170_evkb, raspberry_pi_pico2. 2026-07-24T11:38:40Z hathach thach@tinyusb.org 2026-07-24T11:38:40Z urn:sha1:e65368ea16975710f029f7ff7e2089b9ea90186d Bot findings (Copilot/Codex): no-op board_trace_pinmux stubs for lpcxpresso18s37/43s67 (TRACE_ETM otherwise broke their build), SAME70 ID_PIOD clock enable, capture-script duplicate BeforeTargetConnect on the RA references, profile-script support for --no-timestamps itraces. Deep review (whole branch): same70_xplained board row + caveat restored, stale pico2 72 MHz claim corrected to the shipped 48, explicit SetTracePortWidth(4) in the three references that relied on Ozone's default, coverage-cell guard, median-based SysTick calibration, dead session flag removed, stale RA8M1 divider comment fixed (0x02 = /4 is the validated chip max) and the debugger guard indented. EVKB bench findings: only R1884/D3 remains open (D1/D2 meter-verified); RT1176 trace width is 1 or 4 only - J-Link arms the CSSYS TPIU and its own sampler at 4-bit for any width>=2 request; a powered MCU-Link USB breaks the external probe even with JP4 shorted. 2026-07-24T09:20:13Z hathach thach@tinyusb.org 2026-07-24T09:20:13Z urn:sha1:d3eaeb06e04519b480637f6e7cb007a3de08d923 Fresh bring-up pass on mimxrt1170_evkb: holding the 100M RTL8201 in reset (ENET_RST_B = GPIO_LPSR_04) stops its RMII lines driving against the shared trace pads and doubles the clean trace-pin rate to 50 MHz (100 MHz CSTRACE root; 133 MHz root is marginal, stock 132 corrupts). Validated 3x 8 s TinyUSB captures at 11.46M fetches. D1-D3 remain silent in every configuration - the welded R1882-R1884 are electrically open; reflow is the remaining step to width 4. Board notes gain JP4 (must be shorted for an external probe on J58). 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:54Z urn:sha1:2a2d5f65ad61dc43d20ff479db9a27510592b50c J403 (bottom-side Cortex Debug+ETM footprint, header required): TRACECLK=PD8 peripheral D, TRACED0-3=PD4-7 peripheral C. TRACE_ETM builds hold the KSZ8081 PHY in reset (PD4-7 are its RMII receive outputs and it drives against the trace stream), clock the TPIU from PCK3 (MCK/2) and mux the pins; the ozone reference starts PCK3 in the post-reset/download hooks - TPIU programming while PCK3 is stopped is silently lost. Width-1 validated at the stock 300 MHz core; width 4 blocked on a dead D1 line (suspect probe channel, h743eval crosscheck pending). 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:53Z urn:sha1:853f7e8f70caf4df9786001e84eca048d2664de7 The populated 20-pin Cortex Debug+ETM header carries 4-bit trace (TRACECLK=PC27, D0-3=PC28/PC26/PC25/PC24, mux H). TRACE_ETM builds mux the pins and enable GCLK channel 47 (GCLK_CM4_TRACE) from GCLK0 - without that gate the port stays silent with pins and TPIU armed. Chip-max 120 MHz core / 60 MHz TRACECLK validated (3x 280M-fetch captures). 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:53Z urn:sha1:e90d232b7718656a627775e3ecde63c6fc7c2e84 J-Link's built-in RP2350 script owns the whole chip-side path (component map is not ROM-table-discoverable; a custom JLinkScript replaces the built-in one and kills pin trace), re-arming at every resume - firmware does no trace setup. TRACE_ETM builds pin clk_sys to 48 MHz from crt0 (fly-wire seating-proof; the port is DDR at clk_sys/2 and the J-Trace PRO V2 cliff sits just above 40 MHz TRACECLK - SEGGER requires V3.0+ for this chip), clear TIMER0/1 DBGPAUSE (default freezes the us-timer while any core is debug-halted and sleep_ms spins forever), and run the UART console TX-only (GPIO1 = default UART0 RX = TRACECLK). 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:53Z urn:sha1:4d9e4c9e3895b0c15a04763028d1becd27bbf89c Generic TRCKCR setup gated on DHCSR.C_DEBUGEN (a standalone-boot TRCKCR write wedges the chip un-attachable until power-cycle), two-step write per the hardware manual. ra6m5_ek: div-4 (25 MHz pin) - div-2 is dead on this board at every width/timing; J9 must be closed. ra8m1_ek: chip-max 120 MHz TRCLK / 60 MHz pin via the committed JLinkScript whose empty OnTraceStart defers the trace clock to firmware (J-Link's from-reset enable steps the clock mid-stream at the FSP MOCO-to-PLL switch); ReadIntoTraceCache covers runtime ROM execution. J9 closed on both EKs - open = SWD contention up to apparent bricks. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:52Z urn:sha1:63bccf47c632fcd6834eaca783c5ab15622d8c47 M55 flashless RAM image: Development boot (JP2/BOOT1=1) REQUIRED - flash boot parks the chip un-attachable. 300 MHz core (TRACE_ETM selects IC1/4; 600 MHz kills the stream in the startup burst), 18.75 MHz TRACECLK (cpu/16) width 4; N6 trace components are ROM-table-discoverable, no J-Link script. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:52Z urn:sha1:93443d3b4686b63e2263758c17e11e66a589d8a5 300 MHz core, 50 MHz TRACECLK, width 2: SB11/SB12 stub TRACED2/3 onto Zio CN8 and kill width 4 under IRQ-heavy USB traffic (removal = width-4 TODO at 600 MHz). Session note: --attach while a host actively polls the device wedges its USB session. 2026-07-24T08:56:14Z hathach thach@tinyusb.org 2026-07-24T08:28:52Z urn:sha1:34dcb9fe523f501d492bf4d7dabfd1bcd1a1c8b3 metro_m7_1011 (custom ETM-header rework): 500 MHz core, 66 MHz TRACECLK width 4, +50 ps; trace_etm_init ungates the 132 MHz trace root that BOARD_BootClockRUN leaves gated. mimxrt1170_evkb: 996 MHz CM7 at width 1, CSTRACE pinned to 50 MHz (stock 132 corrupts - the Ethernet PHY loads the CLK net) and the CM7 platform trace-funnel port enabled in firmware: J-Link does not program that funnel and everything reads register-perfect yet silent without it. FlexSPI boot needs the committed SP/PC hooks; D1-D3 stay dead pending the R1882-R1884 continuity check (width-4 TODO).