tinyusb.git/hw, branch worktree-ch569-hydrausb3

ch32h417: register in CI matrix, lwIP throughput, docs and presets

2026-07-11T22:02:59Z

Final integration for the CH32H417 port. - .github/workflows/ci_set_matrix.py: add ch32h417 (riscv-gcc) so CI builds it. - examples/device/net_lwip_webserver: enable LWIP_HIGH_THROUGHPUT for the H417 (SuperSpeed iperf). - docs/reference/{boards,dependencies}.rst + hw/bsp/BoardPresets.json: regenerated for the new board and dependency. usbtest quirks intentionally left at 0 for the H417: its endpoint engine fixes the two CH569 5 Gbps silicon limitations (RB_EP_TX/RX_HALT gives a repeatable STALL for case 13; the reworked EP0/chain path is expected free of the wLength%4==1 ctrl_out drop), so the H417 targets a full 30/30 at SuperSpeed rather than 27/27. The HIL entry (test/hil/tinyusb.json) is deliberately deferred: it needs the chip's ESIG unique id read from the board on first flash, which is pending hardware access. Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

Add WCH CH32H417 family + nanoCH32H417 board (BSP + USB2 HS dcd)

2026-07-11T21:50:23Z

First stage of the CH32H417/CH32H416 SuperSpeed port (the second WCH SuperSpeed device family after CH569). This lands the family scaffolding and the USB2.0 high-speed device driver; the USB3 dcd is a stub for now (SPEED=super does not link yet). - tools/get_deps.py, src/tusb_option.h (OPT_MCU_CH32H417 2260 + CH32H416 alias): openwch/ch32h417 SDK dependency. - src/common/tusb_mcu.h: OPT_MCU_CH32H417 block with distinct USB IP tokens (TUP_USBIP_WCH_USB30_H417 / _USBHS_H417) so neither the CH569 nor the CH32V307 drivers match; SPEED=super|high selectors mirror the CH569 port; EP0 = 512 on SS. - hw/bsp/ch32h417: family runs entirely on the V3F core (core 0, boot core), single image in the 512 KB shared SRAM (the only SRAM on the bus matrix, USB-DMA reachable). family.c aliases USBSS/USBSS_LINK/USBHS(/TIM12) to one forwarder (the CH569 LTO identical-code-folding hazard applies), SysTick0 tick, USART1 PA9 debug, ESIG unique id. Linker derived from the EVT V3F script. Board nanoCH32H417 (MuseLab): green LED PC2 active-low, WCH-LinkE VCP on USART1. - src/portable/wch/dcd_ch32h417_usbhs.c (+ ch32h417_usbhs_reg.h, dcd_ch32h417.h): USB2.0 HS dcd for the H417 USBHS IP (per-EP INT_ST EP_DIR+EP_ID, SETUP_IS flag, DONE flags, split UEP_TX/RX_EN, NAK/STALL/ACK encoding, manual toggle). Core exposed as ch32h417_usb2_* internals for the upcoming USB3 runtime fallback; no RAMX bounce (all shared SRAM is DMA-capable, unlike CH56x). Build-verified: board_test and cdc_msc SPEED=high link cleanly under the full -Werror set (riscv-none-elf-gcc 13.2). Hardware bring-up pending (see next). Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

Merge branch 'usbtest': Linux kernel usbtest battery support

2026-07-08T05:26:08Z

Brings the usbtest device example (gadget-zero source/sink peer for the kernel's usbtest.ko/testusb), the test/hil/usbtest.py battery runner and the extended vendor class driver (interrupt/isochronous endpoints, alt settings) into the CH569 SuperSpeed branch, enabling the battery to run against both CH56x dcds. Conflict resolution: test/hil/tinyusb.json keeps this branch's hydrausb3_v1 fixture entry and adds the usbtest branch's ch32v307v_r1_1v0 entry. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Reach SuperSpeed-class iperf on CH569 net_lwip_webserver

2026-07-08T01:49:16Z

Measurements with the 9*MSS window showed iperf pinned at 51 Mbit/s with the in-flight data exactly tracking the advertised window: the 120 MHz core's TCP receive path is the bottleneck, not the window or the USB link. Recover the software-checksum cost: inbound IP/UDP/TCP checksum VERIFICATION is skipped on the SuperSpeed build (USB already CRC32 protects every payload; outbound generation stays on). iperf over SuperSpeed improves 51 -> 74.5 Mbit/s (device RX, lwiperf). Also from bringing this up on a marginal SS lane that takes seconds to train (normal lanes train in <100 ms): - CFG_TUD_WCH_USB30_FALLBACK is now overridable from the build line; =0 builds SuperSpeed-only, which retries training indefinitely instead of settling for high speed - the fallback keeps retrying twice as long (4.4 s) when far-end RX terminations were seen: terminations mean an SS-capable partner exists, while a USB2-only host (no terminations) still falls back after ~2 s Validated on HydraUSB3 behind a Renesas uPD720201 hub; 65/65 unit tests, full example sweep, pre-commit clean. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Switch CH569 port to the official openwch/ch569 SDK

2026-07-07T16:08:19Z

Replace the hydrausb3/wch-ch56x-bsp dependency with WCH's official EVT (openwch/ch569 @0424d2968); rename the family hw/bsp/ch56x -> hw/bsp/ch569 to match. Adaptations for the EVT layout and API: - family.cmake/mk: EVT/EXAM/SRC paths (Peripheral/src|inc, RVMSIS, Startup) - CH56xSFR.H case-wrapper (EVT includes the uppercase name, which breaks case-sensitive filesystems) - debug_uart: official UART1_BaudRateCfg + explicit TXD1/RXD1 pin setup (the EVT has no pin-configuring UART init) - family.c: .dmadata (RAMX) zeroing moved into board_init (EVT startup only clears .bss) and a self-contained SPI-ROM reader for the factory unique ID (the EVT flash API is a binary blob, not linked) - dcd_ch56x_usbhs.c: plain volatile casts instead of hydrausb3-only pointer typedefs - -Wno-comment for the EVT's nested header comments Validated: full 19-example CMake sweep + Make build green, 65/65 unit tests, pre-commit clean; on HydraUSB3 hardware cdc_msc_throughput enumerates at SuperSpeed 5000M with MSC 124/110 MB/s read/write (direct-IO dd). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Make ch56x FREQ_SYS overridable from the build command line

2026-07-07T12:06:28Z

Allows -DFREQ_SYS=60000000 (CMake) / FREQ_SYS=60000000 (Make) for bring-up at reduced clock; default stays 120 MHz (required for USB3). USB2 HS was verified working on HydraUSB3 at 60 MHz while diagnosing flash-config-related instruction-fetch instability at 120 MHz. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Add SuperSpeed descriptors to all bulk/interrupt class drivers and examples

2026-07-07T11:12:02Z

Class drivers: skip and account the SS endpoint companion descriptor in every descriptor walk (hid, midi, midi2, ecm_rndis, printer, mtp, usbtmc), via a shared usbd_skip_ss_ep_companion() helper in usbd_pvt.h (cdc/ncm already handled; vendor/dfu naturally tolerant). usbtmc buffer grows to 1024 at SS to satisfy its packet-multiple assert. bth/audio/video are left FS/HS-only (ISO-centric; ISO is unsupported on the CH569 dcd). usbd.h: new SS template macros TUD_HID_SS_DESCRIPTOR(+INOUT), TUD_MIDI_SS_DESCRIPTOR (+ DESC_EP_SS part), TUD_MIDI2_DESC_ALT1_EP_SS, TUD_PRINTER_SS_DESCRIPTOR, TUD_MTP_SS_DESCRIPTOR, TUD_USBTMC_BULK_SS_DESCRIPTORS/INT_SS_DESCRIPTOR, with _SS_DESC_LEN counterparts (bulk endpoints hardcode 1024, companion after every EP). Examples: 17 bulk/interrupt examples gain the full SS descriptor set (EP0 512/64 clamp, SS device descriptor bcdUSB 3.20 mps0=2^9, SS config with companions, BOS caps, speed-switched callbacks): cdc_dual_ports, cdc_msc_freertos, dfu, dfu_runtime, dynamic_configuration, hid_boot_interface, hid_composite(+freertos), hid_generic_inout, hid_multiple_interface, midi_test(+freertos), midi2_device, msc_dual_lun, mtp, printer_to_cdc, usbtmc, webusb_serial. msc_dual_lun is un-skipped for CH569 using read-only flash disks (16KB RAM can't hold two 8KB RAM disks, same as ch32v10x/v20x boards). Validation: full example sweep green for hydrausb3_v1 (SPEED=super, 19 device ELFs) and raspberry_pi_pico; wTotalLength == sizeof() verified for every SS configuration array in the built ELFs; ceedling 65/65; pre-commit clean; code-size delta +0.0% on rp2040 (SS code folds out on non-SS builds). Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Add CH569 runtime USB2 fallback, HIL board entry and docs

2026-07-07T04:35:06Z

- CFG_TUD_WCH_USB30_FALLBACK (on by default for SPEED=super): the USB3 dcd owns both controllers on rhport 0. TMR0 times out SuperSpeed link training (2x 0.5 s: shut USB3 down, then bring USB2 up); an LTSSM disabled event (SS rejected by the port) switches immediately. The active controller is dispatched at each dcd entry point; IRQ pendings are cleared on switch and dcd_int_enable is mode-aware (a stale LINK pending otherwise refires on every usbd queue unlock) - Bounded link busy-waits (LINK_STATUS busy can stick once the link is torn down) - board_get_unique_id from the factory ID in read-only info flash (0x77FE4), so the USB serial identifies the chip (HIL requirement) - HIL: replace ch582m_evt (probe moved) with hydrausb3_v1 - Regenerate boards.rst, dependencies.rst, BoardPresets.json Verified on HydraUSB3 v1 (ci rig): SuperSpeed still trains at 5000M with fallback armed (3x replug); with SS terminations disabled the device falls back and enumerates fully at 480M. Full HIL run passes 10/10 device tests including cdc_msc at SuperSpeed and cdc_msc_throughput (MSC 22.1/14.1 MBps read/write at NUMP=1); non-SuperSpeed-aware examples recover onto USB2 via the fallback. Co-Authored-By: Claude Fable 5

Add CH569 USB3.0 SuperSpeed device driver - TinyUSB's first SuperSpeed port

2026-07-07T04:11:41Z

New dcd_ch56x_usb30.c + ch56x_usb30_reg.h (both MIT, written fresh): - Register model from the hydrausb3 project's reverse engineering (wch-ch56x-lib, Apache-2.0) and TeenyUSB's CH56x port (MIT), with LINK-layer bit names per the officially documented CH32H417 (same IP, CH32H417RM chapter 27); TU_VERIFY_STATIC offset asserts guard the vendor header layout - Software-assisted LTSSM in the LINK interrupt: polling/TXEQ/ready sequencing, LMP PORT_CAPABILITY + PORT_CONFIGURATION exchange, warm and hot reset handling. Link-up (ready after TXEQ) is reported as dcd_event_bus_reset with TUSB_SPEED_SUPER - EP0 with fixed 512-byte mps: SETUP via RX flag bit30, unified status stage via bit29 (SET_ADDRESS applied there), manual IN packet sequence - Data endpoints with per-burst DMA re-arm, partial burst-drain accounting, ERDY flow control and NUMP=1 default (multi-packet burst silicon quirk); RAMX bounce slots from a small pool for transfer buffers outside RAMX; isochronous not supported - Board vector forwarders unified into one handler + symbol aliases: gcc identical-code-folding otherwise rewrites one interrupt handler as a call into another whose mret skips the caller's epilogue, leaking a stack frame per interrupt (found the hard way) - hydrausb3_v1 default SPEED flipped to super; skip net_lwip_webserver (16 KB RAMS, same as other small-RAM parts) Verified on HydraUSB3 v1 hardware (ci rig, USB3 host port): - cdc_msc enumerates at 5000M: bcdUSB 3.20, EP0 mps 2^9, endpoint companion descriptors, BOS with USB2-ext + SuperSpeed capability - CDC echo and MSC FAT12 reads functional at SuperSpeed; 30x sustained read stress and 5x replug/reset cycles all re-enumerate at 5000M - SPEED=high regression: still enumerates at 480M - Full example sweep builds for both controllers Co-Authored-By: Claude Fable 5

Add CH569/CH565 family with HydraUSB3 v1 board and USB2 HS dcd

2026-07-07T03:49:55Z

- OPT_MCU_CH569 (2250) + tusb_mcu.h capability block: USB3 SuperSpeed (USBSS) or USB2 HighSpeed (USBHS) selected at compile time via CFG_TUD_WCH_USBIP_USB30/USBHS, both on rhport 0 - New dcd_ch56x_usbhs.c: CH56x USB2 HS device driver ported from dcd_ch32_usbhs.c (same bit encoding, CH56x-specific register layout: R8_UEPn_MOD enables, different DMA/MAX_LEN/control offsets, 8 EPs). Internals exposed as ch56x_usb2_* (dcd_ch56x.h) for the upcoming USB3 dcd's runtime fallback. USB DMA only reaches RAMX: buffers in the .dmadata section, non-RAMX transfer buffers bounce per-endpoint - hw/bsp/ch56x family (SDK dep hydrausb3/wch-ch56x-bsp, Apache-2.0, no binary blobs) + hydrausb3_v1 board: 120 MHz clock (required for USB3), UART1 PA8/PA7 logging, LED PB22, button PB23, linker script with 16-byte aligned NOLOAD .dmadata section in RAMX - SPEED=high|super build option (default high until the USB3 dcd lands) - CI: add ch56x to riscv-gcc matrix; skip FreeRTOS/audio/video examples (as CH583) and msc_dual_lun (16 KB RAMS, as SAMD11/MKL25) Verified: cdc_msc builds via CMake and Make; full example sweep green; .dmadata lands at 0x20020000 (RAMX) with 16-byte alignment. Co-Authored-By: Claude Fable 5