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<title>tinyusb.git/src/common/tusb_sysview.h, branch claude/add-systemview-debug</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/tinyusb.git/atom/src/common/tusb_sysview.h?h=claude%2Fadd-systemview-debug</id>
<link rel='self' href='http://cgit.235523.xyz/tinyusb.git/atom/src/common/tusb_sysview.h?h=claude%2Fadd-systemview-debug'/>
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<updated>2026-09-03T21:21:57Z</updated>
<entry>
<title>sysview: leveled CFG_TUD/TUH_SYSVIEW instrumentation core</title>
<updated>2026-09-03T21:21:57Z</updated>
<author>
<name>hathach</name>
<email>thach@tinyusb.org</email>
</author>
<published>2026-08-11T10:07:06Z</published>
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<id>urn:sha1:4158178230ec491c7eef03df6bbbd8c46811805c</id>
<content type='text'>
tusb_sysview.{c,h} carry the SystemView glue: the TU_SV_* event/function-name
table (offset TU_SV_EVENT_BASE 512), module registration, the leveled
CFG_TUD_SYSVIEW/CFG_TUH_SYSVIEW gates (1 = ISR only, 2 = +stack call sites,
3 = +class drivers), per-task stack high-water reporting with a cached
snapshot refreshed once per rotation, and the dual-role guard that collapses
double-recording when device and host share one vector.

ISR exit emits RecordExitISRToScheduler() when SCB-&gt;ICSR.PENDSVSET is set at
exit (Cortex-M0/M3+), so FreeRTOS captures don't show a causeless task switch
after every USB ISR; RISC-V keeps the plain exit record.

Unit-tested under ceedling against a fake SEGGER_SYSVIEW.h vendor header.
</content>
</entry>
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