tinyusb.git/src/common, branch worktree-ch569-hydrausb3

Add WCH CH32H417 family + nanoCH32H417 board (BSP + USB2 HS dcd)

2026-07-11T21:50:23Z

First stage of the CH32H417/CH32H416 SuperSpeed port (the second WCH SuperSpeed device family after CH569). This lands the family scaffolding and the USB2.0 high-speed device driver; the USB3 dcd is a stub for now (SPEED=super does not link yet). - tools/get_deps.py, src/tusb_option.h (OPT_MCU_CH32H417 2260 + CH32H416 alias): openwch/ch32h417 SDK dependency. - src/common/tusb_mcu.h: OPT_MCU_CH32H417 block with distinct USB IP tokens (TUP_USBIP_WCH_USB30_H417 / _USBHS_H417) so neither the CH569 nor the CH32V307 drivers match; SPEED=super|high selectors mirror the CH569 port; EP0 = 512 on SS. - hw/bsp/ch32h417: family runs entirely on the V3F core (core 0, boot core), single image in the 512 KB shared SRAM (the only SRAM on the bus matrix, USB-DMA reachable). family.c aliases USBSS/USBSS_LINK/USBHS(/TIM12) to one forwarder (the CH569 LTO identical-code-folding hazard applies), SysTick0 tick, USART1 PA9 debug, ESIG unique id. Linker derived from the EVT V3F script. Board nanoCH32H417 (MuseLab): green LED PC2 active-low, WCH-LinkE VCP on USART1. - src/portable/wch/dcd_ch32h417_usbhs.c (+ ch32h417_usbhs_reg.h, dcd_ch32h417.h): USB2.0 HS dcd for the H417 USBHS IP (per-EP INT_ST EP_DIR+EP_ID, SETUP_IS flag, DONE flags, split UEP_TX/RX_EN, NAK/STALL/ACK encoding, manual toggle). Core exposed as ch32h417_usb2_* internals for the upcoming USB3 runtime fallback; no RAMX bounce (all shared SRAM is DMA-capable, unlike CH56x). Build-verified: board_test and cdc_msc SPEED=high link cleanly under the full -Werror set (riscv-none-elf-gcc 13.2). Hardware bring-up pending (see next). Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

Merge branch 'usbtest': Linux kernel usbtest battery support

2026-07-08T05:26:08Z

Brings the usbtest device example (gadget-zero source/sink peer for the kernel's usbtest.ko/testusb), the test/hil/usbtest.py battery runner and the extended vendor class driver (interrupt/isochronous endpoints, alt settings) into the CH569 SuperSpeed branch, enabling the battery to run against both CH56x dcds. Conflict resolution: test/hil/tinyusb.json keeps this branch's hydrausb3_v1 fixture entry and adds the usbtest branch's ch32v307v_r1_1v0 entry. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_019MRGjBT2NBkCoWwyDT4LaE

Enable 4-packet bursts on CH569 SuperSpeed bulk endpoints

2026-07-07T05:28:45Z

- Default CFG_TUD_WCH_USB30_MAX_BURST to 4 (tusb_mcu.h): matches the link layer's header-packet buffer count (NUM_HP_BUF). Burst 8 fails to configure; the TeenyUSB-reported burst corruption quirk did not reproduce with per-burst DMA re-arm (50x MSC write/read-back and 256KB CDC echo integrity all clean at burst 4) - Bounce slots stay one max packet regardless of burst (bounced transfers cap their burst to the slot; zero-copy uses the full burst) so the RAMX pool no longer scales with burst size - cdc_msc/cdc_msc_throughput SS descriptors advertise bMaxBurst = CFG_TUD_WCH_USB30_MAX_BURST-1 via the CFG_EXAMPLE_SS_BULK_MAXBURST knob (0 for non-WCH SuperSpeed ports) Measured on HydraUSB3 v1 at 5 Gbps (HIL cdc_msc_throughput): MSC read 147 MBps write 127 MBps - about 2x the single-packet figures (raw dd: up to 163 MB/s read at 1M blocks). Co-Authored-By: Claude Fable 5

Add CH569/CH565 family with HydraUSB3 v1 board and USB2 HS dcd

2026-07-07T03:49:55Z

- OPT_MCU_CH569 (2250) + tusb_mcu.h capability block: USB3 SuperSpeed (USBSS) or USB2 HighSpeed (USBHS) selected at compile time via CFG_TUD_WCH_USBIP_USB30/USBHS, both on rhport 0 - New dcd_ch56x_usbhs.c: CH56x USB2 HS device driver ported from dcd_ch32_usbhs.c (same bit encoding, CH56x-specific register layout: R8_UEPn_MOD enables, different DMA/MAX_LEN/control offsets, 8 EPs). Internals exposed as ch56x_usb2_* (dcd_ch56x.h) for the upcoming USB3 dcd's runtime fallback. USB DMA only reaches RAMX: buffers in the .dmadata section, non-RAMX transfer buffers bounce per-endpoint - hw/bsp/ch56x family (SDK dep hydrausb3/wch-ch56x-bsp, Apache-2.0, no binary blobs) + hydrausb3_v1 board: 120 MHz clock (required for USB3), UART1 PA8/PA7 logging, LED PB22, button PB23, linker script with 16-byte aligned NOLOAD .dmadata section in RAMX - SPEED=high|super build option (default high until the USB3 dcd lands) - CI: add ch56x to riscv-gcc matrix; skip FreeRTOS/audio/video examples (as CH583) and msc_dual_lun (16 KB RAMS, as SAMD11/MKL25) Verified: cdc_msc builds via CMake and Make; full example sweep green; .dmadata lands at 0x20020000 (RAMX) with 16-byte alignment. Co-Authored-By: Claude Fable 5

Add core SuperSpeed device support

2026-07-07T02:46:25Z

Groundwork for TinyUSB's first SuperSpeed port (WCH CH569): - TUSB_SPEED_SUPER, OPT_MODE_SUPER_SPEED, TUD_OPT_SUPER_SPEED and TUP_RHPORT_SUPERSPEED capability plumbing - Allow CFG_TUD_ENDPOINT0_SIZE 512 on SS builds; EP0 control transfers chunk at the runtime link speed (512 at SS, 64 on USB2 fallback) - Handle SET_SEL, SET_ISOCH_DELAY and U1/U2_ENABLE feature requests - Tolerate SS endpoint companion descriptors in usbd_open_edpt_pair, cdcd_open and mscd_open interface parsing - SS descriptor types/structs and template macros: endpoint companion, BOS USB2-extension + SuperSpeed capability, SS config and CDC/MSC/vendor SS variants (bulk fixed at 1024) - cdc_msc example: SS device/config/BOS descriptors, speed-aware sizes - Unit tests: SS endpoint validation, companion-tolerant endpoint pair open, SET_SEL, SET_ISOCH_DELAY All SS paths compile out when disabled: verified 0-byte code-size delta on stm32f407disco (MinSizeRel) vs master; 65/65 unit tests pass. Co-Authored-By: Claude Fable 5

Merge remote-tracking branch 'origin/master' into usbtest

2026-07-06T09:17:17Z

# Conflicts: # lib/rt-thread/port/msc_device_port.c # src/device/usbd.c

dcd: implement iso alloc/activate for rusb2, ip3511, nrf5x; deprecate CLOSE_API for them

2026-07-03T10:14:20Z

Migrate the ip3511, rusb2 and nrf5x DCDs off the deprecated TUP_DCD_EDPT_CLOSE_API path onto the unified ISO_ALLOC model by implementing dcd_edpt_iso_alloc/activate (previously #if0 stubs / returning false): - rusb2: iso_alloc reserves an ISO-capable pipe (1/2) once and configures it; iso_activate re-arms it in place (PIPEMAXP + SQCLR + PID_BUF) with no pipe free/realloc, avoiding PIPESEL/PIPECFG churn across altsetting changes. - ip3511: iso_alloc reserves the EP command/status entry (type=ISO, INTEN); iso_activate clears stall + resets the data toggle. - nrf5x: iso_alloc validates the fixed EP8; iso_activate enables ISOOUT/ISOIN (with ISOSPLIT when both directions are active) + SOF, mirroring dcd_edpt_open. tusb_mcu.h no longer defines CLOSE_API for these three (they fall through to ISO_ALLOC); dcd_edpt_close is now declared unconditionally in dcd.h since these drivers still use it internally from dcd_edpt_close_all(). The remaining CLOSE_API MCUs (mm32, pic, da1469x, f1c100s, ch32-usbhs) are left for a later per-board pass. Verified on hardware: ip3511 (lpcxpresso11u37) 29/30 and nrf5x (feather_nrf52840) iso 11/11 via the new path (identical to their prior CLOSE_API results); dwc2, fsdev, rp2040 + audio/video still build. rusb2 (ra4m1) has a separate, iso-independent set_interface wedge (still 1/30) tracked for follow-up. Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_01HeF2gZ1M7GWkz6Av4BpKPg

license: use SPDX identifiers for src/ headers (#3749)

2026-07-02T14:55:45Z

* license: use SPDX identifiers for src/ headers Replace the full ~20-line MIT license boilerplate on every src/ file with a two-line SPDX tag (SPDX-FileCopyrightText + SPDX-License-Identifier), following the REUSE convention used by CircuitPython and the Linux kernel. Removes ~3500 lines of duplicated boilerplate.

typec: add stm32u5 support

2026-06-24T19:13:27Z

Signed-off-by: HiFiPhile

hw/bsp+wch: rename the CH58x family to ch583 and OPT_MCU_CH58X to OPT_MCU_CH583

2026-06-22T08:23:08Z

The BSP family and MCU option were named "ch58x"/"CH58X", but the supported part is the CH583/CH582 (and the SDK repo is openwch/ch583); CH585 is a separate MCU family, so the CH58x umbrella was misleading. Rename to the specific family: - hw/bsp/ch58x -> hw/bsp/ch583 (dir), and the BSP-local files ch58x_it.* -> ch583_it.*, system_ch58x.* -> system_ch583.* (include guards/refs updated). The vendor SDK files (CH58x_common.h, CH58x_*.c in hw/mcu/wch/ch583) keep their names. - OPT_MCU_CH58X -> OPT_MCU_CH583 in tusb_option.h, tusb_mcu.h, and the shared WCH USBFS driver (ch32_usbfs_reg.h, dcd_ch32_usbfs.c). OPT_MCU_CH582 is kept as an alias (same value), so either name selects the same code. - FAMILY_MCUS CH58X -> CH583, CFG_TUSB_MCU=OPT_MCU_CH583, mcu:CH58X -> mcu:CH583 in the example skip lists, the CI build matrix (ci_set_matrix.py), the get_deps family tag, and docs/reference/boards.rst. Board names (ch582m_evt, yd-ch582m) are unchanged. Verified: make + cmake build for ch582m_evt, and ci.lan HIL (all device examples pass). Co-Authored-By: Claude Opus 4.8 (1M context)