tinyusb.git/src/portable/synopsys/dwc2/dcd_dwc2.c, branch xfer_isr_fallback

dwc2: cleanup setup_packet pointer cast (review feedback)

2026-06-04T13:46:49Z

Cast DOEPDMA0 through uintptr_t and use sizeof(tusb_control_request_t) instead of the magic constant 8, matching project convention. Add a reference to Programming Guide v4.20a 9.1.2.1 for the DOEPDMAn-8 rule. Addresses Copilot review comment; no functional change. Co-Authored-By: Claude Opus 4.8 (1M context)

Update setup buffer size definition based on DMA configuration

2026-06-04T10:55:44Z

Merge branch 'master' into dwc2_postfix

2026-06-04T08:31:45Z

dwc2: address Copilot review (comment grammar/typo, tinyusb.json f407 dedup)

2026-06-03T16:41:19Z

Co-Authored-By: Claude Opus 4.8 (1M context)

dwc2: remove investigation debug logging

2026-06-03T16:18:28Z

Co-Authored-By: Claude Opus 4.8 (1M context)

dwc2: submit setup packet on SETUP_DONE and drop spurious EP0 RX_COMPLETE on core v3.10a (STM32L476)

2026-06-03T14:44:19Z

DWC2 core rev 3.10a pushes an extra EP0 RX_COMPLETE (RXFLVL PKTSTS 0x3) that is not a real OUT data completion, in two cases flagged on DOEPINT: - STPKTRX (Setup Packet Received): between SETUP_RX and SETUP_DONE - STSPHSRX (Status Phase Received, control write): after the OUT data stage when the host starts the IN status phase

dcd/dwc2: fix back-to-back SETUP reception in DMA mode

2026-06-02T20:59:45Z

Signed-off-by: HiFiPhile

dwc2: process IN EP before OUT

2026-05-29T09:42:47Z

To avoid STATUS IN completion of previous control transfer treated as next DATA IN when IRQ latency is high. Signed-off-by: HiFiPhile

dwc2: move OUT transfer management into RXFLVL IRQ

2026-05-28T22:05:44Z

- GRXSTSP register has internal FIFO, receiving events won't mix up (STATUS OUT & next SETUP) - Improve efficiency, remove 2nd IRQ overhead Signed-off-by: HiFiPhile

dwc2: fix EP0 DMA setup race condition

2026-05-26T22:35:25Z

Signed-off-by: HiFiPhile