tinyusb.git/src/tusb_option.h, branch worktree-ch569-hydrausb3

Add WCH CH32H417 family + nanoCH32H417 board (BSP + USB2 HS dcd)

2026-07-11T21:50:23Z

First stage of the CH32H417/CH32H416 SuperSpeed port (the second WCH SuperSpeed device family after CH569). This lands the family scaffolding and the USB2.0 high-speed device driver; the USB3 dcd is a stub for now (SPEED=super does not link yet). - tools/get_deps.py, src/tusb_option.h (OPT_MCU_CH32H417 2260 + CH32H416 alias): openwch/ch32h417 SDK dependency. - src/common/tusb_mcu.h: OPT_MCU_CH32H417 block with distinct USB IP tokens (TUP_USBIP_WCH_USB30_H417 / _USBHS_H417) so neither the CH569 nor the CH32V307 drivers match; SPEED=super|high selectors mirror the CH569 port; EP0 = 512 on SS. - hw/bsp/ch32h417: family runs entirely on the V3F core (core 0, boot core), single image in the 512 KB shared SRAM (the only SRAM on the bus matrix, USB-DMA reachable). family.c aliases USBSS/USBSS_LINK/USBHS(/TIM12) to one forwarder (the CH569 LTO identical-code-folding hazard applies), SysTick0 tick, USART1 PA9 debug, ESIG unique id. Linker derived from the EVT V3F script. Board nanoCH32H417 (MuseLab): green LED PC2 active-low, WCH-LinkE VCP on USART1. - src/portable/wch/dcd_ch32h417_usbhs.c (+ ch32h417_usbhs_reg.h, dcd_ch32h417.h): USB2.0 HS dcd for the H417 USBHS IP (per-EP INT_ST EP_DIR+EP_ID, SETUP_IS flag, DONE flags, split UEP_TX/RX_EN, NAK/STALL/ACK encoding, manual toggle). Core exposed as ch32h417_usb2_* internals for the upcoming USB3 runtime fallback; no RAMX bounce (all shared SRAM is DMA-capable, unlike CH56x). Build-verified: board_test and cdc_msc SPEED=high link cleanly under the full -Werror set (riscv-none-elf-gcc 13.2). Hardware bring-up pending (see next). Co-Authored-By: Claude Opus 4.8 (1M context) Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm

Add CH569/CH565 family with HydraUSB3 v1 board and USB2 HS dcd

2026-07-07T03:49:55Z

- OPT_MCU_CH569 (2250) + tusb_mcu.h capability block: USB3 SuperSpeed (USBSS) or USB2 HighSpeed (USBHS) selected at compile time via CFG_TUD_WCH_USBIP_USB30/USBHS, both on rhport 0 - New dcd_ch56x_usbhs.c: CH56x USB2 HS device driver ported from dcd_ch32_usbhs.c (same bit encoding, CH56x-specific register layout: R8_UEPn_MOD enables, different DMA/MAX_LEN/control offsets, 8 EPs). Internals exposed as ch56x_usb2_* (dcd_ch56x.h) for the upcoming USB3 dcd's runtime fallback. USB DMA only reaches RAMX: buffers in the .dmadata section, non-RAMX transfer buffers bounce per-endpoint - hw/bsp/ch56x family (SDK dep hydrausb3/wch-ch56x-bsp, Apache-2.0, no binary blobs) + hydrausb3_v1 board: 120 MHz clock (required for USB3), UART1 PA8/PA7 logging, LED PB22, button PB23, linker script with 16-byte aligned NOLOAD .dmadata section in RAMX - SPEED=high|super build option (default high until the USB3 dcd lands) - CI: add ch56x to riscv-gcc matrix; skip FreeRTOS/audio/video examples (as CH583) and msc_dual_lun (16 KB RAMS, as SAMD11/MKL25) Verified: cdc_msc builds via CMake and Make; full example sweep green; .dmadata lands at 0x20020000 (RAMX) with 16-byte alignment. Co-Authored-By: Claude Fable 5

Add core SuperSpeed device support

2026-07-07T02:46:25Z

Groundwork for TinyUSB's first SuperSpeed port (WCH CH569): - TUSB_SPEED_SUPER, OPT_MODE_SUPER_SPEED, TUD_OPT_SUPER_SPEED and TUP_RHPORT_SUPERSPEED capability plumbing - Allow CFG_TUD_ENDPOINT0_SIZE 512 on SS builds; EP0 control transfers chunk at the runtime link speed (512 at SS, 64 on USB2 fallback) - Handle SET_SEL, SET_ISOCH_DELAY and U1/U2_ENABLE feature requests - Tolerate SS endpoint companion descriptors in usbd_open_edpt_pair, cdcd_open and mscd_open interface parsing - SS descriptor types/structs and template macros: endpoint companion, BOS USB2-extension + SuperSpeed capability, SS config and CDC/MSC/vendor SS variants (bulk fixed at 1024) - cdc_msc example: SS device/config/BOS descriptors, speed-aware sizes - Unit tests: SS endpoint validation, companion-tolerant endpoint pair open, SET_SEL, SET_ISOCH_DELAY All SS paths compile out when disabled: verified 0-byte code-size delta on stm32f407disco (MinSizeRel) vs master; 65/65 unit tests pass. Co-Authored-By: Claude Fable 5

license: use SPDX identifiers for src/ headers (#3749)

2026-07-02T14:55:45Z

* license: use SPDX identifiers for src/ headers Replace the full ~20-line MIT license boilerplate on every src/ file with a two-line SPDX tag (SPDX-FileCopyrightText + SPDX-License-Identifier), following the REUSE convention used by CircuitPython and the Linux kernel. Removes ~3500 lines of duplicated boilerplate.

Bump version to 0.21.0; rework changelog, contributors, and docs

2026-06-29T16:38:01Z

Release: - Bump version to 0.21.0 and regenerate tusb_option.h, library.json, repository.yml, sonar-project.properties, boards.rst, dependencies.rst - Add 0.21.0 release notes and split the changelog into per-release files under docs/info/changelog/ (date out of title, driver/class groups as sub-headings, DCD & HCD section after Device/Host stacks) Contributors: - Credit each release's PR authors in a Contributors section - Drop the curated contributors page; add MAINTAINERS.rst Docs: - Update Code of Conduct to Contributor Covenant 3.0 (keep it in the repo, remove it from the built docs) - Sidebar: add a home entry, rename the group to "Documentation", move Changelog into it, add a GitHub Sponsor button, merge external links, rename FAQ; hide the inline toctree on the landing page - Add the make-release skill and update the AGENTS.md release process Co-Authored-By: Claude Opus 4.8 (1M context)

tusb_option: dedupe OPT_MCU_CH583 / make OPT_MCU_CH582 a token alias

2026-06-22T08:28:00Z

The CH58x->CH583 rename left OPT_MCU_CH583 defined twice at 2240 plus a second literal 2240 for OPT_MCU_CH582 -- a duplicate public MCU option macro (redefinition). Collapse to a single canonical OPT_MCU_CH583 and define OPT_MCU_CH582 as a token alias of it (matching the OPT_MCU_SAML21/MIMXRT10XX alias style), so there is one value and CH582 still selects the CH583 code path. Found by Codex review. Co-Authored-By: Claude Opus 4.8 (1M context)

hw/bsp+wch: rename the CH58x family to ch583 and OPT_MCU_CH58X to OPT_MCU_CH583

2026-06-22T08:23:08Z

The BSP family and MCU option were named "ch58x"/"CH58X", but the supported part is the CH583/CH582 (and the SDK repo is openwch/ch583); CH585 is a separate MCU family, so the CH58x umbrella was misleading. Rename to the specific family: - hw/bsp/ch58x -> hw/bsp/ch583 (dir), and the BSP-local files ch58x_it.* -> ch583_it.*, system_ch58x.* -> system_ch583.* (include guards/refs updated). The vendor SDK files (CH58x_common.h, CH58x_*.c in hw/mcu/wch/ch583) keep their names. - OPT_MCU_CH58X -> OPT_MCU_CH583 in tusb_option.h, tusb_mcu.h, and the shared WCH USBFS driver (ch32_usbfs_reg.h, dcd_ch32_usbfs.c). OPT_MCU_CH582 is kept as an alias (same value), so either name selects the same code. - FAMILY_MCUS CH58X -> CH583, CFG_TUSB_MCU=OPT_MCU_CH583, mcu:CH58X -> mcu:CH583 in the example skip lists, the CI build matrix (ci_set_matrix.py), the get_deps family tag, and docs/reference/boards.rst. Board names (ch582m_evt, yd-ch582m) are unchanged. Verified: make + cmake build for ch582m_evt, and ci.lan HIL (all device examples pass). Co-Authored-By: Claude Opus 4.8 (1M context)

Merge remote-tracking branch 'origin/master' into add-ch58x-usbfs

2026-06-18T08:31:03Z

Merge remote-tracking branch 'origin/master' into stm32c5

2026-06-11T10:20:15Z

# Conflicts: # README.rst

abstract OS logic with `CFG_TUSB_OS_HAS_SCHEDULER` to simplify conditional checks

2026-05-28T11:23:46Z