Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/tinyusb.git/atom/src?h=claude%2Fadd-systemview-debug 2026-09-03T21:21:57Z 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-09-03T10:14:28Z urn:sha1:5a0d707dd96ae7821d97793b441b86aabb684855 Cortex-M0/M0+, the WCH RISC-V parts and MAX3266x have no usable DWT cycle counter, so their family.c provides SEGGER_SYSVIEW_X_GetTimestamp() from a free-running hardware timer: a 32-bit general-purpose timer on ST parts (sysview_stm32_tim2.h), SysTick-extended sources on the M0 families, the core's SysTick-equivalent on WCH with the documented ordered read of the split count registers (sysview_wch_timestamp.h), and a TMR on MAX3266x (sysview_max32_tmr.h). max32666fthr's DWT implements only watchpoint comparators (DWT_CTRL.NOCYCCNT=1 read live; UG6971 documents no DWT/trace at all), so SystemView's ARMv7-M default read 0xE0001004 as a frozen 0 and every duration decoded as zero. The TMR runs at 48 MHz (f_PCLK = f_SYS_CLK/2; Continuous mode, CMP=0xFFFFFFFF, prescaler 1 - UG6971 15.2 guarantees TMRn_CNT readable while counting); TMR0 by default - present on every MAX32 part, unused by the examples, FreeRTOS ticks on SysTick - overridable with -DSYSVIEW_MAX32_TMR=n. The family builds SystemView with SEGGER_SYSVIEW_CORE_OTHER and sets CFG_TUSB_SYSVIEW_TIMESTAMP_BSP, a tusb_sysview.c opt-in for ARMv7-M parts without CYCCNT where the BSP also reports the rate via SEGGER_SYSVIEW_X_GetTimestampFreq(); the fixed-1MHz microsecond contract is unreachable on a powers-of-two-only prescaler. SEGGER_SYSVIEW_X_GetInterruptId() gains the ICSR.VECTACTIVE read for CORE_OTHER builds. MAX32650/32690 use different GCR clock-gate names and stay unported. Measured on the rig: seven host-timed 1.000 s gaps at 1.00044-1.00091 (median +0.05%). stm32f0 refuses to configure SYSVIEW for stm32f070xb at CMake time: that variant has no TIM2 at all, and the alternative was an undefined-reference link error with no hint. The shared hw/bsp/sysview_*.h join ci_select rule 16's hw/bsp file list (cross-family build files, compiled only under -DSYSVIEW which no CI leg enables), mirrored in the spec's rule table, so master's classification guard resolves them on both axes. 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-08-11T10:07:23Z urn:sha1:3baa7c8fbafd2cbccc5810626ebbfaa50c0ea4da Level 2 marks the stack's task-side entry points (tud_task/tuh_task inner loop, usbd_edpt_xfer, control transfers); level 3 adds the class drivers (cdc, msc) and the rp2040 dcd/hcd as the reference portable layer. All call sites compile away below their level. 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-08-11T10:07:23Z urn:sha1:4161a1cf63c5ca935766d27bd32f7dd3948e881a tusb_int_handler() brackets the whole USB interrupt with SystemView ISR enter/exit records, honouring its in_isr argument so a handler deferred to task context is not recorded as an interrupt. usbd.h/usbh.h expose the level-1 hooks the handler needs. 2026-09-03T21:21:57Z hathach thach@tinyusb.org 2026-08-11T10:07:06Z urn:sha1:4158178230ec491c7eef03df6bbbd8c46811805c tusb_sysview.{c,h} carry the SystemView glue: the TU_SV_* event/function-name table (offset TU_SV_EVENT_BASE 512), module registration, the leveled CFG_TUD_SYSVIEW/CFG_TUH_SYSVIEW gates (1 = ISR only, 2 = +stack call sites, 3 = +class drivers), per-task stack high-water reporting with a cached snapshot refreshed once per rotation, and the dual-role guard that collapses double-recording when device and host share one vector. ISR exit emits RecordExitISRToScheduler() when SCB->ICSR.PENDSVSET is set at exit (Cortex-M0/M3+), so FreeRTOS captures don't show a causeless task switch after every USB ISR; RISC-V keeps the plain exit record. Unit-tested under ceedling against a fake SEGGER_SYSVIEW.h vendor header. 2026-09-03T13:17:07Z Zixun LI admin@hifiphile.com 2026-09-03T13:17:07Z urn:sha1:1adfb1c74ff3cc6618a9b37e76ab2feadc09f8e8 device/dfu: fix transfer buffer overwrite issue 2026-09-03T13:16:37Z Zixun LI admin@hifiphile.com 2026-09-03T13:16:37Z urn:sha1:67dedc37ef9f0c232cba1edbb6bc007f610961f0 device/cdc: avoid flushing tx buffer on connection 2026-09-02T14:18:44Z HiFiPHile admin@hifiphile.com 2026-09-02T14:18:44Z urn:sha1:e461c6f9c139a0012ef01d53db1aab1c68789b56 HFNUM retains only 16384 host-frame positions, while valid periodic endpoint intervals can be longer. Resubmission after the counter wraps can therefore alias the elapsed time and skip the next established service phase. Cap the host-selected interval to one HFNUM cycle using the root-port frame unit. USB permits a shorter host-provided period, and the bounded interval keeps phase calculation unambiguous for native and split endpoints. 2026-09-02T14:14:26Z HiFiPHile admin@hifiphile.com 2026-09-02T01:54:17Z urn:sha1:14060950b487f931d959699c42b0875c96ca6a01 Periodic DMA channels use their natural service-boundary halt instead of a software CHDIS request. Keep the endpoint busy after an abort so a replacement transfer cannot reuse its state or buffer while the channel remains active. When HCINT.HALTED arrives, release the channel without reporting completion for the aborted transfer. If endpoint closure is also pending, release the endpoint from the same halt path. 2026-09-02T13:21:41Z HiFiPHile admin@hifiphile.com 2026-09-01T15:44:58Z urn:sha1:51761d2dfdf2036395b0b6ada6fdde213f97416f 2026-09-02T13:21:41Z HiFiPHile admin@hifiphile.com 2026-09-01T15:24:13Z urn:sha1:a52b5a0c25d2cfea286d67eb3d9d8891a9b69e8f A disconnect can close endpoint zero after an enumeration control stage completes but before USBH submits the next stage or request. HCD submission then legitimately returns false; treating that result as an invariant violation asserts during rapid replug and can leave enumeration unfinished. Complete an in-progress control request as failed when its DATA or status stage cannot be submitted. Propagate submission failures from every asynchronous enumeration continuation and finish enumeration through the normal failure cleanup path. This keeps controller teardown races out of assertions without fabricating a successful transfer. Validated by interrupting enumeration during rapid STM32U5A5 replug tests with DWC2 DMA and slave modes.