tinyusb.git/src, branch hil-add-ea4088qs

ohci: enumerate a device that was already attached at init

2026-09-03T21:03:39Z

hcd_init() clears every pending interrupt flag before enabling its own set: OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; If a device is already connected at that point, that write drops the RHSC which went with the connect, while the root hub keeps ConnectStatusChange set. The device stays put, so no new edge follows and the attach is never reported - the port sits at CCS=1, CSC=1, PES=0 forever. Host-only builds got away with it because the connect is usually detected after that clear. In a dual build the device stack initialises first and enables the shared USB interrupt, which moves the detection into the window that gets cleared, and the host then never sees the device. Scan the root-hub ports once at the end of hcd_init and raise the attach ourselves, clearing the stale change bit so the next RHSC does not report the same device again. Verified on ea4088_quickstart: dual/host_info_to_device_cdc now enumerates on a plain reset (HIL test passes, "Device 1: ID 1a86:8010 SN 7FD88F0604B5"), host/device_info still enumerates, and device/cdc_msc is unaffected. host/device_info also builds for lpcxpresso55s69, lpcxpresso1769 and mcb1800.

Merge pull request #3799 from hathach/codex/dfu-buffer-fix

2026-09-03T13:17:07Z

device/dfu: fix transfer buffer overwrite issue

Merge pull request #3808 from hathach/cdc_persistent

2026-09-03T13:16:37Z

device/cdc: avoid flushing tx buffer on connection

fix(dwc2): bound periodic intervals to HFNUM range

2026-09-02T14:18:44Z

HFNUM retains only 16384 host-frame positions, while valid periodic endpoint intervals can be longer. Resubmission after the counter wraps can therefore alias the elapsed time and skip the next established service phase. Cap the host-selected interval to one HFNUM cycle using the root-port frame unit. USB permits a shorter host-provided period, and the bounded interval keeps phase calculation unambiguous for native and split endpoints.

fix(dwc2): defer periodic DMA abort cleanup until halt

2026-09-02T14:14:26Z

Periodic DMA channels use their natural service-boundary halt instead of a software CHDIS request. Keep the endpoint busy after an abort so a replacement transfer cannot reuse its state or buffer while the channel remains active. When HCINT.HALTED arrives, release the channel without reporting completion for the aborted transfer. If endpoint closure is also pending, release the endpoint from the same halt path.

Merge remote-tracking branch 'origin/master' into agent/fix-dwc2-host-fifo-allocation

2026-09-02T13:21:41Z

USBH: fail enumeration cleanly after disconnect

2026-09-02T13:21:41Z

A disconnect can close endpoint zero after an enumeration control stage completes but before USBH submits the next stage or request. HCD submission then legitimately returns false; treating that result as an invariant violation asserts during rapid replug and can leave enumeration unfinished. Complete an in-progress control request as failed when its DATA or status stage cannot be submitted. Propagate submission failures from every asynchronous enumeration continuation and finish enumeration through the normal failure cleanup path. This keeps controller teardown races out of assertions without fabricating a successful transfer. Validated by interrupting enumeration during rapid STM32U5A5 replug tests with DWC2 DMA and slave modes.

DWC2 host: clean up channels on disconnect

2026-09-02T13:21:41Z

A root-port disconnect invalidates every active transfer. Retire channel and FIFO interrupt sources plus host-channel state in the disconnect ISR using the Linux DWC2 cleanup model instead of reinitializing the core and PHY, which can sleep on STM32 HS PHYs. Flush posted slave requests, request halts for enabled channels, clear channel interrupt and software ownership, and keep endpoint records closing until USBH processes the remove event. Reject transfer submissions to closing endpoints, preserve fast-replug notification, and re-enable the global host-channel interrupt when a new channel is initialized.

fix(dwc2): queue initial slave OUT packet immediately

2026-09-02T13:21:41Z

In slave mode, channel_xfer_start() enabled an OUT channel but left every FIFO write to a later PTXFEMP interrupt. DWC2 creates the request-queue entry only when the packet's final FIFO word is written, so unrelated interrupt work could consume the selected service frame before the transfer was actually queued. Factor FIFO writes into a capacity-checked helper and write the initial packet while the channel-enable operation is still protected from DWC2 interrupts. Keep FIFO-empty interrupts only for data that does not fit immediately. The protected section never waits for FIFO or request-queue space. When initial periodic OUT submission is too close to the frame boundary, release the unused channel and defer the still-pending endpoint to the next SOF. Internal retries bypass this initial boundary guard. A hardware trace showed HCCHAR enabled for frame 0x0378 while the packet's final FIFO word was delayed until frame 0x03ae. The complete five-commit fix set passed 600 seconds in every O0/O2 and slave/DMA mode. Signed-off-by: HiFiPHile

fix(dwc2): enable periodic channels in the selected frame

2026-09-02T08:50:03Z

Periodic IN and DMA-backed transfers selected ODDFRM before waiting for request-queue space. A DWC2 interrupt could also run between reading HFNUM and writing HCCHAR.CHENA, allowing the selected frame to pass while the transfer still appeared active. Wait for request-queue capacity with controller interrupts enabled, then mask only GAHBCFG.GINT while sampling HFNUM and enabling a new periodic channel. Record the periodic phase from that same HFNUM sample so a boundary after channel enable cannot shift later interval calculations. The bounded critical section contains no queue wait, callback, disable, or allocation loop. Retries that already selected their frame bypass the new selection step. Also clear a retained HCCHAR.CHDIS before every channel enable. A halted channel can otherwise be re-enabled as CHENA|CHDIS and wait for a terminal interrupt that never arrives. Hardware traces captured periodic IN selections at frames 0x3303 and 0x3266 but activation only after 0x330c and 0x3273, respectively.