tinyusb.git/test, branch xfer_isr_fallback

Merge remote-tracking branch 'origin/master' into add-ch58x-usbfs

2026-06-22T08:36:37Z

hw/bsp/ch58x: address review feedback and read the real chip unique id

2026-06-20T16:06:07Z

Fold in the CH58x BSP review fixes: - family.mk: drop stray trailing backslashes on the last LDFLAGS/SRC_C entries (harmless -- GNU Make ends the list at the blank line -- but misleading). - debug_uart.c: uart_write() spun on a full ring buffer with nothing to drain it (only uart_sync() advances tx_consume), so a burst larger than the buffer deadlocked. Drain the FIFO while waiting, like uart_sync() does. - wch-riscv.cfg: move the OpenOCD work area from 0x80000000 (unmapped) to the 0x20000000 SRAM, sized to 32 KB, matching ch32v20x/wch-riscv.cfg. - family.c: implement board_get_unique_id() from the factory MAC. CH58x is a BLE part, so a unique 6-byte MAC lives in FlashROM at ROM_CFG_MAC_ADDR; GetMACAddress() reads it via FLASH_EEPROM_CMD (in libISP583.a), so no extra source file is needed. The read buffer is TU_ATTR_ALIGNED(4) and 8 bytes, per the SDK's documented 4-byte-aligned, word-granular buffer contract (CH58x_flash.c). - test/hil/tinyusb.json: key ch582m_evt off this board's actual MAC (D443627B5450) instead of the fixed placeholder, like every other board. Verified on ci.lan HIL: ch582m_evt enumerates with serial D443627B5450 and all device examples pass. Co-Authored-By: Claude Opus 4.8 (1M context)

test/hil: add ch582m_evt to CI HIL pool

2026-06-19T14:37:34Z

Add the device-only CH582M-EVT (WCH USBFS via the shared dcd_ch32_usbfs.c), riscv-gcc, flashed by openocd_wch probe 7FD88F0604B5, to tinyusb.json. Also reorder device_tests to keep examples sharing a VID:PID non-adjacent: cdc_msc and cdc_msc_throughput both use cafe:4003, and on boards whose CPU-reset does not drop D+ (e.g. WCH CH58x via openocd) back-to-back same-PID firmware leaves the host on the previous example's cached descriptors, so the new example's CDC never enumerates and the test fails. Moving dfu (cafe:4000) between them changes the PID and forces the host to re-enumerate. Remote HIL on ci.lan: all device examples pass, including cdc_msc_throughput (no skip needed). Co-Authored-By: Claude Opus 4.8 (1M context)

test/hil: fix esp32 audio_test_freertos (FreeRTOS tick), skip metro_m4

2026-06-18T12:36:00Z

Enabling the audio test fleet-wide surfaced failures on esp32-p4/s3 and metro_m4_express: the UAC mic enumerates but arecord fails the iso IN read with EIO, while 18 other boards pass strict=1.000. esp32: root cause is the FreeRTOS tick rate. ESP-IDF defaults CONFIG_FREERTOS_HZ to 100, so the audio task wakes only every 10 ms and can't service the 1 ms UAC iso frames -> underrun -> arecord EIO. (The same dwc2 driver passes on STM32, whose FreeRTOSConfig is 1000 Hz.) Set CONFIG_FREERTOS_HZ=1000 in the example sdkconfig.defaults; the example defaults are honored in the generated sdkconfig alongside the BSP's, so this takes effect. metro_m4_express (samd51): not tick-rate -- its FreeRTOSConfig is already 1000 Hz like the passing boards -- so it's a separate iso-IN issue, skipped for now. Co-Authored-By: Claude Opus 4.8 (1M context)

test/hil: fail audio test on missing alsa-utils instead of skipping

2026-06-18T10:15:50Z

arecord (alsa-utils) is a documented HIL host requirement, like mtools/libmtp9/iperf — none of which have a skip-if-missing guard. The audio test was the exception: it silently returned 'skipped' when arecord was absent, masking host misconfiguration. The ci.lan rig had been silently skipping device/audio_test_freertos on every board because alsa-utils was never installed. Remove the shutil.which('arecord') guard so a missing package surfaces as a failure, consistent with the other tool-dependent tests, and drop the now-unused shutil import. Note in the host-setup comment that these packages are required (a missing tool fails its test rather than skipping). Co-Authored-By: Claude Opus 4.8 (1M context)

test/hil: add ch32v103r_r1_1v0 to CI HIL pool

2026-06-18T04:10:29Z

Now that CH32V103 USB device works, add the board to the active HIL pool. It is a WCH RISC-V USBFS part, so it builds under the riscv-gcc bucket; single config (USBFS only, no fsdev variant). cdc_msc_throughput is skipped for this board: its device->host CDC bulk-IN read hard-fails here (a known, pre-existing dcd_ch32_usbfs throughput limitation, not specific to CH32V103). All other device tests pass on ci.lan (verified green, 0 failures). Co-Authored-By: Claude Opus 4.8 (1M context)

Merge pull request #3643 from hathach/musb_ep0_race

2026-06-17T02:20:24Z

dcd/musb: defer EP0 SETUP during DATA_IN/STATUS race

hil: enable nanoch32v203 in CI with fsdev + usbfs variants (#3707)

2026-06-16T10:42:31Z

* hil: enable nanoch32v203 in CI with fsdev + usbfs variants nanoch32v203 was parked in boards-skip; move it into the active pool now that the board is wired to the ci.lan rig. Cover both USB device IPs as build variants: - nanoch32v203-fsdev: RHPORT_DEVICE=0 (USBD / stm32 FSDev IP) - nanoch32v203-usbfs: RHPORT_DEVICE=1 (WCH USBFS IP)

device: clamp EP0 OUT data copy to the control transfer buffer (#3705)

2026-06-16T10:36:17Z

* device: clamp EP0 OUT data copy to the control transfer buffer usbd_control_xfer_cb() copied xferred_bytes from the EP0 bounce buffer into the requester's buffer with no bound. A non-compliant host that sends an OUT data packet larger than the control transfer's data_len (= min(len, wLength), the buffer capacity) would overflow that buffer and over-count total_xferred. Clamp xferred_bytes to the remaining buffer space before the memcpy and accounting.

hil: make serial write timeout fatal

2026-06-13T16:35:35Z

pyserial's posix write() raises SerialTimeoutException after partial progress with the byte count lost, so the retry loop re-sent from the same offset and could duplicate bytes on the wire — surfacing as bogus data-mismatch failures that look like device firmware bugs. write_timeout is already a total per-call deadline, so the loop added duplication risk without extending the budget: write once and treat a timeout as fatal. Default bumped 2 -> 10 s to keep the old overall bound; HIL_SERIAL_WRITE_DEADLINE removed. The per-character CLI loops keep their existing pacing (the 2 ms sleep between single-byte writes already spaces them on the wire); no unbounded ser.flush()/tcdrain is added. Review follow-up for #3643 (hil_test.py l.257/264 findings). Co-Authored-By: Claude Fable 5