Merge pull request #111 from hathach/develop

Added new boards

15 files changed, 939 insertions, 14 deletions

diff --git a/docs/boards.md b/docs/boards.md
index 84319aaf3..be7ebf22d 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -12,6 +12,7 @@ This code base already had supported for a handful of following boards
 ### Nordic nRF5x
 
 - [Adafruit Feather nRF52840 Express](https://www.adafruit.com/product/4062)
+- [Adafruit Circuit Playground Bluefruit](https://www.adafruit.com/product/4333)
 - [Nordic nRF52840 Development Kit (aka pca10056)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK)
 
 ### NXP LPC
@@ -19,15 +20,17 @@ This code base already had supported for a handful of following boards
 - [LPCXpresso 11U68](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058)
 - [LPCXpresso 1347](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045)
 - [LPCXpresso 1769](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000)
-- [LPCXpresso 51U68](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005)
 - [Keil MCB1800 Evaluation Board](http://www.keil.com/mcb1800)
 - [Embedded Artists LPC4088 Quick Start board](https://www.embeddedartists.com/products/lpc4088-quickstart-board)
 - [Embedded Artists LPC4357 Developer Kit](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
+- [LPCXpresso 51U68](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005)
 
 ### MicroChip SAMD
 
-- [Adafruit Feather M4 Express](https://www.adafruit.com/product/3857)
+- [Adafruit Circuit Playground Express](https://www.adafruit.com/product/3333)
+- [Adafruit Feather M0 Express](https://www.adafruit.com/product/3403)
 - [Adafruit Metro M0 Express](https://www.adafruit.com/product/3505)
+- [Adafruit Feather M4 Express](https://www.adafruit.com/product/3857)
 - [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382)
 
 ### ST STM32
diff --git a/hw/bsp/circuitplayground_bluefruit/board.mk b/hw/bsp/circuitplayground_bluefruit/board.mk
new file mode 100644
index 000000000..26b15564d
--- /dev/null
+++ b/hw/bsp/circuitplayground_bluefruit/board.mk
@@ -0,0 +1,56 @@
+CFLAGS += \
+	-mthumb \
+	-mabi=aapcs \
+	-mcpu=cortex-m4 \
+	-mfloat-abi=hard \
+	-mfpu=fpv4-sp-d16 \
+	-DCFG_TUSB_MCU=OPT_MCU_NRF5X \
+	-DNRF52840_XXAA \
+  -DCONFIG_GPIO_AS_PINRESET
+
+# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
+CFLAGS += -Wno-error=undef 
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+
+LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
+
+SRC_C += \
+	hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
+	hw/mcu/nordic/nrfx/mdk/system_nrf52840.c \
+
+INC += \
+	$(TOP)/hw/mcu/nordic/cmsis/Include \
+	$(TOP)/hw/mcu/nordic \
+	$(TOP)/hw/mcu/nordic/nrfx \
+	$(TOP)/hw/mcu/nordic/nrfx/mdk \
+	$(TOP)/hw/mcu/nordic/nrfx/hal \
+	$(TOP)/hw/mcu/nordic/nrfx/drivers/include \
+	$(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+
+SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_nrf52840.S
+
+ASFLAGS += -D__HEAP_SIZE=0
+
+# For TinyUSB port source
+VENDOR = nordic
+CHIP_FAMILY = nrf5x
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# For flash-jlink target
+JLINK_DEVICE = nRF52840_xxAA
+JLINK_IF = swd
+
+# For uf2 conversion
+UF2_FAMILY = 0xADA52840
+
+$(BUILD)/$(BOARD)-firmware.zip: $(BUILD)/$(BOARD)-firmware.hex
+	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
+	
+# flash using adafruit-nrfutil dfu
+flash: $(BUILD)/$(BOARD)-firmware.zip
+	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
+	adafruit-nrfutil --verbose dfu serial --package $^ -p $(SERIAL) -b 115200 --singlebank --touch 1200
diff --git a/hw/bsp/circuitplayground_bluefruit/circuitplayground_bluefruit.c b/hw/bsp/circuitplayground_bluefruit/circuitplayground_bluefruit.c
new file mode 100644
index 000000000..59085fe97
--- /dev/null
+++ b/hw/bsp/circuitplayground_bluefruit/circuitplayground_bluefruit.c
@@ -0,0 +1,194 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+
+#include "nrfx.h"
+#include "nrfx/hal/nrf_gpio.h"
+#include "nrfx/drivers/include/nrfx_power.h"
+
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_sdm.h"
+#include "nrf_soc.h"
+#endif
+
+/*------------------------------------------------------------------*/
+/* MACRO TYPEDEF CONSTANT ENUM
+ *------------------------------------------------------------------*/
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
+#define LED_PIN         _PINNUM(1, 14)
+#define LED_STATE_ON    1
+
+#define BUTTON_PIN      _PINNUM(1, 15)
+
+// tinyusb function that handles power event (detected, ready, removed)
+// We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
+extern void tusb_hal_nrf_power_event(uint32_t event);
+
+void board_init(void)
+{
+  // Config clock source: XTAL or RC in sdk_config.h
+  NRF_CLOCK->LFCLKSRC = (uint32_t)((CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
+  NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
+
+  // LED
+  nrf_gpio_cfg_output(LED_PIN);
+  board_led_write(false);
+
+  // Button
+  nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLDOWN);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock/1000);
+#endif
+
+#if TUSB_OPT_DEVICE_ENABLED
+  // Priorities 0, 1, 4 (nRF52) are reserved for SoftDevice
+  // 2 is highest for application
+  NVIC_SetPriority(USBD_IRQn, 2);
+
+
+  // USB power may already be ready at this time -> no event generated
+  // We need to invoke the handler based on the status initially
+  uint32_t usb_reg;
+
+#ifdef SOFTDEVICE_PRESENT
+  uint8_t sd_en = false;
+  sd_softdevice_is_enabled(&sd_en);
+
+  if ( sd_en ) {
+    sd_power_usbdetected_enable(true);
+    sd_power_usbpwrrdy_enable(true);
+    sd_power_usbremoved_enable(true);
+
+    sd_power_usbregstatus_get(&usb_reg);
+  }else
+#endif
+  {
+    // Power module init
+    const nrfx_power_config_t pwr_cfg = { 0 };
+    nrfx_power_init(&pwr_cfg);
+
+    // Register tusb function as USB power handler
+    const nrfx_power_usbevt_config_t config = { .handler = (nrfx_power_usb_event_handler_t) tusb_hal_nrf_power_event };
+    nrfx_power_usbevt_init(&config);
+
+    nrfx_power_usbevt_enable();
+
+    usb_reg = NRF_POWER->USBREGSTATUS;
+  }
+
+  if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED);
+  if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  // button is active HIGH
+  return nrf_gpio_pin_read(BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+#ifdef SOFTDEVICE_PRESENT
+// process SOC event from SD
+uint32_t proc_soc(void)
+{
+  uint32_t soc_evt;
+  uint32_t err = sd_evt_get(&soc_evt);
+
+  if (NRF_SUCCESS == err)
+  {
+    /*------------- usb power event handler -------------*/
+    int32_t usbevt = (soc_evt == NRF_EVT_POWER_USB_DETECTED   ) ? NRFX_POWER_USB_EVT_DETECTED:
+                     (soc_evt == NRF_EVT_POWER_USB_POWER_READY) ? NRFX_POWER_USB_EVT_READY   :
+                     (soc_evt == NRF_EVT_POWER_USB_REMOVED    ) ? NRFX_POWER_USB_EVT_REMOVED : -1;
+
+    if ( usbevt >= 0) tusb_hal_nrf_power_event(usbevt);
+  }
+
+  return err;
+}
+
+uint32_t proc_ble(void)
+{
+  // do nothing with ble
+  return NRF_ERROR_NOT_FOUND;
+}
+
+void SD_EVT_IRQHandler(void)
+{
+  // process BLE and SOC until there is no more events
+  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
+  {
+
+  }
+}
+
+void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
+{
+  (void) id;
+  (void) pc;
+  (void) info;
+}
+#endif
diff --git a/hw/bsp/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/circuitplayground_bluefruit/nrf52840_s140_v6.ld
new file mode 100755
index 000000000..5314a4e93
--- /dev/null
+++ b/hw/bsp/circuitplayground_bluefruit/nrf52840_s140_v6.ld
@@ -0,0 +1,38 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
+
+  /* SRAM required by S132 depend on
+   * - Attribute Table Size
+   * - Vendor UUID count
+   * - Max ATT MTU
+   * - Concurrent connection peripheral + central + secure links
+   * - Event Len, HVN queue, Write CMD queue
+   */ 
+  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
+}
+
+SECTIONS
+{
+  . = ALIGN(4);
+  .svc_data :
+  {
+    PROVIDE(__start_svc_data = .);
+    KEEP(*(.svc_data))
+    PROVIDE(__stop_svc_data = .);
+  } > RAM
+  
+  .fs_data :
+  {
+    PROVIDE(__start_fs_data = .);
+    KEEP(*(.fs_data))
+    PROVIDE(__stop_fs_data = .);
+  } > RAM
+} INSERT AFTER .data;
+
+INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/circuitplayground_express/board.mk b/hw/bsp/circuitplayground_express/board.mk
new file mode 100644
index 000000000..158f543b3
--- /dev/null
+++ b/hw/bsp/circuitplayground_express/board.mk
@@ -0,0 +1,44 @@
+CFLAGS += \
+  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
+  -D__SAMD21G18A__ \
+  -mthumb \
+  -mabi=aapcs-linux \
+  -mcpu=cortex-m0plus \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMD21
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/circuitplayground_express/samd21g18a_flash.ld
+
+SRC_C += \
+	hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
+	hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
+	hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
+
+INC += \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/pm/ \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
+
+# For TinyUSB port source 
+VENDOR = microchip
+CHIP_FAMILY = samd21
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD21G18
+JLINK_IF = swd
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/circuitplayground_express/circuitplayground_express.c b/hw/bsp/circuitplayground_express/circuitplayground_express.c
new file mode 100644
index 000000000..355e15d39
--- /dev/null
+++ b/hw/bsp/circuitplayground_express/circuitplayground_express.c
@@ -0,0 +1,130 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+
+#include "sam.h"
+#include "hal/include/hal_gpio.h"
+#include "hal/include/hal_init.h"
+#include "hri/hri_nvmctrl_d21.h"
+
+#include "hpl/gclk/hpl_gclk_base.h"
+#include "hpl_pm_config.h"
+#include "hpl/pm/hpl_pm_base.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#define LED_PIN      17
+#define BUTTON_PIN   14 // pin D5
+
+/* Referenced GCLKs, should be initialized firstly */
+#define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
+
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
+
+void board_init(void)
+{
+  // Clock init ( follow hpl_init.c )
+  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
+
+  _pm_init();
+  _sysctrl_init_sources();
+#if _GCLK_INIT_1ST
+  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+  _sysctrl_init_referenced_generators();
+  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+  // Led init
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(LED_PIN, 0);
+
+  // Button init
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_DOWN);
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+  // 1ms tick timer (samd SystemCoreClock may not correct)
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
+
+  /* USB Clock init
+   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
+   * for low speed and full speed operation. */
+  _pm_enable_bus_clock(PM_BUS_APBB, USB);
+  _pm_enable_bus_clock(PM_BUS_AHB, USB);
+  _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+  // USB Pin Init
+  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA24, false);
+  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
+  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA25, false);
+  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
+
+  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
+  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
+
+  // Output 500hz PWM on D12 (PA19 - TCC0 WO[3]) so we can validate the GCLK0 clock speed with a Saleae.
+  _pm_enable_bus_clock(PM_BUS_APBC, TCC0);
+  TCC0->PER.bit.PER = 48000000 / 1000;
+  TCC0->CC[3].bit.CC = 48000000 / 2000;
+  TCC0->CTRLA.bit.ENABLE = true;
+
+  gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
+  _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  // button is active high
+  return gpio_get_pin_level(BUTTON_PIN);
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/circuitplayground_express/samd21g18a_flash.ld b/hw/bsp/circuitplayground_express/samd21g18a_flash.ld
new file mode 100644
index 000000000..7fc42171b
--- /dev/null
+++ b/hw/bsp/circuitplayground_express/samd21g18a_flash.ld
@@ -0,0 +1,144 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/feather_m0_express/board.mk b/hw/bsp/feather_m0_express/board.mk
new file mode 100644
index 000000000..b7ba0b0e1
--- /dev/null
+++ b/hw/bsp/feather_m0_express/board.mk
@@ -0,0 +1,44 @@
+CFLAGS += \
+  -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
+  -D__SAMD21G18A__ \
+  -mthumb \
+  -mabi=aapcs-linux \
+  -mcpu=cortex-m0plus \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMD21
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/feather_m0_express/samd21g18a_flash.ld
+
+SRC_C += \
+	hw/mcu/microchip/samd/asf4/samd21/gcc/gcc/startup_samd21.c \
+	hw/mcu/microchip/samd/asf4/samd21/gcc/system_samd21.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/gclk/hpl_gclk.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/pm/hpl_pm.c \
+	hw/mcu/microchip/samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c \
+	hw/mcu/microchip/samd/asf4/samd21/hal/src/hal_atomic.c
+
+INC += \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/ \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/config \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hal/utils/include \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd51/hpl/pm/ \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hpl/port \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/hri \
+	$(TOP)/hw/mcu/microchip/samd/asf4/samd21/CMSIS/Include
+
+# For TinyUSB port source 
+VENDOR = microchip
+CHIP_FAMILY = samd21
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD21G18
+JLINK_IF = swd
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/feather_m0_express/feather_m0_express.c b/hw/bsp/feather_m0_express/feather_m0_express.c
new file mode 100644
index 000000000..17576bb5a
--- /dev/null
+++ b/hw/bsp/feather_m0_express/feather_m0_express.c
@@ -0,0 +1,130 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+
+#include "sam.h"
+#include "hal/include/hal_gpio.h"
+#include "hal/include/hal_init.h"
+#include "hri/hri_nvmctrl_d21.h"
+
+#include "hpl/gclk/hpl_gclk_base.h"
+#include "hpl_pm_config.h"
+#include "hpl/pm/hpl_pm_base.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#define LED_PIN      17
+#define BUTTON_PIN   15 // pin D5
+
+/* Referenced GCLKs, should be initialized firstly */
+#define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
+
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
+
+void board_init(void)
+{
+  // Clock init ( follow hpl_init.c )
+  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
+
+  _pm_init();
+  _sysctrl_init_sources();
+#if _GCLK_INIT_1ST
+  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+  _sysctrl_init_referenced_generators();
+  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+  // Led init
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(LED_PIN, 0);
+
+  // Button init
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+  // 1ms tick timer (samd SystemCoreClock may not correct)
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
+
+  /* USB Clock init
+   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
+   * for low speed and full speed operation. */
+  _pm_enable_bus_clock(PM_BUS_APBB, USB);
+  _pm_enable_bus_clock(PM_BUS_AHB, USB);
+  _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+  // USB Pin Init
+  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA24, false);
+  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
+  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA25, false);
+  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
+
+  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
+  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
+
+  // Output 500hz PWM on D12 (PA19 - TCC0 WO[3]) so we can validate the GCLK0 clock speed with a Saleae.
+  _pm_enable_bus_clock(PM_BUS_APBC, TCC0);
+  TCC0->PER.bit.PER = 48000000 / 1000;
+  TCC0->CC[3].bit.CC = 48000000 / 2000;
+  TCC0->CTRLA.bit.ENABLE = true;
+
+  gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
+  _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  // button is active low
+  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/feather_m0_express/samd21g18a_flash.ld b/hw/bsp/feather_m0_express/samd21g18a_flash.ld
new file mode 100644
index 000000000..7fc42171b
--- /dev/null
+++ b/hw/bsp/feather_m0_express/samd21g18a_flash.ld
@@ -0,0 +1,144 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/feather_m4_express/feather_m4_express.c b/hw/bsp/feather_m4_express/feather_m4_express.c
index 2261e57b4..a368b3038 100644
--- a/hw/bsp/feather_m4_express/feather_m4_express.c
+++ b/hw/bsp/feather_m4_express/feather_m4_express.c
@@ -36,7 +36,7 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 #define LED_PIN      23
-#define BUTTON_PIN   22  // pin D12
+#define BUTTON_PIN   16  // pin D5
 
 /* Referenced GCLKs, should be initialized firstly */
 #define _GCLK_INIT_1ST 0xFFFFFFFF
diff --git a/hw/bsp/metro_m0_express/metro_m0_express.c b/hw/bsp/metro_m0_express/metro_m0_express.c
index 8c7bd443d..17576bb5a 100644
--- a/hw/bsp/metro_m0_express/metro_m0_express.c
+++ b/hw/bsp/metro_m0_express/metro_m0_express.c
@@ -39,7 +39,7 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 #define LED_PIN      17
-#define BUTTON_PIN   14 // pin D2
+#define BUTTON_PIN   15 // pin D5
 
 /* Referenced GCLKs, should be initialized firstly */
 #define _GCLK_INIT_1ST (1 << 0 | 1 << 1)
diff --git a/hw/bsp/metro_m4_express/metro_m4_express.c b/hw/bsp/metro_m4_express/metro_m4_express.c
index 2abb44b40..583a4dfe6 100644
--- a/hw/bsp/metro_m4_express/metro_m4_express.c
+++ b/hw/bsp/metro_m4_express/metro_m4_express.c
@@ -36,7 +36,7 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 #define LED_PIN      16
-#define BUTTON_PIN   17  // pin D12
+#define BUTTON_PIN   (14 + 32)  // pin D5
 
 /* Referenced GCLKs, should be initialized firstly */
 #define _GCLK_INIT_1ST 0xFFFFFFFF
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 08ddf78ad..b4f981d4a 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -60,15 +60,13 @@
 
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
 #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
-
-#define TU_BREAKPOINT() do                                                                                \
-{                                                                                                         \
-  volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
-  if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
-} while(0)
-
+  #define TU_BREAKPOINT() do                                                                                \
+  {                                                                                                         \
+    volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+    if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
+  } while(0)
 #else
-#define TU_BREAKPOINT()
+  #define TU_BREAKPOINT()
 #endif
 
 /*------------------------------------------------------------------*/
diff --git a/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c b/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c
index ec3177c4b..223c39c1a 100644
--- a/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c
+++ b/src/portable/nxp/lpc_usbd/dcd_lpc_usbd.c
@@ -69,7 +69,7 @@
  * - M3/M4 can transfer nbytes = 1023 (maximum)
  */
 enum {
-  #ifdef __ARM_ARCH_6M__  // Cortex M0/M0+
+  #ifdef __ARM_ARCH_6M__ // Cortex M0/M0+
     DMA_NBYTES_MAX = 64
   #else
     DMA_NBYTES_MAX = 1023