diff options
| author | hathach <[email protected]> | 2014-04-25 11:29:32 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2014-04-25 11:29:32 +0700 |
| commit | 1fb7106061624e27a82dad0f1edcf1caff1501c0 (patch) | |
| tree | d3956a1e7f24f2d8c2a747f261f40c88ac61d207 | |
| parent | 24b613580a0e00c63a48e4cc547542f34fe533f8 (diff) | |
remove unnecessary port from freertos
12 files changed, 0 insertions, 15133 deletions
diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/port.c b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/port.c deleted file mode 100644 index 3c280adaf..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/port.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel AT91R40008 - * port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* Standard includes. */ -#include <stdlib.h> - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware specific definitions. */ -#include "AT91R40008.h" -#include "pio.h" -#include "aic.h" -#include "tc.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) -#define portTICK_PRIORITY_6 ( 6 ) -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ - pxTopOfStack--; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the tick timer to generate the tick interrupts at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ -volatile unsigned long ulDummy; - - /* Enable clock to the tick timer... */ - AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; - - /* Stop the tick timer... */ - portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; - - /* Start with tick timer interrupts disabled... */ - portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; - - /* Clear any pending tick timer interrupts... */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - /* Store interrupt handler function address in tick timer vector register... - The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ - #if configUSE_PREEMPTION == 1 - { - extern void ( vPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vPreemptiveTick; - } - #else // else use cooperative scheduler - { - extern void ( vNonPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned long ) vNonPreemptiveTick; - } - #endif - - /* Tick timer interrupt level-sensitive, priority 6... */ - AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; - - /* Enable the tick timer interrupt... - - First at timer level */ - portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; - - /* Then at the AIC level. */ - AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); - - /* Calculate timer compare value to achieve the desired tick rate... */ - if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) - { - /* The tick rate is fast enough for us to use the faster timer input - clock (main clock / 2). */ - portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); - } - else - { - /* We must use a slower timer input clock (main clock / 8) because the - tick rate is too slow for the faster input clock. */ - portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); - } - - /* Start tick timer... */ - portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; -} -/*-----------------------------------------------------------*/ - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portISR.c deleted file mode 100644 index 05fe16881..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portISR.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to handle interrupts. */ -#define portCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) -volatile unsigned long ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); - void vNonPreemptiveTick( void ) - { - static volatile unsigned long ulDummy; - - /* Clear tick timer interrupt indication. */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - xTaskIncrementTick(); - - /* Acknowledge the interrupt at AIC level... */ - AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; - } - -#else /* else preemption is turned on */ - - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); - void vPreemptiveTick( void ) - { - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); - - /* WARNING - Do not use local (stack) variables here. Use globals - if you must! */ - static volatile unsigned long ulDummy; - - /* Clear tick timer interrupt indication. */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ - if( xTaskIncrementTick() != pdFALSE ) - { - vTaskSwitchContext(); - } - - /* Acknowledge the interrupt at AIC level... */ - AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - void vPortDisableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - -#endif /* THUMB_INTERWORK */ - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h deleted file mode 100644 index dc077bce6..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. - - Changes from V4.5.0 - - + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros - and replaced them with portYIELD_FROM_ISR() macro. Application code - should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() - macros as per the V4.5.1 demo code. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portYIELD() asm volatile ( "SWI 0" ) -#define portNOP() asm volatile ( "NOP" ) - -/* - * These define the timer to use for generating the tick interrupt. - * They are put in this file so they can be shared between "port.c" - * and "portisr.c". - */ -#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 -#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 -#define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 ) -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - -#define portYIELD_FROM_ISR() vTaskSwitchContext() - -/* Critical section handling. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h deleted file mode 100644 index 21b9b0807..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h +++ /dev/null @@ -1,2731 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - -#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ -{ \ - unsigned int mask ; \ - \ - mask = 0x1 << irq_id; \ - /* Disable the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_IDCR = mask ; \ - /* Save the interrupt handler routine pointer and the interrupt priority */ \ - AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ - /* Store the Source Mode Register */ \ - AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ - /* Clear the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_ICCR = mask ; \ -} - - -#endif diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h deleted file mode 100644 index 567ae7451..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h +++ /dev/null @@ -1,4698 +0,0 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7X256.h -// - Object : AT91SAM7X256 definitions -// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// - -// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// - ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - - - -// - Hardware register definition - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#if 0 /*_RB_*/ -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask -#endif -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) -AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// - ***************************************************************************** -// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark -AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority -AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type -AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) -// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode -AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode -AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version -// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value -AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code -AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request -AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort -AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready -AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored -// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox -AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network Interface -// - ***************************************************************************** -// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable -AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode -AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode -AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame -AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame -AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode -AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze -AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat -// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag -AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag -AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag -AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag -AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag -AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag -AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag -AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag -AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag -AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag -AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag -AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag -AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag -AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag -AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag -AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag -AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag -AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag -AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag -AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag -AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag -AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag -AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag -AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag -AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error -AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error -AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error -AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error -AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error -// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy -AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy -AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy -// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment -AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment -AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment -AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment -AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler -AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode -// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field -// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter -AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter -// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field -// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// - ***************************************************************************** -// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. -AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. -AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. -AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. -AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame -AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame -// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. -AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. -AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable -AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) -AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) -AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer -AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable -AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS -AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) -AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS -// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go -AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame -AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) -// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) -AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) -AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) -AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) -AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) -// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) -AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) -// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII -// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address -AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable -AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable -AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable -// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// - ***************************************************************************** -// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- -AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing -AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset -AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading -// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode -AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay -AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode -AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). -AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode -AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. -AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. -AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. -AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. -AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. -AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode -AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size -AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. -AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. -AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. -AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. -AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. -AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key -AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type -AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. -AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. -AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. -AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. -AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. -// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY -AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End -AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End -AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full -AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty -AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection -// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status -AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. -AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. -AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. -AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. -AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. -AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// - ***************************************************************************** -// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing -AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset -// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode -AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode -AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode -AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode -AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). -AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode -AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. -AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. -AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. -AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. -AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode -AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size -AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. -AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. -AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. -AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. -// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY -AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End -AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End -AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full -AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty -AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection -// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status -AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. -AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. -AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. -AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. - -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI1 peripheral ========== -AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register -AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register -AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register -AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register -AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register -AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register -AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register -AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register -AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register -AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register -// - ========== Register definition for SPI1 peripheral ========== -AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register -AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register -AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register -AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register -AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register -AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register -AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register -AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register -AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register -// - ========== Register definition for PDC_SPI0 peripheral ========== -AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register -AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register -AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register -AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register -AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register -AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register -AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register -AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register -AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register -AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register -// - ========== Register definition for SPI0 peripheral ========== -AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register -AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register -AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register -AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register -AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register -AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register -AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register -AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register -AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for CAN_MB0 peripheral ========== -AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register -AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register -AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register -AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register -AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register -AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register -AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register -AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register -// - ========== Register definition for CAN_MB1 peripheral ========== -AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register -AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register -AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register -AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register -AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register -AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register -AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register -AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register -// - ========== Register definition for CAN_MB2 peripheral ========== -AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register -AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register -AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register -AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register -AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register -AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register -AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register -AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register -// - ========== Register definition for CAN_MB3 peripheral ========== -AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register -AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register -AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register -AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register -AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register -AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register -AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register -AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register -// - ========== Register definition for CAN_MB4 peripheral ========== -AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register -AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register -AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register -AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register -AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register -AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register -AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register -AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB5 peripheral ========== -AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register -AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register -AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register -AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register -AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register -AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register -AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register -AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB6 peripheral ========== -AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register -AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register -AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register -AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register -AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register -AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register -AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register -AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register -// - ========== Register definition for CAN_MB7 peripheral ========== -AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register -AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register -AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register -AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register -AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register -AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register -AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register -AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register -// - ========== Register definition for CAN peripheral ========== -AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register -AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register -AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register -AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register -AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register -AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register -AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register -AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register -AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register -AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register -AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register -AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register -// - ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register -AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes -AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes -AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register -AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register -AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register -AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes -AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes -AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register -AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register -AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] -AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer -AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register -AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register -AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes -AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register -AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register -AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register -AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] -AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register -AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register -AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register -AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register -AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register -AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes -AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes -AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes -AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register -AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_AES peripheral ========== -AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register -AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register -AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register -AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register -AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register -AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register -AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register -AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register -AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register -AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register -// - ========== Register definition for AES peripheral ========== -AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register -AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register -AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register -AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register -AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register -AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register -AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register -AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register -AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register -AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register -AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register -// - ========== Register definition for PDC_TDES peripheral ========== -AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register -AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register -AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register -AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register -AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register -AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register -AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register -AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register -AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register -AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register -// - ========== Register definition for TDES peripheral ========== -AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register -AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register -AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register -AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register -AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register -AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register -AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register -AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register -AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register -AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register -AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register -AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register -AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register - -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync -AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock -AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data -AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data -AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock -AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync -AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data -AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input -AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send -AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 -AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send -AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock -AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send -AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send -AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 -AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 -AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 -AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 -AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 -AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 -AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 -AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error -AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input -AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 -AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 -AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 -AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 -AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 -AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 -AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected -AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 -AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock -AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 -AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger -AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 -AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 -AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input -AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 -AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 -AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 -AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 -AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 -AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 -AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 -AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 -AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 -AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready -AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 -AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready -AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 -AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator -AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 -AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 -AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 -AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 -AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 -AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 -AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 -AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 -AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 -AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 -AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 -AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 -AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 -AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 -AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 -AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 -AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 -AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error -AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 -AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock -AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 -AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output - -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 -AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_CAN EQU (15) ;- Control Area Network Controller -AT91C_ID_EMAC EQU (16) ;- Ethernet MAC -AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter -AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit -AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) - -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address -AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address -AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address -AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address -AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address -AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address -AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address -AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address -AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address -AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address -AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address -AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address -AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address -AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address -AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address -AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address - -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) -AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address -AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) - - - -#endif /* AT91SAM7X256_H */ diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c deleted file mode 100644 index bb2ad9be7..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c +++ /dev/null @@ -1,51 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - - -#include "AT91SAM7X256.h" - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h deleted file mode 100644 index 5720bad3f..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h +++ /dev/null @@ -1,4558 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in �second, system clock freq in MHz -//*---------------------------------------------------------------------------- -__inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -__inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Enable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Disable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -}/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, - int id_reg, - int data_low_reg, - int data_high_reg, - int control_reg) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_EnableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_DisableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_EnableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_DisableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsInterruptMasked( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsStatusSet( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgModeReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetModeReg ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgBaudrateReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetBaudrate ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInternalCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetTimestamp ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetErrorCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitTransferRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitAbortRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, - unsigned char version) -{ - if(version==0) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id<<18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetFamilyID ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageCtrlReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageStatus ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_Open -//* \brief Open a CAN Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR AES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_EnableIt -//* \brief Enable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_EnableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pAES->AES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_DisableIt -//* \brief Disable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_DisableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pAES->AES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetStatus -//* \brief Return AES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetInterruptMaskStatus -//* \brief Return AES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsInterruptMasked -//* \brief Test if AES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsInterruptMasked( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsStatusSet -//* \brief Test if AES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsStatusSet( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgModeReg -//* \brief Configure the Mode Register of the AES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgModeReg ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pAES->AES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetModeReg -//* \brief Return the Mode Register of the AES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetModeReg ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - return pAES->AES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_StartProcessing ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SoftReset -//* \brief Reset AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SoftReset ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_LoadNewSeed -//* \brief Load New Seed in the random number generator -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_LoadNewSeed ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_LOADSEED; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetCryptoKey -//* \brief Set Cryptographic Key x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetCryptoKey ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int keyword - ) -{ - pAES->AES_KEYWxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_InputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int indata - ) -{ - pAES->AES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetOutputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index - ) -{ - return pAES->AES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetInitializationVector -//* \brief Set Initialization Vector (or Counter) x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetInitializationVector ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int initvector - ) -{ - pAES->AES_IVxR[index] = initvector; -} - -/* ***************************************************************************** - SOFTWARE API FOR TDES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_EnableIt -//* \brief Enable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_EnableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pTDES->TDES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_DisableIt -//* \brief Disable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_DisableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pTDES->TDES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetStatus -//* \brief Return TDES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetInterruptMaskStatus -//* \brief Return TDES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsInterruptMasked -//* \brief Test if TDES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsInterruptMasked( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsStatusSet -//* \brief Test if TDES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsStatusSet( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgModeReg -//* \brief Configure the Mode Register of the TDES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgModeReg ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pTDES->TDES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetModeReg -//* \brief Return the Mode Register of the TDES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetModeReg ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - return pTDES->TDES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_StartProcessing ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SoftReset -//* \brief Reset TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SoftReset ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey1 -//* \brief Set Cryptographic Key 1 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey1 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY1WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey2 -//* \brief Set Cryptographic Key 2 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey2 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY2WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey3 -//* \brief Set Cryptographic Key 3 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey3 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY3WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_InputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int indata - ) -{ - pTDES->TDES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetOutputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index - ) -{ - return pTDES->TDES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetInitializationVector -//* \brief Set Initialization Vector x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetInitializationVector ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int initvector - ) -{ - pTDES->TDES_IVxR[index] = initvector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA27_DRXD ) | - ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB30_PCK2 ) | - ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A - ((unsigned int) AT91C_PB20_PCK0 ) | - ((unsigned int) AT91C_PB0_PCK0 ) | - ((unsigned int) AT91C_PB22_PCK2 ) | - ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA30_PCK2 ) | - ((unsigned int) AT91C_PA13_PCK1 ) | - ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_RK ) | - ((unsigned int) AT91C_PA22_TK ) | - ((unsigned int) AT91C_PA21_TF ) | - ((unsigned int) AT91C_PA24_RD ) | - ((unsigned int) AT91C_PA26_RF ) | - ((unsigned int) AT91C_PA23_TD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB26_RI1 ) | - ((unsigned int) AT91C_PB24_DSR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA7_SCK1 ) | - ((unsigned int) AT91C_PA8_RTS1 ) | - ((unsigned int) AT91C_PA6_TXD1 ) | - ((unsigned int) AT91C_PA5_RXD1 ) | - ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_RXD0 ) | - ((unsigned int) AT91C_PA4_CTS0 ) | - ((unsigned int) AT91C_PA3_RTS0 ) | - ((unsigned int) AT91C_PA2_SCK0 ) | - ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB16_NPCS13 ) | - ((unsigned int) AT91C_PB10_NPCS11 ) | - ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA4_NPCS13 ) | - ((unsigned int) AT91C_PA29_NPCS13 ) | - ((unsigned int) AT91C_PA21_NPCS10 ) | - ((unsigned int) AT91C_PA22_SPCK1 ) | - ((unsigned int) AT91C_PA25_NPCS11 ) | - ((unsigned int) AT91C_PA2_NPCS11 ) | - ((unsigned int) AT91C_PA24_MISO1 ) | - ((unsigned int) AT91C_PA3_NPCS12 ) | - ((unsigned int) AT91C_PA26_NPCS12 ) | - ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB13_NPCS01 ) | - ((unsigned int) AT91C_PB17_NPCS03 ) | - ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA16_MISO0 ) | - ((unsigned int) AT91C_PA13_NPCS01 ) | - ((unsigned int) AT91C_PA15_NPCS03 ) | - ((unsigned int) AT91C_PA17_MOSI0 ) | - ((unsigned int) AT91C_PA18_SPCK0 ) | - ((unsigned int) AT91C_PA14_NPCS02 ) | - ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A - ((unsigned int) AT91C_PA7_NPCS01 ) | - ((unsigned int) AT91C_PA9_NPCS03 ) | - ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -__inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ0 ) | - ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A - ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgPMC -//* \brief Enable Peripheral clock in PMC for AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_AES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_TWCK ) | - ((unsigned int) AT91C_PA10_TWD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A - ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgPMC -//* \brief Enable Peripheral clock in PMC for TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TDES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB2_ETX0 ) | - ((unsigned int) AT91C_PB12_ETXER ) | - ((unsigned int) AT91C_PB16_ECOL ) | - ((unsigned int) AT91C_PB11_ETX3 ) | - ((unsigned int) AT91C_PB6_ERX1 ) | - ((unsigned int) AT91C_PB15_ERXDV ) | - ((unsigned int) AT91C_PB13_ERX2 ) | - ((unsigned int) AT91C_PB3_ETX1 ) | - ((unsigned int) AT91C_PB8_EMDC ) | - ((unsigned int) AT91C_PB5_ERX0 ) | - //((unsigned int) AT91C_PB18_EF100 ) | - ((unsigned int) AT91C_PB14_ERX3 ) | - ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | - ((unsigned int) AT91C_PB1_ETXEN ) | - ((unsigned int) AT91C_PB10_ETX2 ) | - ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | - ((unsigned int) AT91C_PB9_EMDIO ) | - ((unsigned int) AT91C_PB7_ERXER ) | - ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB23_TIOA0 ) | - ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A - ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB25_TIOA1 ) | - ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A - ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB28_TIOB2 ) | - ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPIO -//* \brief Configure PIO controllers to drive CAN signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA20_CANTX ) | - ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -#endif // lib_AT91SAM7X256_H diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/port.c deleted file mode 100644 index db2acb543..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/port.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* Standard includes. */ -#include <stdlib.h> - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Processor constants. */ -#include "AT91SAM7X256.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( unsigned char ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned long ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned long ) 0x02 ) - -/* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( unsigned long ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) - -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( unsigned short ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( unsigned short ) 0x1 << 25 ) -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* To ensure asserts in tasks.c don't fail, although in this case the assert - is not really required. */ - pxTopOfStack--; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the timer 0 to generate the tick interrupts at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ -AT91PS_PITC pxPIT = AT91C_BASE_PITC; - - /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - on whether the preemptive or cooperative scheduler is being used. */ - #if configUSE_PREEMPTION == 0 - - extern void ( vNonPreemptiveTick ) ( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); - - #else - - extern void ( vPreemptiveTick )( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); - - #endif - - /* Configure the PIT period. */ - pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; - - /* Enable the interrupt. Global interrupts are disables at this point so - this is safe. */ - AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; -} -/*-----------------------------------------------------------*/ - - - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c deleted file mode 100644 index bd4adadb1..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -#include "AT91SAM7X256.h" - -/* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) -volatile unsigned long ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); - void vNonPreemptiveTick( void ) - { - unsigned long ulDummy; - - /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ - xTaskIncrementTick(); - - /* Clear the PIT interrupt. */ - ulDummy = AT91C_BASE_PITC->PITC_PIVR; - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = ulDummy; - } - -#else - - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); - void vPreemptiveTick( void ) - { - /* Save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Increment the tick count - this may wake a task. */ - if( xTaskIncrementTick() != pdFALSE ) - { - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - } - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;; - - portRESTORE_CONTEXT(); - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); -void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - -void vPortDisableInterruptsFromThumb( void ) -{ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - -void vPortEnableInterruptsFromThumb( void ) -{ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h deleted file mode 100644 index 6a4879cf3..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. - - Changes from V4.5.0 - - + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros - and replaced them with portYIELD_FROM_ISR() macro. Application code - should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() - macros as per the V4.5.1 demo code. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -#define portNOP() asm volatile ( "NOP" ); -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - - -#define portYIELD_FROM_ISR() vTaskSwitchContext() -#define portYIELD() asm volatile ( "SWI 0" ) -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/port.c b/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/port.c deleted file mode 100644 index ce15b146d..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/port.c +++ /dev/null @@ -1,1246 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Constants required to access and manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 ) -#define portNVIC_SYSPRI1 ( ( volatile unsigned long * ) 0xe000ed1c ) -#define portNVIC_SYS_CTRL_STATE ( ( volatile unsigned long * ) 0xe000ed24 ) -#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) - -/* Constants required to access and manipulate the MPU. */ -#define portMPU_TYPE ( ( volatile unsigned long * ) 0xe000ed90 ) -#define portMPU_REGION_BASE_ADDRESS ( ( volatile unsigned long * ) 0xe000ed9C ) -#define portMPU_REGION_ATTRIBUTE ( ( volatile unsigned long * ) 0xe000edA0 ) -#define portMPU_CTRL ( ( volatile unsigned long * ) 0xe000ed94 ) -#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ -#define portMPU_ENABLE ( 0x01UL ) -#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) -#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) -#define portMPU_REGION_VALID ( 0x10UL ) -#define portMPU_REGION_ENABLE ( 0x01UL ) -#define portPERIPHERALS_START_ADDRESS 0x40000000UL -#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL - -/* Constants required to access and manipulate the SysTick. */ -#define portNVIC_SYSTICK_CLK ( 0x00000004UL ) -#define portNVIC_SYSTICK_INT ( 0x00000002UL ) -#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) -#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) -#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) -#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) - -/* Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_PC ( 6 ) - -/* Set the privilege level to user mode if xRunningPrivileged is false. */ -#define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. Note this is not saved as part of the task context as context -switches can only occur when uxCriticalNesting is zero. */ -static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; - -/* - * Configure a number of standard MPU regions that are used by all tasks. - */ -static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; - -/* - * Return the smallest MPU region size that a given number of bytes will fit - * into. The region size is returned as the value that should be programmed - * into the region attribute register for that region. - */ -static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION; - -/* - * Checks to see if being called from the context of an unprivileged task, and - * if so raises the privilege level and returns false - otherwise does nothing - * other than return true. - */ -static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked )); - -/* - * Standard FreeRTOS exception handlers. - */ -void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; -void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION; -void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; - -/* - * Starts the scheduler by restoring the context of the first task to run. - */ -static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; - -/* - * C portion of the SVC handler. The SVC handler is split between an asm entry - * and a C wrapper for simplicity of coding and maintenance. - */ -static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION; - -/* - * Prototypes for all the MPU wrappers. - */ -signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ); -void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions ); -void MPU_vTaskDelete( xTaskHandle pxTaskToDelete ); -void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ); -void MPU_vTaskDelay( portTickType xTicksToDelay ); -unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask ); -void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); -eTaskState MPU_eTaskGetState( xTaskHandle pxTask ); -void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend ); -signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask ); -void MPU_vTaskResume( xTaskHandle pxTaskToResume ); -void MPU_vTaskSuspendAll( void ); -signed portBASE_TYPE MPU_xTaskResumeAll( void ); -portTickType MPU_xTaskGetTickCount( void ); -unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void ); -void MPU_vTaskList( signed char *pcWriteBuffer ); -void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer ); -void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue ); -pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask ); -portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ); -unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask ); -xTaskHandle MPU_xTaskGetCurrentTaskHandle( void ); -portBASE_TYPE MPU_xTaskGetSchedulerState( void ); -xTaskHandle MPU_xTaskGetIdleTaskHandle( void ); -unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime ); -xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType ); -signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); -portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue ); -unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue ); -signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); -xQueueHandle MPU_xQueueCreateMutex( void ); -xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ); -portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ); -portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex ); -signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); -signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); -void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName ); -void MPU_vQueueDelete( xQueueHandle xQueue ); -void *MPU_pvPortMalloc( size_t xSize ); -void MPU_vPortFree( void *pv ); -void MPU_vPortInitialiseBlocks( void ); -size_t MPU_xPortGetFreeHeapSize( void ); -xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength ); -xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks ); -portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet ); -portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet ); -signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle xQueue, void * const pvBuffer ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - if( xRunPrivileged == pdTRUE ) - { - *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; - } - else - { - *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; - } - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortSVCHandler( void ) -{ - /* Assumes psp was in use. */ - __asm volatile - ( - #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" - #else - " mrs r0, psp \n" - #endif - " b %0 \n" - ::"i"(prvSVCHandler):"r0" - ); -} -/*-----------------------------------------------------------*/ - -static void prvSVCHandler( unsigned long *pulParam ) -{ -unsigned char ucSVCNumber; - - /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and - xPSR. The first argument (r0) is pulParam[ 0 ]. */ - ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ]; - switch( ucSVCNumber ) - { - case portSVC_START_SCHEDULER : *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI; - prvRestoreContextOfFirstTask(); - break; - - case portSVC_YIELD : *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - /* Barriers are normally not required - but do ensure the code is completely - within the specified behaviour for the - architecture. */ - __asm volatile( "dsb" ); - __asm volatile( "isb" ); - - break; - - case portSVC_RAISE_PRIVILEGE : __asm volatile - ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ - :::"r1" - ); - break; - - default : /* Unknown SVC call. */ - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvRestoreContextOfFirstTask( void ) -{ - __asm volatile - ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ - " ldr r0, [r0] \n" - " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" - " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */ - " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */ - " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */ - " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */ - " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */ - " msr control, r3 \n" - " msr psp, r0 \n" /* Restore the task stack pointer. */ - " mov r0, #0 \n" - " msr basepri, r0 \n" - " ldr r14, =0xfffffffd \n" /* Load exec return code. */ - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst2: .word pxCurrentTCB \n" - ); -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See - http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); - - /* Make PendSV and SysTick the same priority as the kernel. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Configure the regions in the MPU that are common to all tasks. */ - prvSetupMPU(); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Start the first task. */ - __asm volatile( " svc %0 \n" - :: "i" (portSVC_START_SCHEDULER) ); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void xPortPendSVHandler( void ) -{ - /* This is a naked function. */ - - __asm volatile - ( - " mrs r0, psp \n" - " \n" - " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ - " ldr r2, [r3] \n" - " \n" - " mrs r1, control \n" - " stmdb r0!, {r1, r4-r11} \n" /* Save the remaining registers. */ - " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ - " \n" - " stmdb sp!, {r3, r14} \n" - " mov r0, %0 \n" - " msr basepri, r0 \n" - " bl vTaskSwitchContext \n" - " mov r0, #0 \n" - " msr basepri, r0 \n" - " ldmia sp!, {r3, r14} \n" - " \n" /* Restore the context. */ - " ldr r1, [r3] \n" - " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */ - " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */ - " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */ - " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */ - " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */ - " msr control, r3 \n" - " \n" - " msr psp, r0 \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst: .word pxCurrentTCB \n" - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) - ); -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ -unsigned long ulDummy; - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - { - /* Increment the RTOS tick. */ - if( xTaskIncrementTick() != pdFALSE ) - { - /* Pend a context switch. */ - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - } - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} -/*-----------------------------------------------------------*/ - -static void prvSetupMPU( void ) -{ -extern unsigned long __privileged_functions_end__[]; -extern unsigned long __FLASH_segment_start__[]; -extern unsigned long __FLASH_segment_end__[]; -extern unsigned long __privileged_data_start__[]; -extern unsigned long __privileged_data_end__[]; - - /* Check the expected MPU is present. */ - if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE ) - { - /* First setup the entire flash for unprivileged read only access. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portUNPRIVILEGED_FLASH_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_ONLY ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Setup the first 16K for privileged only access (even though less - than 10K is actually being used). This is where the kernel code is - placed. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portPRIVILEGED_FLASH_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Setup the privileged data RAM region. This is where the kernel data - is placed. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portPRIVILEGED_RAM_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) | - ( portMPU_REGION_ENABLE ); - - /* By default allow everything to access the general peripherals. The - system peripherals and registers are protected. */ - *portMPU_REGION_BASE_ADDRESS = ( portPERIPHERALS_START_ADDRESS ) | - ( portMPU_REGION_VALID ) | - ( portGENERAL_PERIPHERALS_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | - ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | - ( portMPU_REGION_ENABLE ); - - /* Enable the memory fault exception. */ - *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE; - - /* Enable the MPU with the background region configured. */ - *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); - } -} -/*-----------------------------------------------------------*/ - -static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) -{ -unsigned long ulRegionSize, ulReturnValue = 4; - - /* 32 is the smallest region size, 31 is the largest valid value for - ulReturnValue. */ - for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) - { - if( ulActualSizeInBytes <= ulRegionSize ) - { - break; - } - else - { - ulReturnValue++; - } - } - - /* Shift the code by one before returning so it can be written directly - into the the correct bit position of the attribute register. */ - return ( ulReturnValue << 1UL ); -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvRaisePrivilege( void ) -{ - __asm volatile - ( - " mrs r0, control \n" - " tst r0, #1 \n" /* Is the task running privileged? */ - " itte ne \n" - " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */ - " svcne %0 \n" /* Switch to privileged. */ - " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */ - " bx lr \n" - :: "i" (portSVC_RAISE_PRIVILEGE) : "r0" - ); - - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth ) -{ -extern unsigned long __SRAM_segment_start__[]; -extern unsigned long __SRAM_segment_end__[]; -extern unsigned long __privileged_data_start__[]; -extern unsigned long __privileged_data_end__[]; -long lIndex; -unsigned long ul; - - if( xRegions == NULL ) - { - /* No MPU regions are specified so allow access to all RAM. */ - xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); - - xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have - just removed the privileged only parameters. */ - xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + 1 ); - - xMPUSettings->xRegion[ 1 ].ulRegionAttribute = - ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) | - ( portMPU_REGION_ENABLE ); - - /* Invalidate all other regions. */ - for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) - { - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; - xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; - } - } - else - { - /* This function is called automatically when the task is created - in - which case the stack region parameters will be valid. At all other - times the stack parameters will not be valid and it is assumed that the - stack region has already been configured. */ - if( usStackDepth > 0 ) - { - /* Define the region that allows access to the stack. */ - xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( unsigned long ) pxBottomOfStack ) | - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ - - xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ - ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( portMPU_REGION_ENABLE ); - } - - lIndex = 0; - - for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) - { - if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) - { - /* Translate the generic region definition contained in - xRegions into the CM3 specific MPU settings that are then - stored in xMPUSettings. */ - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = - ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) | - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ - - xMPUSettings->xRegion[ ul ].ulRegionAttribute = - ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | - ( xRegions[ lIndex ].ulParameters ) | - ( portMPU_REGION_ENABLE ); - } - else - { - /* Invalidate the region. */ - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; - xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; - } - - lIndex++; - } - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskAllocateMPURegions( xTask, xRegions ); - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - void MPU_vTaskDelete( xTaskHandle pxTaskToDelete ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelete( pxTaskToDelete ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - void MPU_vTaskDelay( portTickType xTicksToDelay ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelay( xTicksToDelay ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask ) - { - unsigned portBASE_TYPE uxReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskPriorityGet( pxTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskPrioritySet( pxTask, uxNewPriority ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_eTaskGetState == 1 ) - eTaskState MPU_eTaskGetState( xTaskHandle pxTask ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - eTaskState eReturn; - - eReturn = eTaskGetState( pxTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return eReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) - xTaskHandle MPU_xTaskGetIdleTaskHandle( void ) - { - xTaskHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetIdleTaskHandle(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return eReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSuspend( pxTaskToSuspend ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskIsTaskSuspended( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - void MPU_vTaskResume( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskResume( pxTaskToResume ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -void MPU_vTaskSuspendAll( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSuspendAll(); - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xTaskResumeAll( void ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskResumeAll(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -portTickType MPU_xTaskGetTickCount( void ) -{ -portTickType xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetTickCount(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskGetNumberOfTasks(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - void MPU_vTaskList( signed char *pcWriteBuffer ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskList( pcWriteBuffer ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskGetRunTimeStats( pcWriteBuffer ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSetApplicationTaskTag( xTask, pxTagValue ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask ) - { - pdTASK_HOOK_CODE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetApplicationTaskTag( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime ) - { - unsigned portBASE_TYPE uxReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) - unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask ) - { - unsigned portBASE_TYPE uxReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskGetStackHighWaterMark( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - xTaskHandle MPU_xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetCurrentTaskHandle(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetSchedulerState == 1 ) - portBASE_TYPE MPU_xTaskGetSchedulerState( void ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetSchedulerState(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType ) -{ -xQueueHandle xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue ) -{ -portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGenericReset( pxQueue, xNewQueue ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); -unsigned portBASE_TYPE uxReturn; - - uxReturn = uxQueueMessagesWaiting( pxQueue ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); -signed portBASE_TYPE xReturn; - - xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle pxQueue, void * const pvBuffer ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); -signed portBASE_TYPE xReturn; - - xReturn = xQueuePeekFromISR( pxQueue, pvBuffer ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - xQueueHandle MPU_xQueueCreateMutex( void ) - { - xQueueHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_COUNTING_SEMAPHORES == 1 - xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) - { - xQueueHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGiveMutexRecursive( xMutex ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_QUEUE_SETS == 1 ) - xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength ) - { - xQueueSetHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueCreateSet( uxEventQueueLength ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_QUEUE_SETS == 1 ) - xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks ) - { - xQueueSetMemberHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_QUEUE_SETS == 1 ) - portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_QUEUE_SETS == 1 ) - portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configQUEUE_REGISTRY_SIZE > 0 - void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vQueueAddToRegistry( xQueue, pcName ); - - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -void MPU_vQueueDelete( xQueueHandle xQueue ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vQueueDelete( xQueue ); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void *MPU_pvPortMalloc( size_t xSize ) -{ -void *pvReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - pvReturn = pvPortMalloc( xSize ); - - portRESET_PRIVILEGE( xRunningPrivileged ); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void MPU_vPortFree( void *pv ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vPortFree( pv ); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void MPU_vPortInitialiseBlocks( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vPortInitialiseBlocks(); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -size_t MPU_xPortGetFreeHeapSize( void ) -{ -size_t xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xPortGetFreeHeapSize(); - - portRESET_PRIVILEGE( xRunningPrivileged ); - - return xReturn; -} - -/* Functions that the application writer wants to execute in privileged mode -can be defined in application_defined_privileged_functions.h. The functions -must take the same format as those above whereby the privilege state on exit -equals the privilege state on entry. For example: - -void MPU_FunctionName( [parameters ] ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - FunctionName( [parameters ] ); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -*/ - -#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1 - #include "application_defined_privileged_functions.h" -#endif - diff --git a/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/portmacro.h deleted file mode 100644 index 9a5b64373..000000000 --- a/vendor/freertos/freertos/Source/portable/GCC/ARM_CM3_MPU/portmacro.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* MPU specific constants. */ -#define portUSING_MPU_WRAPPERS 1 -#define portPRIVILEGE_BIT ( 0x80000000UL ) - -#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) -#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) -#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) -#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) -#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) -#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - -#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) -#define portPRIVILEGED_FLASH_REGION ( 1UL ) -#define portPRIVILEGED_RAM_REGION ( 2UL ) -#define portGENERAL_PERIPHERALS_REGION ( 3UL ) -#define portSTACK_REGION ( 4UL ) -#define portFIRST_CONFIGURABLE_REGION ( 5UL ) -#define portLAST_CONFIGURABLE_REGION ( 7UL ) -#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) -#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ - -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" ) - -typedef struct MPU_REGION_REGISTERS -{ - unsigned portLONG ulRegionBaseAddress; - unsigned portLONG ulRegionAttribute; -} xMPU_REGION_REGISTERS; - -/* Plus 1 to create space for the stack region. */ -typedef struct MPU_SETTINGS -{ - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; -} xMPU_SETTINGS; - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ - -/* SVC numbers for various services. */ -#define portSVC_START_SCHEDULER 0 -#define portSVC_YIELD 1 -#define portSVC_RAISE_PRIVILEGE 2 - -/* Scheduler utilities. */ - -#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) ) -#define portYIELD_WITHIN_API() *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET - -#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) -#define portNVIC_PENDSVSET 0x10000000 -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other - * registers. r0 is clobbered. - */ -#define portSET_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, %0 \n" \ - " msr basepri, r0 \n" \ - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \ - ) - -/* - * Set basepri back to 0 without effective other registers. - * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see - * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. - */ -#define portCLEAR_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, #0 \n" \ - " msr basepri, r0 \n" \ - :::"r0" \ - ) - -/* FAQ: Setting BASEPRI to 0 is not a bug. Please see -http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */ -#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x - - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() -#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define portNOP() - - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - |