Merge branch 'master' into ep0_direct

# Conflicts: # hw/bsp/same7x/boards/same70_qmtech/board.cmake # hw/bsp/same7x/boards/same70_xplained/board.cmake # hw/bsp/same7x/family.cmake
author: hathach <[email protected]> 2026-03-11 13:34:59 +0700
committer: hathach <[email protected]> 2026-03-11 13:34:59 +0700
commit: 336e89792f9b572c5087b1df479d4e89542f6360 (patch)
tree: 866a0acbf5dbc952b183768f2b916ff9fe36a591
parent: 60154a128795bcd6ca36042cac1b8bebf1a2764e (diff)
parent: 7249c65b2a5b995ff7c2b45c1171f218b9d71112 (diff)
444 files changed, 25601 insertions, 8318 deletions
diff --git a/.circleci/config2.yml b/.circleci/config2.yml
index 352d0f4fa..bb0ac350f 100644
--- a/.circleci/config2.yml
+++ b/.circleci/config2.yml
@@ -110,7 +110,7 @@ commands:
           no_output_timeout: 20m
           command: |
             if [ << parameters.toolchain >> == esp-idf ]; then
-              docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.2 python tools/build.py << parameters.build-args >> << parameters.family >>
+              docker run --rm -v $PWD:/project -w /project espressif/idf:v5.5.3 python tools/build.py << parameters.build-args >> --target all << parameters.family >>
             else
               # Toolchain option default is gcc
               if [ << parameters.toolchain >> == arm-clang ]; then
@@ -124,7 +124,11 @@ commands:
 
               # circleci docker return $nproc as 36 core, limit parallel to 4 (resource-class = large)
               # Required for IAR, also prevent crashed/killed by docker
-              python tools/build.py -s << parameters.build-system >> $TOOLCHAIN_OPTION -j 4 << parameters.build-args >> << parameters.family >>
+              BUILD_PY_ARGS="-s << parameters.build-system >> $TOOLCHAIN_OPTION -j 4 << parameters.build-args >> --target all"
+              if [ << parameters.build-system >> == "cmake" ]; then
+                BUILD_PY_ARGS="$BUILD_PY_ARGS --target tinyusb_metrics"
+              fi
+              python tools/build.py $BUILD_PY_ARGS << parameters.family >>
             fi
 
       # Only collect and persist metrics for cmake builds (excluding esp-idf and --one-random)
diff --git a/.github/actions/get_deps/action.yml b/.github/actions/get_deps/action.yml
index a84db893b..bbe94f0fa 100644
--- a/.github/actions/get_deps/action.yml
+++ b/.github/actions/get_deps/action.yml
@@ -22,6 +22,7 @@ runs:
         NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.13.1/ninja-linux.zip
         wget $NINJA_URL -O ninja-linux.zip
         unzip ninja-linux.zip -d ninja-bin
+        pip install membrowse
         echo >> $GITHUB_PATH "${{ github.workspace }}/ninja-bin"
       shell: bash
 
diff --git a/.github/actions/setup_toolchain/espressif/action.yml b/.github/actions/setup_toolchain/espressif/action.yml
index e9d645ac8..90ef753c4 100644
--- a/.github/actions/setup_toolchain/espressif/action.yml
+++ b/.github/actions/setup_toolchain/espressif/action.yml
@@ -7,7 +7,7 @@ inputs:
   toolchain_version:
     description: 'Toolchain version'
     required: false
-    default: 'v5.3.2'
+    default: 'v5.5.3'
 
 runs:
   using: "composite"
diff --git a/.github/membrowse_pr_message.j2 b/.github/membrowse_pr_message.j2
new file mode 100644
index 000000000..fbba1ee78
--- /dev/null
+++ b/.github/membrowse_pr_message.j2
@@ -0,0 +1,38 @@
+{#- Top 10 targets with biggest memory changes + project dashboard link -#}
+{% set section_columns = ['.text', '.rodata', '.data', '.bss'] -%}
+{#- --- Compute per-target total absolute delta and collect changed targets --- -#}
+{% set changed = [] -%}
+{% for target in targets -%}
+{% if target.has_changes -%}
+{% set ns = namespace(total_delta=0, total_current=0) -%}
+{% for region in target.regions -%}
+{% set ns.total_delta = ns.total_delta + region.delta -%}
+{% set ns.total_current = ns.total_current + region.used_size -%}
+{% endfor -%}
+{% set total_old = ns.total_current - ns.total_delta -%}
+{% set pct = (ns.total_delta / total_old * 100) if total_old > 0 else 0 -%}
+{% set abs_pct = (ns.total_delta | abs) if total_old == 0 else (pct | abs) -%}
+{% set _ = changed.append({'target': target, 'total_current': ns.total_current, 'total_old': total_old, 'total_delta': ns.total_delta, 'pct': pct, 'abs_pct': abs_pct}) -%}
+{% endif -%}
+{% endfor -%}
+{#- --- Sort by absolute percentage change descending and take top 10 --- -#}
+{% set sorted_changed = changed | sort(attribute='abs_pct', reverse=true) -%}
+{% set top10 = sorted_changed[:10] -%}
+{#- --- Render --- -#}
+{% if top10 %}
+### Top {{ top10 | length }} targets by memory change (%) (out of {{ targets | length }} targets) {% if dashboard_url %} [View Project Dashboard →]({{ dashboard_url }}){% endif %}
+
+| target | .text | .rodata | .data | .bss | total | % diff |
+|--------|-------|---------|-------|------|-------|--------|
+{% for info in top10 -%}
+{% set target = info.target -%}
+{% set section_map = {} -%}
+{% for section in target.sections -%}
+{% set _ = section_map.update({section.name: section}) -%}
+{% endfor -%}
+| {% if target.comparison_url %}[{{ target.name }}]({{ target.comparison_url }}){% else %}{{ target.name }}{% endif %} |
+{%- for col in section_columns %} {% if col in section_map %}{{ "{:,}".format(section_map[col].old.size) }} → {{ "{:,}".format(section_map[col].size) }} ({{ section_map[col].delta_str }}){% else %}—{% endif %} |{% endfor %} {{ "{:,}".format(info.total_old) }} → {{ "{:,}".format(info.total_current) }} ({% if info.total_delta >= 0 %}+{{ "{:,}".format(info.total_delta) }}{% else %}{{ "{:,}".format(info.total_delta) }}{% endif %}) | {% if info.total_old > 0 %}{% if info.pct >= 0 %}+{% endif %}{{ "%.1f" | format(info.pct) }}%{% else %}N/A{% endif %} |
+{% endfor %}
+{% else %}
+No memory changes detected across {{ targets | length }} target{{ 's' if targets | length != 1 else '' }}.{% if dashboard_url %} [View Project Dashboard →]({{ dashboard_url }}){% endif %}
+{% endif -%}
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
deleted file mode 100644
index aa148eb79..000000000
--- a/.github/pull_request_template.md
+++ /dev/null
@@ -1,5 +0,0 @@
-**Describe the PR**
-A clear and concise description of what this PR solve.
-
-**Additional context**
-If applicable, add any other context about the PR and/or screenshots here.
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 781d3b002..ab1d3611f 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -3,32 +3,11 @@ name: Build
 on:
   workflow_dispatch:
   push:
-    paths:
-      - 'src/**'
-      - 'examples/**'
-      - 'lib/**'
-      - 'hw/**'
-      - 'tools/build.py'
-      - 'tools/get_deps.py'
-      - '.github/actions/**'
-      - '.github/workflows/build.yml'
-      - '.github/workflows/build_util.yml'
-      - '.github/workflows/ci_set_matrix.py'
+    branches: [master]
   pull_request:
-    paths:
-      - 'src/**'
-      - 'examples/**'
-      - 'lib/**'
-      - 'hw/**'
-      - 'test/hil/**'
-      - 'tools/build.py'
-      - 'tools/get_deps.py'
-      - '.github/actions/**'
-      - '.github/workflows/build.yml'
-      - '.github/workflows/build_util.yml'
-      - '.github/workflows/ci_set_matrix.py'
   release:
     types: [ published ]
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.ref }}
   cancel-in-progress: true
@@ -37,6 +16,36 @@ env:
   HIL_JSON: test/hil/tinyusb.json
 
 jobs:
+  # Check if the code changes and we need to run ci build
+  # Cannot use paths filter in the on-event since we want this workflow to run even when there are no code changes, to register the commit chain
+  check-paths:
+    runs-on: ubuntu-latest
+    permissions:
+      contents: read
+      pull-requests: read
+    outputs:
+      code_changed: ${{ steps.filter.outputs.code }}
+    steps:
+      - uses: actions/checkout@v6
+        with:
+          fetch-depth: 2  # Needed for push commit comparison
+      - uses: dorny/paths-filter@v3
+        id: filter
+        with:
+          filters: |
+            code:
+              - 'src/**'
+              - 'examples/**'
+              - 'lib/**'
+              - 'hw/**'
+              - 'test/hil/**'
+              - 'tools/build.py'
+              - 'tools/get_deps.py'
+              - '.github/actions/**'
+              - '.github/workflows/build.yml'
+              - '.github/workflows/build_util.yml'
+              - '.github/workflows/ci_set_matrix.py'
+
   set-matrix:
     runs-on: ubuntu-latest
     outputs:
@@ -64,7 +73,7 @@ jobs:
   # For Make and IAR build: will be done on CircleCI only (one random per family as well)
   # ------------------------------------------------------------------------------
   cmake:
-    needs: set-matrix
+    needs: [ check-paths, set-matrix ]
     uses: ./.github/workflows/build_util.yml
     strategy:
       fail-fast: false
@@ -82,9 +91,14 @@ jobs:
       build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
       build-options: '--one-first'
       upload-metrics: true
+      upload-artifacts: false
+      upload-membrowse: true
+      code-changed: ${{ needs.check-paths.outputs.code_changed == 'true' }}
+    secrets: inherit
 
   code-metrics:
-    needs: cmake
+    needs: [ check-paths, cmake ]
+    if: needs.check-paths.outputs.code_changed == 'true'
     runs-on: ubuntu-latest
     permissions:
       pull-requests: write
@@ -181,24 +195,29 @@ jobs:
   # Build Make/CMake on Windows/MacOS
   # ---------------------------------------
   build-os:
-    if: github.event_name == 'pull_request'
+    needs: [ check-paths ]
+    if: needs.check-paths.outputs.code_changed == 'true'
     uses: ./.github/workflows/build_util.yml
     strategy:
       fail-fast: false
       matrix:
         os: [ windows-latest, macos-latest ]
+        build-system: [ 'make', 'cmake' ]
     with:
       os: ${{ matrix.os }}
-      build-system: 'cmake-make'
+      build-system: ${{ matrix.build-system }}
       toolchain: 'arm-gcc-${{ matrix.os }}'
-      build-args: '["stm32h7"]'
+      build-args: '["stm32h7rs"]'
       build-options: '--one-random'
 
   # ---------------------------------------
   # Zephyr
   # ---------------------------------------
   zephyr:
-    if: github.event_name == 'push'
+    needs: [ check-paths ]
+    # skip zephyr build due to failed build, fix later
+    if: false
+    #if: needs.check-paths.outputs.code_changed == 'true'
     runs-on: ubuntu-latest
     steps:
       - name: Checkout TinyUSB
@@ -220,10 +239,8 @@ jobs:
   # Run on PR only (hil-tinyusb), hil-hfp only run on non-forked PR
   # ---------------------------------------
   hil-build:
-    if: |
-      github.repository_owner == 'hathach' &&
-      (github.event_name == 'pull_request' || github.event_name == 'workflow_dispatch')
-    needs: set-matrix
+    needs: [ check-paths, set-matrix ]
+    if: needs.check-paths.outputs.code_changed == 'true' && github.repository_owner == 'hathach'
     uses: ./.github/workflows/build_util.yml
     strategy:
       fail-fast: false
@@ -242,7 +259,6 @@ jobs:
   # self-hosted on local VM, for attached hardware checkout HIL_JSON
   # ---------------------------------------
   hil-tinyusb:
-    if: github.repository_owner == 'hathach' && github.event_name != 'push'
     needs: hil-build
     runs-on: [ self-hosted, X64, hathach, hardware-in-the-loop ]
     steps:
@@ -275,7 +291,14 @@ jobs:
 
       - name: Test on actual hardware
         run: |
-          python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS
+          python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS || \
+          (if [ -f "${{ env.HIL_JSON }}.skip" ]; then
+            SKIP_BOARDS=$(cat "${{ env.HIL_JSON }}.skip")
+            echo "Re-running with SKIP_BOARDS=$SKIP_BOARDS"
+            python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS
+          else
+            exit 1
+          fi)
 
   # ---------------------------------------
   # Hardware in the loop (HIL)
@@ -283,10 +306,11 @@ jobs:
   # Since IAR Token secret is not passed to forked PR, only build non-forked PR
   # ---------------------------------------
   hil-hfp:
+    needs: [ check-paths ]
     if: |
+      needs.check-paths.outputs.code_changed == 'true' &&
       github.repository_owner == 'hathach' &&
-      github.event.pull_request.head.repo.fork == false &&
-      github.event_name != 'push'
+      !(github.event_name == 'pull_request' && github.event.pull_request.head.repo.fork == true)
     runs-on: [ self-hosted, Linux, X64, hifiphile ]
     env:
       IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
@@ -315,7 +339,7 @@ jobs:
         run: python3 tools/get_deps.py $BUILD_ARGS
 
       - name: Build
-        run: python3 tools/build.py -j 4 --toolchain iar $BUILD_ARGS
+        run: python3 tools/build.py --toolchain iar $BUILD_ARGS
 
       - name: Test on actual hardware (hardware in the loop)
         run: python3 test/hil/hil_test.py hfp.json
diff --git a/.github/workflows/build_util.yml b/.github/workflows/build_util.yml
index 540ee8b47..d03c9af81 100644
--- a/.github/workflows/build_util.yml
+++ b/.github/workflows/build_util.yml
@@ -3,6 +3,10 @@ name: Reusable build util
 on:
   workflow_call:
     inputs:
+      os:
+        required: false
+        type: string
+        default: 'ubuntu-latest'
       build-system:
         required: true
         type: string
@@ -24,10 +28,14 @@ on:
         required: false
         default: false
         type: boolean
-      os:
+      upload-membrowse:
         required: false
-        type: string
-        default: 'ubuntu-latest'
+        default: false
+        type: boolean
+      code-changed:
+        required: false
+        default: true
+        type: boolean
 
 jobs:
   family:
@@ -39,6 +47,8 @@ jobs:
     steps:
       - name: Checkout TinyUSB
         uses: actions/checkout@v6
+        with:
+          fetch-depth: ${{ !inputs.upload-membrowse && 1 || 0 }}
 
       - name: Setup Toolchain
         id: setup-toolchain
@@ -52,29 +62,40 @@ jobs:
           arg: ${{ matrix.arg }}
 
       - name: Build
+        if: ${{ inputs.code-changed }}
         env:
           IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }}
-          TOOLCHAIN: ${{ inputs.toolchain }}
         run: |
-          if [ "$TOOLCHAIN" == "esp-idf" ]; then
-            docker run --rm -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py ${{ matrix.arg }}
-          elif [ "${{ inputs.build-system }}" == "cmake-make" ] || [ "${{ inputs.build-system }}" == "make-cmake" ]; then
-            python tools/build.py -s make ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
-            python tools/build.py -s cmake ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
+          if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then
+            docker run --rm -e MEMBROWSE_API_KEY="$MEMBROWSE_API_KEY" -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py --target all ${{ matrix.arg }}
           else
-            python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} ${{ matrix.arg }}
+            BUILD_PY_ARGS="-s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }} --target all"
+            if [ "${{ inputs.upload-metrics }}" = "true" ]; then
+              BUILD_PY_ARGS="$BUILD_PY_ARGS --target tinyusb_metrics"
+            fi
+            python tools/build.py $BUILD_PY_ARGS ${{ matrix.arg }}
           fi
         shell: bash
 
+      - name: Membrowse Upload
+        if: inputs.toolchain != 'esp-idf' && inputs.upload-membrowse == true
+        env:
+          MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }}
+        run: |
+          # if code-changed is false --> there is no elf -> membrowse target upload with --identical flag
+          BUILD_PY_ARGS="-s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ inputs.build-options }}"
+          python tools/build.py $BUILD_PY_ARGS --target examples-membrowse-upload -j 1 ${{ matrix.arg }}
+        shell: bash
+
       - name: Upload Artifacts for Metrics
-        if: ${{ inputs.upload-metrics }}
+        if: inputs.upload-metrics == true && inputs.code-changed == true
         uses: actions/upload-artifact@v5
         with:
           name: metrics-${{ matrix.arg }}
           path: cmake-build/cmake-build-*/metrics.json
 
       - name: Upload Artifacts for Hardware Testing
-        if: ${{ inputs.upload-artifacts }}
+        if: inputs.upload-artifacts == true && inputs.code-changed == true
         uses: actions/upload-artifact@v5
         with:
           name: binaries-${{ matrix.arg }}
@@ -86,3 +107,4 @@ jobs:
             cmake-build/cmake-build-*/*/*/partition_table/partition-table.bin
             cmake-build/cmake-build-*/*/*/config.env
             cmake-build/cmake-build-*/*/*/flash_args
+            cmake-build/hw/mcu/**/*.ld
diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py
index c276d5253..cd7dfa76b 100755
--- a/.github/workflows/ci_set_matrix.py
+++ b/.github/workflows/ci_set_matrix.py
@@ -15,30 +15,76 @@ toolchain_list = [
 
 # family: [supported toolchain]
 family_list = {
-    "at32f402_405 at32f403a_407 at32f413 at32f415 at32f423 at32f425 at32f435_437 broadcom_32bit da1469x": ["arm-gcc"],
+    "at32f402_405": ["arm-gcc"],
+    "at32f403a_407": ["arm-gcc"],
+    "at32f413": ["arm-gcc"],
+    "at32f415": ["arm-gcc"],
+    "at32f423": ["arm-gcc"],
+    "at32f425": ["arm-gcc"],
+    "at32f435_437": ["arm-gcc"],
+    "at32f45x": ["arm-gcc"],
+    "broadcom_32bit": ["arm-gcc"],
     "broadcom_64bit": ["aarch64-gcc"],
-    "ch32v10x ch32v20x ch32v30x fomu gd32vf103 hpmicro": ["riscv-gcc"],
+    "ch32v10x": ["riscv-gcc"],
+    "ch32v20x": ["riscv-gcc"],
+    "ch32v30x": ["riscv-gcc"],
+    "da1469x": ["arm-gcc"],
+    "fomu": ["riscv-gcc"],
+    "gd32vf103": ["riscv-gcc"],
+    "hpmicro": ["riscv-gcc"],
     "imxrt": ["arm-gcc", "arm-clang"],
-    "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"],
-    "lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"],
-    "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"],
-    "maxim mcx mm32 msp432e4 rw61x tm4c": ["arm-gcc"],
+    "kinetis_k": ["arm-gcc", "arm-clang"],
+    "kinetis_k32l2": ["arm-gcc", "arm-clang"],
+    "kinetis_kl": ["arm-gcc", "arm-clang"],
+    "lpc11": ["arm-gcc", "arm-clang"],
+    "lpc13": ["arm-gcc", "arm-clang"],
+    "lpc15": ["arm-gcc", "arm-clang"],
+    "lpc17": ["arm-gcc", "arm-clang"],
+    "lpc18": ["arm-gcc", "arm-clang"],
+    "lpc40": ["arm-gcc", "arm-clang"],
+    "lpc43": ["arm-gcc", "arm-clang"],
+    "lpc51": ["arm-gcc", "arm-clang"],
+    "lpc54": ["arm-gcc", "arm-clang"],
+    "lpc55": ["arm-gcc", "arm-clang"],
+    "maxim": ["arm-gcc"],
+    "mcx": ["arm-gcc"],
+    "mm32": ["arm-gcc"],
     "msp430": ["msp430-gcc"],
+    "msp432e4": ["arm-gcc"],
     "nrf": ["arm-gcc", "arm-clang"],
-    "nuc100_120 nuc121_125 nuc126 nuc505 xmc4000": ["arm-gcc"],
+    "nuc100_120": ["arm-gcc"],
+    "nuc121_125": ["arm-gcc"],
+    "nuc126": ["arm-gcc"],
+    "nuc505": ["arm-gcc"],
     "ra": ["arm-gcc"],
     "rp2040": ["arm-gcc"],
+    "rw61x": ["arm-gcc"],
     "rx": ["rx-gcc"],
-    "samd11 samd2x_l2x samd5x_e5x samg": ["arm-gcc", "arm-clang"],
-    "stm32c0 stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
+    "samd11": ["arm-gcc", "arm-clang"],
+    "samd2x_l2x": ["arm-gcc", "arm-clang"],
+    "samd5x_e5x": ["arm-gcc", "arm-clang"],
+    "samg": ["arm-gcc", "arm-clang"],
+    "stm32c0": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f0": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f1": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f2": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
     "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"],
     "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"],
-    "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32g0": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32g4": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
     "stm32h7": ["arm-gcc", "arm-clang", "arm-iar"],
-    "stm32h7rs stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32h7rs": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32l0": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
     "stm32n6": ["arm-gcc"],
-    "stm32u0 stm32u5 stm32wb stm32wba": ["arm-gcc", "arm-clang", "arm-iar"],
-    "-bespressif_s2_devkitc": ["esp-idf"],
+    "stm32u0": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32u5": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32wba": ["arm-gcc", "arm-clang", "arm-iar"],
+    "tm4c": ["arm-gcc"],
+    "xmc4000": ["arm-gcc"],
     # S3, P4 will be built by hil test
     # "-bespressif_s3_devkitm": ["esp-idf"],
     # "-bespressif_p4_function_ev": ["esp-idf"],
diff --git a/.github/workflows/claude-code-review.yml b/.github/workflows/claude-code-review.yml
new file mode 100644
index 000000000..5d7efc115
--- /dev/null
+++ b/.github/workflows/claude-code-review.yml
@@ -0,0 +1,32 @@
+name: Claude Code Review
+
+on:
+  pull_request_target:
+    types: [opened, synchronize, ready_for_review, reopened]
+
+jobs:
+  claude-review:
+    if: false
+    runs-on: ubuntu-latest
+    permissions:
+      contents: read
+      pull-requests: write
+      issues: read
+      id-token: write
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+        with:
+          fetch-depth: 1
+
+      - name: Run Claude Code Review
+        id: claude-review
+        uses: anthropics/claude-code-action@v1
+        with:
+          claude_code_oauth_token: ${{ secrets.CLAUDE_CODE_OAUTH_TOKEN }}
+          plugin_marketplaces: 'https://github.com/anthropics/claude-code.git'
+          plugins: 'code-review@claude-code-plugins'
+          prompt: '/code-review:code-review ${{ github.repository }}/pull/${{ github.event.pull_request.number }}'
+          # See https://github.com/anthropics/claude-code-action/blob/main/docs/usage.md
+          # or https://code.claude.com/docs/en/cli-reference for available options
diff --git a/.github/workflows/claude.yml b/.github/workflows/claude.yml
new file mode 100644
index 000000000..9471a0591
--- /dev/null
+++ b/.github/workflows/claude.yml
@@ -0,0 +1,49 @@
+name: Claude Code
+
+on:
+  issue_comment:
+    types: [created]
+  pull_request_review_comment:
+    types: [created]
+  issues:
+    types: [opened, assigned]
+  pull_request_review:
+    types: [submitted]
+
+jobs:
+  claude:
+    if: |
+      (github.event_name == 'issue_comment' && contains(github.event.comment.body, '@claude')) ||
+      (github.event_name == 'pull_request_review_comment' && contains(github.event.comment.body, '@claude')) ||
+      (github.event_name == 'pull_request_review' && contains(github.event.review.body, '@claude')) ||
+      (github.event_name == 'issues' && (contains(github.event.issue.body, '@claude') || contains(github.event.issue.title, '@claude')))
+    runs-on: ubuntu-latest
+    permissions:
+      contents: read
+      pull-requests: read
+      issues: read
+      id-token: write
+      actions: read # Required for Claude to read CI results on PRs
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v4
+        with:
+          fetch-depth: 1
+
+      - name: Run Claude Code
+        id: claude
+        uses: anthropics/claude-code-action@v1
+        with:
+          claude_code_oauth_token: ${{ secrets.CLAUDE_CODE_OAUTH_TOKEN }}
+
+          # This is an optional setting that allows Claude to read CI results on PRs
+          additional_permissions: |
+            actions: read
+
+          # Optional: Give a custom prompt to Claude. If this is not specified, Claude will perform the instructions specified in the comment that tagged it.
+          # prompt: 'Update the pull request description to include a summary of changes.'
+
+          # Optional: Add claude_args to customize behavior and configuration
+          # See https://github.com/anthropics/claude-code-action/blob/main/docs/usage.md
+          # or https://code.claude.com/docs/en/cli-reference for available options
+          # claude_args: '--allowed-tools Bash(gh pr:*)'
diff --git a/.github/workflows/membrowse-comment.yml b/.github/workflows/membrowse-comment.yml
new file mode 100644
index 000000000..368a52638
--- /dev/null
+++ b/.github/workflows/membrowse-comment.yml
@@ -0,0 +1,31 @@
+name: Membrowse Comment
+
+on:
+  workflow_run:
+    workflows: ["Build"]
+    types:
+      - completed
+
+jobs:
+  post-comment:
+    runs-on: ubuntu-latest
+    if: >
+      github.event.workflow_run.event == 'pull_request' &&
+      github.event.workflow_run.conclusion == 'success'
+    permissions:
+      contents: read
+      actions: read
+      pull-requests: write
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v6
+
+      - name: Post Membrowse PR comment
+        if: ${{ secrets.MEMBROWSE_API_KEY != '' }}
+        uses: membrowse/membrowse-action/comment-action@v1
+        with:
+          api_key: ${{ secrets.MEMBROWSE_API_KEY }}
+          commit: ${{ github.event.workflow_run.head_sha }}
+          comment_template: .github/membrowse_pr_message.j2
+        env:
+          GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
diff --git a/.github/workflows/membrowse-onboard.yml b/.github/workflows/membrowse-onboard.yml
new file mode 100644
index 000000000..aa7204ffa
--- /dev/null
+++ b/.github/workflows/membrowse-onboard.yml
@@ -0,0 +1,62 @@
+name: Onboard to Membrowse
+
+on:
+  workflow_dispatch:
+    inputs:
+      num_commits:
+        description: 'Number of commits to process'
+        required: true
+        default: '10'
+        type: string
+
+jobs:
+  load-targets:
+    runs-on: ubuntu-22.04
+    outputs:
+      targets: ${{ steps.load.outputs.targets }}
+      toolchains: ${{ steps.load.outputs.toolchains }}
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v5
+
+      - name: Load target matrix
+        id: load
+        run: |
+          echo "targets=$(jq -c '.targets' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT
+          echo "toolchains=$(jq -c '.toolchains' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT
+
+  onboard:
+    needs: load-targets
+    runs-on: ubuntu-22.04
+    strategy:
+      fail-fast: false
+      matrix:
+        include: ${{ fromJson(needs.load-targets.outputs.targets) }}
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v5
+        with:
+          fetch-depth: 0
+          submodules: recursive
+
+      - name: Install packages
+        run: |
+          ${{ fromJson(needs.load-targets.outputs.toolchains)[matrix.toolchain].setup_cmd }} && python3 tools/get_deps.py ${{ matrix.get_deps || matrix.port }}
+
+      - name: Setup ccache
+        uses: hendrikmuhs/[email protected]
+        with:
+          key: ${{ matrix.port }}-${{ matrix.board }}
+
+      - name: Run Membrowse Onboard Action
+        uses: membrowse/membrowse-action/onboard-action@v1
+        with:
+          target_name: ${{ matrix.port }}-${{ matrix.board }}-${{ matrix.example }}
+          num_commits: ${{ github.event.inputs.num_commits }}
+          build_script: python3 tools/build.py -s cmake -b ${{ matrix.board }}
+          elf: cmake-build/cmake-build-${{ matrix.board }}/device/${{ matrix.example }}/${{ matrix.example }}.elf
+          ld: ${{ matrix.ld }}
+          linker_vars: ${{ matrix.linker_vars || '' }}
+          api_key: ${{ secrets.MEMBROWSE_API_KEY }}
+          api_url: ${{ vars.MEMBROWSE_API_URL }}
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 0754253ad..6f87e2a29 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -96,6 +96,7 @@
       <configuration PROFILE_NAME="itsybitsy_m4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=itsybitsy_m4" />
       <configuration PROFILE_NAME="same54_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same54_xplained -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="samg55_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=samg55_xplained" />
+      <configuration PROFILE_NAME="same70_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same70_xplained -DLOG=1" />
       <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="nrf52840dk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nrf52840dk -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="nrf52840dk-zephyr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nrf52840dk -DLOG=1 -DTRACE_ETM=1 -DRTOS=zephyr" BUILD_OPTIONS="-v" />
@@ -103,6 +104,8 @@
       <configuration PROFILE_NAME="metro m7 1011 sd" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011_sd -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="metro_m7_1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1024 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1024_evk -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1050 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1050_evkb -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mimxrt1060_evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=1" />
       <configuration PROFILE_NAME="mimxrt1064_evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
       <configuration PROFILE_NAME="rt1170 evkb" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1170_evkb -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
@@ -126,8 +129,10 @@
       <configuration PROFILE_NAME="stm32h743eval_host1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DRHPORT_HOST=1 -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32h743eval IAR" ENABLED="false" CONFIG_NAME="Debug" TOOLCHAIN_NAME="iccarm" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1 -DIAR_CSTAT=1" />
       <configuration PROFILE_NAME="stm32h743nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743nucleo -DLOG=1" />
+      <configuration PROFILE_NAME="stm32h7s3nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h7s3nucleo -DLOG=1" />
       <configuration PROFILE_NAME="stm32l0538disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l0538disco -DLOG=0 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32u083cdk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u083cdk -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32u5a5nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u5a5nucleo -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32wb55nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32wb55nucleo" />
@@ -167,6 +172,7 @@
       <configuration PROFILE_NAME="mm32f327x_mb39" ENABLED="false" GENERATION_OPTIONS="-DBOARD=mm32f327x_mb39" />
       <configuration PROFILE_NAME="fomu" ENABLED="false" GENERATION_OPTIONS="-DBOARD=fomu" />
       <configuration PROFILE_NAME="sipeed_longan_nano" ENABLED="false" GENERATION_OPTIONS="-DBOARD=sipeed_longan_nano" />
+      <configuration PROFILE_NAME="ch32v103r_r1_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v103r_r1_1v0" />
       <configuration PROFILE_NAME="nanoch32v203" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nanoch32v203" />
       <configuration PROFILE_NAME="ch32v203c_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DLOG=0" />
       <configuration PROFILE_NAME="ch32v203c_r0_1v0 USBFS" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DPORT=1" />
diff --git a/.idea/debugServers/ST_LINK.xml b/.idea/debugServers/ST_LINK.xml
index 7c21d3879..c4dadd5bb 100644
--- a/.idea/debugServers/ST_LINK.xml
+++ b/.idea/debugServers/ST_LINK.xml
@@ -1,10 +1,10 @@
 <component name="DebugServers">
-  <stlink-debug-target name="ST-LINK" uniqueID="300d1a6f-85c0-4eb3-9753-f033d01e2eff">
+  <stlink-debug-target name="ST-LINK" uniqueID="cf98f5f4-9c5b-4340-ab06-16ddd7f07062">
     <debugger version="1">
       <debugger kind="GDB" isBundled="true" />
       <env />
     </debugger>
-    <gdbserver exe="$USER_HOME$/st/stm32cubeide_1.16.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.1.400.202404281720/tools/bin/ST-LINK_gdbserver" programmer="$USER_HOME$/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin" />
+    <gdbserver exe="/opt/st/stm32cubeclt_1.20.0/STLink-gdb-server/bin/ST-LINK_gdbserver" programmer="/opt/st/stm32cubeclt_1.20.0/STM32CubeProgrammer/bin" />
     <st-link />
     <device interface="SWD" />
     <connection port="61234" warmup-ms="500" />
diff --git a/.idea/debugServers/mcxa153.xml b/.idea/debugServers/mcxa153.xml
new file mode 100644
index 000000000..0e493cbd5
--- /dev/null
+++ b/.idea/debugServers/mcxa153.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="mcxa153" uniqueID="6a023429-69e6-4f8c-a592-4995cdf255db">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="MCXA153" reset-before="false" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/ra6m1.xml b/.idea/debugServers/ra6m1.xml
new file mode 100644
index 000000000..17c902ec4
--- /dev/null
+++ b/.idea/debugServers/ra6m1.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="ra6m1" uniqueID="c8cdc79a-939b-4342-92b1-d24da72d12fe">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="R7FA6M1AD" reset-before="false" frequency="16000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/ra6m5.xml b/.idea/debugServers/ra6m5.xml
new file mode 100644
index 000000000..d8dfbdeeb
--- /dev/null
+++ b/.idea/debugServers/ra6m5.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="ra6m5" uniqueID="19100d9f-7329-47da-b566-f9faf297f47c">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="R7FA6M5BH" reset-before="false" frequency="16000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/rt1011.xml b/.idea/debugServers/rt1011.xml
new file mode 100644
index 000000000..b4be501bd
--- /dev/null
+++ b/.idea/debugServers/rt1011.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="rt1011" uniqueID="e10c53c4-acf5-4a6f-a05d-32b7b042d70a">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="MIMXRT1011xxx5A" reset-before="false" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/rt1170.xml b/.idea/debugServers/rt1170.xml
new file mode 100644
index 000000000..9a564ed57
--- /dev/null
+++ b/.idea/debugServers/rt1170.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="rt1170" uniqueID="cfc772e4-782e-49a3-99fb-b6f726e14f9d">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="MIMXRT1176xxxA_M7" reset-before="false" frequency="16000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/stm32f072.xml b/.idea/debugServers/stm32f072.xml
new file mode 100644
index 000000000..c56f5a8fb
--- /dev/null
+++ b/.idea/debugServers/stm32f072.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="stm32f072" uniqueID="f5c65701-0f8d-4923-a7ea-3ee2547147ae">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="STM32F072RB" reset-before="false" frequency="12000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/stm32f303.xml b/.idea/debugServers/stm32f303.xml
new file mode 100644
index 000000000..84aafc1e3
--- /dev/null
+++ b/.idea/debugServers/stm32f303.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="stm32f303" uniqueID="1cdd63e5-1736-42be-bff3-4c48e1f169fa">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="STM32F303VC" reset-before="false" frequency="12000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/.idea/debugServers/stm32l053.xml b/.idea/debugServers/stm32l053.xml
new file mode 100644
index 000000000..5365189cc
--- /dev/null
+++ b/.idea/debugServers/stm32l053.xml
@@ -0,0 +1,13 @@
+<component name="DebugServers">
+  <jlink-debug-target name="stm32l053" uniqueID="51d156d7-86a6-4006-814a-ed14981d7b49">
+    <debugger version="1">
+      <debugger kind="GDB" isBundled="true" />
+      <env />
+    </debugger>
+    <gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
+    <console port="19021" />
+    <target device="STM32L053R8" reset-before="false" frequency="12000" />
+    <connection extended-remote="false" port="4444" warmup-ms="500" />
+    <swo />
+  </jlink-debug-target>
+</component>
+\ No newline at end of file
diff --git a/AGENTS.md b/AGENTS.md
index 73bf1f599..bbbd7c36d 100644
--- a/AGENTS.md
+++ b/AGENTS.md
@@ -21,6 +21,8 @@ information that does not match the info here.
 - For specific board families: `python3 tools/get_deps.py FAMILY_NAME` (e.g., rp2040, stm32f4), or
   `python3 tools/get_deps.py -b BOARD_NAME`
 - Dependencies are cached in `lib/` and `hw/mcu/` directories
+- For **Espressif** boards, initialize the ESP-IDF environment before any build/flash/monitor command:
+  `. $HOME/code/esp-idf/export.sh`
 
 ## Build Examples
 
@@ -59,6 +61,19 @@ make BOARD=raspberry_pi_pico all
 
 -- takes 2-3 seconds. NEVER CANCEL. Set timeout to 5+ minutes.
 
+**Option 4: Espressif Example with ESP-IDF**
+
+Only ESP-IDF-enabled examples are supported for Espressif boards. Use FreeRTOS examples such as `examples/device/cdc_msc_freertos`
+that contain `idf_component_register()` support.
+
+```bash
+. $HOME/code/esp-idf/export.sh
+cd examples/device/cdc_msc_freertos
+idf.py -DBOARD=espressif_s3_devkitc build
+```
+
+Use `-DBOARD=...` with any supported board under `hw/bsp/espressif/boards/`. NEVER CANCEL. Set timeout to 10+ minutes.
+
 
 ## Build Options
 
@@ -90,6 +105,81 @@ make BOARD=raspberry_pi_pico all
     - CMake: `ninja cdc_msc-uf2`
     - Make: `make BOARD=raspberry_pi_pico all uf2`
 - **List all targets** (CMake/Ninja): `ninja -t targets`
+- **Espressif flash**:
+    - Run `. $HOME/code/esp-idf/export.sh`
+    - `cd examples/device/cdc_msc_freertos`
+    - `idf.py -DBOARD=espressif_s3_devkitc flash`
+- **Espressif serial monitor / chip log output**:
+    - Run `. $HOME/code/esp-idf/export.sh`
+    - `cd examples/device/cdc_msc_freertos`
+    - `idf.py -DBOARD=espressif_s3_devkitc monitor`
+
+## GDB Debugging
+
+Look up the board's `JLINK_DEVICE` and `OPENOCD_OPTION` from `hw/bsp/*/boards/*/board.cmake` (or `board.mk`).
+
+### JLinkGDBServer
+
+**Terminal 1 – start the GDB server:**
+```bash
+JLinkGDBServer -device stm32h743xi -if SWD -speed 4000 \
+  -port 2331 -swoport 2332 -telnetport 2333 -nogui
+```
+
+**Terminal 2 – connect GDB:**
+```bash
+arm-none-eabi-gdb /tmp/build/firmware.elf
+(gdb) target remote :2331
+(gdb) monitor reset halt
+(gdb) load
+(gdb) continue
+```
+
+To break on entry instead of running immediately:
+```bash
+(gdb) monitor reset halt
+(gdb) load
+(gdb) break main
+(gdb) continue
+```
+
+### OpenOCD
+
+**Terminal 1 – start the GDB server:**
+```bash
+openocd -f interface/stlink.cfg -f target/stm32h7x.cfg
+# or with J-Link probe:
+openocd -f interface/jlink.cfg -f target/stm32h7x.cfg
+```
+
+For boards that define `OPENOCD_OPTION` in `board.cmake`, use those options directly:
+```bash
+openocd $(cat hw/bsp/FAMILY/boards/BOARD/board.cmake | grep OPENOCD_OPTION | ...)
+```
+
+**Terminal 2 – connect GDB (OpenOCD default port is 3333):**
+```bash
+arm-none-eabi-gdb /tmp/build/firmware.elf
+(gdb) target remote :3333
+(gdb) monitor reset halt
+(gdb) load
+(gdb) continue
+```
+
+### RTT Logging with JLinkGDBServer
+
+- Build with RTT logging enabled (example):
+  `cd examples/device/cdc_msc && make BOARD=stm32h743eval LOG=2 LOGGER=rtt all`
+- Flash with J-Link:
+  `cd examples/device/cdc_msc && make BOARD=stm32h743eval LOG=2 LOGGER=rtt flash-jlink`
+- Launch GDB server with RTT port (keep this running in terminal 1):
+  `JLinkGDBServer -device stm32h743xi -if SWD -speed 4000 -port 2331 -swoport 2332 -telnetport 2333 -RTTTelnetPort 19021 -nogui`
+- Read RTT output (terminal 2):
+  `JLinkRTTClient`
+- Capture RTT to file (optional):
+  `JLinkRTTClient | tee rtt.log`
+- For non-interactive capture:
+  `timeout 20s JLinkRTTClient > rtt.log`
 
 ## Unit Testing
 
@@ -101,9 +191,15 @@ make BOARD=raspberry_pi_pico all
 
 ## Hardware-in-the-Loop (HIL) Testing
 
+- `-B examples` means `examples` is the parent folder that contains multi-board build outputs such as `examples/cmake-build-BOARD_NAME/...`
+- Select config file before running HIL tests:
+    - if GitHub Actions self-hosted runner service is running, use `tinyusb.json`
+    - otherwise use `local.json`
+    - example:
+      `HIL_CONFIG=$( (systemctl list-units --type=service --state=running 2>/dev/null; systemctl --user list-units --type=service --state=running 2>/dev/null) | grep -q 'actions\.runner' && echo tinyusb.json || echo local.json )`
 - Run tests on actual hardware, one of following ways:
-    - test a specific board `python test/hil/hil_test.py -b BOARD_NAME -B examples local.json`
-    - test all boards in config `python test/hil/hil_test.py -B examples local.json`
+    - test a specific board `python test/hil/hil_test.py -b BOARD_NAME -B examples $HIL_CONFIG`
+    - test all boards in config `python test/hil/hil_test.py -B examples $HIL_CONFIG`
 - In case of error, enabled verbose mode with `-v` flag for detailed logs. Also try to observe script output, and try to
   modify hil_test.py (temporarily) to add more debug prints to pinpoint the issue.
 - Requires pre-built (all) examples for target boards (see Build Examples section 2)
@@ -236,6 +332,9 @@ take 2-5 minutes. NEVER CANCEL. Set timeout to 20+ minutes.
 - `examples/device/cdc_msc/`: Most commonly used example for testing
 - `test/unit-test/project.yml`: Ceedling test configuration
 
+#### MCU Reference Manuals and Datasheets
+- Look in `$HOME/Documents/Calibre Library` for all MCU reference manuals, datasheets and board schematics.
+
 #### Debugging Build Issues
 - **Missing compiler**: Install `gcc-arm-none-eabi` package
 - **Missing dependencies**: Run `python3 tools/get_deps.py FAMILY`
diff --git a/CLAUDE.md b/CLAUDE.md
new file mode 120000
index 000000000..47dc3e3d8
--- /dev/null
+++ b/CLAUDE.md
@@ -0,0 +1 @@
+AGENTS.md
+\ No newline at end of file
diff --git a/README.rst b/README.rst
index 2ad0b3439..ba42a7afe 100644
--- a/README.rst
+++ b/README.rst
@@ -1,7 +1,7 @@
 TinyUSB
 =======
 
-|Build Status| |CircleCI Status| |Documentation Status| |Static Analysis| |Fuzzing Status| |License|
+|Build Status| |CircleCI Status| |Documentation Status| |Static Analysis| |Fuzzing Status| |Membrowse| |License|
 
 Sponsors
 --------
@@ -87,6 +87,7 @@ Supports multiple device configurations by dynamically changing USB descriptors,
 -  Communication Device Class (CDC)
 -  Device Firmware Update (DFU): DFU mode (WIP) and Runtime
 -  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
+-  Printer class
 -  Mass Storage Class (MSC): with multiple LUNs
 -  Musical Instrument Digital Interface (MIDI)
 -  Media Transfer Protocol (MTP/PTP)
@@ -101,10 +102,11 @@ If you have a special requirement, ``usbd_app_driver_get_cb()`` can be used to w
 Host Stack
 ----------
 
-- Human Interface Device (HID): Keyboard, Mouse, Generic
-- Mass Storage Class (MSC)
 - Communication Device Class: CDC-ACM
 - Vendor serial over USB: FTDI, CP210x, CH34x, PL2303
+- Human Interface Device (HID): Keyboard, Mouse, Generic
+- Mass Storage Class (MSC)
+- Musical Instrument Digital Interface (MIDI)
 - Hub with multiple-level support
 
 Similar to the Device Stack, if you have a special requirement, ``usbh_app_driver_get_cb()`` can be used to write your own class driver without modifying the stack.
@@ -141,7 +143,8 @@ Supported CPUs
 +--------------+-----------------------------+--------+------+-----------+------------------------+--------------------+
 | Artery AT32  | F403a_407, F413             | ✔      |      |           | fsdev                  | 512 USB RAM        |
 |              +-----------------------------+--------+------+-----------+------------------------+--------------------+
-|              | F415, F435_437, F423, F425  | ✔      | ✔    |           | dwc2                   |                    |
+|              | F415, F435_437, F423,       | ✔      | ✔    |           | dwc2                   |                    |
+|              | F425, F45x                  |        |      |           |                        |                    |
 |              +-----------------------------+--------+------+-----------+------------------------+--------------------+
 |              | F402_F405                   | ✔      | ✔    | ✔         | dwc2                   | F405 is HS         |
 +--------------+-----------------------------+--------+------+-----------+------------------------+--------------------+
@@ -203,7 +206,9 @@ Supported CPUs
 |              |         +-------------------+--------+------+-----------+------------------------+--------------------+
 |              |         | 51u               | ✔      | ✖    | ✖         | lpc_ip3511             |                    |
 |              |         +-------------------+--------+------+-----------+------------------------+--------------------+
-|              |         | 54, 55            | ✔      |      | ✔         | lpc_ip3511             |                    |
+|              |         | 54                | ⚠      | ⚠    | ✔         | lpc_ip3511, lpc_ip3516 | NRND, read errata |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | 55                | ✔      | ✔    | ✔         | lpc_ip3511, lpc_ip3516 |                    |
 |              +---------+-------------------+--------+------+-----------+------------------------+--------------------+
 |              | MCX     | N9                | ✔      |      | ✔         | ci_fs, ci_hs, ehci     |                    |
 |              |         +-------------------+--------+------+-----------+------------------------+--------------------+
@@ -292,6 +297,8 @@ The following tools are provided freely to support the development of the TinyUS
    :target: https://github.com/hathach/tinyusb/actions/workflows/static_analysis.yml
 .. |Fuzzing Status| image:: https://oss-fuzz-build-logs.storage.googleapis.com/badges/tinyusb.svg
    :target: https://oss-fuzz-build-logs.storage.googleapis.com/index.html#tinyusb
+.. |Membrowse| image:: https://membrowse.com/badge.svg
+   :target: https://membrowse.com/public/hathach/tinyusb
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
 
diff --git a/docs/faq.rst b/docs/faq.rst
index a5fe09495..97e8e72ff 100644
--- a/docs/faq.rst
+++ b/docs/faq.rst
@@ -15,7 +15,7 @@ Yes, TinyUSB is released under the MIT license, allowing commercial use with min
 
 **Q: Does TinyUSB require an RTOS?**
 
-No, TinyUSB works in bare metal environments. It also supports FreeRTOS, RT-Thread, and Mynewt.
+No, TinyUSB works in bare metal environments. It also supports FreeRTOS, RT-Thread, ThreadX, and Mynewt.
 
 **Q: How much memory does TinyUSB use?**
 
diff --git a/docs/getting_started.rst b/docs/getting_started.rst
index 0c3fcec80..8442305d4 100644
--- a/docs/getting_started.rst
+++ b/docs/getting_started.rst
@@ -34,7 +34,10 @@ Get the Code
    $ python tools/get_deps.py -b stm32h743eval  # or python tools/get_deps.py stm32h7
 
 .. note::
-   For rp2040 `pico-sdk <https://github.com/raspberrypi/pico-sdk>`_ or `esp-idf <https://github.com/espressif/esp-idf>`_ for Espressif targets are required; install them per vendor instructions.
+   Some MCU families require additional SDKs, please follow their instructions to install and set it up
+
+   * **rp2040**: Requires `pico-sdk <https://github.com/raspberrypi/pico-sdk>`_
+   * **Espressif (esp32)**: Requires `esp-idf <https://github.com/espressif/esp-idf>`_. Only a few examples support the ESP-IDF build system. Look for ones with `src/CMakeLists.txt` that contain `idf_component_register()`, such as `cdc_msc_freertos`.
 
 Simple Device Example
 ---------------------
diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 12da5c90b..f6dd3cd91 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -44,6 +44,9 @@ at_start_f423              AT-START-F423                  at32f423       https:/
 at_start_f425              AT-START-F425                  at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
 at_start_f435              AT-START-F435                  at32f435_437   https://www.arterychip.com/en/product/AT32F435.jsp
 at_start_f437              AT-START-F437                  at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
+at_start_f455              AT-START-F455                  at32f45x       https://www.arterychip.com/en/product/AT32F455.jsp
+at_start_f456              AT-START-F456                  at32f45x       https://www.arterychip.com/en/product/AT32F456.jsp
+at_start_f457              AT-START-F457                  at32f45x       https://www.arterychip.com/en/product/AT32F457.jsp
 =========================  =============================  =============  ====================================================  ======
 
 Bridgetek
@@ -289,6 +292,7 @@ stm32h723nucleo      STM32 H723 Nucleo                  stm32h7    https://www.s
 stm32h743eval        STM32 H743 Eval                    stm32h7    https://www.st.com/en/evaluation-tools/stm32h743i-eval.html
 stm32h743nucleo      STM32 H743 Nucleo                  stm32h7    https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
 stm32h745disco       STM32 H745 Discovery               stm32h7    https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
+stm32h747disco       STM32 H747 Discovery               stm32h7    https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
 stm32h750_weact      STM32 H750 WeAct                   stm32h7    https://www.adafruit.com/product/5032
 stm32h750bdk         STM32 H750b Discovery Kit          stm32h7    https://www.st.com/en/evaluation-tools/stm32h750b-dk.html
 waveshare_openh743i  Waveshare Open H743i               stm32h7    https://www.waveshare.com/openh743i-c-standard.htm
@@ -330,6 +334,7 @@ Board              Name                   Family    URL
 msp_exp430f5529lp  MSP430F5529 LaunchPad  msp430    https://www.ti.com/tool/MSP-EXP430F5529LP
 msp_exp432e401y    MSP432E401Y LaunchPad  msp432e4  https://www.ti.com/tool/MSP-EXP432E401Y
 ek_tm4c123gxl      TM4C123G LaunchPad     tm4c      https://www.ti.com/tool/EK-TM4C123GXL
+ek_tm4c1294xl      TM4C1294 LaunchPad     tm4c      https://www.ti.com/tool/EK-TM4C1294XL
 =================  =====================  ========  =========================================  ======
 
 Tomu
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index de1603383..ce5f265d5 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -16,6 +16,7 @@ hw/mcu/artery/at32f415                    https://github.com/ArteryTek/AT32F415_
 hw/mcu/artery/at32f423                    https://github.com/ArteryTek/AT32F423_Firmware_Library.git        2afa7f12852e57a9e8aab3a892c641e1a8635a18  at32f423
 hw/mcu/artery/at32f425                    https://github.com/ArteryTek/AT32F425_Firmware_Library.git        620233e1357d5c1b7e2bde6b9dd5196822b91817  at32f425
 hw/mcu/artery/at32f435_437                https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git    25439cc6650a8ae0345934e8707a5f38c7ae41f8  at32f435_437
+hw/mcu/artery/at32f45x                    https://github.com/ArteryTek/AT32F45x_Firmware_Library.git        3d4a1b38be8ebac292e2350ca53bc4bfa4430233  at32f45x
 hw/mcu/bridgetek/ft9xx/ft90x-sdk          https://github.com/BRTSG-FOSS/ft90x-sdk.git                       91060164afe239fcb394122e8bf9eb24d3194eb1  brtmm90x
 hw/mcu/broadcom                           https://github.com/adafruit/broadcom-peripherals.git              08370086080759ed54ac1136d62d2ad24c6fa267  broadcom_32bit broadcom_64bit
 hw/mcu/gd/nuclei-sdk                      https://github.com/Nuclei-Software/nuclei-sdk.git                 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7  gd32vf103
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 660df67cb..7173f455e 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -30,6 +30,7 @@ set(EXAMPLE_LIST
   msc_dual_lun
   mtp
   net_lwip_webserver
+  printer_to_cdc
   uac2_headset
   uac2_speaker_fb
   usbtmc
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 5767c7453..c9c6dd46c 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -155,7 +155,7 @@ void tud_resume_cb(void) {
 // In a real application, this would be replaced with actual I2S receive callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) {
     return; // not enough time
   }
@@ -408,7 +408,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/audio_4_channel_mic_freertos/skip.txt b/examples/device/audio_4_channel_mic_freertos/skip.txt
index 4c2780096..db01347ed 100644
--- a/examples/device/audio_4_channel_mic_freertos/skip.txt
+++ b/examples/device/audio_4_channel_mic_freertos/skip.txt
@@ -9,7 +9,6 @@ mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
-mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 mcu:STM32L0
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 2441eefbc..876a41d06 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -138,7 +138,7 @@ void tud_resume_cb(void) {
 // In a real application, this would be replaced with actual I2S receive callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) {
     return; // not enough time
   }
@@ -402,7 +402,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/audio_test_freertos/skip.txt b/examples/device/audio_test_freertos/skip.txt
index 2da7808e7..7463aa86a 100644
--- a/examples/device/audio_test_freertos/skip.txt
+++ b/examples/device/audio_test_freertos/skip.txt
@@ -9,7 +9,6 @@ mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
-mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 family:broadcom_32bit
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index baeec870f..952176997 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -146,7 +146,7 @@ void tud_resume_cb(void) {
 // In a real application, this would be replaced with actual I2S receive callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) {
     return; // not enough time
   }
@@ -614,7 +614,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index ee0829e5b..71e7e1da7 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -39,11 +39,35 @@ enum {
 
 #define HELLO_STR   "Hello from TinyUSB\r\n"
 
-int main(void) {
-  board_init();
-  board_led_write(true);
+// board test example does not use both device and host stack
+#if CFG_TUSB_OS != OPT_OS_NONE
+uint32_t tusb_time_millis_api(void) {
+  return osal_time_millis();
+}
+
+void tusb_time_delay_ms_api(uint32_t ms) {
+  osal_task_delay(ms);
+}
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Task parameter type: ULONG for ThreadX, void* for FreeRTOS and noos
+#if CFG_TUSB_OS == OPT_OS_THREADX
+  #define RTOS_PARAM ULONG
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  #define RTOS_PARAM void*
+  static void freertos_init(void);
+#else
+  #define RTOS_PARAM void*
+#endif
 
+static void board_test_loop(RTOS_PARAM param) {
+  (void) param;
   uint32_t start_ms = 0;
+  (void) start_ms;
   bool led_state = false;
 
   while (1) {
@@ -58,26 +82,94 @@ int main(void) {
     }
 
     // Blink and print every interval ms
-    if (!(board_millis() - start_ms < interval_ms)) {
-      start_ms = board_millis();
-
-      if (ch < 0) {
-        // skip if echoing
-        printf(HELLO_STR);
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(interval_ms / portTICK_PERIOD_MS);
+    #elif CFG_TUSB_OS == OPT_OS_THREADX
+    tx_thread_sleep(_osal_ms2tick(interval_ms));
+    #else
+    if (tusb_time_millis_api() - start_ms < interval_ms) {
+      continue; // not enough time
+    }
+    #endif
+    start_ms = tusb_time_millis_api();
 
-        #ifndef LOGGER_UART
-        board_uart_write(HELLO_STR, sizeof(HELLO_STR)-1);
-        #endif
-      }
+    if (ch < 0) {
+      // skip if echoing
+      printf(HELLO_STR);
 
-      board_led_write(led_state);
-      led_state = !led_state; // toggle
+      #ifndef LOGGER_UART
+      board_uart_write(HELLO_STR, sizeof(HELLO_STR)-1);
+      #endif
     }
+
+    board_led_write(led_state);
+    led_state = !led_state; // toggle
   }
 }
 
+int main(void) {
+  board_init();
+  board_led_write(true);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init();
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+  tx_kernel_enter();
+#else
+  board_test_loop(NULL);
+#endif
+
+  return 0;
+}
+
 #ifdef ESP_PLATFORM
 void app_main(void) {
   main();
 }
 #endif
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#ifdef ESP_PLATFORM
+#define MAIN_STACK_SIZE   4096
+#else
+#define MAIN_STACK_SIZE   512
+#endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+static StackType_t  _main_stack[MAIN_STACK_SIZE];
+static StaticTask_t _main_taskdef;
+#endif
+
+static void freertos_init(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(board_test_loop, "main", MAIN_STACK_SIZE, NULL, 1, _main_stack, &_main_taskdef);
+  #else
+  xTaskCreate(board_test_loop, "main", MAIN_STACK_SIZE, NULL, 1, NULL);
+  #endif
+
+  #ifndef ESP_PLATFORM
+  vTaskStartScheduler();
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// ThreadX
+//--------------------------------------------------------------------+
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+
+#define MAIN_TASK_STACK_SIZE  1024
+static TX_THREAD _main_thread;
+static ULONG _main_thread_stack[MAIN_TASK_STACK_SIZE / sizeof(ULONG)];
+
+void tx_application_define(void *first_unused_memory) {
+  (void) first_unused_memory;
+  static CHAR main_thread_name[] = "main";
+  tx_thread_create(&_main_thread, main_thread_name, board_test_loop, 0,
+                   _main_thread_stack, MAIN_TASK_STACK_SIZE,
+                   1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+}
+#endif
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 5ccb06a8a..6f918218d 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -157,7 +157,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index 0da4032a7..710c01ee2 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -104,6 +104,8 @@
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // CDC Endpoint transfer buffer size, more is faster
+// Leave it as default size (512 for HS, 64 for FS) unless your host application
+// is able to send ZLP (Zero Length Packet) to terminate transfer !
 #define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 #ifdef __cplusplus
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 06a4f732f..b00a0e3a9 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -160,7 +160,7 @@ void led_blinking_task(void) {
 
   if (blink_enable) {
     // Blink every interval ms
-    if (board_millis() - start_ms < blink_interval_ms) {
+    if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
       return; // not enough time
     }
     start_ms += blink_interval_ms;
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index e091c2985..017acd039 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -238,7 +238,7 @@ int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, u
   (void) buffer;
   (void) bufsize;
 
-  // currently no other commands is supported
+  // currently no other commands are supported
 
   // Set Sense = Invalid Command Operation
   (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index fdb2ddf18..3f2f05f20 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -104,6 +104,8 @@
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // CDC Endpoint transfer buffer size, more is faster
+// Leave it as default size (512 for HS, 64 for FS) unless your host application
+// is able to send ZLP (Zero Length Packet) to terminate transfer !
 #define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // MSC Buffer size of Device Mass storage
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index d90741df7..d3a096eb0 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -9,7 +9,6 @@ mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
-mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 mcu:STM32L0
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index 29ff86281..ff918205e 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -324,20 +324,17 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
 // - READ10 and WRITE10 has their own callbacks
 int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) {
-  // read10 & write10 has their own callback and MUST not be handled here
+  (void) lun;
+  (void) scsi_cmd;
   (void) buffer;
   (void) bufsize;
 
-  switch (scsi_cmd[0]) {
-    default:
-      // Set Sense = Invalid Command Operation
-      tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+  // currently no other commands are supported
 
-      // negative means error -> tinyusb could stall and/or response with failed status
-      return -1;
-  }
+  // Set Sense = Invalid Command Operation
+  (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
 
-  return -1;
+  return -1; // stall/failed command request;
 }
 
 #endif
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 6b1937a8d..8277b1604 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -111,6 +111,8 @@
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // CDC Endpoint transfer buffer size, more is faster
+// Leave it as default size (512 for HS, 64 for FS) unless your host application
+// is able to send ZLP (Zero Length Packet) to terminate transfer !
 #define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // MSC Buffer size of Device Mass storage
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
index 22c462be7..cb7b3a142 100644
--- a/examples/device/cdc_uac2/src/main.c
+++ b/examples/device/cdc_uac2/src/main.c
@@ -65,8 +65,6 @@ int main(void)
     // printf("Hello, world!\r\n");
 #endif
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/cdc_uac2/src/tusb_config.h b/examples/device/cdc_uac2/src/tusb_config.h
index b7ece8b7c..5eb2e8f74 100644
--- a/examples/device/cdc_uac2/src/tusb_config.h
+++ b/examples/device/cdc_uac2/src/tusb_config.h
@@ -160,6 +160,8 @@ extern "C" {
 #define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 // CDC Endpoint transfer buffer size, more is faster
+// Leave it as default size (512 for HS, 64 for FS) unless your host application
+// is able to send ZLP (Zero Length Packet) to terminate transfer !
 #define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 #ifdef __cplusplus
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
index 73a262d0c..7760c402b 100644
--- a/examples/device/cdc_uac2/src/uac2_app.c
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -66,7 +66,7 @@ uint8_t current_resolution;
 // In a real application, this would be replaced with actual I2S send/receive callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) {
     return; // not enough time
   }
@@ -303,7 +303,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return;
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/dfu/skip.txt b/examples/device/dfu/skip.txt
index 9dde06c30..79d3da9d2 100644
--- a/examples/device/dfu/skip.txt
+++ b/examples/device/dfu/skip.txt
@@ -1,3 +1,3 @@
-mcu:TM4C123
+mcu:TM4C
 mcu:BCM2835
 family:espressif
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 77632bf1a..fb3c22630 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -199,7 +199,7 @@ void led_blinking_task(void) {
   static bool     led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 5de651bcd..6f412e8de 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -132,7 +132,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index dac74bb7a..8ebb42f9a 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -170,7 +170,7 @@ void midi_task(void) {
   while( tud_midi_available() ) tud_midi_packet_read(packet);
 
   // send note every 1000 ms
-  if (board_millis() - start_ms < 286) {
+  if (tusb_time_millis_api() - start_ms < 286) {
     return; // not enough time
   }
   start_ms += 286;
@@ -209,7 +209,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return;// not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index e95b2e197..b545e4652 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -215,20 +215,17 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
 // - READ10 and WRITE10 has their own callbacks
 int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) {
-  // read10 & write10 has their own callback and MUST not be handled here
+  (void) lun;
+  (void) scsi_cmd;
   (void) buffer;
   (void) bufsize;
 
-  switch (scsi_cmd[0]) {
-    default:
-      // Set Sense = Invalid Command Operation
-      tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+  // currently no other commands are supported
 
-      // negative means error -> tinyusb could stall and/or response with failed status
-      return -1;
-  }
+  // Set Sense = Invalid Command Operation
+  (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
 
-  return -1;
+  return -1; // stall/failed command request;
 }
 
 #endif
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 44a91db67..7f2153ae9 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -67,8 +67,6 @@ int main(void) {
 
     hid_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -109,7 +107,7 @@ void hid_task(void) {
   const uint32_t  interval_ms = 10;
   static uint32_t start_ms    = 0;
 
-  if (board_millis() - start_ms < interval_ms) {
+  if (tusb_time_millis_api() - start_ms < interval_ms) {
     return; // not enough time
   }
   start_ms += interval_ms;
@@ -238,7 +236,7 @@ void led_blinking_task(void) {
   }
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 9693d564d..7c9d5af8d 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -209,7 +209,7 @@ void hid_task(void) {
   const uint32_t  interval_ms = 10;
   static uint32_t start_ms    = 0;
 
-  if (board_millis() - start_ms < interval_ms) {
+  if (tusb_time_millis_api() - start_ms < interval_ms) {
     return; // not enough time
   }
   start_ms += interval_ms;
@@ -298,7 +298,7 @@ void led_blinking_task(void) {
   }
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index 01990a5b4..06920db67 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -9,7 +9,6 @@ mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
-mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 family:broadcom_32bit
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 9837a47d9..2a6b91a8a 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -168,7 +168,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 0bccd13c1..c71a9cbad 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -120,7 +120,7 @@ void hid_task(void)
   const uint32_t interval_ms = 10;
   static uint32_t start_ms = 0;
 
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   uint32_t const btn = board_button_read();
@@ -205,7 +205,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index fd58e3021..1154c1d60 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -134,7 +134,7 @@ void midi_task(void)
   }
 
   // send note periodically
-  if (board_millis() - start_ms < 286) {
+  if (tusb_time_millis_api() - start_ms < 286) {
     return; // not enough time
   }
   start_ms += 286;
@@ -174,7 +174,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/midi_test_freertos/skip.txt b/examples/device/midi_test_freertos/skip.txt
index 01990a5b4..06920db67 100644
--- a/examples/device/midi_test_freertos/skip.txt
+++ b/examples/device/midi_test_freertos/skip.txt
@@ -9,7 +9,6 @@ mcu:MKL25ZXX
 mcu:MSP430x5xx
 mcu:RP2040
 mcu:SAMD11
-mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 family:broadcom_32bit
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 62b1c872a..a4ade6f9b 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -31,7 +31,7 @@
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
 /* Blink pattern
@@ -41,71 +41,177 @@
  */
 enum {
   BLINK_NOT_MOUNTED = 250,
-  BLINK_MOUNTED = 1000,
-  BLINK_SUSPENDED = 2500,
+  BLINK_MOUNTED     = 1000,
+  BLINK_SUSPENDED   = 2500,
 };
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-void led_blinking_task(void);
+// Task parameter type: ULONG for ThreadX, void* for FreeRTOS and noos
+#if CFG_TUSB_OS == OPT_OS_THREADX
+  #define RTOS_PARAM ULONG
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  #define RTOS_PARAM void*
+  static void freertos_init(void);
+#else
+  #define RTOS_PARAM void*
+#endif
 
-/*------------- MAIN -------------*/
-int main(void) {
-  board_init();
+void led_blinking_task(RTOS_PARAM param);
 
-  // init device stack on configured roothub port
+//--------------------------------------------------------------------+
+// USB Device Task
+//--------------------------------------------------------------------+
+static void usb_device_init(void) {
   tusb_rhport_init_t dev_init = {
-    .role = TUSB_ROLE_DEVICE,
+    .role  = TUSB_ROLE_DEVICE,
     .speed = TUSB_SPEED_AUTO
   };
   tusb_init(BOARD_TUD_RHPORT, &dev_init);
-
   board_init_after_tusb();
+}
+
+#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
+static void usb_device_task(RTOS_PARAM param) {
+  (void) param;
+  usb_device_init();
 
   while (1) {
-    tud_task(); // tinyusb device task
-    led_blinking_task();
+    tud_task();
   }
 }
+#endif
 
 //--------------------------------------------------------------------+
-// Device callbacks
+// Main
 //--------------------------------------------------------------------+
+int main(void) {
+  board_init();
 
-// Invoked when device is mounted
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init();
+
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+  tx_kernel_enter();
+
+#else
+  // noos + pico-sdk: init USB then run polling loop
+  usb_device_init();
+
+  while (1) {
+    tud_task();
+    led_blinking_task(NULL);
+  }
+#endif
+}
+
+#ifdef ESP_PLATFORM
+void app_main(void) {
+  main();
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
 void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
-// Invoked when device is unmounted
 void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
-// Invoked when usb bus is suspended
-// remote_wakeup_en : if host allow us  to perform remote wakeup
-// Within 7ms, device must draw an average of current less than 2.5 mA from bus
 void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
-// Invoked when usb bus is resumed
 void tud_resume_cb(void) {
   blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
-// BLINKING TASK
+// Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void) {
+void led_blinking_task(RTOS_PARAM param) {
+  (void) param;
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
-  start_ms += blink_interval_ms;
+  while (1) {
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+    tx_thread_sleep(_osal_ms2tick(blink_interval_ms));
+#else
+    if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
+      return; // not enough time
+    }
+#endif
+
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#ifdef ESP_PLATFORM
+#define USBD_STACK_SIZE   4096
+#else
+#define USBD_STACK_SIZE   (3*configMINIMAL_STACK_SIZE/2 * (CFG_TUSB_DEBUG ? 2 : 1))
+#endif
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+#if configSUPPORT_STATIC_ALLOCATION
+static StackType_t  _usb_device_stack[USBD_STACK_SIZE];
+static StaticTask_t _usb_device_taskdef;
+static StackType_t  _blinky_stack[BLINKY_STACK_SIZE];
+static StaticTask_t _blinky_taskdef;
+#endif
+
+
+static void freertos_init(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(usb_device_task,     "usbd",   USBD_STACK_SIZE,   NULL, configMAX_PRIORITIES - 1, _usb_device_stack, &_usb_device_taskdef);
+  xTaskCreateStatic(led_blinking_task,   "blinky", BLINKY_STACK_SIZE, NULL, 1,                        _blinky_stack,     &_blinky_taskdef);
+  #else
+  xTaskCreate(usb_device_task,           "usbd",   USBD_STACK_SIZE,   NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(led_blinking_task,         "blinky", BLINKY_STACK_SIZE, NULL, 1,                        NULL);
+  #endif
+  #ifndef ESP_PLATFORM
+  vTaskStartScheduler();
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// ThreadX
+//--------------------------------------------------------------------+
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+
+#define USBD_STACK_SIZE   4096
+#define BLINKY_STACK_SIZE 512
+
+static TX_THREAD _usb_device_thread;
+static ULONG     _usb_device_stack[USBD_STACK_SIZE / sizeof(ULONG)];
+static TX_THREAD _blinky_thread;
+static ULONG     _blinky_stack[BLINKY_STACK_SIZE / sizeof(ULONG)];
+
+void tx_application_define(void *first_unused_memory) {
+  (void) first_unused_memory;
+  static CHAR usbd_name[]   = "usbd";
+  static CHAR blinky_name[] = "blinky";
+  tx_thread_create(&_usb_device_thread, usbd_name, usb_device_task, 0,
+                   _usb_device_stack, USBD_STACK_SIZE,
+                   0, 0, TX_NO_TIME_SLICE, TX_AUTO_START);
+  tx_thread_create(&_blinky_thread, blinky_name, led_blinking_task, 0,
+                   _blinky_stack, BLINKY_STACK_SIZE,
+                   1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
 }
+
+#endif
diff --git a/examples/device/mtp/src/main.c b/examples/device/mtp/src/main.c
index 57d1535b2..6ffa435d1 100644
--- a/examples/device/mtp/src/main.c
+++ b/examples/device/mtp/src/main.c
@@ -102,7 +102,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/mtp/src/mtp_fs_example.c b/examples/device/mtp/src/mtp_fs_example.c
index 7fd7db61b..60fc9f79e 100644
--- a/examples/device/mtp/src/mtp_fs_example.c
+++ b/examples/device/mtp/src/mtp_fs_example.c
@@ -557,7 +557,7 @@ static int32_t fs_send_object_info(tud_mtp_cb_data_t* cb_data) {
       return MTP_RESP_INVALID_STORAGE_ID;
     }
 
-    if (obj_info->parent_object != 0) { // not root
+    if (obj_info->parent_object != 0 && obj_info->parent_object != 0xFFFFFFFFu) { // not root
       fs_file_t* parent = fs_get_file(obj_info->parent_object);
       if (parent == NULL || 0u == parent->association_type) {
         return MTP_RESP_INVALID_PARENT_OBJECT;
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 867cf2812..8bd8a8c21 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -276,8 +276,6 @@ int main(void) {
     sys_check_timeouts(); // service lwip
     handle_link_state_switch();
   }
-
-  return 0;
 }
 
 /* lwip has provision for using a mutex, when applicable */
@@ -291,5 +289,5 @@ void sys_arch_unprotect(sys_prot_t pval) {
 
 /* lwip needs a millisecond time source, and the TinyUSB board support code has one available */
 uint32_t sys_now(void) {
-  return board_millis();
+  return tusb_time_millis_api();
 }
diff --git a/examples/device/printer_to_cdc/CMakeLists.txt b/examples/device/printer_to_cdc/CMakeLists.txt
new file mode 100644
index 000000000..3c8ab3653
--- /dev/null
+++ b/examples/device/printer_to_cdc/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+project(printer_to_cdc C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT_NAME})
+
+# Example source
+target_sources(${PROJECT_NAME} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT_NAME} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT_NAME} noos)
diff --git a/examples/device/printer_to_cdc/Makefile b/examples/device/printer_to_cdc/Makefile
new file mode 100644
index 000000000..1a4b428dc
--- /dev/null
+++ b/examples/device/printer_to_cdc/Makefile
@@ -0,0 +1,11 @@
+include ../../../hw/bsp/family_support.mk
+
+INC += \
+	src \
+
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(EXAMPLE_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../../hw/bsp/family_rules.mk
diff --git a/examples/device/printer_to_cdc/README.md b/examples/device/printer_to_cdc/README.md
new file mode 100644
index 000000000..ecb9a678f
--- /dev/null
+++ b/examples/device/printer_to_cdc/README.md
@@ -0,0 +1,80 @@
+#### Printer to CDC
+
+This example demonstrates a USB composite device with a Printer class interface and a CDC serial interface. Data flows bidirectionally between the two:
+
+- Data sent to the Printer (from host) is forwarded to the CDC serial port
+- Data sent to the CDC serial port (from host) is forwarded to the Printer IN endpoint
+
+This is useful for debugging printer class communication or as a reference for implementing printer class devices.
+
+#### USB Interfaces
+
+| Interface | Class | Description |
+|-----------|-------|-------------|
+| 0 | CDC ACM | Virtual serial port |
+| 2 | Printer | USB Printer (bidirectional, protocol 2) |
+
+#### How to Test
+
+The device exposes two endpoints on the host:
+- `/dev/ttyACM0` (CDC serial port)
+- `/dev/usb/lp0` (USB printer)
+
+Note: the actual device numbers may vary depending on your system.
+
+**Prerequisites (Linux):**
+
+```bash
+# Load the USB printer kernel module if not already loaded
+sudo modprobe usblp
+
+# Check devices exist
+ls /dev/ttyACM* /dev/usb/lp*
+```
+
+**Test Printer to CDC (host writes to printer, reads from CDC):**
+
+```bash
+# Terminal 1: read from CDC
+cat /dev/ttyACM0
+
+# Terminal 2: write to printer
+echo "hello from printer" > /dev/usb/lp0
+# "hello from printer" appears in Terminal 1
+```
+
+**Test CDC to Printer (host writes to CDC, reads from printer):**
+
+```bash
+# Terminal 1: read from printer IN endpoint
+cat /dev/usb/lp0
+
+# Terminal 2: write to CDC
+echo "hello from cdc" > /dev/ttyACM0
+# "hello from cdc" appears in Terminal 1
+```
+
+**Interactive bidirectional test:**
+
+```bash
+# Terminal 1: open CDC serial port
+minicom -D /dev/ttyACM0
+
+# Terminal 2: send to printer
+echo "tinyusb print example" > /dev/usb/lp0
+# Text appears in minicom. Type in minicom to send data back through printer TX.
+```
+
+#### IEEE 1284 Device ID
+
+The device responds to GET_DEVICE_ID requests with:
+
+```
+MFG:TinyUSB;MDL:Printer to CDC;CMD:PS;CLS:PRINTER;
+```
+
+Verify with:
+
+```bash
+cat /sys/class/usbmisc/lp0/device/ieee1284_id
+```
diff --git a/examples/device/printer_to_cdc/src/main.c b/examples/device/printer_to_cdc/src/main.c
new file mode 100644
index 000000000..ffaf709b4
--- /dev/null
+++ b/examples/device/printer_to_cdc/src/main.c
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* This example demonstrates a USB Printer + CDC composite device.
+ * Data received on the Printer interface is forwarded to the CDC serial port,
+ * and data received on the CDC serial port is forwarded back to the Printer interface.
+ *
+ * To test:
+ *   1. Flash the device
+ *   2. Open a serial terminal on the CDC port (e.g. /dev/ttyACM0)
+ *   3. Send data to the printer: echo "hello" > /dev/usb/lp0
+ *   4. The data appears on the CDC serial terminal
+ *   5. Type in the serial terminal to send data back through the printer TX
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#include "usb_descriptors.h"
+
+// -------------------------------------------------------------------+
+// Tasks
+// -------------------------------------------------------------------+
+
+// Forward data from Printer RX to CDC TX
+static void printer_to_cdc_task(void) {
+  uint32_t avail = tud_printer_read_available();
+  if (avail == 0 || !tud_cdc_write_available()) {
+    return;
+  }
+
+  uint8_t buf[64];
+  uint32_t count = tud_printer_read(buf, TU_MIN(sizeof(buf), tud_cdc_write_available()));
+  if (count > 0) {
+    tud_cdc_write(buf, count);
+    tud_cdc_write_flush();
+  }
+}
+
+// Forward data from CDC RX to Printer TX
+static void cdc_to_printer_task(void) {
+  uint32_t avail = tud_printer_write_available();
+  if (tud_cdc_available() == 0 || avail == 0) {
+    return;
+  }
+
+  uint8_t buf[64];
+  uint32_t count = tud_cdc_read(buf, TU_MIN(sizeof(buf), avail));
+  if (count > 0) {
+    tud_printer_write(buf, count);
+    tud_printer_write_flush();
+  }
+}
+
+int main(void) {
+  board_init();
+  // init device stack on configured roothub port
+  tusb_rhport_init_t dev_init = {.role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO};
+  tusb_init(BOARD_TUD_RHPORT, &dev_init);
+  board_init_after_tusb();
+
+  while (1) {
+    tud_task();             // tinyusb device task
+    printer_to_cdc_task();  // forward printer data to CDC
+    cdc_to_printer_task();  // forward CDC data to printer
+  }
+}
+
+//--------------------------------------------------------------------+
+// Printer callbacks
+//--------------------------------------------------------------------+
+
+void tud_printer_rx_cb(uint8_t itf) {
+  (void)itf;
+}
+
+// IEEE 1284 Device ID: first 2 bytes are big-endian total length (including the 2 length bytes).
+// The rest is the Device ID string using standard abbreviated keys.
+static const char printer_device_id[] =
+  "\x00\x34" // total length = 52 = 0x0034 (big-endian)
+  "MFG:TinyUSB;"
+  "MDL:Printer to CDC;"
+  "CMD:PS;"
+  "CLS:PRINTER;";
+
+TU_VERIFY_STATIC(sizeof(printer_device_id) - 1 == 52, "device ID length mismatch");
+
+uint8_t const *tud_printer_get_device_id_cb(uint8_t itf) {
+  (void)itf;
+  return (uint8_t const *)printer_device_id;
+}
diff --git a/examples/device/printer_to_cdc/src/tusb_config.h b/examples/device/printer_to_cdc/src/tusb_config.h
new file mode 100644
index 000000000..c38e8e1ee
--- /dev/null
+++ b/examples/device/printer_to_cdc/src/tusb_config.h
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+  #define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+  #define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+  #define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+  #define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+  #define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_HID     0
+#define CFG_TUD_CDC     1
+#define CFG_TUD_MSC     0
+#define CFG_TUD_MIDI    0
+#define CFG_TUD_VENDOR  0
+#define CFG_TUD_PRINTER 1
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// Printer buffer sizes
+#define CFG_TUD_PRINTER_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_PRINTER_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_PRINTER_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/printer_to_cdc/src/usb_descriptors.c b/examples/device/printer_to_cdc/src/usb_descriptors.c
new file mode 100644
index 000000000..30d309ed4
--- /dev/null
+++ b/examples/device/printer_to_cdc/src/usb_descriptors.c
@@ -0,0 +1,208 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#include "usb_descriptors.h"
+
+#define USB_VID   0xCafe
+#define USB_PID   0x4005
+#define USB_BCD   0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+static tusb_desc_device_t const desc_device = {
+  .bLength            = sizeof(tusb_desc_device_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE,
+  .bcdUSB             = USB_BCD,
+
+  // Use Interface Association Descriptor (IAD) for CDC
+  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+  .idVendor           = USB_VID,
+  .idProduct          = USB_PID,
+  .bcdDevice          = 0x0100,
+
+  .iManufacturer      = 0x01,
+  .iProduct           = 0x02,
+  .iSerialNumber      = 0x03,
+
+  .bNumConfigurations = 0x01
+};
+
+uint8_t const *tud_descriptor_device_cb(void) {
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+// Endpoint numbers
+#if defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+  #define EPNUM_PRINTER_OUT 0x04
+  #define EPNUM_PRINTER_IN  0x85
+#else
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+  #define EPNUM_PRINTER_OUT 0x03
+  #define EPNUM_PRINTER_IN  0x83
+#endif
+
+// full speed configuration
+static uint8_t const desc_fs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 16, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+
+  // Interface number, string index, EP Bulk Out address, EP Bulk In address, EP size
+  TUD_PRINTER_DESCRIPTOR(ITF_NUM_PRINTER, 5, EPNUM_PRINTER_OUT, EPNUM_PRINTER_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// high speed configuration
+static uint8_t const desc_hs_configuration[] = {
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 16, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+
+  TUD_PRINTER_DESCRIPTOR(ITF_NUM_PRINTER, 5, EPNUM_PRINTER_OUT, EPNUM_PRINTER_IN, 512),
+};
+
+// other speed configuration
+static uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+static tusb_desc_device_qualifier_t const desc_device_qualifier = {
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *) &desc_device_qualifier;
+}
+
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void) index;
+
+  // if link speed is high return fullspeed config, and vice versa
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // TUD_OPT_HIGH_SPEED
+
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void) index;
+
+#if TUD_OPT_HIGH_SPEED
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+  STRID_CDC,
+  STRID_PRINTER,
+};
+
+static char const *string_desc_arr[] = {
+  (const char[]) { 0x09, 0x04 }, // 0: supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  NULL,                          // 3: Serial, use unique ID if possible
+  "TinyUSB CDC",                 // 4: CDC Interface
+  "TinyUSB Printer",             // 5: Printer Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { return NULL; }
+
+      const char *str = string_desc_arr[index];
+
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1;
+      if (chr_count > max_count) { chr_count = max_count; }
+
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+  return _desc_str;
+}
diff --git a/examples/device/printer_to_cdc/src/usb_descriptors.h b/examples/device/printer_to_cdc/src/usb_descriptors.h
new file mode 100644
index 000000000..830593b4d
--- /dev/null
+++ b/examples/device/printer_to_cdc/src/usb_descriptors.h
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef USB_DESCRIPTORS_H_
+#define USB_DESCRIPTORS_H_
+
+enum {
+  ITF_NUM_CDC,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_PRINTER,
+  ITF_NUM_TOTAL,
+};
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_PRINTER_DESC_LEN)
+
+#endif /* USB_DESCRIPTORS_H_ */
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 96fa66f1e..0ea63d8f7 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -559,7 +559,7 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const *p_reques
 // In a real application, this would be replaced with actual I2S send/receive callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) return;// not enough time
   start_ms = curr_ms;
   // When new data arrived, copy data from speaker buffer, to microphone buffer
@@ -605,7 +605,7 @@ void audio_control_task(void) {
   static uint32_t start_ms = 0;
   static uint32_t btn_prev = 0;
 
-  if (board_millis() - start_ms < interval_ms) return;// not enough time
+  if (tusb_time_millis_api() - start_ms < interval_ms) return;// not enough time
   start_ms += interval_ms;
 
   uint32_t btn = board_button_read();
@@ -644,7 +644,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return;
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) return;
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c
index 7b4e2d64c..c3e97bb28 100644
--- a/examples/device/uac2_speaker_fb/src/main.c
+++ b/examples/device/uac2_speaker_fb/src/main.c
@@ -534,8 +534,9 @@ bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const
   uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
   uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
 
-  if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0)
+  if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0) {
     blink_interval_ms = BLINK_MOUNTED;
+  }
 
   return true;
 }
@@ -569,7 +570,8 @@ bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t fu
 
   fifo_count = tud_audio_available();
   // Same averaging method used in UAC2 class
-  fifo_count_avg = (uint32_t) (((uint64_t) fifo_count_avg * 63 + ((uint32_t) fifo_count << 16)) >> 6);
+  const uint32_t ff_count32 = (uint32_t) fifo_count << 16;
+  fifo_count_avg = (uint32_t) (((uint64_t) fifo_count_avg * 63 + ff_count32) >> 6);
 
   return true;
 }
@@ -583,7 +585,7 @@ bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t fu
 // In a real application, this would be replaced with actual I2S transmit callback.
 void audio_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) return;// not enough time
   start_ms = curr_ms;
 
@@ -610,7 +612,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return;
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) return;
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
@@ -624,7 +626,7 @@ void led_blinking_task(void) {
 // Every 1ms, we will sent 1 debug information report
 void audio_debug_task(void) {
   static uint32_t start_ms = 0;
-  uint32_t curr_ms = board_millis();
+  uint32_t curr_ms = tusb_time_millis_api();
   if (start_ms == curr_ms) return;// not enough time
   start_ms = curr_ms;
 
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 5cbbb85ef..b1269b117 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -124,12 +124,12 @@ void led_blinking_task(void)
     {
       led_state = true;
       board_led_write(true);
-      start_ms = board_millis();
+      start_ms = tusb_time_millis_api();
       doPulse = false;
     }
     else if (led_state == true)
     {
-      if ( board_millis() - start_ms < 750) //Spec says blink must be between 500 and 1000 ms.
+      if ( tusb_time_millis_api() - start_ms < 750) //Spec says blink must be between 500 and 1000 ms.
       {
         return; // not enough time
       }
@@ -140,7 +140,7 @@ void led_blinking_task(void)
   else
   {
     // Blink every interval ms
-    if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
     start_ms += blink_interval_ms;
 
     board_led_write(led_state);
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 4c3724ac4..35e8618f5 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -209,19 +209,19 @@ void usbtmc_app_task_iter(void) {
   case 0:
     break;
   case 1:
-    queryDelayStart = board_millis();
+    queryDelayStart = tusb_time_millis_api();
     queryState = 2;
     break;
   case 2:
-    if( (board_millis() - queryDelayStart) > resp_delay) {
-      queryDelayStart = board_millis();
+    if( (tusb_time_millis_api() - queryDelayStart) > resp_delay) {
+      queryDelayStart = tusb_time_millis_api();
       queryState=3;
       status |= 0x10u; // MAV
       status |= 0x40u; // SRQ
     }
     break;
   case 3:
-    if( (board_millis() - queryDelayStart) > resp_delay) {
+    if( (tusb_time_millis_api() - queryDelayStart) > resp_delay) {
       queryState = 4;
     }
     break;
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index ffa2a7afa..df9f77a1c 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -231,7 +231,7 @@ static void video_send_frame(void) {
   if (!already_sent) {
     already_sent = 1;
     tx_busy = 1;
-    start_ms = board_millis();
+    start_ms = tusb_time_millis_api();
 #if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS)
     tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
 #elif defined (CFG_EXAMPLE_VIDEO_READONLY)
@@ -247,7 +247,7 @@ static void video_send_frame(void) {
 #endif
   }
 
-  unsigned cur = board_millis();
+  unsigned cur = tusb_time_millis_api();
   if (cur - start_ms < interval_ms) {
     return; // not enough time
   }
@@ -316,7 +316,7 @@ void led_blinking_task(void* param) {
     #if CFG_TUSB_OS == OPT_OS_FREERTOS
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
     #else
-    if (board_millis() - start_ms < blink_interval_ms) {
+    if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
       return; // not enough time
     }
     #endif
diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c
index 79b149f2b..debd336fd 100644
--- a/examples/device/video_capture_2ch/src/main.c
+++ b/examples/device/video_capture_2ch/src/main.c
@@ -221,13 +221,13 @@ static void video_send_frame(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
   if (!(already_sent & (1u << idx))) {
     already_sent |= 1u << idx;
     tx_busy |= 1u << idx;
-    start_ms[idx] = board_millis();
+    start_ms[idx] = tusb_time_millis_api();
 
     fb_size = get_framebuf(ctl_idx, stm_idx, frame_num[idx], &fp);
     tud_video_n_frame_xfer(ctl_idx, stm_idx, fp, fb_size);
   }
 
-  unsigned cur = board_millis();
+  unsigned cur = tusb_time_millis_api();
   if (cur - start_ms[idx] < interval_ms[idx]) return; // not enough time
   if (tx_busy & (1u << idx)) return;
   start_ms[idx] += interval_ms[idx];
@@ -280,7 +280,7 @@ void led_blinking_task(void* param) {
     #if CFG_TUSB_OS == OPT_OS_FREERTOS
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
     #else
-    if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
     #endif
 
     start_ms += blink_interval_ms;
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 155768b76..4be5e4db4 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -257,7 +257,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return; // not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index 4978f1fab..8727ea938 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -12,6 +12,7 @@ else ()
   set(EXAMPLE_LIST
     host_hid_to_device_cdc
     host_info_to_device_cdc
+    dynamic_switch
     )
 
   foreach (example ${EXAMPLE_LIST})
diff --git a/examples/dual/dynamic_switch/CMakeLists.txt b/examples/dual/dynamic_switch/CMakeLists.txt
new file mode 100644
index 000000000..7cad30727
--- /dev/null
+++ b/examples/dual/dynamic_switch/CMakeLists.txt
@@ -0,0 +1,30 @@
+cmake_minimum_required(VERSION 3.20)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+project(dynamic_switch C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT_NAME})
+
+# Example source
+target_sources(${PROJECT_NAME} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT_NAME} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT_NAME} noos)
diff --git a/examples/dual/dynamic_switch/CMakePresets.json b/examples/dual/dynamic_switch/CMakePresets.json
new file mode 100644
index 000000000..5cd8971e9
--- /dev/null
+++ b/examples/dual/dynamic_switch/CMakePresets.json
@@ -0,0 +1,6 @@
+{
+  "version": 6,
+  "include": [
+    "../../../hw/bsp/BoardPresets.json"
+  ]
+}
diff --git a/examples/dual/dynamic_switch/Makefile b/examples/dual/dynamic_switch/Makefile
new file mode 100644
index 000000000..44ab54ad7
--- /dev/null
+++ b/examples/dual/dynamic_switch/Makefile
@@ -0,0 +1,16 @@
+include ../../../hw/bsp/family_support.mk
+
+INC += \
+	src \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(EXAMPLE_PATH)/, $(EXAMPLE_SOURCE))
+
+# Include device and host stack
+SRC_C += \
+	src/class/cdc/cdc_device.c \
+	src/host/hub.c \
+	src/host/usbh.c
+
+include ../../../hw/bsp/family_rules.mk
diff --git a/examples/dual/dynamic_switch/README.md b/examples/dual/dynamic_switch/README.md
new file mode 100644
index 000000000..034787f18
--- /dev/null
+++ b/examples/dual/dynamic_switch/README.md
@@ -0,0 +1,60 @@
+# Dynamic Switch Example
+
+This example demonstrates TinyUSB's dual-role capability by allowing runtime switching between USB device and host modes.
+
+## Features
+
+- **Button-triggered mode switching**: Press the board button to switch between device and host modes
+- **Device Mode**: Acts as a USB CDC (Virtual Serial Port) that echoes all received data
+- **Host Mode**: Enumerates connected USB devices and prints device information
+- **Dynamic switching**: Deinitializes the current stack and reinitializes in the new mode
+
+## Usage
+
+1. **Build and flash** the example to your board
+2. **Default behavior**: The board starts in **Device mode**
+3. **Device mode**:
+   - Connect the board to a PC
+   - Open a serial terminal (e.g., `screen /dev/ttyACM0` or PuTTY)
+   - Type characters - they will be echoed back to you
+4. **Switch to Host mode**:
+   - Press the board button
+   - Connect a USB device to the board
+   - The board will enumerate the device and print its descriptors to the debug console
+5. **Switch back to Device mode**: Press the button again
+
+## LED Patterns
+
+The onboard LED indicates the USB connection status:
+
+- **Fast blink (250ms)**: Not mounted/connected
+- **Slow blink (1000ms)**: Successfully mounted/connected
+- **Very slow blink (2500ms)**: Suspended (device mode only)
+
+## Serial Output
+
+The example prints status messages to the debug UART:
+
+```
+======================================
+TinyUSB Dynamic Switch Example
+Press button to switch between device and host modes
+Starting in DEVICE mode...
+======================================
+
+[DEVICE] Mounted
+
+--- Switching USB mode ---
+Stopping DEVICE mode...
+Starting HOST mode...
+Mode switch complete!
+
+[HOST] Device attached, address = 1
+Device 1: ID 1234:5678 SN ABC123
+Device Descriptor:
+  bLength             18
+  bDescriptorType     1
+  bcdUSB              0200
+  bDeviceClass        239
+  ...
+```
diff --git a/examples/dual/dynamic_switch/only.txt b/examples/dual/dynamic_switch/only.txt
new file mode 100644
index 000000000..70be49b28
--- /dev/null
+++ b/examples/dual/dynamic_switch/only.txt
@@ -0,0 +1,12 @@
+family:espressif
+mcu:LPC43XX
+mcu:MIMXRT1XXX
+mcu:STM32C0
+mcu:STM32G0
+mcu:STM32H5
+mcu:STM32F2
+mcu:STM32F4
+mcu:STM32U5
+mcu:STM32F7
+mcu:STM32H7
+mcu:STM32H7RS
diff --git a/examples/dual/dynamic_switch/src/CMakeLists.txt b/examples/dual/dynamic_switch/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/dual/dynamic_switch/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/dual/dynamic_switch/src/main.c b/examples/dual/dynamic_switch/src/main.c
new file mode 100644
index 000000000..c9ad2a835
--- /dev/null
+++ b/examples/dual/dynamic_switch/src/main.c
@@ -0,0 +1,496 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* This example demonstrates dynamic switching between device and host modes:
+ * - Press button to switch between device and host modes
+ * - Device mode: CDC echo (echoes input back to output)
+ * - Host mode: Prints connected device information
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  #ifdef ESP_PLATFORM
+    #define USBD_STACK_SIZE     4096
+    #define USBH_STACK_SIZE     4096
+  #else
+    // Increase stack size when debug log is enabled
+    #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+    #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+  #endif
+
+  #define CDC_STACK_SIZE      (configMINIMAL_STACK_SIZE * (CFG_TUSB_DEBUG ? 2 : 1))
+  #define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// English
+#define LANGUAGE_ID 0x0409
+
+/* Blink pattern
+ * - 250 ms  : not mounted
+ * - 1000 ms : mounted
+ * - 2500 ms : suspended
+ */
+enum {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+// static task for FreeRTOS
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t usb_stack[USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE];
+StaticTask_t usb_taskdef;
+
+StackType_t cdc_stack[CDC_STACK_SIZE];
+StaticTask_t cdc_taskdef;
+#endif
+#endif
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+static tusb_role_t current_role = TUSB_ROLE_DEVICE;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+static void usb_task(void *param);
+void led_blinking_task(void *param);
+void cdc_task(void *params);
+#else
+void led_blinking_task(void);
+void cdc_task(void);
+#endif
+void usb_mode_switch(void);
+static void print_device_info(uint8_t daddr);
+static void print_utf16(uint16_t* temp_buf, size_t buf_len);
+
+// Declare buffer for USB transfer
+CFG_TUH_MEM_SECTION struct {
+  TUH_EPBUF_TYPE_DEF(tusb_desc_device_t, device);
+  TUH_EPBUF_DEF(serial, 64*sizeof(uint16_t));
+  TUH_EPBUF_DEF(buf, 128*sizeof(uint16_t));
+} desc;
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
+
+int main(void) {
+  board_init();
+
+  printf("\r\n======================================\r\n");
+  printf("TinyUSB Dynamic Switch Example\r\n");
+  printf("Press button to switch between device and host modes\r\n");
+  printf("Starting in DEVICE mode...\r\n");
+  printf("======================================\r\n\r\n");
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Create FreeRTOS tasks
+#if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_task, "usb", USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE,
+                    NULL, configMAX_PRIORITIES-1, usb_stack, &usb_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
+#else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_task, "usb", USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE,
+              NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL);
+#endif
+
+#ifndef ESP_PLATFORM
+  // only start scheduler for non-espressif mcu
+  vTaskStartScheduler();
+#endif
+
+#else
+  // Initialize in device mode by default
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_RHPORT, &dev_init);
+  current_role = TUSB_ROLE_DEVICE;
+
+  board_init_after_tusb();
+
+  while (1) {
+    // Check for button press to switch modes
+    static bool pending_switch = false;
+    if (board_button_read()) {
+      if (!pending_switch) {
+        pending_switch = true;
+        usb_mode_switch();
+      }
+    } else {
+      pending_switch = false;
+    }
+
+    // Process USB tasks based on current mode
+    if (current_role == TUSB_ROLE_DEVICE) {
+      tud_task();
+      cdc_task();
+    } else {
+      tuh_task();
+    }
+
+    led_blinking_task();
+  }
+#endif
+}
+
+#ifdef ESP_PLATFORM
+void app_main(void) {
+  main();
+}
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+// USB Task for FreeRTOS
+// This top level thread processes all usb events and mode switching
+static void usb_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tusb_rhport_init_t dev_init = {
+    .role = TUSB_ROLE_DEVICE,
+    .speed = TUSB_SPEED_AUTO
+  };
+  tusb_init(BOARD_RHPORT, &dev_init);
+  current_role = TUSB_ROLE_DEVICE;
+
+  board_init_after_tusb();
+
+  // RTOS forever loop
+  while (1) {
+    // Check for button press to switch modes
+    static bool pending_switch = false;
+    if (board_button_read()) {
+      if (!pending_switch) {
+        pending_switch = true;
+        usb_mode_switch();
+      }
+    } else {
+      pending_switch = false;
+    }
+
+    // Process USB tasks based on current mode
+    // Use _ext version to allow return and read button state
+    if (current_role == TUSB_ROLE_DEVICE) {
+      tud_task_ext(10, false);
+    } else {
+      tuh_task_ext(10, false);
+    }
+  }
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Mode Switching
+//--------------------------------------------------------------------+
+
+void usb_mode_switch(void) {
+  printf("\r\n--- Switching USB mode ---\r\n");
+
+  // Deinitialize current mode
+  if (current_role == TUSB_ROLE_DEVICE) {
+    printf("Stopping DEVICE mode...\r\n");
+    tusb_deinit(BOARD_RHPORT);
+  } else {
+    printf("Stopping HOST mode...\r\n");
+    tusb_deinit(BOARD_RHPORT);
+  }
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  vTaskDelay(pdMS_TO_TICKS(100)); // Small delay for clean transition
+#else
+  tusb_time_delay_ms_api(100); // Small delay for clean transition
+#endif  // Switch to the other mode
+  if (current_role == TUSB_ROLE_DEVICE) {
+    printf("Starting HOST mode...\r\n");
+    tusb_rhport_init_t host_init = {
+      .role = TUSB_ROLE_HOST,
+      .speed = TUSB_SPEED_AUTO
+    };
+    tusb_init(BOARD_RHPORT, &host_init);
+    current_role = TUSB_ROLE_HOST;
+  } else {
+    printf("Starting DEVICE mode...\r\n");
+    tusb_rhport_init_t dev_init = {
+      .role = TUSB_ROLE_DEVICE,
+      .speed = TUSB_SPEED_AUTO
+    };
+    tusb_init(BOARD_RHPORT, &dev_init);
+    current_role = TUSB_ROLE_DEVICE;
+  }
+
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+  printf("Mode switch complete!\r\n\r\n");
+}
+
+//--------------------------------------------------------------------+
+// Device Mode: CDC Task
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void cdc_task(void *params) {
+  (void) params;
+
+  // RTOS forever loop
+  while (1) {
+    // Only process CDC when in device mode
+    if (current_role == TUSB_ROLE_DEVICE) {
+      // Connected and there are data available
+      while (tud_cdc_available()) {
+        uint8_t buf[64];
+
+        // Read data
+        uint32_t count = tud_cdc_read(buf, sizeof(buf));
+
+        // Echo back
+        tud_cdc_write(buf, count);
+
+        // Add newline for carriage return
+        for (uint32_t i = 0; i < count; i++) {
+          if (buf[i] == '\r') {
+            tud_cdc_write_char('\n');
+            break;
+          }
+        }
+      }
+
+      tud_cdc_write_flush();
+    }
+
+    vTaskDelay(pdMS_TO_TICKS(10));
+  }
+}
+#else
+void cdc_task(void) {
+  // Connected and there are data available
+  if (tud_cdc_available()) {
+    uint8_t buf[64];
+
+    // Read data
+    uint32_t count = tud_cdc_read(buf, sizeof(buf));
+
+    // Echo back
+    for (uint32_t i = 0; i < count; i++) {
+      tud_cdc_write_char(buf[i]);
+
+      if (buf[i] == '\r') {
+        tud_cdc_write_char('\n');
+      }
+    }
+
+    tud_cdc_write_flush();
+  }
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Device Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+  printf("[DEVICE] Mounted\r\n");
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  printf("[DEVICE] Unmounted\r\n");
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void) remote_wakeup_en;
+  printf("[DEVICE] Suspended\r\n");
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  printf("[DEVICE] Resumed\r\n");
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// Host Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb(uint8_t daddr) {
+  printf("[HOST] Device attached, address = %d\r\n", daddr);
+  blink_interval_ms = BLINK_MOUNTED;
+  print_device_info(daddr);
+}
+
+// Invoked when device is unmounted (unplugged)
+void tuh_umount_cb(uint8_t daddr) {
+  printf("[HOST] Device removed, address = %d\r\n", daddr);
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// Host Device Info
+//--------------------------------------------------------------------+
+
+static void print_device_info(uint8_t daddr) {
+  // Get Device Descriptor
+  uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc.device, 18);
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    printf("Failed to get device descriptor\r\n");
+    return;
+  }
+
+  printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct);
+
+  xfer_result = XFER_RESULT_FAILED;
+  if (desc.device.iSerialNumber != 0) {
+    xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial));
+  }
+  if (XFER_RESULT_SUCCESS != xfer_result) {
+    uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial;
+    serial[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * 3 + 2));
+    serial[1] = 'n';
+    serial[2] = '/';
+    serial[3] = 'a';
+    serial[4] = 0;
+  }
+  print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2);
+  printf("\r\n");
+
+  printf("Device Descriptor:\r\n");
+  printf("  bLength             %u\r\n", desc.device.bLength);
+  printf("  bDescriptorType     %u\r\n", desc.device.bDescriptorType);
+  printf("  bcdUSB              %04x\r\n", desc.device.bcdUSB);
+  printf("  bDeviceClass        %u\r\n", desc.device.bDeviceClass);
+  printf("  bDeviceSubClass     %u\r\n", desc.device.bDeviceSubClass);
+  printf("  bDeviceProtocol     %u\r\n", desc.device.bDeviceProtocol);
+  printf("  bMaxPacketSize0     %u\r\n", desc.device.bMaxPacketSize0);
+  printf("  idVendor            0x%04x\r\n", desc.device.idVendor);
+  printf("  idProduct           0x%04x\r\n", desc.device.idProduct);
+  printf("  bcdDevice           %04x\r\n", desc.device.bcdDevice);
+
+  // Get Manufacturer string
+  if (desc.device.iManufacturer) {
+    if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf))) {
+      printf("  iManufacturer       %u     ", desc.device.iManufacturer);
+      print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
+      printf("\r\n");
+    }
+  }
+
+  // Get Product string
+  if (desc.device.iProduct) {
+    if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf))) {
+      printf("  iProduct            %u     ", desc.device.iProduct);
+      print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
+      printf("\r\n");
+    }
+  }
+
+  // Get Serial string
+  if (desc.device.iSerialNumber) {
+    printf("  iSerialNumber       %u     ", desc.device.iSerialNumber);
+    print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2);
+    printf("\r\n");
+  } else {
+    printf("  iSerialNumber       0\r\n");
+  }
+
+  printf("  bNumConfigurations  %u\r\n", desc.device.bNumConfigurations);
+  printf("\r\n");
+}
+
+static void print_utf16(uint16_t* temp_buf, size_t buf_len) {
+  if (temp_buf[0] == 0 || (temp_buf[0] >> 8) != TUSB_DESC_STRING) {
+    printf("(invalid)");
+    return;
+  }
+
+  size_t chr_count = (temp_buf[0] & 0xff) / 2 - 1;
+  if (chr_count > buf_len - 1) {
+    chr_count = buf_len - 1;
+  }
+
+  for (size_t i = 0; i < chr_count; i++) {
+    uint16_t ch = temp_buf[1 + i];
+    if (ch <= 0x7F) {
+      putchar((char) ch);
+    } else {
+      // TODO support UTF16 to UTF8 conversion
+      putchar('?');
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void led_blinking_task(void *param) {
+  (void) param;
+  static bool led_state = false;
+
+  // RTOS forever loop
+  while (1) {
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+    vTaskDelay(pdMS_TO_TICKS(blink_interval_ms));
+  }
+}
+#else
+void led_blinking_task(void) {
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
+    return; // not enough time
+  }
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
+#endif
diff --git a/examples/dual/dynamic_switch/src/tusb_config.h b/examples/dual/dynamic_switch/src/tusb_config.h
new file mode 100644
index 000000000..af0d55f14
--- /dev/null
+++ b/examples/dual/dynamic_switch/src/tusb_config.h
@@ -0,0 +1,158 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used can be defined by board.mk, default to port 0
+#ifndef BOARD_RHPORT
+  #if defined(BOARD_TUD_RHPORT)
+    #define BOARD_RHPORT BOARD_TUD_RHPORT
+  #else
+    #define BOARD_RHPORT 0
+    #define BOARD_TUD_RHPORT 0
+  #endif
+#endif
+
+#if defined(BOARD_TUH_RHPORT)
+  #if BOARD_TUH_RHPORT != BOARD_RHPORT
+    #undef BOARD_TUH_RHPORT
+    #define BOARD_TUH_RHPORT BOARD_RHPORT
+  #endif
+#else
+  #define BOARD_TUH_RHPORT BOARD_RHPORT
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_MAX_SPEED
+  #if defined(BOARD_TUD_MAX_SPEED)
+    #define BOARD_MAX_SPEED BOARD_TUD_MAX_SPEED
+  #else
+    #define BOARD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+  #endif
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device and Host stacks (dual role)
+#define CFG_TUD_ENABLED 1
+#define CFG_TUH_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_MAX_SPEED
+#define CFG_TUH_MAX_SPEED BOARD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
+#endif
+
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN __attribute__((aligned(4)))
+#endif
+
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION CFG_TUD_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN CFG_TUD_MEM_ALIGN
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC 1
+#define CFG_TUD_MSC 0
+#define CFG_TUD_HID 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_VENDOR 0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+//--------------------------------------------------------------------
+// HOST CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB 1
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+
+#define CFG_TUH_CDC 0
+#define CFG_TUH_HID 0
+#define CFG_TUH_MSC 0
+#define CFG_TUH_VENDOR 0
+
+// max endpoint pair supported by each device
+#define CFG_TUH_ENDPOINT_MAX 16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/dual/dynamic_switch/src/usb_descriptors.c b/examples/dual/dynamic_switch/src/usb_descriptors.c
new file mode 100644
index 000000000..54ffc2c18
--- /dev/null
+++ b/examples/dual/dynamic_switch/src/usb_descriptors.c
@@ -0,0 +1,199 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define PID_MAP(itf, n) ((CFG_TUD_##itf) ? (1 << (n)) : 0)
+#define USB_PID (0x4000 | PID_MAP(CDC, 0) | PID_MAP(MSC, 1) | PID_MAP(HID, 2) | \
+                 PID_MAP(MIDI, 3) | PID_MAP(VENDOR, 4))
+
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+static tusb_desc_device_t const desc_device = {
+  .bLength            = sizeof(tusb_desc_device_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE,
+  .bcdUSB             = USB_BCD,
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+  .idVendor           = USB_VID,
+  .idProduct          = USB_PID,
+  .bcdDevice          = 0x0100,
+
+  .iManufacturer      = 0x01,
+  .iProduct           = 0x02,
+  .iSerialNumber      = 0x03,
+
+  .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum {
+  ITF_NUM_CDC = 0,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_TOTAL
+};
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+  // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+#else
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#endif
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+static uint8_t const desc_fs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+static uint8_t const desc_hs_configuration[] = {
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+};
+#endif
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+static char const *string_desc_arr[] = {
+  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  NULL,                          // 3: Serials, will use unique ID if possible
+  "TinyUSB CDC",                 // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
+
+  switch (index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
+
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
+
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+      if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { return NULL; }
+
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if (chr_count > max_count) { chr_count = max_count; }
+
+      // Convert ASCII string into UTF-16
+      for (size_t i = 0; i < chr_count; i++) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+  return _desc_str;
+}
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 8c53588c3..c8fca48f8 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -98,8 +98,6 @@ int main(void) {
     tuh_task(); // tinyusb host task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -284,7 +282,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c
index 00d059b66..7cf43aef3 100644
--- a/examples/dual/host_info_to_device_cdc/src/main.c
+++ b/examples/dual/host_info_to_device_cdc/src/main.c
@@ -213,13 +213,13 @@ void cdc_task(void) {
   static uint32_t connected_ms = 0;
 
   if (!tud_cdc_connected()) {
-    connected_ms = board_millis();
+    connected_ms = tusb_time_millis_api();
     return;
   }
 
   // delay a bit otherwise we can outpace host's terminal. Linux will set LineState (DTR) then Line Coding.
   // If we send data before Linux's terminal set Line Coding, it can be ignored --> missing data with hardware test loop
-  if (board_millis() - connected_ms < 100) {
+  if (tusb_time_millis_api() - connected_ms < 100) {
     return; // wait for stable connection
   }
 
@@ -246,10 +246,9 @@ static void print_device_info(uint8_t daddr, const tusb_desc_device_t* desc_devi
   cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device->idVendor, desc_device->idProduct);
   uint8_t xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
   if (XFER_RESULT_SUCCESS != xfer_result) {
-    serial[0] = 'n';
-    serial[1] = '/';
-    serial[2] = 'a';
-    serial[3] = 0;
+    serial[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * 1 + 2));
+    serial[1] = '0';
+    serial[2] = 0;
   }
   print_utf16(serial, TU_ARRAY_SIZE(serial));
   cdc_printf("\r\n");
@@ -310,7 +309,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) {
+  if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
     return;// not enough time
   }
   start_ms += blink_interval_ms;
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index f07d63f9d..1ddfc2b5c 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -8,6 +8,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/bare_api/skip.txt b/examples/host/bare_api/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/bare_api/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index c693d6b00..544f38102 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -37,11 +37,13 @@
 #define BUF_COUNT   4
 
 
-tusb_desc_device_t desc_device;
+CFG_TUH_MEM_SECTION tusb_desc_device_t desc_device;
 
-uint8_t buf_pool[BUF_COUNT][64];
+CFG_TUH_MEM_SECTION uint8_t buf_pool[BUF_COUNT][64];
 uint8_t buf_owner[BUF_COUNT] = { 0 }; // device address that owns buffer
 
+CFG_TUH_MEM_SECTION uint16_t temp_buf[128]; // temp buffer for string descriptor
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -74,8 +76,6 @@ int main(void) {
     tuh_task();
     led_blinking_task();
   }
-
-  return 0;
 }
 
 /*------------- TinyUSB Callbacks -------------*/
@@ -120,8 +120,6 @@ void print_device_descriptor(tuh_xfer_t *xfer) {
   printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
 
   // Get String descriptor using Sync API
-  uint16_t temp_buf[128];
-
   printf("  iManufacturer       %u     ", desc_device.iManufacturer);
   if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) {
     print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
@@ -335,7 +333,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < interval_ms) {
+  if (tusb_time_millis_api() - start_ms < interval_ms) {
     return; // not enough time
   }
   start_ms += interval_ms;
@@ -386,12 +384,12 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
   return (int) total_bytes;
 }
 
-static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
-  if ((temp_buf[0] & 0xff) == 0) return;// empty
-  size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
-  size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
-  _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
-  ((uint8_t *) temp_buf)[utf8_len] = '\0';
+static void print_utf16(uint16_t *buf, size_t buf_len) {
+  if ((buf[0] & 0xff) == 0) return;// empty
+  size_t utf16_len = ((buf[0] & 0xff) - 2) / sizeof(uint16_t);
+  size_t utf8_len = (size_t) _count_utf8_bytes(buf + 1, utf16_len);
+  _convert_utf16le_to_utf8(buf + 1, utf16_len, (uint8_t *) buf, sizeof(uint16_t) * buf_len);
+  ((uint8_t *) buf)[utf8_len] = '\0';
 
-  printf("%s", (char *) temp_buf);
+  printf("%s", (char *) buf);
 }
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index f07d63f9d..1ddfc2b5c 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -8,6 +8,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/cdc_msc_hid/skip.txt b/examples/host/cdc_msc_hid/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/cdc_msc_hid/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index c309a7cae..c27ad93fe 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -92,7 +92,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < interval_ms) {
+  if (tusb_time_millis_api() - start_ms < interval_ms) {
     return;// not enough time
   }
   start_ms += interval_ms;
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
index b0460b362..753fa7cd3 100644
--- a/examples/host/cdc_msc_hid_freertos/only.txt
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -6,6 +6,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/cdc_msc_hid_freertos/skip.txt b/examples/host/cdc_msc_hid_freertos/skip.txt
index 2ba4438fd..54e7be1ba 100644
--- a/examples/host/cdc_msc_hid_freertos/skip.txt
+++ b/examples/host/cdc_msc_hid_freertos/skip.txt
@@ -1 +1,2 @@
 mcu:RP2040
+board:lpcxpresso54114
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
index 714c1078a..742935dcf 100644
--- a/examples/host/device_info/only.txt
+++ b/examples/host/device_info/only.txt
@@ -9,6 +9,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/device_info/skip.txt b/examples/host/device_info/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/device_info/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
index 5b914a2ee..b0e38dd6b 100644
--- a/examples/host/device_info/src/main.c
+++ b/examples/host/device_info/src/main.c
@@ -105,7 +105,6 @@ int main(void) {
     tuh_task();     // tinyusb host task
     led_blinking_task(NULL);
   }
-  return 0;
 #endif
 }
 
@@ -130,11 +129,10 @@ void tuh_mount_cb(uint8_t daddr) {
   }
   if (XFER_RESULT_SUCCESS != xfer_result) {
     uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial;
-    serial[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * 3 + 2));
-    serial[1] = 'n';
-    serial[2] = '/';
-    serial[3] = 'a';
-    serial[4] = 0;
+
+    serial[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * 1 + 2));
+    serial[1] = '0'; // simply 0
+    serial[2] = 0;
   }
   print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2);
   printf("\r\n");
@@ -247,7 +245,7 @@ void led_blinking_task(void* param) {
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
 #else
-    if (board_millis() - start_ms < blink_interval_ms) {
+    if (tusb_time_millis_api() - start_ms < blink_interval_ms) {
       return; // not enough time
     }
 #endif
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index 8ec2f5cfe..45ca6846f 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -8,6 +8,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/hid_controller/skip.txt b/examples/host/hid_controller/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/hid_controller/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index f8c3d029b..5417811f0 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -168,7 +168,7 @@ void hid_app_task(void)
     const uint32_t interval_ms = 200;
     static uint32_t start_ms = 0;
 
-    uint32_t current_time_ms = board_millis();
+    uint32_t current_time_ms = tusb_time_millis_api();
     if ( current_time_ms - start_ms >= interval_ms)
     {
       start_ms = current_time_ms;
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index fa70d7d1a..a9eebc90b 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -79,7 +79,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt
index 9d647a340..c71aacd87 100644
--- a/examples/host/midi_rx/only.txt
+++ b/examples/host/midi_rx/only.txt
@@ -11,6 +11,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/midi_rx/skip.txt b/examples/host/midi_rx/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/midi_rx/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/midi_rx/src/main.c b/examples/host/midi_rx/src/main.c
index 78b1a11b9..fb36906c6 100644
--- a/examples/host/midi_rx/src/main.c
+++ b/examples/host/midi_rx/src/main.c
@@ -58,8 +58,6 @@ int main(void) {
     led_blinking_task();
     midi_host_rx_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -72,7 +70,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < interval_ms) return;// not enough time
+  if (tusb_time_millis_api() - start_ms < interval_ms) return;// not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index f07d63f9d..1ddfc2b5c 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -8,6 +8,8 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:LPC54
+mcu:LPC55
 mcu:MAX3421
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
diff --git a/examples/host/msc_file_explorer/skip.txt b/examples/host/msc_file_explorer/skip.txt
new file mode 100644
index 000000000..308796869
--- /dev/null
+++ b/examples/host/msc_file_explorer/skip.txt
@@ -0,0 +1 @@
+board:lpcxpresso54114
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index f9ec0ff5f..f6bf9a60a 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -92,8 +92,6 @@ int main(void) {
     msc_app_task();
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -118,7 +116,7 @@ void led_blinking_task(void) {
   static bool led_state = false;
 
   // Blink every interval ms
-  if (board_millis() - start_ms < interval_ms) return; // not enough time
+  if (tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 40a9ef57e..6ac63e937 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -49,11 +49,14 @@
 #define CLI_BINDING_COUNT   8
 
 static EmbeddedCli *_cli;
-static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
+static CLI_UINT     cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
 
 //------------- Elm Chan FatFS -------------//
-static FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device
-static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX];
+static CFG_TUH_MEM_SECTION FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device
+static volatile bool              _disk_busy[CFG_TUH_DEVICE_MAX];
+
+static CFG_TUH_MEM_SECTION FIL     file1, file2;
+static CFG_TUH_MEM_SECTION uint8_t rw_buf[512];
 
 // define the buffer to be place in USB/DMA memory with correct alignment/cache line size
 CFG_TUH_MEM_SECTION static struct {
@@ -67,34 +70,30 @@ CFG_TUH_MEM_SECTION static struct {
 
 bool cli_init(void);
 
-bool msc_app_init(void)
-{
-  for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) {
+bool msc_app_init(void) {
+  for (size_t i = 0; i < CFG_TUH_DEVICE_MAX; i++) {
     _disk_busy[i] = false;
   }
 
-  // disable stdout buffered for echoing typing command
-  #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
+// disable stdout buffered for echoing typing command
+#ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
   setbuf(stdout, NULL);
-  #endif
+#endif
 
   cli_init();
 
   return true;
 }
 
-void msc_app_task(void)
-{
+void msc_app_task(void) {
   if (!_cli) {
     return;
   }
 
   int ch = board_getchar();
-  if ( ch > 0 )
-  {
-    while( ch > 0 )
-    {
-      embeddedCliReceiveChar(_cli, (char) ch);
+  if (ch > 0) {
+    while (ch > 0) {
+      embeddedCliReceiveChar(_cli, (char)ch);
       ch = board_getchar();
     }
     embeddedCliProcess(_cli);
@@ -105,33 +104,32 @@ void msc_app_task(void)
 //
 //--------------------------------------------------------------------+
 
-static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) {
-  msc_cbw_t const* cbw = cb_data->cbw;
-  msc_csw_t const* csw = cb_data->csw;
+static bool inquiry_complete_cb(uint8_t dev_addr, const tuh_msc_complete_data_t *cb_data) {
+  const msc_cbw_t *cbw = cb_data->cbw;
+  const msc_csw_t *csw = cb_data->csw;
 
-  if (csw->status != 0)
-  {
+  if (csw->status != 0) {
     printf("Inquiry failed\r\n");
     return false;
   }
 
   // Print out Vendor ID, Product ID and Rev
-  printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev);
+  printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id,
+         scsi_resp.inquiry.product_rev);
 
   // Get capacity of device
-  uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
-  uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+  const uint32_t block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+  const uint32_t block_size  = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024 * 1024) / block_size));
   // printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
 
   // For simplicity: we only mount 1 LUN per device
-  uint8_t const drive_num = dev_addr-1;
-  char drive_path[3] = "0:";
+  const uint8_t drive_num     = dev_addr - 1;
+  char          drive_path[3] = "0:";
   drive_path[0] += drive_num;
 
-  if ( f_mount(&fatfs[drive_num], drive_path, 1) != FR_OK )
-  {
+  if (f_mount(&fatfs[drive_num], drive_path, 1) != FR_OK) {
     puts("mount failed");
   }
 
@@ -139,151 +137,134 @@ static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const
   f_chdir(drive_path);
 
   // print the drive label
-//  char label[34];
-//  if ( FR_OK == f_getlabel(drive_path, label, NULL) )
-//  {
-//    puts(label);
-//  }
+  //  char label[34];
+  //  if ( FR_OK == f_getlabel(drive_path, label, NULL) )
+  //  {
+  //    puts(label);
+  //  }
 
   return true;
 }
 
 //------------- IMPLEMENTATION -------------//
-void tuh_msc_mount_cb(uint8_t dev_addr)
-{
+void tuh_msc_mount_cb(uint8_t dev_addr) {
   printf("A MassStorage device is mounted\r\n");
 
-  uint8_t const lun = 0;
+  const uint8_t lun = 0;
   tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0);
 }
 
-void tuh_msc_umount_cb(uint8_t dev_addr)
-{
+void tuh_msc_umount_cb(uint8_t dev_addr) {
   printf("A MassStorage device is unmounted\r\n");
 
-  uint8_t const drive_num = dev_addr-1;
-  char drive_path[3] = "0:";
+  const uint8_t drive_num     = dev_addr - 1;
+  char          drive_path[3] = "0:";
   drive_path[0] += drive_num;
 
   f_unmount(drive_path);
 
-//  if ( phy_disk == f_get_current_drive() )
-//  { // active drive is unplugged --> change to other drive
-//    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
-//    {
-//      if ( disk_is_ready(i) )
-//      {
-//        f_chdrive(i);
-//        cli_init(); // refractor, rename
-//      }
-//    }
-//  }
+  //  if ( phy_disk == f_get_current_drive() )
+  //  { // active drive is unplugged --> change to other drive
+  //    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
+  //    {
+  //      if ( disk_is_ready(i) )
+  //      {
+  //        f_chdrive(i);
+  //        cli_init(); // refractor, rename
+  //      }
+  //    }
+  //  }
 }
 
 //--------------------------------------------------------------------+
 // DiskIO
 //--------------------------------------------------------------------+
 
-static void wait_for_disk_io(BYTE pdrv)
-{
-  while(_disk_busy[pdrv])
-  {
+static void wait_for_disk_io(BYTE pdrv) {
+  while (_disk_busy[pdrv]) {
     tuh_task();
   }
 }
 
-static bool disk_io_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
-  (void) dev_addr; (void) cb_data;
-  _disk_busy[dev_addr-1] = false;
+static bool disk_io_complete(uint8_t dev_addr, const tuh_msc_complete_data_t *cb_data) {
+  (void)dev_addr;
+  (void)cb_data;
+  _disk_busy[dev_addr - 1] = false;
   return true;
 }
 
-DSTATUS disk_status (
-	BYTE pdrv		/* Physical drive nmuber to identify the drive */
-)
-{
+DSTATUS disk_status(BYTE pdrv /* Physical drive nmuber to identify the drive */
+) {
   uint8_t dev_addr = pdrv + 1;
   return tuh_msc_mounted(dev_addr) ? 0 : STA_NODISK;
 }
 
-DSTATUS disk_initialize (
-	BYTE pdrv				/* Physical drive nmuber to identify the drive */
-)
-{
-  (void) pdrv;
-	return 0; // nothing to do
+DSTATUS disk_initialize(BYTE pdrv /* Physical drive nmuber to identify the drive */
+) {
+  (void)pdrv;
+  return 0;                       // nothing to do
 }
 
-DRESULT disk_read (
-	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
-	BYTE *buff,		/* Data buffer to store read data */
-	LBA_t sector,	/* Start sector in LBA */
-	UINT count		/* Number of sectors to read */
-)
-{
-	uint8_t const dev_addr = pdrv + 1;
-	uint8_t const lun = 0;
+DRESULT disk_read(BYTE  pdrv,     /* Physical drive nmuber to identify the drive */
+                  BYTE *buff,     /* Data buffer to store read data */
+                  LBA_t sector,   /* Start sector in LBA */
+                  UINT  count     /* Number of sectors to read */
+) {
+  const uint8_t dev_addr = pdrv + 1;
+  const uint8_t lun      = 0;
 
-	_disk_busy[pdrv] = true;
-	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
-	wait_for_disk_io(pdrv);
+  _disk_busy[pdrv] = true;
+  tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t)count, disk_io_complete, 0);
+  wait_for_disk_io(pdrv);
 
-	return RES_OK;
+  return RES_OK;
 }
 
 #if FF_FS_READONLY == 0
 
-DRESULT disk_write (
-	BYTE pdrv,			/* Physical drive nmuber to identify the drive */
-	const BYTE *buff,	/* Data to be written */
-	LBA_t sector,		/* Start sector in LBA */
-	UINT count			/* Number of sectors to write */
-)
-{
-	uint8_t const dev_addr = pdrv + 1;
-	uint8_t const lun = 0;
+DRESULT disk_write(BYTE        pdrv,   /* Physical drive nmuber to identify the drive */
+                   const BYTE *buff,   /* Data to be written */
+                   LBA_t       sector, /* Start sector in LBA */
+                   UINT        count   /* Number of sectors to write */
+) {
+  const uint8_t dev_addr = pdrv + 1;
+  const uint8_t lun      = 0;
 
-	_disk_busy[pdrv] = true;
-	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
-	wait_for_disk_io(pdrv);
+  _disk_busy[pdrv] = true;
+  tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t)count, disk_io_complete, 0);
+  wait_for_disk_io(pdrv);
 
-	return RES_OK;
+  return RES_OK;
 }
 
 #endif
 
-DRESULT disk_ioctl (
-	BYTE pdrv,		/* Physical drive nmuber (0..) */
-	BYTE cmd,		/* Control code */
-	void *buff		/* Buffer to send/receive control data */
-)
-{
-  uint8_t const dev_addr = pdrv + 1;
-  uint8_t const lun = 0;
-  switch ( cmd )
-  {
+DRESULT disk_ioctl(BYTE  pdrv, /* Physical drive nmuber (0..) */
+                   BYTE  cmd,  /* Control code */
+                   void *buff  /* Buffer to send/receive control data */
+) {
+  const uint8_t dev_addr = pdrv + 1;
+  const uint8_t lun      = 0;
+  switch (cmd) {
     case CTRL_SYNC:
       // nothing to do since we do blocking
       return RES_OK;
 
     case GET_SECTOR_COUNT:
-      *((DWORD*) buff) = (WORD) tuh_msc_get_block_count(dev_addr, lun);
+      *((DWORD *)buff) = (WORD)tuh_msc_get_block_count(dev_addr, lun);
       return RES_OK;
 
     case GET_SECTOR_SIZE:
-      *((WORD*) buff) = (WORD) tuh_msc_get_block_size(dev_addr, lun);
+      *((WORD *)buff) = (WORD)tuh_msc_get_block_size(dev_addr, lun);
       return RES_OK;
 
     case GET_BLOCK_SIZE:
-      *((DWORD*) buff) = 1;    // erase block size in units of sector size
+      *((DWORD *)buff) = 1; // erase block size in units of sector size
       return RES_OK;
 
     default:
       return RES_PARERR;
   }
-
-	return RES_OK;
 }
 
 //--------------------------------------------------------------------+
@@ -300,12 +281,11 @@ void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context);
 
 static void cli_write_char(EmbeddedCli *cli, char c) {
-  (void) cli;
-  putchar((int) c);
+  (void)cli;
+  putchar((int)c);
 }
 
-bool cli_init(void)
-{
+bool cli_init(void) {
   EmbeddedCliConfig *config = embeddedCliDefaultConfig();
   config->cliBuffer         = cli_buffer;
   config->cliBufferSize     = CLI_BUFFER_SIZE;
@@ -321,230 +301,173 @@ bool cli_init(void)
 
   _cli->writeChar = cli_write_char;
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "cat",
-    "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..",
-    true,
-    NULL,
-    cli_cmd_cat
-  });
+  embeddedCliAddBinding(_cli,
+                        (CliCommandBinding){"cat", "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..",
+                                            true, NULL, cli_cmd_cat});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "cd",
-    "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
-    true,
-    NULL,
-    cli_cmd_cd
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"cd", "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
+                                                  true, NULL, cli_cmd_cd});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "cp",
-    "Usage: cp SOURCE DEST\r\n\tCopy SOURCE to DEST.",
-    true,
-    NULL,
-    cli_cmd_cp
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"cp", "Usage: cp SOURCE DEST\r\n\tCopy SOURCE to DEST.", true, NULL,
+                                                  cli_cmd_cp});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "ls",
-    "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).",
-    true,
-    NULL,
-    cli_cmd_ls
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"ls",
+                                                  "Usage: ls [DIR]...\r\n\tList information about the FILEs (the "
+                                                  "current directory by default).",
+                                                  true, NULL, cli_cmd_ls});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "pwd",
-    "Usage: pwd\r\n\tPrint the name of the current working directory.",
-    true,
-    NULL,
-    cli_cmd_pwd
-  });
+  embeddedCliAddBinding(_cli,
+                        (CliCommandBinding){"pwd", "Usage: pwd\r\n\tPrint the name of the current working directory.",
+                                            true, NULL, cli_cmd_pwd});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "mkdir",
-    "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..",
-    true,
-    NULL,
-    cli_cmd_mkdir
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"mkdir",
+                                                  "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not "
+                                                  "already exist..",
+                                                  true, NULL, cli_cmd_mkdir});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "mv",
-    "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST.",
-    true,
-    NULL,
-    cli_cmd_mv
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"mv", "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST.", true,
+                                                  NULL, cli_cmd_mv});
 
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "rm",
-    "Usage: rm [FILE]...\r\n\tRemove (unlink) the FILE(s).",
-    true,
-    NULL,
-    cli_cmd_rm
-  });
+  embeddedCliAddBinding(_cli, (CliCommandBinding){"rm", "Usage: rm [FILE]...\r\n\tRemove (unlink) the FILE(s).", true,
+                                                  NULL, cli_cmd_rm});
 
   return true;
 }
 
-void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // need at least 1 argument
-  if ( argc == 0 )
-  {
+  if (argc == 0) {
     printf("invalid arguments\r\n");
     return;
   }
 
-  for(uint16_t i=0; i<argc; i++)
-  {
-    FIL fi;
-    const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1
+  for (uint16_t i = 0; i < argc; i++) {
+    FIL        *fi    = &file1;
+    const char *fpath = embeddedCliGetToken(args, i + 1); // token count from 1
 
-    if ( FR_OK != f_open(&fi, fpath, FA_READ) )
-    {
+    if (FR_OK != f_open(fi, fpath, FA_READ)) {
       printf("%s: No such file or directory\r\n", fpath);
-    }else
-    {
-      uint8_t buf[512];
+    } else {
       UINT count = 0;
-      while ( (FR_OK == f_read(&fi, buf, sizeof(buf), &count)) && (count > 0) )
-      {
-        for(UINT c = 0; c < count; c++)
-        {
-          const uint8_t ch = buf[c];
-          if (isprint(ch) || iscntrl(ch))
-          {
+      while ((FR_OK == f_read(fi, rw_buf, sizeof(rw_buf), &count)) && (count > 0)) {
+        for (UINT c = 0; c < count; c++) {
+          const uint8_t ch = rw_buf[c];
+          if (isprint(ch) || iscntrl(ch)) {
             putchar(ch);
-          }else
-          {
+          } else {
             putchar('.');
           }
         }
       }
     }
 
-    f_close(&fi);
+    f_close(fi);
   }
 }
 
-void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // only support 1 argument
-  if ( argc != 1 )
-  {
+  if (argc != 1) {
     printf("invalid arguments\r\n");
     return;
   }
 
   // default is current directory
-  const char* dpath = args;
+  const char *dpath = args;
 
-  if ( FR_OK != f_chdir(dpath) )
-  {
+  if (FR_OK != f_chdir(dpath)) {
     printf("%s: No such file or directory\r\n", dpath);
     return;
   }
 }
 
-void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
-  if ( argc != 2 )
-  {
+  if (argc != 2) {
     printf("invalid arguments\r\n");
     return;
   }
 
   // default is current directory
-  const char* src = embeddedCliGetToken(args, 1);
-  const char* dst = embeddedCliGetToken(args, 2);
+  const char *src = embeddedCliGetToken(args, 1);
+  const char *dst = embeddedCliGetToken(args, 2);
 
-  FIL f_src;
-  FIL f_dst;
+  FIL *f_src = &file1;
+  FIL *f_dst = &file2;
 
-  if ( FR_OK != f_open(&f_src, src, FA_READ) )
-  {
+  if (FR_OK != f_open(f_src, src, FA_READ)) {
     printf("cannot stat '%s': No such file or directory\r\n", src);
     return;
   }
 
-  if ( FR_OK != f_open(&f_dst, dst, FA_WRITE | FA_CREATE_ALWAYS) )
-  {
+  if (FR_OK != f_open(f_dst, dst, FA_WRITE | FA_CREATE_ALWAYS)) {
     printf("cannot create '%s'\r\n", dst);
     return;
-  }else
-  {
-    uint8_t buf[512];
+  } else {
     UINT rd_count = 0;
-    while ( (FR_OK == f_read(&f_src, buf, sizeof(buf), &rd_count)) && (rd_count > 0) )
-    {
+    while ((FR_OK == f_read(f_src, rw_buf, sizeof(rw_buf), &rd_count)) && (rd_count > 0)) {
       UINT wr_count = 0;
 
-      if ( FR_OK != f_write(&f_dst, buf, rd_count, &wr_count) )
-      {
+      if (FR_OK != f_write(f_dst, rw_buf, rd_count, &wr_count)) {
         printf("cannot write to '%s'\r\n", dst);
         break;
       }
     }
   }
 
-  f_close(&f_src);
-  f_close(&f_dst);
+  f_close(f_src);
+  f_close(f_dst);
 }
 
-void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // only support 1 argument
-  if ( argc > 1 )
-  {
+  if (argc > 1) {
     printf("invalid arguments\r\n");
     return;
   }
 
   // default is current directory
-  const char* dpath = ".";
-  if (argc) dpath = args;
+  const char *dpath = ".";
+  if (argc) {
+    dpath = args;
+  }
 
   DIR dir;
-  if ( FR_OK != f_opendir(&dir, dpath) )
-  {
+  if (FR_OK != f_opendir(&dir, dpath)) {
     printf("cannot access '%s': No such file or directory\r\n", dpath);
     return;
   }
 
   FILINFO fno;
-  while( (f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0) )
-  {
-    if ( fno.fname[0] != '.' ) // ignore . and .. entry
+  while ((f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0)) {
+    if (fno.fname[0] != '.') // ignore . and .. entry
     {
-      if ( fno.fattrib & AM_DIR )
-      {
+      if (fno.fattrib & AM_DIR) {
         // directory
         printf("/%s\r\n", fno.fname);
-      }else
-      {
+      } else {
         printf("%-40s", fno.fname);
-        if (fno.fsize < 1024)
-        {
+        if (fno.fsize < 1024) {
           printf("%" PRIu32 " B\r\n", fno.fsize);
-        }else
-        {
+        } else {
           printf("%" PRIu32 " KB\r\n", fno.fsize / 1024);
         }
       }
@@ -554,90 +477,81 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
   f_closedir(&dir);
 }
 
-void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
   uint16_t argc = embeddedCliGetTokenCount(args);
 
-  if (argc != 0)
-  {
+  if (argc != 0) {
     printf("invalid arguments\r\n");
     return;
   }
 
   char path[256];
-  if (FR_OK != f_getcwd(path, sizeof(path)))
-  {
+  if (FR_OK != f_getcwd(path, sizeof(path))) {
     printf("cannot get current working directory\r\n");
   }
 
   puts(path);
 }
 
-void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // only support 1 argument
-  if ( argc != 1 )
-  {
+  if (argc != 1) {
     printf("invalid arguments\r\n");
     return;
   }
 
   // default is current directory
-  const char* dpath = args;
+  const char *dpath = args;
 
-  if ( FR_OK != f_mkdir(dpath) )
-  {
+  if (FR_OK != f_mkdir(dpath)) {
     printf("%s: cannot create this directory\r\n", dpath);
     return;
   }
 }
 
-void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
-  if ( argc != 2 )
-  {
+  if (argc != 2) {
     printf("invalid arguments\r\n");
     return;
   }
 
   // default is current directory
-  const char* src = embeddedCliGetToken(args, 1);
-  const char* dst = embeddedCliGetToken(args, 2);
+  const char *src = embeddedCliGetToken(args, 1);
+  const char *dst = embeddedCliGetToken(args, 2);
 
-  if ( FR_OK != f_rename(src, dst) )
-  {
+  if (FR_OK != f_rename(src, dst)) {
     printf("cannot mv %s to %s\r\n", src, dst);
     return;
   }
 }
 
-void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
+void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context) {
+  (void)cli;
+  (void)context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // need at least 1 argument
-  if ( argc == 0 )
-  {
+  if (argc == 0) {
     printf("invalid arguments\r\n");
     return;
   }
 
-  for(uint16_t i=0; i<argc; i++)
-  {
-    const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1
+  for (uint16_t i = 0; i < argc; i++) {
+    const char *fpath = embeddedCliGetToken(args, i + 1); // token count from 1
 
-    if ( FR_OK != f_unlink(fpath) )
-    {
+    if (FR_OK != f_unlink(fpath)) {
       printf("cannot remove '%s': No such file or directory\r\n", fpath);
     }
   }
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index de0db4721..f6191bfe8 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -184,7 +184,7 @@ void led_blinking_task(void)
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json
index 440ef8733..fabbeed93 100644
--- a/hw/bsp/BoardPresets.json
+++ b/hw/bsp/BoardPresets.json
@@ -175,6 +175,10 @@
       "inherits": "default"
     },
     {
+      "name": "ek_tm4c1294xl",
+      "inherits": "default"
+    },
+    {
       "name": "f1c100s",
       "inherits": "default"
     },
@@ -719,6 +723,10 @@
       "inherits": "default"
     },
     {
+      "name": "stm32h747disco",
+      "inherits": "default"
+    },
+    {
       "name": "stm32h750_weact",
       "inherits": "default"
     },
@@ -1109,6 +1117,11 @@
       "configurePreset": "ek_tm4c123gxl"
     },
     {
+      "name": "ek_tm4c1294xl",
+      "description": "Build preset for the ek_tm4c1294xl board",
+      "configurePreset": "ek_tm4c1294xl"
+    },
+    {
       "name": "espressif_addax_1",
       "description": "Build preset for the espressif_addax_1 board",
       "configurePreset": "espressif_addax_1"
@@ -1834,6 +1847,11 @@
       "configurePreset": "stm32h745disco"
     },
     {
+      "name": "stm32h747disco",
+      "description": "Build preset for the stm32h747disco board",
+      "configurePreset": "stm32h747disco"
+    },
+    {
       "name": "stm32h750_weact",
       "description": "Build preset for the stm32h750_weact board",
       "configurePreset": "stm32h750_weact"
@@ -2543,6 +2561,19 @@
       ]
     },
     {
+      "name": "ek_tm4c1294xl",
+      "steps": [
+        {
+          "type": "configure",
+          "name": "ek_tm4c1294xl"
+        },
+        {
+          "type": "build",
+          "name": "ek_tm4c1294xl"
+        }
+      ]
+    },
+    {
       "name": "espressif_addax_1",
       "steps": [
         {
@@ -4428,6 +4459,19 @@
       ]
     },
     {
+      "name": "stm32h747disco",
+      "steps": [
+        {
+          "type": "configure",
+          "name": "stm32h747disco"
+        },
+        {
+          "type": "build",
+          "name": "stm32h747disco"
+        }
+      ]
+    },
+    {
       "name": "stm32h750_weact",
       "steps": [
         {
diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c
index a6c2217fe..b7dbcbd98 100644
--- a/hw/bsp/at32f402_405/family.c
+++ b/hw/bsp/at32f402_405/family.c
@@ -258,7 +258,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len)
   {
     system_ticks++;
   }
-  uint32_t board_millis(void)
+  uint32_t tusb_time_millis_api(void)
   {
     return system_ticks;
   }
diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c
index dd9b85dc5..d4a7e446d 100644
--- a/hw/bsp/at32f403a_407/family.c
+++ b/hw/bsp/at32f403a_407/family.c
@@ -250,7 +250,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c
index bdaed523c..adf29e097 100644
--- a/hw/bsp/at32f413/family.c
+++ b/hw/bsp/at32f413/family.c
@@ -250,7 +250,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c
index 2fbd4c821..b592bf6c5 100644
--- a/hw/bsp/at32f415/family.c
+++ b/hw/bsp/at32f415/family.c
@@ -246,7 +246,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c
index f30c6a83f..71cb559dc 100644
--- a/hw/bsp/at32f423/family.c
+++ b/hw/bsp/at32f423/family.c
@@ -250,7 +250,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c
index 4ff4c8d6a..7f443509e 100644
--- a/hw/bsp/at32f425/family.c
+++ b/hw/bsp/at32f425/family.c
@@ -254,7 +254,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c
index 01dd429f8..6c6bc4d72 100644
--- a/hw/bsp/at32f435_437/family.c
+++ b/hw/bsp/at32f435_437/family.c
@@ -320,7 +320,7 @@ volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void) {
   system_ticks++;
 }
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 void SVC_Handler(void) {
diff --git a/hw/bsp/at32f45x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f45x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..c5b89452e
--- /dev/null
+++ b/hw/bsp/at32f45x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,176 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+// Include MCU header
+  #include "at32f45x.h"
+#endif
+
+/* Cortex-M4 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      system_core_clock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
+  #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/at32f45x/at32f45x_clock.c b/hw/bsp/at32f45x/at32f45x_clock.c
new file mode 100644
index 000000000..a66a8b1aa
--- /dev/null
+++ b/hw/bsp/at32f45x/at32f45x_clock.c
@@ -0,0 +1,114 @@
+/**
+  **************************************************************************
+  * @file     at32f45x_clock.c
+  * @brief    system clock config program
+  **************************************************************************
+  *
+  * Copyright (c) 2025, Artery Technology, All rights reserved.
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x_clock.h"
+
+/**
+  * @brief  system clock config program
+  * @note   the system clock is configured as follow:
+  *         - system clock        = (hext * pll_ns)/(pll_ms * pll_fp)
+  *         - system clock source = pll (hext)
+  *         - hext                = 8000000
+  *         - sclk                = 192000000
+  *         - ahbdiv              = 1
+  *         - ahbclk              = 192000000
+  *         - apb2div             = 1
+  *         - apb2clk             = 192000000
+  *         - apb1div             = 1
+  *         - apb1clk             = 192000000
+  *         - pll_ns              = 96
+  *         - pll_ms              = 1
+  *         - pll_fp              = 4
+  * @param  none
+  * @retval none
+  */
+void system_clock_config(void)
+{
+  /* reset crm */
+  crm_reset();
+
+  /* set the flash clock divider */
+  flash_psr_set(FLASH_WAIT_CYCLE_5);
+
+  /* enable pwc periph clock */
+  crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
+
+  /* config ldo voltage */
+  pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
+
+  crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
+
+  /* wait till hext is ready */
+  while(crm_hext_stable_wait() == ERROR)
+  {
+  }
+
+  /* config pll clock resource */
+  crm_pll_config(CRM_PLL_SOURCE_HEXT, 96, 1, CRM_PLL_FP_4);
+
+  /* config pllu divider */
+  crm_pllu_div_set(CRM_PLL_FU_16);
+
+  /* pllu enable  */
+  crm_pllu_output_set(TRUE);
+
+  /* enable pll */
+  crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
+
+  /* wait till pll is ready */
+  while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
+  {
+  }
+
+  /* config ahbclk */
+  crm_ahb_div_set(CRM_AHB_DIV_1);
+
+  /* config apb3clk, the maximum frequency of APB3 clock is 90 MHz */
+  crm_apb3_div_set(CRM_APB3_DIV_4);
+
+  /* config apb2clk, the maximum frequency of APB2 clock is 192 MHz */
+  crm_apb2_div_set(CRM_APB2_DIV_1);
+
+  /* config apb1clk, the maximum frequency of APB1 clock is 192 MHz */
+  crm_apb1_div_set(CRM_APB1_DIV_1);
+
+  /* enable auto step mode */
+  crm_auto_step_mode_enable(TRUE);
+
+  /* select pll as system clock source */
+  crm_sysclk_switch(CRM_SCLK_PLL);
+
+  /* wait till pll is used as system clock source */
+  while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
+  {
+  }
+
+  /* disable auto step mode */
+  crm_auto_step_mode_enable(FALSE);
+
+  /* update system_core_clock global variable */
+  system_core_clock_update();
+}
diff --git a/hw/bsp/at32f45x/at32f45x_clock.h b/hw/bsp/at32f45x/at32f45x_clock.h
new file mode 100644
index 000000000..a372a605b
--- /dev/null
+++ b/hw/bsp/at32f45x/at32f45x_clock.h
@@ -0,0 +1,44 @@
+/**
+  **************************************************************************
+  * @file     at32f45x_clock.h
+  * @brief    header file of clock program
+  **************************************************************************
+  *
+  * Copyright (c) 2025, Artery Technology, All rights reserved.
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CLOCK_H
+#define __AT32F45x_CLOCK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/* exported functions ------------------------------------------------------- */
+void system_clock_config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/at32f45x/at32f45x_conf.h b/hw/bsp/at32f45x/at32f45x_conf.h
new file mode 100644
index 000000000..90182437f
--- /dev/null
+++ b/hw/bsp/at32f45x/at32f45x_conf.h
@@ -0,0 +1,174 @@
+/**
+  **************************************************************************
+  * @file     at32f45x_conf.h
+  * @brief    at32f45x config header file
+  **************************************************************************
+  *
+  * Copyright (c) 2025, Artery Technology, All rights reserved.
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CONF_H
+#define __AT32F45x_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief in the following line adjust the value of high speed external crystal (hext)
+  * used in your application
+  *
+  * tip: to avoid modifying this file each time you need to use different hext, you
+  *      can define the hext value in your toolchain compiler preprocessor.
+  *
+  */
+#if !defined  HEXT_VALUE
+#define HEXT_VALUE                       ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */
+#endif
+
+/**
+  * @brief in the following line adjust the high speed external crystal (hext) startup
+  * timeout value
+  */
+#define HEXT_STARTUP_TIMEOUT             ((uint16_t)0x3000)  /*!< time out for hext start up */
+#define HICK_VALUE                       ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
+#define LEXT_VALUE                       ((uint32_t)32768)   /*!< value of the low speed external clock in hz */
+
+/* module define -------------------------------------------------------------*/
+#define ACC_MODULE_ENABLED
+#define ADC_MODULE_ENABLED
+#define AES_MODULE_ENABLED
+#define CAN_MODULE_ENABLED
+#define CRC_MODULE_ENABLED
+#define CRM_MODULE_ENABLED
+#define DAC_MODULE_ENABLED
+#define DEBUG_MODULE_ENABLED
+#define DMA_MODULE_ENABLED
+#define EMAC_MODULE_ENABLED
+#define ERTC_MODULE_ENABLED
+#define EXINT_MODULE_ENABLED
+#define FLASH_MODULE_ENABLED
+#define GPIO_MODULE_ENABLED
+#define I2C_MODULE_ENABLED
+#define MISC_MODULE_ENABLED
+#define PWC_MODULE_ENABLED
+#define QSPI_MODULE_ENABLED
+#define SCFG_MODULE_ENABLED
+#define SDIO_MODULE_ENABLED
+#define SPI_MODULE_ENABLED
+#define TMR_MODULE_ENABLED
+#define TRNG_MODULE_ENABLED
+#define USART_MODULE_ENABLED
+#define USB_MODULE_ENABLED
+#define WWDT_MODULE_ENABLED
+#define WDT_MODULE_ENABLED
+#define XMC_MODULE_ENABLED
+
+/* includes ------------------------------------------------------------------*/
+#ifdef ACC_MODULE_ENABLED
+#include "at32f45x_acc.h"
+#endif
+#ifdef ADC_MODULE_ENABLED
+#include "at32f45x_adc.h"
+#endif
+#ifdef AES_MODULE_ENABLED
+#include "at32f45x_aes.h"
+#endif
+#ifdef CAN_MODULE_ENABLED
+#include "at32f45x_can.h"
+#endif
+#ifdef CRC_MODULE_ENABLED
+#include "at32f45x_crc.h"
+#endif
+#ifdef CRM_MODULE_ENABLED
+#include "at32f45x_crm.h"
+#endif
+#ifdef DAC_MODULE_ENABLED
+#include "at32f45x_dac.h"
+#endif
+#ifdef DEBUG_MODULE_ENABLED
+#include "at32f45x_debug.h"
+#endif
+#ifdef DMA_MODULE_ENABLED
+#include "at32f45x_dma.h"
+#endif
+#ifdef EMAC_MODULE_ENABLED
+#include "at32f45x_emac.h"
+#endif
+#ifdef ERTC_MODULE_ENABLED
+#include "at32f45x_ertc.h"
+#endif
+#ifdef EXINT_MODULE_ENABLED
+#include "at32f45x_exint.h"
+#endif
+#ifdef FLASH_MODULE_ENABLED
+#include "at32f45x_flash.h"
+#endif
+#ifdef GPIO_MODULE_ENABLED
+#include "at32f45x_gpio.h"
+#endif
+#ifdef I2C_MODULE_ENABLED
+#include "at32f45x_i2c.h"
+#endif
+#ifdef MISC_MODULE_ENABLED
+#include "at32f45x_misc.h"
+#endif
+#ifdef PWC_MODULE_ENABLED
+#include "at32f45x_pwc.h"
+#endif
+#ifdef QSPI_MODULE_ENABLED
+#include "at32f45x_qspi.h"
+#endif
+#ifdef SCFG_MODULE_ENABLED
+#include "at32f45x_scfg.h"
+#endif
+#ifdef SDIO_MODULE_ENABLED
+#include "at32f45x_sdio.h"
+#endif
+#ifdef SPI_MODULE_ENABLED
+#include "at32f45x_spi.h"
+#endif
+#ifdef TMR_MODULE_ENABLED
+#include "at32f45x_tmr.h"
+#endif
+#ifdef TRNG_MODULE_ENABLED
+#include "at32f45x_trng.h"
+#endif
+#ifdef USART_MODULE_ENABLED
+#include "at32f45x_usart.h"
+#endif
+#ifdef USB_MODULE_ENABLED
+#include "at32f45x_usb.h"
+#endif
+#ifdef WDT_MODULE_ENABLED
+#include "at32f45x_wdt.h"
+#endif
+#ifdef WWDT_MODULE_ENABLED
+#include "at32f45x_wwdt.h"
+#endif
+#ifdef XMC_MODULE_ENABLED
+#include "at32f45x_xmc.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/at32f45x/at32f45x_int.c b/hw/bsp/at32f45x/at32f45x_int.c
new file mode 100644
index 000000000..b3ba6ad9c
--- /dev/null
+++ b/hw/bsp/at32f45x/at32f45x_int.c
@@ -0,0 +1,100 @@
+/**
+  **************************************************************************
+  * @file     at32f45x_int.c
+  * @brief    main interrupt service routines.
+  **************************************************************************
+  *
+  * Copyright (c) 2025, Artery Technology, All rights reserved.
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x_int.h"
+
+/** @addtogroup AT32F45X_BSP
+  * @{
+  */
+
+/** @addtogroup AT32F45X_USB_Device_Keyboard
+  * @{
+  */
+
+/**
+  * @brief  this function handles nmi exception.
+  * @param  none
+  * @retval none
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  this function handles memory manage exception.
+  * @param  none
+  * @retval none
+  */
+void MemManage_Handler(void)
+{
+  /* go to infinite loop when memory manage exception occurs */
+  while(1)
+  {
+  }
+}
+
+/**
+  * @brief  this function handles bus fault exception.
+  * @param  none
+  * @retval none
+  */
+void BusFault_Handler(void)
+{
+  /* go to infinite loop when bus fault exception occurs */
+  while(1)
+  {
+  }
+}
+
+/**
+  * @brief  this function handles usage fault exception.
+  * @param  none
+  * @retval none
+  */
+void UsageFault_Handler(void)
+{
+  /* go to infinite loop when usage fault exception occurs */
+  while(1)
+  {
+  }
+}
+
+/**
+  * @brief  this function handles debug monitor exception.
+  * @param  none
+  * @retval none
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/hw/bsp/at32f45x/at32f45x_int.h b/hw/bsp/at32f45x/at32f45x_int.h
new file mode 100644
index 000000000..3a2667e9d
--- /dev/null
+++ b/hw/bsp/at32f45x/at32f45x_int.h
@@ -0,0 +1,59 @@
+/**
+  **************************************************************************
+  * @file     at32f45x_int.h
+  * @brief    header file of main interrupt service routines.
+  **************************************************************************
+  *
+  * Copyright (c) 2025, Artery Technology, All rights reserved.
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_INT_H
+#define __AT32F45x_INT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/* exported types ------------------------------------------------------------*/
+/* exported constants --------------------------------------------------------*/
+/* exported macro ------------------------------------------------------------*/
+/* exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+void OTGFS1_IRQHandler(void);
+void OTGFS1_WKUP_IRQHandler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/at32f45x/boards/at_start_f455/board.cmake b/hw/bsp/at32f45x/boards/at_start_f455/board.cmake
new file mode 100644
index 000000000..f06f9599e
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f455/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F455ZET7)
+set(MCU_LINKER_NAME AT32F455xE)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f45x/boards/at_start_f455/board.h b/hw/bsp/at32f45x/boards/at_start_f455/board.h
new file mode 100644
index 000000000..64e27c016
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f455/board.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F455
+   url: https://www.arterychip.com/en/product/AT32F455.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_DP                       GPIO_PINS_12
+#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+#define OTG_PIN_DM                       GPIO_PINS_11
+#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+#define OTG_PIN_MUX                      GPIO_MUX_10
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f45x/boards/at_start_f455/board.mk b/hw/bsp/at32f45x/boards/at_start_f455/board.mk
new file mode 100644
index 000000000..7c24ad288
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f455/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F455ZET7
+MCU_LINKER_NAME = AT32F455xE
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f45x/boards/at_start_f456/board.cmake b/hw/bsp/at32f45x/boards/at_start_f456/board.cmake
new file mode 100644
index 000000000..a5048d3b1
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f456/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F456ZET7)
+set(MCU_LINKER_NAME AT32F456xE)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f45x/boards/at_start_f456/board.h b/hw/bsp/at32f45x/boards/at_start_f456/board.h
new file mode 100644
index 000000000..d3d734a9b
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f456/board.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F456
+   url: https://www.arterychip.com/en/product/AT32F456.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_DP                       GPIO_PINS_12
+#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+#define OTG_PIN_DM                       GPIO_PINS_11
+#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+#define OTG_PIN_MUX                      GPIO_MUX_10
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f45x/boards/at_start_f456/board.mk b/hw/bsp/at32f45x/boards/at_start_f456/board.mk
new file mode 100644
index 000000000..596d99d61
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f456/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F456ZET7
+MCU_LINKER_NAME = AT32F456xE
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f45x/boards/at_start_f457/board.cmake b/hw/bsp/at32f45x/boards/at_start_f457/board.cmake
new file mode 100644
index 000000000..c8cd886be
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f457/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F457ZET7)
+set(MCU_LINKER_NAME AT32F457xE)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f45x/boards/at_start_f457/board.h b/hw/bsp/at32f45x/boards/at_start_f457/board.h
new file mode 100644
index 000000000..2216b1ed3
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f457/board.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F457
+   url: https://www.arterychip.com/en/product/AT32F457.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_DP                       GPIO_PINS_12
+#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+#define OTG_PIN_DM                       GPIO_PINS_11
+#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+#define OTG_PIN_MUX                      GPIO_MUX_10
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f45x/boards/at_start_f457/board.mk b/hw/bsp/at32f45x/boards/at_start_f457/board.mk
new file mode 100644
index 000000000..4cb4adad5
--- /dev/null
+++ b/hw/bsp/at32f45x/boards/at_start_f457/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F457ZET7
+MCU_LINKER_NAME = AT32F457xE
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f45x/family.c b/hw/bsp/at32f45x/family.c
new file mode 100644
index 000000000..fa0c1139f
--- /dev/null
+++ b/hw/bsp/at32f45x/family.c
@@ -0,0 +1,258 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: Artery
+*/
+
+#include "at32f45x_clock.h"
+#include "at32f45x_int.h"
+#include "board.h"
+#include "bsp/board_api.h"
+
+void usb_clock48m_select(usb_clk48_s clk_s);
+void led_and_button_init(void);
+void uart_print_init(uint32_t baudrate);
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTGFS1_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+void OTGFS1_WKUP_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+void board_init(void) {
+  /* config nvic priority group */
+  nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
+
+  /* config system clock */
+  system_clock_config();
+
+  /* enable usb clock */
+  crm_periph_clock_enable(OTG_CLOCK, TRUE);
+
+  /* select usb 48m clcok source */
+  usb_clock48m_select(USB_CLK_HEXT);
+
+  /* vbus ignore */
+  board_vbus_sense_init();
+
+  /* configure systick */
+  systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV);
+  SysTick_Config(system_core_clock / 1000);
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+/* otgfs use vbus pin */
+#ifndef USB_VBUS_IGNORE
+  gpio_init_type gpio_init_struct;
+  crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE);
+  gpio_default_para_init(&gpio_init_struct);
+  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+  gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
+  gpio_init_struct.gpio_pins = OTG_PIN_VBUS;
+  gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
+  gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX);
+  gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
+#endif
+
+  /* config led and key */
+  led_and_button_init();
+
+  /* config usart printf */
+  uart_print_init(115200);
+  printf("usart printf config success!\r\n");
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+/**
+  * @brief  usb 48M clock select
+  * @param  clk_s:USB_CLK_HICK, USB_CLK_HEXT
+  * @retval none
+  */
+void usb_clock48m_select(usb_clk48_s clk_s)
+{
+  if(clk_s == USB_CLK_HICK)
+  {
+    crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK);
+
+    /* enable the acc calibration ready interrupt */
+    crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE);
+
+    /* update the c1\c2\c3 value */
+    acc_write_c1(7980);
+    acc_write_c2(8000);
+    acc_write_c3(8020);
+
+    /* open acc calibration */
+    acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE);
+  }
+  else
+  {
+    crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLLU);
+  }
+}
+
+void uart_print_init(uint32_t baudrate) {
+  gpio_init_type gpio_init_struct;
+  /* enable the uart and gpio clock */
+  crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE);
+  crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE);
+  gpio_default_para_init(&gpio_init_struct);
+  /* configure the uart tx pin */
+  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+  gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
+  gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN;
+  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
+  gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct);
+  gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM);
+  /* configure uart param */
+  usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT);
+  usart_transmitter_enable(PRINT_UART, TRUE);
+  usart_enable(PRINT_UART, TRUE);
+}
+
+void led_and_button_init(void) {
+  /* LED */
+  gpio_init_type gpio_led_init_struct;
+  /* enable the led clock */
+  LED_GPIO_CLK_EN();
+  /* set default parameter */
+  gpio_default_para_init(&gpio_led_init_struct);
+  /* configure the led gpio */
+  gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+  gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
+  gpio_led_init_struct.gpio_pins = LED_PIN;
+  gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE;
+  gpio_init(LED_PORT, &gpio_led_init_struct);
+  /* Button */
+  gpio_init_type gpio_button_init_struct;
+  /* enable the button clock */
+  BUTTON_GPIO_CLK_EN();
+  /* set default parameter */
+  gpio_default_para_init(&gpio_button_init_struct);
+  /* configure the button gpio */
+  gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+  gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT;
+  gpio_button_init_struct.gpio_pins = BUTTON_PIN;
+  gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN;
+  gpio_init(BUTTON_PORT, &gpio_button_init_struct);
+}
+
+void board_led_write(bool state) {
+  gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN);
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8);
+  uint32_t *id32 = (uint32_t *) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = at32_uuid[0];
+  id32[1] = at32_uuid[1];
+  id32[2] = at32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+  int txsize = len;
+  uint16_t timeout = 0xffff;
+  while (txsize--) {
+    while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) {
+      timeout--;
+      if (timeout == 0) {
+        return 0;
+      }
+    }
+    PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF);
+    buf++;
+  }
+  return len;
+#else
+  (void) buf;
+  (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t tusb_time_millis_api(void) {
+  return system_ticks;
+}
+
+void SVC_Handler(void) {
+}
+
+void PendSV_Handler(void) {
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void);
+void _init(void) {
+}
+
+#ifdef USE_FULL_ASSERT
+void assert_failed(const char *file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     e.g.: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/at32f45x/family.cmake b/hw/bsp/at32f45x/family.cmake
new file mode 100644
index 000000000..fe13347af
--- /dev/null
+++ b/hw/bsp/at32f45x/family.cmake
@@ -0,0 +1,97 @@
+include_guard()
+
+set(AT32_FAMILY at32f45x)
+set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries)
+
+string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "")
+
+#------------------------------------
+# Startup & Linker script
+#------------------------------------
+set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s)
+set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s)
+if (NOT DEFINED LD_FILE_GNU)
+set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld)
+endif ()
+set(LD_FILE_Clang ${LD_FILE_GNU})
+set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+function(family_add_board BOARD_TARGET)
+  add_library(${BOARD_TARGET} STATIC
+    ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c
+    ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c
+    ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c
+    ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c
+    ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c
+    ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${AT32_SDK_LIB}/cmsis/cm4/core_support
+    ${AT32_SDK_LIB}/cmsis/cm4/device_support
+    ${AT32_SDK_LIB}/drivers/inc
+    )
+
+  update_board(${BOARD_TARGET})
+endfunction()
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+  family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER})
+
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
+    ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+
+  set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
+    SKIP_LINTING ON
+    COMPILE_OPTIONS -w)
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/at32f45x/family.mk b/hw/bsp/at32f45x/family.mk
new file mode 100644
index 000000000..e42f27557
--- /dev/null
+++ b/hw/bsp/at32f45x/family.mk
@@ -0,0 +1,40 @@
+AT32_FAMILY = at32f45x
+AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+
+CFLAGS_GCC += \
+  -flto
+
+CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_AT32F45X \
+
+LDFLAGS_GCC += \
+	-flto --specs=nosys.specs -nostdlib -nostartfiles
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	$(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \
+	$(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \
+	$(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \
+	$(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \
+	$(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \
+	$(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(AT32_SDK_LIB)/drivers/inc \
+	$(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \
+	$(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support
+
+SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s
+SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s
+
+LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld
+LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf
+
+flash: flash-atlink
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 483d9dc28..71c209950 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -161,10 +161,6 @@ void board_putchar(int c) {
   (void) sys_write(0, (const char*)&c, 1);
 }
 
-uint32_t tusb_time_millis_api(void) {
-  return board_millis();
-}
-
 //--------------------------------------------------------------------
 // FreeRTOS hooks
 //--------------------------------------------------------------------
@@ -255,3 +251,53 @@ void vApplicationSetupTimerInterrupt(void) {
 #endif
 
 #endif
+
+//--------------------------------------------------------------------
+// ThreadX hooks for ARM Cortex-M
+//--------------------------------------------------------------------
+#if CFG_TUSB_OS == OPT_OS_THREADX && defined(__ARM_ARCH)
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+
+// Newlib linker symbol: end of statically allocated RAM (start of heap)
+extern ULONG _end;
+
+// CMSIS standard variable for system clock frequency
+extern uint32_t SystemCoreClock;
+
+// Cortex-M SysTick registers (fixed addresses on all Cortex-M)
+#define _TX_SYST_CSR    (*((volatile uint32_t *)0xE000E010U))
+#define _TX_SYST_RVR    (*((volatile uint32_t *)0xE000E014U))
+#define _TX_SYST_CVR    (*((volatile uint32_t *)0xE000E018U))
+// SCB->SHP[10] = PendSV priority, [11] = SysTick priority (byte access at SCB base + 0xD22)
+#define _TX_SCB_SHPR3   (*((volatile uint32_t *)0xE000ED20U))
+
+VOID _tx_initialize_low_level(VOID) {
+  // Set the first available memory address for tx_application_define
+  _tx_initialize_unused_memory = (VOID *)(&_end);
+
+  // Configure SysTick for ThreadX tick rate: enable with processor clock + interrupt
+  _TX_SYST_RVR = (SystemCoreClock / TX_TIMER_TICKS_PER_SECOND) - 1u;
+  _TX_SYST_CVR = 0u;
+  _TX_SYST_CSR = 0x07u; // CLKSOURCE=1, TICKINT=1, ENABLE=1
+
+  // SHPR3 bits[31:24] = SysTick priority, bits[23:16] = PendSV priority
+  // PendSV must be lowest priority (0xFF). SysTick must be higher than PendSV (0x40)
+  // so SysTick can preempt the PendSV scheduler idle loop (__tx_ts_wait) to tick the timer.
+  _TX_SCB_SHPR3 = (_TX_SCB_SHPR3 & 0x0000FFFFU) | 0x40FF0000U;
+}
+
+// Weak callback for board-specific SysTick work (e.g. HAL_IncTick on STM32)
+void osal_threadx_tick_cb(void);
+TU_ATTR_WEAK void osal_threadx_tick_cb(void) { }
+
+// SysTick drives the ThreadX timer tick
+extern void _tx_timer_interrupt(void);
+void SysTick_Handler(void);
+void SysTick_Handler(void) {
+  osal_threadx_tick_cb();
+  _tx_timer_interrupt();
+}
+
+#endif
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 606ac484f..4487871eb 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -98,43 +98,6 @@ int board_uart_read(uint8_t *buf, int len);
 // Send characters to UART. Return number of sent bytes
 int board_uart_write(void const *buf, int len);
 
-#if CFG_TUSB_OS == OPT_OS_NONE
-// Get current milliseconds, must be implemented when no RTOS is used
-uint32_t board_millis(void);
-
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-static inline uint32_t board_millis(void) {
-  return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
-}
-
-#elif CFG_TUSB_OS == OPT_OS_MYNEWT
-static inline uint32_t board_millis(void) {
-  return os_time_ticks_to_ms32( os_time_get() );
-}
-
-#elif CFG_TUSB_OS == OPT_OS_PICO
-#include "pico/time.h"
-static inline uint32_t board_millis(void) {
-  return to_ms_since_boot(get_absolute_time());
-}
-
-#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
-static inline uint32_t board_millis(void) {
-  return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
-}
-
-#elif CFG_TUSB_OS == OPT_OS_CUSTOM
-// Implement your own board_millis() in any of .c file
-uint32_t board_millis(void);
-
-#elif CFG_TUSB_OS == OPT_OS_ZEPHYR
-static inline uint32_t board_millis(void) {
-  return k_uptime_get_32();
-}
-#else
-  #error "board_millis() is not implemented for this OS"
-#endif
-
 //--------------------------------------------------------------------+
 // Helper functions
 //--------------------------------------------------------------------+
@@ -175,8 +138,8 @@ static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars
 
 // TODO remove
 static inline void board_delay(uint32_t ms) {
-  uint32_t start_ms = board_millis();
-  while ( board_millis() - start_ms < ms ) {
+  uint32_t start_ms = tusb_time_millis_api();
+  while ( tusb_time_millis_api() - start_ms < ms ) {
     // take chance to run usb background
     #if CFG_TUD_ENABLED
     tud_task();
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index f8f3b0b70..399397bb4 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) {
   SYSTMR->CS_b.M1 = 1;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index f8f3b0b70..399397bb4 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) {
   SYSTMR->CS_b.M1 = 1;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 15ff4b8ee..ff24cfe89 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -234,7 +234,7 @@ int board_uart_write(void const *buf, int len)
 }
 
 // Get current milliseconds
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
     uint32_t safe_ms;
 
diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c
index 7eae62fa4..dd84b7c77 100644
--- a/hw/bsp/ch32f20x/family.c
+++ b/hw/bsp/ch32f20x/family.c
@@ -101,7 +101,7 @@ void SysTick_Handler(void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c
index dfc041462..344dcaf0b 100644
--- a/hw/bsp/ch32v10x/family.c
+++ b/hw/bsp/ch32v10x/family.c
@@ -61,7 +61,7 @@ static uint32_t SysTick_Config(uint32_t ticks) {
   return 0;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c
index 690acee1e..4c22450f9 100644
--- a/hw/bsp/ch32v20x/family.c
+++ b/hw/bsp/ch32v20x/family.c
@@ -85,7 +85,7 @@ static uint32_t SysTick_Config(uint32_t ticks) {
   return 0;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/ch32v30x/family.c b/hw/bsp/ch32v30x/family.c
index c694f1a08..6295f7723 100644
--- a/hw/bsp/ch32v30x/family.c
+++ b/hw/bsp/ch32v30x/family.c
@@ -144,7 +144,7 @@ __attribute__((interrupt)) void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/cxd56/family.c b/hw/bsp/cxd56/family.c
index a8e2fd52b..fd92bb9d9 100644
--- a/hw/bsp/cxd56/family.c
+++ b/hw/bsp/cxd56/family.c
@@ -96,7 +96,7 @@ int board_uart_write(void const *buf, int len)
 }
 
 // Get current milliseconds
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   struct timespec tp;
 
diff --git a/hw/bsp/da1469x/family.c b/hw/bsp/da1469x/family.c
index a64ffce67..a4f7f2e8d 100644
--- a/hw/bsp/da1469x/family.c
+++ b/hw/bsp/da1469x/family.c
@@ -140,7 +140,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/efm32/family.c b/hw/bsp/efm32/family.c
index 39166bc4d..d318e20d6 100644
--- a/hw/bsp/efm32/family.c
+++ b/hw/bsp/efm32/family.c
@@ -689,7 +689,7 @@ void SysTick_Handler(void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
index fe4db4fc1..455ca90a1 100644
--- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
@@ -1,2 +1,3 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32p4")
+list(APPEND SDKCONFIG_DEFAULTS "${CMAKE_CURRENT_LIST_DIR}/sdkconfig.defaults")
diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults
new file mode 100644
index 000000000..6b0a548f6
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults
@@ -0,0 +1,2 @@
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+CONFIG_ESP32P4_REV_MIN_1=y
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index a837417f4..04d8a4001 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -50,7 +50,7 @@ static void max3421_init(void);
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32H4, OPT_MCU_ESP32P4)
-static bool usb_init(void);
+static bool usb_init(uint8_t rhport, bool is_host);
 #endif
 
 //--------------------------------------------------------------------+
@@ -90,8 +90,14 @@ void board_init(void) {
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
-  usb_init();
+#if CONFIG_USB_OTG_SUPPORTED
+  #if CFG_TUD_ENABLED
+  usb_init(BOARD_TUD_RHPORT, false);
+  #endif
+
+  #if CFG_TUH_ENABLED
+  usb_init(BOARD_TUH_RHPORT, true);
+  #endif
 #endif
 
 #ifdef HIL_TS3USB30_MODE_PIN
@@ -179,24 +185,30 @@ void board_reset_to_bootloader(void) {
 
 static usb_phy_handle_t phy_hdl;
 
-bool usb_init(void) {
+bool usb_init(uint8_t rhport, bool is_host) {
+  (void) rhport;
   // Configure USB PHY
   usb_phy_config_t phy_conf = {
     .controller = USB_PHY_CTRL_OTG,
+#if defined(CONFIG_SOC_USB_UTMI_PHY_NUM) && CONFIG_SOC_USB_UTMI_PHY_NUM > 0
+    .target = USB_PHY_TARGET_UTMI,
+#else
     .target = USB_PHY_TARGET_INT,
+#endif
 
     // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver
-#if CFG_TUD_ENABLED
-    .otg_mode = USB_OTG_MODE_DEVICE,
-#elif CFG_TUH_ENABLED
-    .otg_mode = USB_OTG_MODE_HOST,
-#endif
+    .otg_mode = is_host ? USB_OTG_MODE_HOST : USB_OTG_MODE_DEVICE,
     // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322
     // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS
     .otg_speed = USB_PHY_SPEED_UNDEFINED,
   };
 
-  usb_new_phy(&phy_conf, &phy_hdl);
+  esp_err_t const err = usb_new_phy(&phy_conf, &phy_hdl);
+  if (err != ESP_OK) {
+    printf("usb_new_phy failed: %s\r\n", esp_err_to_name(err));
+    phy_hdl = NULL;
+    return false;
+  }
 
   return true;
 }
@@ -351,5 +363,4 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx
   ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact));
   return true;
 }
-
 #endif
diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c
index 9e864363f..1e71333d4 100644
--- a/hw/bsp/f1c100s/family.c
+++ b/hw/bsp/f1c100s/family.c
@@ -79,7 +79,7 @@ int board_uart_write(void const* buf, int len) {
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index baa8422fe..c166a0618 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -105,6 +105,12 @@ set(WARN_FLAGS_GNU
   )
 set(WARN_FLAGS_Clang ${WARN_FLAGS_GNU})
 
+set(WARN_FLAGS_IAR
+  --warnings_are_errors
+  --diag_suppress=Pa089
+  --diag_suppress=Pe236
+  )
+
 # Optimization
 if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "")
   set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE)
@@ -238,6 +244,7 @@ function(family_add_bloaty TARGET)
     COMMAND ${BLOATY_EXE} ${OPTION_LIST} $<TARGET_FILE:${TARGET}>
     VERBATIM)
 
+  set_property(TARGET ${TARGET}-bloaty PROPERTY FOLDER ${TARGET})
   # post build
   #  add_custom_command(TARGET ${TARGET} POST_BUILD
   #    COMMAND ${BLOATY_EXE} --csv ${OPTION_LIST} $<TARGET_FILE:${TARGET}> > ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}_bloaty.csv
@@ -258,12 +265,103 @@ function(family_add_linkermap TARGET)
     VERBATIM
     )
 
+  set_property(TARGET ${TARGET}-linkermap PROPERTY FOLDER ${TARGET})
+
   # post build
   add_custom_command(TARGET ${TARGET} POST_BUILD
     COMMAND python ${LINKERMAP_PY} ${OPTION_LIST} $<TARGET_FILE:${TARGET}>.map
     VERBATIM)
 endfunction()
 
+# Add membrowse target (installed with pip install membrowse)
+function(family_add_membrowse TARGET)
+  find_program(MEMBROWSE_EXE membrowse)
+  if (MEMBROWSE_EXE STREQUAL MEMBROWSE_EXE-NOTFOUND)
+    # force anyway, bash login shell will find it from pip install path
+    set(MEMBROWSE_EXE membrowse)
+  endif ()
+
+  set(OPTION "")
+  if (DEFINED MEMBROWSE_OPTION)
+    string(APPEND OPTION " ${MEMBROWSE_OPTION}")
+  endif ()
+
+  # For Ninja generator, extract all linker scripts from Ninja commands (with INCLUDE) and pass them to membrowse.
+  if (CMAKE_GENERATOR MATCHES "Ninja")
+    set(TARGET_ELF_PATH "$<TARGET_FILE_DIR:${TARGET}>/$<TARGET_FILE_NAME:${TARGET}>")
+    set(MEMBROWSE_LD_SCRIPTS_CMD
+      "ld_scripts=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?:-Wl,--script=|-T\\s*)\\K[A-Za-z0-9_./-]+\\.ld' | xargs)\"; \
+all_ld_scripts=\"\"; \
+pending_ld_scripts=\"$ld_scripts\"; \
+while [ -n \"$pending_ld_scripts\" ]; do \
+  next_pending=\"\"; \
+  for script in $pending_ld_scripts; do \
+    case \" $all_ld_scripts \" in *\" $script \"*) continue ;; esac; \
+    all_ld_scripts=\"$all_ld_scripts $script\"; \
+    script_dir=$(dirname \"$script\"); \
+    include_scripts=$(grep -hoP '^\\s*INCLUDE\\s+[<\"]?\\K[^\">[:space:]]+\\.ld' \"$script\" 2>/dev/null | xargs); \
+    for include_script in $include_scripts; do \
+      resolved_script=\"\"; \
+      if [ -f \"$include_script\" ]; then \
+        resolved_script=\"$include_script\"; \
+      elif [ -f \"$script_dir/$include_script\" ]; then \
+        resolved_script=\"$script_dir/$include_script\"; \
+      fi; \
+      if [ -n \"$resolved_script\" ]; then \
+        case \" $all_ld_scripts $next_pending \" in *\" $resolved_script \"*) ;; *) next_pending=\"$next_pending $resolved_script\" ;; esac; \
+      fi; \
+    done; \
+  done; \
+  pending_ld_scripts=\"$(echo \"$next_pending\" | xargs)\"; \
+done; \
+ld_scripts=\"$(echo \"$all_ld_scripts\" | xargs)\"")
+    set(MEMBROWSE_LD_DEFS_CMD
+      "ld_symbols=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?<=--defsym[=,])[^[:space:]]+' | xargs)\"; \
+ld_defs=\"\"; \
+for symbol in $ld_symbols; do \
+  ld_defs=\"$ld_defs --def $symbol\"; \
+done; \
+ld_defs=\"$(echo \"$ld_defs\" | xargs)\"")
+    set(MEMBROWSE_PREPARE_CMD
+      "if [ -f \"${TARGET_ELF_PATH}\" ]; then \
+  ${MEMBROWSE_LD_SCRIPTS_CMD}; \
+  ${MEMBROWSE_LD_DEFS_CMD}; \
+  if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
+  else \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs\"; \
+  fi; \
+else \
+  if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
+  else \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical\"; \
+  fi; \
+fi; \
+echo \"$MEMBROWSE_CMD\"")
+
+    add_custom_target(${TARGET}-membrowse
+      DEPENDS ${TARGET}
+      COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=0 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
+      VERBATIM
+      )
+    set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET})
+
+    add_custom_target(${TARGET}-membrowse-upload
+      COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=1 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
+      VERBATIM
+      )
+
+    if (NOT TARGET examples-membrowse-upload)
+      add_custom_target(examples-membrowse-upload)
+    endif ()
+    add_dependencies(examples-membrowse-upload ${TARGET}-membrowse-upload)
+
+    set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET})
+  endif ()
+endfunction()
+
+
 #-------------------------------------------------------------
 # Common Target Configure
 # Most families use these settings except rp2040 and espressif
@@ -288,6 +386,26 @@ function(family_add_rtos TARGET RTOS)
 
     target_link_libraries(${TARGET} PUBLIC freertos_kernel)
     target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS)
+  elseif (RTOS STREQUAL "threadx")
+    if (NOT TARGET threadx)
+      # Derive THREADX_ARCH from CMAKE_SYSTEM_CPU if not explicitly set
+      if (NOT DEFINED THREADX_ARCH)
+        string(REPLACE "-" "_" THREADX_ARCH ${CMAKE_SYSTEM_CPU})
+      endif ()
+      # Derive THREADX_TOOLCHAIN from TOOLCHAIN if not explicitly set
+      if (NOT DEFINED THREADX_TOOLCHAIN)
+        if (TOOLCHAIN STREQUAL "iar")
+          set(THREADX_TOOLCHAIN "iar")
+        elseif (TOOLCHAIN STREQUAL "clang")
+          set(THREADX_TOOLCHAIN "ac6")
+        else ()
+          set(THREADX_TOOLCHAIN "gnu")
+        endif ()
+      endif ()
+      add_subdirectory(${TOP}/lib/threadx ${CMAKE_BINARY_DIR}/lib/threadx)
+    endif ()
+    target_link_libraries(${TARGET} PUBLIC threadx)
+    target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_THREADX)
   elseif (RTOS STREQUAL "zephyr")
     target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR)
     target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include)
@@ -355,6 +473,7 @@ function(family_configure_common TARGET RTOS)
       target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
     endif ()
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_compile_options(${TARGET} PRIVATE $<$<OR:$<COMPILE_LANGUAGE:C>,$<COMPILE_LANGUAGE:CXX>>:${WARN_FLAGS_IAR}>)
     target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map")
 
     if (IAR_CSTAT)
@@ -377,6 +496,7 @@ function(family_configure_common TARGET RTOS)
     # Analyze size with bloaty and linkermap
     family_add_bloaty(${TARGET})
     family_add_linkermap(${TARGET})
+    family_add_membrowse(${TARGET})
   endif ()
 
   # run size after build
@@ -508,6 +628,8 @@ exit"
     COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${BINARY_TARGET}>/${BINARY_TARGET}.jlink
     VERBATIM
     )
+
+  set_property(TARGET ${NAME_TARGET}-jlink PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -521,6 +643,8 @@ function(family_flash_stlink TARGET)
     DEPENDS ${TARGET}
     COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $<TARGET_FILE:${TARGET}> --go
     )
+
+  set_property(TARGET ${TARGET}-stlink PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -534,6 +658,8 @@ function(family_flash_stflash TARGET)
     DEPENDS ${TARGET}
     COMMAND ${ST_FLASH} write $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin 0x8000000
     )
+
+  set_property(TARGET ${TARGET}-stflash PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -560,6 +686,8 @@ function(family_flash_openocd TARGET)
     COMMAND ${OPENOCD} -c "tcl_port disabled; gdb_port disabled" ${OPTION_LIST} -c "init; halt; program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
     VERBATIM
     )
+
+  set_property(TARGET ${TARGET}-openocd PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -621,6 +749,8 @@ function(family_flash_wlink_rs TARGET)
     DEPENDS ${TARGET}
     COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}>
     )
+
+  set_property(TARGET ${TARGET}-wlink-rs PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -634,6 +764,8 @@ function(family_flash_pyocd TARGET)
     DEPENDS ${TARGET}
     COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
     )
+
+  set_property(TARGET ${TARGET}-pyocd PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -643,6 +775,7 @@ function(family_flash_uf2 TARGET FAMILY_ID)
     DEPENDS ${TARGET}
     COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} --deploy $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.uf2
     )
+  set_property(TARGET ${TARGET}-uf2 PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -657,6 +790,8 @@ function(family_flash_teensy TARGET)
     COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
     COMMAND ${TEENSY_CLI} --mcu=${TEENSY_MCU} -w -s $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
     )
+
+  set_property(TARGET ${TARGET}-teensy PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -675,6 +810,8 @@ function(family_flash_nxplink TARGET)
     DEPENDS ${TARGET}
     COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
     )
+
+  set_property(TARGET ${TARGET}-nxplink PROPERTY FOLDER ${TARGET})
 endfunction()
 
 
@@ -688,6 +825,8 @@ function(family_flash_dfu_util TARGET OPTION)
     COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
     VERBATIM
     )
+
+  set_property(TARGET ${TARGET}-dfu-util PROPERTY FOLDER ${TARGET})
 endfunction()
 
 function(family_flash_msp430flasher TARGET)
@@ -703,6 +842,8 @@ function(family_flash_msp430flasher TARGET)
     COMMAND ${CMAKE_COMMAND} -E env LD_LIBRARY_PATH=${MSP430FLASHER_PARENT_DIR}
             ${MSP430FLASHER} -w $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex -z [VCC]
     )
+
+  set_property(TARGET ${TARGET}-msp430flasher PROPERTY FOLDER ${TARGET})
 endfunction()
 
 function(family_flash_uniflash TARGET)
@@ -717,6 +858,8 @@ function(family_flash_uniflash TARGET)
     COMMAND ${DSLITE} ${UNIFLASH_OPTION} -f $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
     VERBATIM
     )
+
+  set_property(TARGET ${TARGET}-uniflash PROPERTY FOLDER ${TARGET})
 endfunction()
 
 #----------------------------------
diff --git a/hw/bsp/fomu/family.c b/hw/bsp/fomu/family.c
index 9d7977bea..cf04a1f6f 100644
--- a/hw/bsp/fomu/family.c
+++ b/hw/bsp/fomu/family.c
@@ -117,7 +117,7 @@ int board_uart_write(void const * buf, int len)
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 9d15755fc..4c1099317 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -179,7 +179,7 @@ void eclic_mtip_handler(void) {
   system_ticks++;
   SysTick_Reload(TIMER_TICKS);
 }
-uint32_t board_millis(void) { return system_ticks; }
+uint32_t tusb_time_millis_api(void) { return system_ticks; }
 #endif
 
 #ifdef USE_FULL_ASSERT
diff --git a/hw/bsp/hpmicro/family.c b/hw/bsp/hpmicro/family.c
index ffec2523a..a80a8d913 100644
--- a/hw/bsp/hpmicro/family.c
+++ b/hw/bsp/hpmicro/family.c
@@ -108,7 +108,7 @@ int board_uart_write(void const *buf, int len) {
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // Get current milliseconds, must be implemented when no RTOS is used
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return (hpm_csr_get_core_cycle() / clock_get_core_clock_ticks_per_ms());
 }
 
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index d54b41bdb..c1ee34b1a 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -239,7 +239,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c
index 98ef52739..1505defe0 100644
--- a/hw/bsp/kinetis_k/family.c
+++ b/hw/bsp/kinetis_k/family.c
@@ -143,7 +143,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/kinetis_k32l2/family.c b/hw/bsp/kinetis_k32l2/family.c
index 2062b8b18..ec8dc6ecf 100644
--- a/hw/bsp/kinetis_k32l2/family.c
+++ b/hw/bsp/kinetis_k32l2/family.c
@@ -148,7 +148,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c
index c257f4b2b..f89434d06 100644
--- a/hw/bsp/kinetis_kl/family.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -142,7 +142,7 @@ void SysTick_Handler(void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c
index c9f18bd2f..76c2bd17c 100644
--- a/hw/bsp/lpc11/family.c
+++ b/hw/bsp/lpc11/family.c
@@ -130,7 +130,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc13/family.c b/hw/bsp/lpc13/family.c
index e212c6a63..8513f4df4 100644
--- a/hw/bsp/lpc13/family.c
+++ b/hw/bsp/lpc13/family.c
@@ -83,7 +83,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index 5f22df175..0d092d3a9 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -140,7 +140,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/lpc17/family.c b/hw/bsp/lpc17/family.c
index ba59fccca..f398f7e3c 100644
--- a/hw/bsp/lpc17/family.c
+++ b/hw/bsp/lpc17/family.c
@@ -145,7 +145,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 6c02c711f..2043cef99 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -143,7 +143,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c
index 5ea95e9b8..237cd996b 100644
--- a/hw/bsp/lpc40/family.c
+++ b/hw/bsp/lpc40/family.c
@@ -156,7 +156,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index f440fb119..56834a1b0 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -185,8 +185,10 @@ void board_init(void)
    */
   Chip_USB1_Init();
 
+#ifdef _BOARD_EA4357_H
   // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
   Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
+#endif
 
   #if defined(BOARD_TUD_RHPORT) &&  BOARD_TUD_RHPORT == 0
     // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
@@ -257,7 +259,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
index 1f549bf50..6e632d266 100644
--- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
@@ -7,7 +7,4 @@ function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC51U68JBD64
     )
-  target_link_libraries(${TARGET} PUBLIC
-    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower.a
-    )
 endfunction()
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
index 5627cb024..072037e90 100644
--- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
@@ -1,4 +1,4 @@
-MCU = LPC51U68
+MCU_VARIANT = LPC51U68
 
 CFLAGS += \
   -DCPU_LPC51U68JBD64 \
diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c
index bec86f87f..847972350 100644
--- a/hw/bsp/lpc51/family.c
+++ b/hw/bsp/lpc51/family.c
@@ -122,7 +122,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake
index 1823b64fc..00c6731ae 100644
--- a/hw/bsp/lpc51/family.cmake
+++ b/hw/bsp/lpc51/family.cmake
@@ -1,7 +1,8 @@
 include_guard()
 
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
@@ -16,41 +17,52 @@ set(FAMILY_MCUS LPC51 CACHE INTERNAL "")
 # Startup & Linker script
 #------------------------------------
 if (NOT DEFINED LD_FILE_GNU)
-set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld)
+  set(LD_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld)
 endif ()
 set(LD_FILE_Clang ${LD_FILE_GNU})
+
 if (NOT DEFINED STARTUP_FILE_GNU)
-set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  set(STARTUP_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
 endif ()
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+if (NOT DEFINED LD_FILE_IAR)
+  set(LD_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/${MCU_VARIANT}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+  set(STARTUP_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/startup_${MCU_VARIANT}.s)
+endif ()
+
 #------------------------------------
 # Board Target
 #------------------------------------
 function(family_add_board BOARD_TARGET)
   add_library(${BOARD_TARGET} STATIC
     # driver
-    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
+    ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_reset.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${TOP}/lib/sct_neopixel
     # driver
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/flexcomm
-    ${SDK_DIR}/drivers/lpc_iocon
-    ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/lpuart
+    ${MCUX_DIR}/drivers/common
+    ${MCUX_DIR}/drivers/common
+    ${MCUX_DIR}/drivers/flexcomm
+    ${MCUX_DIR}/drivers/flexcomm/usart
+    ${MCUX_DIR}/drivers/lpc_iocon
+    ${MCUX_DIR}/drivers/lpc_gpio
     # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}
+    ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers
     ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/LPC51U68/periph
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index 91d1261cb..34987d183 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -1,8 +1,7 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-
 include $(TOP)/$(BOARD_PATH)/board.mk
-MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 CPU_CORE ?= cortex-m0plus
+MCUX_DIR = /hw/mcu/nxp/mcuxsdk-core
+SDK_DIR = /hw/mcu/nxp/mcux-devices-lpc
 
 CFLAGS += \
   -flto \
@@ -18,29 +17,28 @@ LDFLAGS_GCC += \
   --specs=nosys.specs --specs=nano.specs \
 
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld
+LD_FILE = $(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/$(MCU_VARIANT)_flash.ld
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_$(MCU).c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_power.c \
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \
 
 INC += \
-    $(TOP)/$(BOARD_PATH) \
-    $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
-
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers \
+	$(TOP)/$(SDK_DIR)/LPC51U68/periph \
+	$(TOP)/$(MCUX_DIR)/drivers/common \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_gpio
 
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
+SRC_S += $(TOP)$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/startup_$(MCU_VARIANT).S
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
index c0bbeecd5..b306f885a 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
@@ -6,10 +6,8 @@ set(PYOCD_TARGET LPC54114)
 
 set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld)
 
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
-endif()
+# Only Port 0 Full-Speed
+set(RHPORT_DEVICE 0)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
index c43ca9d7d..1158d0675 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h
@@ -36,6 +36,18 @@
  extern "C" {
 #endif
 
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x80u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0100u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
 // LED
 #define LED_PORT              0
 #define LED_PIN               29
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
index f0715fa12..aea608e60 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
@@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54608:LPCXpresso54608)
 set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld)
 
 # Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
 endif()
 
 function(update_board TARGET)
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
index e985e97e0..7a5cbea87 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
@@ -36,6 +36,18 @@
  extern "C" {
 #endif
 
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x0100u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
 // LED
 #define LED_PORT              2
 #define LED_PIN               2
@@ -54,6 +66,15 @@
 // USB0 VBUS
 #define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
 
+// Power switch
+#define USBFS_POWER_PORT      4
+#define USBFS_POWER_PIN       7
+#define USBFS_POWER_STATE_ON  0
+
+#define USBHS_POWER_PORT      4
+#define USBHS_POWER_PIN       9
+#define USBHS_POWER_STATE_ON  0
+
 // XTAL
 //#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
 
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
index 1dea6f353..b0d0d404f 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
@@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54628:LPCXpresso54628)
 set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld)
 
 # Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-  set(PORT 1)
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
 endif()
 
 function(update_board TARGET)
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
index 837d26aef..5c858ed99 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h
@@ -36,6 +36,18 @@
  extern "C" {
 #endif
 
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x0100u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
 // LED
 #define LED_PORT              2
 #define LED_PIN               2
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 7bb73afbc..806bd53dc 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -41,18 +41,6 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN     0x80u   // Enables digital function
-#define IOCON_PIO_FUNC0          0x00u
-#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
-#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
-#define IOCON_PIO_INPFILT_OFF    0x0100u // Input filter disabled
-#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
-#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
-#define IOCON_PIO_MODE_PULLUP    0x10u
-#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
-#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
-
 // Digital pin function n enabled
 #define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0)
 #define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1)
@@ -149,37 +137,71 @@ void board_init(void) {
   USART_Init(UART_DEV, &uart_config, 12000000);
 #endif
 
-  // USB
-  IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
-
 #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
   // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
-  #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
+  #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
+    /* PORT0 PIN22 configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
+
     // Port0 is Full Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
     CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
     CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
 
-    /*According to reference manual, device mode setting has to be set by access usb host register */
-    CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
-    USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-    CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
+    if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) {
+      /*According to reference manual, device mode setting has to be set by access usb host register */
+      CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
+      USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+      CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
+
+      CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+    } else {
+    #ifdef USBFS_POWER_PORT
+      /* Configure USB0 Power Switch Pin */
+      IOCON_PinMuxSet(IOCON, USBFS_POWER_PORT, USBFS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
 
-    CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+      gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBFS_POWER_STATE_ON};
+      GPIO_PinInit(GPIO, USBFS_POWER_PORT, USBFS_POWER_PIN, &power_pin_config);
+    #endif
+      CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+      USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
+    }
   #endif
 
-  #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
-    // Port1 is High Speed
-    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
+ #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+  // Port1 is High Speed
+
+  /* Turn on USB1 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
 
-    /*According to reference manual, device mode setting has to be set by access usb host register */
-    CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
+  /* reset the IP to make sure it's in reset state. */
+  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
+
+  if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) {
+    /* According to reference manual, device mode setting has to be set by access usb host register */
+    CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+
+    USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
     USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
-    CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
 
+    CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+    /* enable USB Device clock */
     CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U);
+  } else {
+  #ifdef USBHS_POWER_PORT
+    /* Configure USB1 Power Switch Pin */
+    IOCON_PinMuxSet(IOCON, USBHS_POWER_PORT, USBHS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
+
+    gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBHS_POWER_STATE_ON};
+    GPIO_PinInit(GPIO, USBHS_POWER_PORT, USBHS_POWER_PIN, &power_pin_config);
+  #endif
+    CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 0U);
+  }
   #endif
 #else
+  IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
   // LPC5411x series only has full speed device
   POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy
   CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
@@ -217,7 +239,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index c6145bd41..ebc0689fd 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -12,13 +12,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
 
 set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
 
-if (NOT DEFINED PORT)
-  set(PORT 0)
-endif()
+# ----------------------
+# Port & Speed Selection
+# ----------------------
 
-# Host port will be the other port if available
-set(HOST_PORT $<NOT:${PORT}>)
+# default device port to USB1 highspeed, host to USB0 fullspeed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif ()
+
+# port 0 is fullspeed, port 1 is highspeed
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
 
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
 #------------------------------------
 # Startup & Linker script
 #------------------------------------
@@ -26,11 +42,20 @@ if (NOT DEFINED LD_FILE_GNU)
 set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
 endif ()
 set(LD_FILE_Clang ${LD_FILE_GNU})
+
 if (NOT DEFINED STARTUP_FILE_GNU)
 set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
 endif ()
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+if (NOT DEFINED LD_FILE_IAR)
+  set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/${MCU_CORE}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+  set(STARTUP_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/startup_${MCU_CORE}.s)
+endif ()
+
 #------------------------------------
 # Board Target
 #------------------------------------
@@ -64,24 +89,23 @@ function(family_add_board BOARD_TARGET)
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
-    BOARD_TUD_RHPORT=${PORT}
-    BOARD_TUH_RHPORT=${HOST_PORT}
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
     __STARTUP_CLEAR_BSS
     )
 
-  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
-  if (PORT EQUAL 1)
+ # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (RHPORT_DEVICE EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
-      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
       )
-  else ()
+  endif ()
+  if (RHPORT_HOST EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
-      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
-      #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
+      CFG_TUH_USBIP_IP3516=1
       )
   endif ()
 
@@ -107,11 +131,23 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
+  if (RHPORT_HOST EQUAL 0)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/ohci/ohci.c
+      )
+  elseif (RHPORT_HOST EQUAL 1)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
+      )
+  endif ()
+
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     target_link_options(${TARGET} PUBLIC
       "LINKER:--script=${LD_FILE_GNU}"
       --specs=nosys.specs --specs=nano.specs
       -nostartfiles
+      "LINKER:--defsym=__stack_size__=0x1000"
+      "LINKER:--defsym=__heap_size__=0"
       )
   elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
     target_link_options(${TARGET} PUBLIC
@@ -120,6 +156,8 @@ function(family_configure_example TARGET RTOS)
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
     target_link_options(${TARGET} PUBLIC
       "LINKER:--config=${LD_FILE_IAR}"
+      "LINKER:--config_def=__stack_size__=0x1000"
+      "LINKER:--config_def=__heap_size__=0"
       )
   endif ()
 
diff --git a/hw/bsp/lpc54/iar/LPC54608_flash.icf b/hw/bsp/lpc54/iar/LPC54608_flash.icf
new file mode 100644
index 000000000..408ab90ed
--- /dev/null
+++ b/hw/bsp/lpc54/iar/LPC54608_flash.icf
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC546xx User manual Rev.1.9  5 June 2017
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b241125
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
diff --git a/hw/bsp/lpc54/iar/LPC54628_flash.icf b/hw/bsp/lpc54/iar/LPC54628_flash.icf
new file mode 100644
index 000000000..cc6615bd6
--- /dev/null
+++ b/hw/bsp/lpc54/iar/LPC54628_flash.icf
@@ -0,0 +1,82 @@
+/*
+** ###################################################################
+**     Processor:           LPC54628J512ET180
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC546xx User manual Rev.1.9  5 June 2017
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b241125
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
diff --git a/hw/bsp/lpc54/iar/startup_LPC54608.s b/hw/bsp/lpc54/iar/startup_LPC54608.s
new file mode 100644
index 000000000..05c4350e5
--- /dev/null
+++ b/hw/bsp/lpc54/iar/startup_LPC54608.s
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+;  @file:    startup_LPC54608.s
+;  @purpose: CMSIS Cortex-M4 Core Device Startup File
+;            LPC54608
+;  @version: 2.0
+;  @date:    2024-10-29
+;  @build:   b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__iar_init$$done:              ; The vector table is not needed
+                      ; until after copy initialization is done
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     MemManage_Handler                             ;MPU Fault Handler
+        DCD     BusFault_Handler                              ;Bus Fault Handler
+        DCD     UsageFault_Handler                            ;Usage Fault Handler
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0xFFFFFFFF                                    ;ECRP
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     DebugMon_Handler                              ;Debug Monitor Handler
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     WDT_BOD_IRQHandler                            ;Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler                               ;DMA controller
+        DCD     GINT0_IRQHandler                              ;GPIO group 0
+        DCD     GINT1_IRQHandler                              ;GPIO group 1
+        DCD     PIN_INT0_IRQHandler                           ;Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler                           ;Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler                           ;Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler                           ;Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler                             ;Micro-tick Timer
+        DCD     MRT0_IRQHandler                               ;Multi-rate timer
+        DCD     CTIMER0_IRQHandler                            ;Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler                            ;Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler                               ;SCTimer/PWM
+        DCD     CTIMER3_IRQHandler                            ;Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler                          ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler                          ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler                          ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler                          ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler                          ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler                          ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler                          ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler                          ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler                          ;ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler                          ;ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler                         ;ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler                              ;Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler                             ;Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler                       ;USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler                               ;USB device
+        DCD     RTC_IRQHandler                                ;RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler                         ;Reserved interrupt
+        DCD     Reserved47_IRQHandler                         ;Reserved interrupt
+        DCD     PIN_INT4_IRQHandler                           ;Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler                           ;Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler                           ;Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler                           ;Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler                            ;Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler                            ;Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler                                ;Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler                             ;SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler                          ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler                          ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler                               ;SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler                          ;CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler                          ;CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler                          ;CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler                          ;CAN1 interrupt1
+        DCD     USB1_IRQHandler                               ;USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler                       ;USB1 activity
+        DCD     ETHERNET_IRQHandler                           ;Ethernet
+        DCD     ETHERNET_PMT_IRQHandler                       ;Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler                     ;Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler                             ;EEPROM interrupt
+        DCD     LCD_IRQHandler                                ;LCD interrupt
+        DCD     SHA_IRQHandler                                ;SHA interrupt
+        DCD     SMARTCARD0_IRQHandler                         ;Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler                         ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        MOVS    r0,#56
+        LDR     r1, =0x40000220
+        STR     r0, [r1]           ;Enable SRAM clock used by Stack
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END
diff --git a/hw/bsp/lpc54/iar/startup_LPC54628.s b/hw/bsp/lpc54/iar/startup_LPC54628.s
new file mode 100644
index 000000000..fec5f7fca
--- /dev/null
+++ b/hw/bsp/lpc54/iar/startup_LPC54628.s
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+;  @file:    startup_LPC54628.s
+;  @purpose: CMSIS Cortex-M4 Core Device Startup File
+;            LPC54628
+;  @version: 2.0
+;  @date:    2024-10-29
+;  @build:   b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__iar_init$$done:              ; The vector table is not needed
+                      ; until after copy initialization is done
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     MemManage_Handler                             ;MPU Fault Handler
+        DCD     BusFault_Handler                              ;Bus Fault Handler
+        DCD     UsageFault_Handler                            ;Usage Fault Handler
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0xFFFFFFFF                                    ;ECRP
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     DebugMon_Handler                              ;Debug Monitor Handler
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     WDT_BOD_IRQHandler                            ;Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler                               ;DMA controller
+        DCD     GINT0_IRQHandler                              ;GPIO group 0
+        DCD     GINT1_IRQHandler                              ;GPIO group 1
+        DCD     PIN_INT0_IRQHandler                           ;Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler                           ;Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler                           ;Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler                           ;Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler                             ;Micro-tick Timer
+        DCD     MRT0_IRQHandler                               ;Multi-rate timer
+        DCD     CTIMER0_IRQHandler                            ;Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler                            ;Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler                               ;SCTimer/PWM
+        DCD     CTIMER3_IRQHandler                            ;Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler                          ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler                          ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler                          ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler                          ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler                          ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler                          ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler                          ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler                          ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler                          ;ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler                          ;ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler                         ;ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler                              ;Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler                             ;Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler                       ;USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler                               ;USB device
+        DCD     RTC_IRQHandler                                ;RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler                         ;Reserved interrupt
+        DCD     Reserved47_IRQHandler                         ;Reserved interrupt
+        DCD     PIN_INT4_IRQHandler                           ;Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler                           ;Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler                           ;Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler                           ;Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler                            ;Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler                            ;Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler                                ;Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler                             ;SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler                          ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler                          ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler                               ;SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler                          ;CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler                          ;CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler                          ;CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler                          ;CAN1 interrupt1
+        DCD     USB1_IRQHandler                               ;USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler                       ;USB1 activity
+        DCD     ETHERNET_IRQHandler                           ;Ethernet
+        DCD     ETHERNET_PMT_IRQHandler                       ;Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler                     ;Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler                             ;EEPROM interrupt
+        DCD     LCD_IRQHandler                                ;LCD interrupt
+        DCD     SHA_IRQHandler                                ;SHA interrupt
+        DCD     SMARTCARD0_IRQHandler                         ;Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler                         ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        MOVS    r0,#56
+        LDR     r1, =0x40000220
+        STR     r0, [r1]           ;Enable SRAM clock used by Stack
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h
index dc11e47fc..fec7e9067 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.h
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.h
@@ -37,26 +37,17 @@
 #endif
 
 // LED
-#define LED_PORT              0
-#define LED_PIN               1
+#define LED_PORT              BOARD_INITLEDSPINS_LED_PORT
+#define LED_PIN               BOARD_INITLEDSPINS_LED_PIN
 #define LED_STATE_ON          1
 
 // WAKE button
-#define BUTTON_PORT           0
-#define BUTTON_PIN            5
+#define BUTTON_PORT           BOARD_INITBUTTONSPINS_S1_PORT
+#define BUTTON_PIN            BOARD_INITBUTTONSPINS_S1_PIN
 #define BUTTON_STATE_ACTIVE   0
 
-// Number of neopixels
-#define NEOPIXEL_NUMBER       2
-#define NEOPIXEL_PORT         0
-#define NEOPIXEL_PIN          27
-#define NEOPIXEL_CH           6
-#define NEOPIXEL_TYPE         0
-
 // UART
 #define UART_DEV              USART0
-#define UART_RX_PINMUX        0U, 29U, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0U, 30U, IOCON_PIO_DIG_FUNC1_EN
 
 // XTAL
 #define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.mk b/hw/bsp/lpc55/boards/double_m33_express/board.mk
index d28700ca7..c0282686f 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.mk
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.mk
@@ -1,10 +1,17 @@
 MCU_VARIANT = LPC55S69
 MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
+RHPORT_DEVICE ?= 1
 
 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
 LD_FILE = $(BOARD_PATH)/LPC55S69_cm33_core0_uf2.ld
 
+SRC_C += \
+	$(TOP)/$(BOARD_PATH)/board/clock_config.c \
+	$(TOP)/$(BOARD_PATH)/board/pin_mux.c \
+	$(TOP)/$(BOARD_PATH)/board/peripherals.c
+
+INC += $(TOP)/$(BOARD_PATH)/board
+
 JLINK_DEVICE = LPC55S69
 PYOCD_TARGET = LPC55S69
 
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c
new file mode 100644
index 000000000..99a738f18
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v18.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FXCOM0_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 144 MHz}
+- {id: USB0_clock.outFreq, value: 48 MHz}
+- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_PLL_USB_OUT, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV}
+- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0DIV.scale, value: '2'}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '18'}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2'}
+- {id: SYSCON.USB0CLKDIV.scale, value: '3'}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */
+
+    POWER_SetVoltageForFreq(144000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(144000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(18U),
+        .pllRate = 144000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #endif
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);               /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false);         /*!< Set USB0CLKDIV divider to value 3 */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+    CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK);                 /*!< Switch USB0_CLK to MAIN_CLK */
+    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to PLL0_DIV */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h
new file mode 100644
index 000000000..9112ede78
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK          0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK            0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK           0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK           0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK           0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK           0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK           0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK            0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK            0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK            0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK            0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK            0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK            0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK            0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK            0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK            0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK              0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK          0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK      0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK          0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK   0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK            0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK           0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK               0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK              0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK          0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK          0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK            12000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK             0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK              0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK          0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK             0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK               0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK        0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK          0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK         0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK         0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK         0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK         0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK         0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK          0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK          0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK          0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK          0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK          0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK          0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK          0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK          0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK          0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK            0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK        0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK    0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK        0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK          0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK         0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK             0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK            0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK        0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK        0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK          96000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK           0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK            0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK        0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK           0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK             0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK           0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK           100000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK             0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK         0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         144000000U  /*!< Core clock frequency: 144000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK           48000000UL     /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK           144000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK             48000000UL     /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK         16000000UL     /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c
new file mode 100644
index 000000000..890a20fc6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+functionalGroups:
+- name: BOARD_InitPeripherals_cm33_core0
+  UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1
+  called_from_default_init: true
+  selectedCore: cm33_core0
+- name: BOARD_InitPeripherals_cm33_core1
+  UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48
+  selectedCore: cm33_core1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system'
+- global_system_definitions:
+  - user_definitions: ''
+  - user_includes: ''
+  - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals_cm33_core0 functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DEBUG_UART initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'DEBUG_UART'
+- type: 'flexcomm_usart'
+- mode: 'polling'
+- custom_name_enabled: 'true'
+- type_id: 'flexcomm_usart_2.2.0'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'FLEXCOMM0'
+- config_sets:
+  - usartConfig_t:
+    - usartConfig:
+      - clockSource: 'FXCOMFunctionClock'
+      - clockSourceFreq: 'ClocksTool_DefaultInit'
+      - baudRate_Bps: '115200'
+      - syncMode: 'kUSART_SyncModeDisabled'
+      - parityMode: 'kUSART_ParityDisabled'
+      - stopBitCount: 'kUSART_OneStopBit'
+      - bitCountPerChar: 'kUSART_8BitsPerChar'
+      - loopback: 'false'
+      - txWatermark: 'kUSART_TxFifo0'
+      - rxWatermark: 'kUSART_RxFifo1'
+      - enableRx: 'true'
+      - enableTx: 'true'
+      - clockPolarity: 'kUSART_RxSampleOnFallingEdge'
+      - enableContinuousSCLK: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const usart_config_t DEBUG_UART_config = {
+  .baudRate_Bps = 115200UL,
+  .syncMode = kUSART_SyncModeDisabled,
+  .parityMode = kUSART_ParityDisabled,
+  .stopBitCount = kUSART_OneStopBit,
+  .bitCountPerChar = kUSART_8BitsPerChar,
+  .loopback = false,
+  .txWatermark = kUSART_TxFifo0,
+  .rxWatermark = kUSART_RxFifo1,
+  .enableRx = true,
+  .enableTx = true,
+  .enableMode32k = false,
+  .clockPolarity = kUSART_RxSampleOnFallingEdge,
+  .enableContinuousSCLK = false
+};
+
+static void DEBUG_UART_init(void) {
+  /* Reset FLEXCOMM device */
+  RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+  USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'NVIC'
+- config_sets:
+  - nvic:
+    - interrupt_table: []
+    - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals_cm33_core0(void)
+{
+  /* Initialize components */
+  DEBUG_UART_init();
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals_cm33_core0();
+}
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h
new file mode 100644
index 000000000..fc4d72c33
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_usart.h"
+#include "fsl_clock.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */
+/* Definition of peripheral ID */
+#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0)
+/* Definition of the clock source frequency */
+#define DEBUG_UART_CLOCK_SOURCE 48000000UL
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+extern const usart_config_t DEBUG_UART_config;
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals_cm33_core0(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c
new file mode 100644
index 000000000..16e112dfc
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+pin_labels:
+- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitDEBUG_UARTPins();
+    BOARD_InitUSBPins();
+    BOARD_InitLEDsPins();
+    BOARD_InitBUTTONsPins();
+    BOARD_InitPins_Core0();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitDEBUG_UARTPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX);
+
+    const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSWD_DEBUGPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSWD_DEBUGPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitSWD_DEBUGPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */
+                                    IOCON_PIO_FUNC6 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI |
+                                    /* Analog switch is open (disabled) */
+                                    IOCON_PIO_ASW_DI);
+    /* PORT0 PIN10 (coords: 21) is configured as SWO */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO);
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled) */
+                                           IOCON_PIO_ASW_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled), only for A0 version */
+                                           IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled) */
+                                          IOCON_PIO_ASW_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled), only for A0 version */
+                                          IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSBPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP}
+  - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM}
+  - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
+  - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
+  - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
+  - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp}
+  - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28,
+    mode: pullUp}
+  - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp}
+  - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSBPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitUSBPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */
+                                IOCON_PIO_FUNC7 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS);
+
+    IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][12] = ((IOCON->PIO[1][12] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][29] = ((IOCON->PIO[1][29] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][30] = ((IOCON->PIO[1][30] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '7', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: OUTPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitLEDsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    gpio_pin_config_t LED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_1 (pin 7)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config);
+
+    IOCON->PIO[0][1] = ((IOCON->PIO[0][1] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT01 (pin 7) is configured as PIO0_1. */
+                        | IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBUTTONsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBUTTONsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitBUTTONsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    gpio_pin_config_t S1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_5 (pin 88)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config);
+
+    const uint32_t S1 = (/* Pin is configured as PIO0_5 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins_Core0:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins_Core0
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins_Core0(void)
+{
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitI2SPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled,
+    open_drain: disabled}
+  - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1,
+    identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitI2SPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitI2SPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */
+                                  IOCON_PIO_FUNC1 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI |
+                                  /* Analog switch is closed (enabled) */
+                                  IOCON_PIO_ASW_EN);
+    /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK);
+
+    const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS);
+
+    const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX);
+
+    const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */
+                                  IOCON_PIO_FUNC7 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK);
+
+    const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX);
+
+    const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+
+    const uint32_t MCLK = (/* Pin is configured as MCLK */
+                           IOCON_PIO_FUNC1 |
+                           /* No addition pin function */
+                           IOCON_PIO_MODE_INACT |
+                           /* Standard mode, output slew rate control is enabled */
+                           IOCON_PIO_SLEW_STANDARD |
+                           /* Input function is not inverted */
+                           IOCON_PIO_INV_DI |
+                           /* Enables digital function */
+                           IOCON_PIO_DIGITAL_EN |
+                           /* Open drain is disabled */
+                           IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN31 (coords: 91) is configured as MCLK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCELPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCELPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitACCELPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t ACCL_INTR_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_19 (pin 58)  */
+    GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config);
+
+    const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */
+                                IOCON_PIO_FUNC0 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI |
+                                /* Analog switch is open (disabled) */
+                                IOCON_PIO_ASW_DI);
+    /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h
new file mode 100644
index 000000000..33f000d0a
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U)
+/* @} */
+
+/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_ASW_DIS_EN 0x00u    /*!<@brief Analog switch is closed (enabled), only for A0 version */
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC6 0x06u         /*!<@brief Selects pin function 6 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U)
+/* @} */
+
+/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U)
+/* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Enables digital function */
+#define IOCON_PIO_DIGITAL_EN 0x0100u
+/*!
+ * @brief Selects pin function 7 */
+#define IOCON_PIO_FUNC7 0x07u
+/*!
+ * @brief Input function is not inverted */
+#define IOCON_PIO_INV_DI 0x00u
+/*!
+ * @brief No addition pin function */
+#define IOCON_PIO_MODE_INACT 0x00u
+/*!
+ * @brief Open drain is disabled */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u
+/*!
+ * @brief Standard mode, output slew rate control is enabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_28_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 7. */
+#define PIO0_28_FUNC_ALT7 0x07u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_28_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_12_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_12_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_12_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_29_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_29_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_29_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_30_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_30_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_30_MODE_PULL_UP 0x02u
+
+/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS
+  @{ */
+#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U                   /*!<@brief PORT pin number */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define PIO0_1_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_1_FUNC_ALT0 0x00u        /*!<@brief Selects pin function.: Alternative connection 0. */
+
+/*! @name PIO0_1 (number 7), P18[2]/SD1_CLK
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 0U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_PIN 1U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 1U)      /*!<@brief PORT pin mask */
+                                                        /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S1_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_PIN 5U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC2 0x02u         /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_FUNC7 0x07u         /*!<@brief Selects pin function 7 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO
+  @{ */
+#define BOARD_INITI2SPINS_MCLK_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_MCLK_PIN 31U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
+#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex
new file mode 100644
index 000000000..47d0909d6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex
@@ -0,0 +1,1283 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>LPC55S69</processor>
+      <package>LPC55S69JBD100</package>
+      <board>LPCXpresso55S69</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33_core0">
+         <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
+         <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <custom_copyright>
+         <text>/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+</text>
+         <enabled>true</enabled>
+      </custom_copyright>
+      <update_include_paths>true</update_include_paths>
+      <enable_parallel_routing>true</enable_parallel_routing>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>25.09.10</processor_version>
+            <pin_labels>
+               <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED"/>
+            </pin_labels>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSWD_DEBUGPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullDown"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DEBUG_SWD_SWO"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSBPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/>
+                  <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/>
+                  <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/>
+                  <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/>
+                  <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/>
+                  <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 1" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitPins_Core0">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitPins_Core1">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core1</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitI2SPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="FC6_I2S_CLK"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitACCELPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>25.09.10</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources/>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings/>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="PLL1_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/>
+                  <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/>
+                  <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/>
+                  <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/>
+                  <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.2.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data>true</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>25.09.10</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_i2c" quick_selection="QS_I2C_Master">
+                        <setting name="i2c_mode" value="kI2C_Master"/>
+                        <setting name="clockSource" value="FXCOMFunctionClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="i2c_master_config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="baudRate_Bps" value="100000"/>
+                           <setting name="enableTimeout" value="false"/>
+                           <setting name="timeout_Ms" value="35"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="usartConfig_t">
+                        <struct name="usartConfig">
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="syncMode" value="kUSART_SyncModeDisabled"/>
+                           <setting name="parityMode" value="kUSART_ParityDisabled"/>
+                           <setting name="stopBitCount" value="kUSART_OneStopBit"/>
+                           <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/>
+                           <setting name="loopback" value="false"/>
+                           <setting name="txWatermark" value="kUSART_TxFifo0"/>
+                           <setting name="rxWatermark" value="kUSART_RxFifo1"/>
+                           <setting name="enableRx" value="true"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/>
+                           <setting name="enableContinuousSCLK" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+            <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+                  <setting name="global_init" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet">
+               <config_set_global name="global_enet"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="10.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+            <tool_options>
+               <option id="_output_type_" value="c_code"/>
+               <option id="_legacy_source_names_" value="yes"/>
+            </tool_options>
+         </tee_profile>
+         <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true">
+            <description></description>
+            <options/>
+            <ahb>
+               <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/>
+               <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/>
+               <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/>
+               <masters>
+                  <master id="HASH" security="ns_user"/>
+                  <master id="MCM33C" security="ns_user"/>
+                  <master id="MCM33S" security="ns_user"/>
+                  <master id="PQ" security="ns_user"/>
+                  <master id="SDIO" security="ns_user"/>
+                  <master id="SDMA0" security="ns_user"/>
+                  <master id="SDMA1" security="ns_user"/>
+                  <master id="USBFSD" security="ns_user"/>
+                  <master id="USBFSH" security="ns_user"/>
+               </masters>
+               <peripherals>
+                  <peripheral id="ADC0" security="s_priv"/>
+                  <peripheral id="AHB_SECURE_CTRL" security="s_priv"/>
+                  <peripheral id="ANACTRL" security="s_priv"/>
+                  <peripheral id="CASPER" security="s_priv"/>
+                  <peripheral id="CRC_ENGINE" security="s_priv"/>
+                  <peripheral id="CTIMER0" security="s_priv"/>
+                  <peripheral id="CTIMER1" security="s_priv"/>
+                  <peripheral id="CTIMER2" security="s_priv"/>
+                  <peripheral id="CTIMER3" security="s_priv"/>
+                  <peripheral id="CTIMER4" security="s_priv"/>
+                  <peripheral id="DBGMAILBOX" security="s_priv"/>
+                  <peripheral id="DMA0" security="s_priv"/>
+                  <peripheral id="DMA1" security="s_priv"/>
+                  <peripheral id="FLASH" security="s_priv"/>
+                  <peripheral id="FLEXCOMM0" security="s_priv"/>
+                  <peripheral id="FLEXCOMM1" security="s_priv"/>
+                  <peripheral id="FLEXCOMM2" security="s_priv"/>
+                  <peripheral id="FLEXCOMM3" security="s_priv"/>
+                  <peripheral id="FLEXCOMM4" security="s_priv"/>
+                  <peripheral id="FLEXCOMM5" security="s_priv"/>
+                  <peripheral id="FLEXCOMM6" security="s_priv"/>
+                  <peripheral id="FLEXCOMM7" security="s_priv"/>
+                  <peripheral id="GINT0" security="s_priv"/>
+                  <peripheral id="GINT1" security="s_priv"/>
+                  <peripheral id="GPIO" security="s_priv"/>
+                  <peripheral id="HASHCRYPT" security="s_priv"/>
+                  <peripheral id="INPUTMUX" security="s_priv"/>
+                  <peripheral id="IOCON" security="s_priv"/>
+                  <peripheral id="MAILBOX" security="s_priv"/>
+                  <peripheral id="MRT0" security="s_priv"/>
+                  <peripheral id="OSTIMER" security="s_priv"/>
+                  <peripheral id="PINT" security="s_priv"/>
+                  <peripheral id="PLU" security="s_priv"/>
+                  <peripheral id="PMC" security="s_priv"/>
+                  <peripheral id="POWERQUAD" security="s_priv"/>
+                  <peripheral id="PRINCE" security="s_priv"/>
+                  <peripheral id="PUF" security="s_priv"/>
+                  <peripheral id="RNG" security="s_priv"/>
+                  <peripheral id="RTC" security="s_priv"/>
+                  <peripheral id="SCT0" security="s_priv"/>
+                  <peripheral id="SDIF" security="s_priv"/>
+                  <peripheral id="SECGPIO" security="s_priv"/>
+                  <peripheral id="SECPINT" security="s_priv"/>
+                  <peripheral id="SPI8" security="s_priv"/>
+                  <peripheral id="SYSCON" security="s_priv"/>
+                  <peripheral id="SYSCTL" security="s_priv"/>
+                  <peripheral id="USB0" security="s_priv"/>
+                  <peripheral id="USBFSH" security="s_priv"/>
+                  <peripheral id="USBHSD" security="s_priv"/>
+                  <peripheral id="USBHSH" security="s_priv"/>
+                  <peripheral id="USBPHY" security="s_priv"/>
+                  <peripheral id="UTICK0" security="s_priv"/>
+                  <peripheral id="WWDT" security="s_priv"/>
+               </peripherals>
+               <interrupts>
+                  <masking>
+                     <interrupt id="acmp_capt_irq" masked="Masked"/>
+                     <interrupt id="adc_irq" masked="Masked"/>
+                     <interrupt id="casper_irq" masked="Masked"/>
+                     <interrupt id="ctimer0_irq" masked="Masked"/>
+                     <interrupt id="ctimer1_irq" masked="Masked"/>
+                     <interrupt id="ctimer2_irq" masked="Masked"/>
+                     <interrupt id="ctimer3_irq" masked="Masked"/>
+                     <interrupt id="ctimer4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm0_irq" masked="Masked"/>
+                     <interrupt id="flexcomm1_irq" masked="Masked"/>
+                     <interrupt id="flexcomm2_irq" masked="Masked"/>
+                     <interrupt id="flexcomm3_irq" masked="Masked"/>
+                     <interrupt id="flexcomm4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm5_irq" masked="Masked"/>
+                     <interrupt id="flexcomm6_irq" masked="Masked"/>
+                     <interrupt id="flexcomm7_irq" masked="Masked"/>
+                     <interrupt id="global_irq0" masked="Masked"/>
+                     <interrupt id="global_irq1" masked="Masked"/>
+                     <interrupt id="lspi_hs_irq" masked="Masked"/>
+                     <interrupt id="mailbox_irq" masked="Masked"/>
+                     <interrupt id="mrt_irq" masked="Masked"/>
+                     <interrupt id="os_event_irq" masked="Masked"/>
+                     <interrupt id="pin_int4" masked="Masked"/>
+                     <interrupt id="pin_int5" masked="Masked"/>
+                     <interrupt id="pin_int6" masked="Masked"/>
+                     <interrupt id="pin_int7" masked="Masked"/>
+                     <interrupt id="pin_irq0" masked="Masked"/>
+                     <interrupt id="pin_irq1" masked="Masked"/>
+                     <interrupt id="pin_irq2" masked="Masked"/>
+                     <interrupt id="pin_irq3" masked="Masked"/>
+                     <interrupt id="plu_irq" masked="Masked"/>
+                     <interrupt id="pq_irq" masked="Masked"/>
+                     <interrupt id="qddkey_irq" masked="Masked"/>
+                     <interrupt id="rtc_irq" masked="Masked"/>
+                     <interrupt id="sct_irq" masked="Masked"/>
+                     <interrupt id="sdio_irq" masked="Masked"/>
+                     <interrupt id="sdma0_irq" masked="Masked"/>
+                     <interrupt id="sdma1_irq" masked="Masked"/>
+                     <interrupt id="sec_hypervisor_call_irq" masked="Masked"/>
+                     <interrupt id="sec_int0" masked="Masked"/>
+                     <interrupt id="sec_int1" masked="Masked"/>
+                     <interrupt id="sec_vio_irq" masked="Masked"/>
+                     <interrupt id="sha_irq" masked="Masked"/>
+                     <interrupt id="sys_irq" masked="Masked"/>
+                     <interrupt id="usb0_irq" masked="Masked"/>
+                     <interrupt id="usb0_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_irq" masked="Masked"/>
+                     <interrupt id="usb1_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_utmi_irq" masked="Masked"/>
+                     <interrupt id="utick_irq" masked="Masked"/>
+                  </masking>
+                  <security>
+                     <interrupt id="acmp_capt_irq" secure="Secure"/>
+                     <interrupt id="adc_irq" secure="Secure"/>
+                     <interrupt id="casper_irq" secure="Secure"/>
+                     <interrupt id="ctimer0_irq" secure="Secure"/>
+                     <interrupt id="ctimer1_irq" secure="Secure"/>
+                     <interrupt id="ctimer2_irq" secure="Secure"/>
+                     <interrupt id="ctimer3_irq" secure="Secure"/>
+                     <interrupt id="ctimer4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm0_irq" secure="Secure"/>
+                     <interrupt id="flexcomm1_irq" secure="Secure"/>
+                     <interrupt id="flexcomm2_irq" secure="Secure"/>
+                     <interrupt id="flexcomm3_irq" secure="Secure"/>
+                     <interrupt id="flexcomm4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm5_irq" secure="Secure"/>
+                     <interrupt id="flexcomm6_irq" secure="Secure"/>
+                     <interrupt id="flexcomm7_irq" secure="Secure"/>
+                     <interrupt id="global_irq0" secure="Secure"/>
+                     <interrupt id="global_irq1" secure="Secure"/>
+                     <interrupt id="lspi_hs_irq" secure="Secure"/>
+                     <interrupt id="mailbox_irq" secure="Secure"/>
+                     <interrupt id="mrt_irq" secure="Secure"/>
+                     <interrupt id="os_event_irq" secure="Secure"/>
+                     <interrupt id="pin_int4" secure="Secure"/>
+                     <interrupt id="pin_int5" secure="Secure"/>
+                     <interrupt id="pin_int6" secure="Secure"/>
+                     <interrupt id="pin_int7" secure="Secure"/>
+                     <interrupt id="pin_irq0" secure="Secure"/>
+                     <interrupt id="pin_irq1" secure="Secure"/>
+                     <interrupt id="pin_irq2" secure="Secure"/>
+                     <interrupt id="pin_irq3" secure="Secure"/>
+                     <interrupt id="plu_irq" secure="Secure"/>
+                     <interrupt id="pq_irq" secure="Secure"/>
+                     <interrupt id="qddkey_irq" secure="Secure"/>
+                     <interrupt id="rtc_irq" secure="Secure"/>
+                     <interrupt id="sct_irq" secure="Secure"/>
+                     <interrupt id="sdio_irq" secure="Secure"/>
+                     <interrupt id="sdma0_irq" secure="Secure"/>
+                     <interrupt id="sdma1_irq" secure="Secure"/>
+                     <interrupt id="sec_hypervisor_call_irq" secure="Secure"/>
+                     <interrupt id="sec_int0" secure="Secure"/>
+                     <interrupt id="sec_int1" secure="Secure"/>
+                     <interrupt id="sec_vio_irq" secure="Secure"/>
+                     <interrupt id="sha_irq" secure="Secure"/>
+                     <interrupt id="sys_irq" secure="Secure"/>
+                     <interrupt id="usb0_irq" secure="Secure"/>
+                     <interrupt id="usb0_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_irq" secure="Secure"/>
+                     <interrupt id="usb1_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_utmi_irq" secure="Secure"/>
+                     <interrupt id="utick_irq" secure="Secure"/>
+                  </security>
+               </interrupts>
+               <ports>
+                  <port id="pio0">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+                  <port id="pio1">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+               </ports>
+            </ahb>
+            <saus>
+               <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false">
+                  <region start="0" size="268435456" security="ns" enabled="true" index="0"/>
+                  <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="2"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="3"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="4"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="5"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="6"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="7"/>
+               </sau>
+            </saus>
+            <global_options>
+               <option id="AIRCR_PRIS" value="no"/>
+               <option id="AIRCR_BFHFNMINS" value="no"/>
+               <option id="AIRCR_SYSRESETREQS" value="no"/>
+               <option id="SCR_SLEEPDEEPS" value="no"/>
+               <option id="SHCSR_SECUREFAULTENA" value="no"/>
+               <option id="CPACR_CP0" value="3"/>
+               <option id="CPACR_CP1" value="3"/>
+               <option id="CPACR_CP2" value="0"/>
+               <option id="CPACR_CP3" value="0"/>
+               <option id="CPACR_CP4" value="0"/>
+               <option id="CPACR_CP5" value="0"/>
+               <option id="CPACR_CP6" value="0"/>
+               <option id="CPACR_CP7" value="0"/>
+               <option id="CPACR_CP10" value="3"/>
+               <option id="CPACR_CP11" value="3"/>
+               <option id="NSACR_CP0" value="yes"/>
+               <option id="NSACR_CP1" value="yes"/>
+               <option id="NSACR_CP2" value="no"/>
+               <option id="NSACR_CP3" value="no"/>
+               <option id="NSACR_CP4" value="no"/>
+               <option id="NSACR_CP5" value="no"/>
+               <option id="NSACR_CP6" value="no"/>
+               <option id="NSACR_CP7" value="no"/>
+               <option id="NSACR_CP10" value="yes"/>
+               <option id="NSACR_CP11" value="yes"/>
+               <option id="CPPWR_SU0" value="no"/>
+               <option id="CPPWR_SUS0" value="no"/>
+               <option id="CPPWR_SU1" value="no"/>
+               <option id="CPPWR_SUS1" value="no"/>
+               <option id="CPPWR_SU2" value="no"/>
+               <option id="CPPWR_SUS2" value="no"/>
+               <option id="CPPWR_SU3" value="no"/>
+               <option id="CPPWR_SUS3" value="no"/>
+               <option id="CPPWR_SU4" value="no"/>
+               <option id="CPPWR_SUS4" value="no"/>
+               <option id="CPPWR_SU5" value="no"/>
+               <option id="CPPWR_SUS5" value="no"/>
+               <option id="CPPWR_SU6" value="no"/>
+               <option id="CPPWR_SUS6" value="no"/>
+               <option id="CPPWR_SU7" value="no"/>
+               <option id="CPPWR_SUS7" value="no"/>
+               <option id="CPPWR_SU10" value="no"/>
+               <option id="CPPWR_SUS10" value="no"/>
+               <option id="CPPWR_SU11" value="no"/>
+               <option id="CPPWR_SUS11" value="no"/>
+               <option id="SEC_GPIO_MASK0_LOCK" value="no"/>
+               <option id="SEC_GPIO_MASK1_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
+               <option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
+               <option id="CPU0_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU0_LOCK_NS_MPU" value="no"/>
+               <option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
+               <option id="CPU0_LOCK_S_MPU" value="no"/>
+               <option id="CPU0_LOCK_SAU" value="no"/>
+               <option id="CPU0_LOCK_REG_LOCK" value="no"/>
+               <option id="CPU1_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU1_LOCK_NS_MPU" value="no"/>
+               <option id="CPU1_LOCK_REG_LOCK" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/>
+            </global_options>
+            <mpus>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+            </mpus>
+         </functional_group>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex
new file mode 100644
index 000000000..cc59745f9
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex
@@ -0,0 +1,856 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="LPCXpresso55S28" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="485a5299-e2fe-41ab-bc43-80d8d2a4ae02" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>LPC55S28</processor>
+      <package>LPC55S28JBD100</package>
+      <board>LPCXpresso55S28</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33_core0">
+         <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <custom_copyright>
+         <text>/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+</text>
+         <enabled>true</enabled>
+      </custom_copyright>
+      <update_include_paths>true</update_include_paths>
+      <enable_parallel_routing>true</enable_parallel_routing>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>25.09.10</processor_version>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSWD_DEBUGPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullDown"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DEBUG_SWD_SWO"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSBPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/>
+                  <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/>
+                  <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/>
+                  <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/>
+                  <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/>
+                  <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitPins_Core0">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitI2SPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="FC6_I2S_CLK"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitACCELPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>25.09.10</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources/>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL1_Mode" value="Normal" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SYSTICK0_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="PLL1_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/>
+                  <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/>
+                  <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/>
+                  <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.SYSTICKCLKSEL0.sel" value="SYSCON.SYSTICKCLKDIV0" locked="false"/>
+                  <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/>
+                  <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>N/A</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.2.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data>true</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>25.09.10</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="DEBUG_UART" uuid="30367b6e-4b43-4345-bc10-e4052723fa66" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="usartConfig_t">
+                        <struct name="usartConfig">
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="syncMode" value="kUSART_SyncModeDisabled"/>
+                           <setting name="parityMode" value="kUSART_ParityDisabled"/>
+                           <setting name="stopBitCount" value="kUSART_OneStopBit"/>
+                           <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/>
+                           <setting name="loopback" value="false"/>
+                           <setting name="txWatermark" value="kUSART_TxFifo0"/>
+                           <setting name="rxWatermark" value="kUSART_RxFifo1"/>
+                           <setting name="enableRx" value="true"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/>
+                           <setting name="enableContinuousSCLK" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="ACCEL" uuid="796441cb-6cbf-48af-8003-54caaeb9a132" type="flexcomm_i2c" type_id="flexcomm_i2c_2.0.1" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_i2c" quick_selection="QS_I2C_Master">
+                        <setting name="i2c_mode" value="kI2C_Master"/>
+                        <setting name="clockSource" value="FXCOMFunctionClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="i2c_master_config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="baudRate_Bps" value="100000"/>
+                           <setting name="enableTimeout" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="SW" uuid="723cdb07-2d95-4daf-94b4-1dfaf0ce6c04" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="LEDS" uuid="7ec70f15-5deb-44fa-b8cf-2d12230a37ac" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="NVIC" uuid="d00e8bd3-19f3-445c-9444-103d6461e0d1" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="4e239a4c-f368-4554-b66e-d1af6e8b1f5d" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+                  <setting name="global_init" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="7bbbd3b5-f7c2-4cb2-8b95-c037fdaf8e02" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_can" uuid="1560ea56-1bfb-4123-a192-daeeed8f2a1d" type_id="generic_can">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="4305ffdd-d7f2-418a-b81b-8a042e7e4c75" type_id="uart_cmsis_common">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="fe22d2c9-7984-4e79-a7b1-8d26fad750be" type_id="generic_uart">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_enet" uuid="f5a27f2d-a41b-4143-ad53-b9ee09903619" type_id="generic_enet">
+               <config_set_global name="global_enet"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="03fd1bc8-0fd6-4b47-a53c-1c40e2aa781e" type_id="gpio_adapter_common">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="10.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
index d935b70e6..b3d6ec722 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -1,10 +1,17 @@
 set(MCU_VARIANT LPC55S28)
 set(MCU_CORE LPC55S28)
+set(MCU_DRIVER_VARIANT LPC55S69)
 
 set(JLINK_DEVICE LPC55S28)
+set(JLINK_OPTION "-USB 000727031389")
+
 set(PYOCD_TARGET LPC55S28)
 set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
 
+# device fullspeed, host highspeed
+set(RHPORT_DEVICE 0)
+set(RHPORT_HOST 1)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
index 907aee6a4..c8d3a2b8f 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h
@@ -36,20 +36,18 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              1
-#define LED_PIN               6
+// LED: use red LED from generated pin_mux
+#define LED_PORT              BOARD_INITLEDSPINS_LED_RED_PORT
+#define LED_PIN               BOARD_INITLEDSPINS_LED_RED_PIN
 #define LED_STATE_ON          0
 
-// WAKE button
-#define BUTTON_PORT           1
-#define BUTTON_PIN            18
+// WAKE button: use S2 from generated pin_mux
+#define BUTTON_PORT           BOARD_INITBUTTONSPINS_S2_PORT
+#define BUTTON_PIN            BOARD_INITBUTTONSPINS_S2_PIN
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
 
 // XTAL
 #define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
index ec0828e41..db2e11fd7 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk
@@ -1,9 +1,20 @@
 MCU_VARIANT = LPC55S28
 MCU_CORE = LPC55S28
-PORT ?= 1
+MCU_DRIVER_VARIANT = LPC55S69
+
+# device fullspeed, host highspeed
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 1
 
 CFLAGS += -DCPU_LPC55S28JBD100
 
+SRC_C += \
+	$(TOP)/$(BOARD_PATH)/board/clock_config.c \
+	$(TOP)/$(BOARD_PATH)/board/pin_mux.c \
+	$(TOP)/$(BOARD_PATH)/board/peripherals.c
+
+INC += $(TOP)/$(BOARD_PATH)/board
+
 JLINK_DEVICE = LPC55S28
 PYOCD_TARGET = LPC55S28
 
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c
new file mode 100644
index 000000000..c1e8e0575
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v18.0
+processor: LPC55S28
+package_id: LPC55S28JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S28
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FXCOM0_clock.outFreq, value: 48 MHz}
+- {id: SYSTICK0_clock.outFreq, value: 144 MHz}
+- {id: System_clock.outFreq, value: 144 MHz}
+- {id: USB0_clock.outFreq, value: 48 MHz}
+- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_PLL_USB_OUT, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV}
+- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0DIV.scale, value: '2'}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '18'}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2'}
+- {id: SYSCON.SYSTICKCLKSEL0.sel, value: SYSCON.SYSTICKCLKDIV0}
+- {id: SYSCON.USB0CLKDIV.scale, value: '3'}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */
+
+    POWER_SetVoltageForFreq(144000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(144000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(18U),
+        .pllRate = 144000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 0U, true);               /*!< Reset SYSTICKCLKDIV0 divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 1U, false);              /*!< Set SYSTICKCLKDIV0 divider to value 1 */
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #endif
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);               /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false);         /*!< Set USB0CLKDIV divider to value 3 */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+    CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK);                 /*!< Switch USB0_CLK to MAIN_CLK */
+    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to PLL0_DIV */
+    CLOCK_AttachClk(kSYSTICK_DIV0_to_SYSTICK0);                 /*!< Switch SYSTICK0 to SYSTICK_DIV0 */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h
new file mode 100644
index 000000000..fdd472793
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK          0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK            0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK           0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK           0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK           0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK           0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK           0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK            0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK            0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK            0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK            0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK            0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK            0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK            0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK            0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK            0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK              0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK          0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK      0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK          0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK   0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK            0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK           0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK               0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK              0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK          0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK            12000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK             0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK              0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK          0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK             0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK               0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK        0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK          0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK         0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK         0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK         0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK         0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK         0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK          0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK          0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK          0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK          0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK          0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK          0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK          0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK          0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK          0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK            0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK        0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK    0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK        0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK          0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK         0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK             0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK            0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK        0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK          96000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK           0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK            0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK        0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK           0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK             0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK           0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK           100000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK             0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK         0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         144000000U  /*!< Core clock frequency: 144000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK           48000000UL     /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK         144000000UL    /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK           144000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK             48000000UL     /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK         16000000UL     /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c
new file mode 100644
index 000000000..f3b986b6c
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: LPC55S28
+package_id: LPC55S28JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S28
+functionalGroups:
+- name: BOARD_InitPeripherals
+  UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1
+  called_from_default_init: true
+  selectedCore: cm33_core0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions:
+  - user_definitions: ''
+  - user_includes: ''
+  - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DEBUG_UART initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'DEBUG_UART'
+- type: 'flexcomm_usart'
+- mode: 'polling'
+- custom_name_enabled: 'true'
+- type_id: 'flexcomm_usart_2.2.0'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'FLEXCOMM0'
+- config_sets:
+  - usartConfig_t:
+    - usartConfig:
+      - clockSource: 'FXCOMFunctionClock'
+      - clockSourceFreq: 'ClocksTool_DefaultInit'
+      - baudRate_Bps: '115200'
+      - syncMode: 'kUSART_SyncModeDisabled'
+      - parityMode: 'kUSART_ParityDisabled'
+      - stopBitCount: 'kUSART_OneStopBit'
+      - bitCountPerChar: 'kUSART_8BitsPerChar'
+      - loopback: 'false'
+      - txWatermark: 'kUSART_TxFifo0'
+      - rxWatermark: 'kUSART_RxFifo1'
+      - enableRx: 'true'
+      - enableTx: 'true'
+      - clockPolarity: 'kUSART_RxSampleOnFallingEdge'
+      - enableContinuousSCLK: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const usart_config_t DEBUG_UART_config = {
+  .baudRate_Bps = 115200UL,
+  .syncMode = kUSART_SyncModeDisabled,
+  .parityMode = kUSART_ParityDisabled,
+  .stopBitCount = kUSART_OneStopBit,
+  .bitCountPerChar = kUSART_8BitsPerChar,
+  .loopback = false,
+  .txWatermark = kUSART_TxFifo0,
+  .rxWatermark = kUSART_RxFifo1,
+  .enableRx = true,
+  .enableTx = true,
+  .enableMode32k = false,
+  .clockPolarity = kUSART_RxSampleOnFallingEdge,
+  .enableContinuousSCLK = false
+};
+
+static void DEBUG_UART_init(void) {
+  /* Reset FLEXCOMM device */
+  RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+  USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'NVIC'
+- config_sets:
+  - nvic:
+    - interrupt_table: []
+    - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+  /* Initialize components */
+  DEBUG_UART_init();
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals();
+}
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h
new file mode 100644
index 000000000..3f498f4af
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_usart.h"
+#include "fsl_clock.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals functional group */
+/* Definition of peripheral ID */
+#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0)
+/* Definition of the clock source frequency */
+#define DEBUG_UART_CLOCK_SOURCE 48000000UL
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+extern const usart_config_t DEBUG_UART_config;
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c
new file mode 100644
index 000000000..924961d42
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c
@@ -0,0 +1,795 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: LPC55S28
+package_id: LPC55S28JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S28
+external_user_signals: {}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitDEBUG_UARTPins();
+    BOARD_InitUSBPins();
+    BOARD_InitLEDsPins();
+    BOARD_InitBUTTONsPins();
+    BOARD_InitPins_Core0();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitDEBUG_UARTPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX);
+
+    const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSWD_DEBUGPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSWD_DEBUGPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitSWD_DEBUGPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */
+                                    IOCON_PIO_FUNC6 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI |
+                                    /* Analog switch is open (disabled) */
+                                    IOCON_PIO_ASW_DI);
+    /* PORT0 PIN10 (coords: 21) is configured as SWO */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO);
+
+    const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                       IOCON_PIO_FUNC6 |
+                                       /* Selects pull-down function */
+                                       IOCON_PIO_MODE_PULLDOWN |
+                                       /* Standard mode, output slew rate control is enabled */
+                                       IOCON_PIO_SLEW_STANDARD |
+                                       /* Input function is not inverted */
+                                       IOCON_PIO_INV_DI |
+                                       /* Enables digital function */
+                                       IOCON_PIO_DIGITAL_EN |
+                                       /* Open drain is disabled */
+                                       IOCON_PIO_OPENDRAIN_DI |
+                                       /* Analog switch is closed (enabled) */
+                                       IOCON_PIO_ASW_EN);
+    /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+
+    const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                      IOCON_PIO_FUNC6 |
+                                      /* Selects pull-up function */
+                                      IOCON_PIO_MODE_PULLUP |
+                                      /* Standard mode, output slew rate control is enabled */
+                                      IOCON_PIO_SLEW_STANDARD |
+                                      /* Input function is not inverted */
+                                      IOCON_PIO_INV_DI |
+                                      /* Enables digital function */
+                                      IOCON_PIO_DIGITAL_EN |
+                                      /* Open drain is disabled */
+                                      IOCON_PIO_OPENDRAIN_DI |
+                                      /* Analog switch is closed (enabled) */
+                                      IOCON_PIO_ASW_EN);
+    /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSBPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP}
+  - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM}
+  - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
+  - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
+  - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
+  - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp}
+  - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp}
+  - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28,
+    mode: pullUp}
+  - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSBPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitUSBPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */
+                                IOCON_PIO_FUNC7 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS);
+
+    IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][12] = ((IOCON->PIO[1][12] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][29] = ((IOCON->PIO[1][29] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][30] = ((IOCON->PIO[1][30] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitLEDsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t LED_BLUE_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_4 (pin 1)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
+
+    gpio_pin_config_t LED_RED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_6 (pin 5)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
+
+    gpio_pin_config_t LED_GREEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_7 (pin 9)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
+
+    const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */
+                               IOCON_PIO_FUNC0 |
+                               /* Selects pull-up function */
+                               IOCON_PIO_MODE_PULLUP |
+                               /* Standard mode, output slew rate control is enabled */
+                               IOCON_PIO_SLEW_STANDARD |
+                               /* Input function is not inverted */
+                               IOCON_PIO_INV_DI |
+                               /* Enables digital function */
+                               IOCON_PIO_DIGITAL_EN |
+                               /* Open drain is disabled */
+                               IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE);
+
+    const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */
+                              IOCON_PIO_FUNC0 |
+                              /* Selects pull-up function */
+                              IOCON_PIO_MODE_PULLUP |
+                              /* Standard mode, output slew rate control is enabled */
+                              IOCON_PIO_SLEW_STANDARD |
+                              /* Input function is not inverted */
+                              IOCON_PIO_INV_DI |
+                              /* Enables digital function */
+                              IOCON_PIO_DIGITAL_EN |
+                              /* Open drain is disabled */
+                              IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED);
+
+    const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */
+                                IOCON_PIO_FUNC0 |
+                                /* Selects pull-up function */
+                                IOCON_PIO_MODE_PULLUP |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBUTTONsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBUTTONsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitBUTTONsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t S1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_5 (pin 88)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config);
+
+    gpio_pin_config_t S3_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_9 (pin 10)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config);
+
+    gpio_pin_config_t S2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_18 (pin 64)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config);
+
+    const uint32_t S1 = (/* Pin is configured as PIO0_5 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1);
+
+    const uint32_t S2 = (/* Pin is configured as PIO1_18 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2);
+
+    const uint32_t S3 = (/* Pin is configured as PIO1_9 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI |
+                         /* Analog switch is closed (enabled) */
+                         IOCON_PIO_ASW_EN);
+    /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins_Core0:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins_Core0
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins_Core0(void)
+{
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitI2SPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled,
+    open_drain: disabled}
+  - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1,
+    identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitI2SPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitI2SPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */
+                                  IOCON_PIO_FUNC1 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI |
+                                  /* Analog switch is closed (enabled) */
+                                  IOCON_PIO_ASW_EN);
+    /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK);
+
+    const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS);
+
+    const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX);
+
+    const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */
+                                  IOCON_PIO_FUNC7 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK);
+
+    const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX);
+
+    const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+
+    const uint32_t MCLK = (/* Pin is configured as MCLK */
+                           IOCON_PIO_FUNC1 |
+                           /* No addition pin function */
+                           IOCON_PIO_MODE_INACT |
+                           /* Standard mode, output slew rate control is enabled */
+                           IOCON_PIO_SLEW_STANDARD |
+                           /* Input function is not inverted */
+                           IOCON_PIO_INV_DI |
+                           /* Enables digital function */
+                           IOCON_PIO_DIGITAL_EN |
+                           /* Open drain is disabled */
+                           IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN31 (coords: 91) is configured as MCLK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCELPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCELPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitACCELPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t ACCL_INTR_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_19 (pin 58)  */
+    GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config);
+
+    const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */
+                                IOCON_PIO_FUNC0 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI |
+                                /* Analog switch is open (disabled) */
+                                IOCON_PIO_ASW_DI);
+    /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h
new file mode 100644
index 000000000..2a99795ef
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h
@@ -0,0 +1,433 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U)
+/* @} */
+
+/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC6 0x06u         /*!<@brief Selects pin function 6 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U)
+/* @} */
+
+/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U)
+/* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Enables digital function */
+#define IOCON_PIO_DIGITAL_EN 0x0100u
+/*!
+ * @brief Selects pin function 7 */
+#define IOCON_PIO_FUNC7 0x07u
+/*!
+ * @brief Input function is not inverted */
+#define IOCON_PIO_INV_DI 0x00u
+/*!
+ * @brief No addition pin function */
+#define IOCON_PIO_MODE_INACT 0x00u
+/*!
+ * @brief Open drain is disabled */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u
+/*!
+ * @brief Standard mode, output slew rate control is enabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_28_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 7. */
+#define PIO0_28_FUNC_ALT7 0x07u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_28_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_12_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_12_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_12_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_29_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_29_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_29_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_30_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_30_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_30_MODE_PULL_UP 0x02u
+
+/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS
+  @{ */
+#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U                   /*!<@brief PORT pin number */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U)      /*!<@brief PORT pin mask */
+                                                             /* @} */
+
+/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_RED_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_RED_PIN 6U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U)      /*!<@brief PORT pin mask */
+                                                            /* @} */
+
+/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S1_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_PIN 5U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S2_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S2_PIN 18U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U)      /*!<@brief PORT pin mask */
+                                                           /* @} */
+
+/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S3_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S3_PIN 9U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC2 0x02u         /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_FUNC7 0x07u         /*!<@brief Selects pin function 7 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO
+  @{ */
+#define BOARD_INITI2SPINS_MCLK_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_MCLK_PIN 31U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
+#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex
new file mode 100644
index 000000000..9e31688b7
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex
@@ -0,0 +1,1329 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>LPC55S69</processor>
+      <package>LPC55S69JBD100</package>
+      <board>LPCXpresso55S69</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33_core0">
+         <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
+         <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <custom_copyright>
+         <text>/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+</text>
+         <enabled>true</enabled>
+      </custom_copyright>
+      <update_include_paths>true</update_include_paths>
+      <enable_parallel_routing>true</enable_parallel_routing>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>25.09.10</processor_version>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSWD_DEBUGPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullDown"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DEBUG_SWD_SWO"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSBPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/>
+                  <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/>
+                  <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/>
+                  <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/>
+                  <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/>
+                  <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitPins_Core0">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitPins_Core1">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core1</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitI2SPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="FC6_I2S_CLK"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitACCELPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>25.09.10</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources/>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings/>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="PLL1_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/>
+                  <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/>
+                  <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/>
+                  <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/>
+                  <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.2.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data>true</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>25.09.10</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_i2c" quick_selection="QS_I2C_Master">
+                        <setting name="i2c_mode" value="kI2C_Master"/>
+                        <setting name="clockSource" value="FXCOMFunctionClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="i2c_master_config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="baudRate_Bps" value="100000"/>
+                           <setting name="enableTimeout" value="false"/>
+                           <setting name="timeout_Ms" value="35"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="usartConfig_t">
+                        <struct name="usartConfig">
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="syncMode" value="kUSART_SyncModeDisabled"/>
+                           <setting name="parityMode" value="kUSART_ParityDisabled"/>
+                           <setting name="stopBitCount" value="kUSART_OneStopBit"/>
+                           <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/>
+                           <setting name="loopback" value="false"/>
+                           <setting name="txWatermark" value="kUSART_TxFifo0"/>
+                           <setting name="rxWatermark" value="kUSART_RxFifo1"/>
+                           <setting name="enableRx" value="true"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/>
+                           <setting name="enableContinuousSCLK" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+            <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+                  <setting name="global_init" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet">
+               <config_set_global name="global_enet"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="10.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+            <tool_options>
+               <option id="_output_type_" value="c_code"/>
+               <option id="_legacy_source_names_" value="yes"/>
+            </tool_options>
+         </tee_profile>
+         <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true">
+            <description></description>
+            <options/>
+            <ahb>
+               <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/>
+               <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/>
+               <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/>
+               <masters>
+                  <master id="HASH" security="ns_user"/>
+                  <master id="MCM33C" security="ns_user"/>
+                  <master id="MCM33S" security="ns_user"/>
+                  <master id="PQ" security="ns_user"/>
+                  <master id="SDIO" security="ns_user"/>
+                  <master id="SDMA0" security="ns_user"/>
+                  <master id="SDMA1" security="ns_user"/>
+                  <master id="USBFSD" security="ns_user"/>
+                  <master id="USBFSH" security="ns_user"/>
+               </masters>
+               <peripherals>
+                  <peripheral id="ADC0" security="s_priv"/>
+                  <peripheral id="AHB_SECURE_CTRL" security="s_priv"/>
+                  <peripheral id="ANACTRL" security="s_priv"/>
+                  <peripheral id="CASPER" security="s_priv"/>
+                  <peripheral id="CRC_ENGINE" security="s_priv"/>
+                  <peripheral id="CTIMER0" security="s_priv"/>
+                  <peripheral id="CTIMER1" security="s_priv"/>
+                  <peripheral id="CTIMER2" security="s_priv"/>
+                  <peripheral id="CTIMER3" security="s_priv"/>
+                  <peripheral id="CTIMER4" security="s_priv"/>
+                  <peripheral id="DBGMAILBOX" security="s_priv"/>
+                  <peripheral id="DMA0" security="s_priv"/>
+                  <peripheral id="DMA1" security="s_priv"/>
+                  <peripheral id="FLASH" security="s_priv"/>
+                  <peripheral id="FLEXCOMM0" security="s_priv"/>
+                  <peripheral id="FLEXCOMM1" security="s_priv"/>
+                  <peripheral id="FLEXCOMM2" security="s_priv"/>
+                  <peripheral id="FLEXCOMM3" security="s_priv"/>
+                  <peripheral id="FLEXCOMM4" security="s_priv"/>
+                  <peripheral id="FLEXCOMM5" security="s_priv"/>
+                  <peripheral id="FLEXCOMM6" security="s_priv"/>
+                  <peripheral id="FLEXCOMM7" security="s_priv"/>
+                  <peripheral id="GINT0" security="s_priv"/>
+                  <peripheral id="GINT1" security="s_priv"/>
+                  <peripheral id="GPIO" security="s_priv"/>
+                  <peripheral id="HASHCRYPT" security="s_priv"/>
+                  <peripheral id="INPUTMUX" security="s_priv"/>
+                  <peripheral id="IOCON" security="s_priv"/>
+                  <peripheral id="MAILBOX" security="s_priv"/>
+                  <peripheral id="MRT0" security="s_priv"/>
+                  <peripheral id="OSTIMER" security="s_priv"/>
+                  <peripheral id="PINT" security="s_priv"/>
+                  <peripheral id="PLU" security="s_priv"/>
+                  <peripheral id="PMC" security="s_priv"/>
+                  <peripheral id="POWERQUAD" security="s_priv"/>
+                  <peripheral id="PRINCE" security="s_priv"/>
+                  <peripheral id="PUF" security="s_priv"/>
+                  <peripheral id="RNG" security="s_priv"/>
+                  <peripheral id="RTC" security="s_priv"/>
+                  <peripheral id="SCT0" security="s_priv"/>
+                  <peripheral id="SDIF" security="s_priv"/>
+                  <peripheral id="SECGPIO" security="s_priv"/>
+                  <peripheral id="SECPINT" security="s_priv"/>
+                  <peripheral id="SPI8" security="s_priv"/>
+                  <peripheral id="SYSCON" security="s_priv"/>
+                  <peripheral id="SYSCTL" security="s_priv"/>
+                  <peripheral id="USB0" security="s_priv"/>
+                  <peripheral id="USBFSH" security="s_priv"/>
+                  <peripheral id="USBHSD" security="s_priv"/>
+                  <peripheral id="USBHSH" security="s_priv"/>
+                  <peripheral id="USBPHY" security="s_priv"/>
+                  <peripheral id="UTICK0" security="s_priv"/>
+                  <peripheral id="WWDT" security="s_priv"/>
+               </peripherals>
+               <interrupts>
+                  <masking>
+                     <interrupt id="acmp_capt_irq" masked="Masked"/>
+                     <interrupt id="adc_irq" masked="Masked"/>
+                     <interrupt id="casper_irq" masked="Masked"/>
+                     <interrupt id="ctimer0_irq" masked="Masked"/>
+                     <interrupt id="ctimer1_irq" masked="Masked"/>
+                     <interrupt id="ctimer2_irq" masked="Masked"/>
+                     <interrupt id="ctimer3_irq" masked="Masked"/>
+                     <interrupt id="ctimer4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm0_irq" masked="Masked"/>
+                     <interrupt id="flexcomm1_irq" masked="Masked"/>
+                     <interrupt id="flexcomm2_irq" masked="Masked"/>
+                     <interrupt id="flexcomm3_irq" masked="Masked"/>
+                     <interrupt id="flexcomm4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm5_irq" masked="Masked"/>
+                     <interrupt id="flexcomm6_irq" masked="Masked"/>
+                     <interrupt id="flexcomm7_irq" masked="Masked"/>
+                     <interrupt id="global_irq0" masked="Masked"/>
+                     <interrupt id="global_irq1" masked="Masked"/>
+                     <interrupt id="lspi_hs_irq" masked="Masked"/>
+                     <interrupt id="mailbox_irq" masked="Masked"/>
+                     <interrupt id="mrt_irq" masked="Masked"/>
+                     <interrupt id="os_event_irq" masked="Masked"/>
+                     <interrupt id="pin_int4" masked="Masked"/>
+                     <interrupt id="pin_int5" masked="Masked"/>
+                     <interrupt id="pin_int6" masked="Masked"/>
+                     <interrupt id="pin_int7" masked="Masked"/>
+                     <interrupt id="pin_irq0" masked="Masked"/>
+                     <interrupt id="pin_irq1" masked="Masked"/>
+                     <interrupt id="pin_irq2" masked="Masked"/>
+                     <interrupt id="pin_irq3" masked="Masked"/>
+                     <interrupt id="plu_irq" masked="Masked"/>
+                     <interrupt id="pq_irq" masked="Masked"/>
+                     <interrupt id="qddkey_irq" masked="Masked"/>
+                     <interrupt id="rtc_irq" masked="Masked"/>
+                     <interrupt id="sct_irq" masked="Masked"/>
+                     <interrupt id="sdio_irq" masked="Masked"/>
+                     <interrupt id="sdma0_irq" masked="Masked"/>
+                     <interrupt id="sdma1_irq" masked="Masked"/>
+                     <interrupt id="sec_hypervisor_call_irq" masked="Masked"/>
+                     <interrupt id="sec_int0" masked="Masked"/>
+                     <interrupt id="sec_int1" masked="Masked"/>
+                     <interrupt id="sec_vio_irq" masked="Masked"/>
+                     <interrupt id="sha_irq" masked="Masked"/>
+                     <interrupt id="sys_irq" masked="Masked"/>
+                     <interrupt id="usb0_irq" masked="Masked"/>
+                     <interrupt id="usb0_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_irq" masked="Masked"/>
+                     <interrupt id="usb1_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_utmi_irq" masked="Masked"/>
+                     <interrupt id="utick_irq" masked="Masked"/>
+                  </masking>
+                  <security>
+                     <interrupt id="acmp_capt_irq" secure="Secure"/>
+                     <interrupt id="adc_irq" secure="Secure"/>
+                     <interrupt id="casper_irq" secure="Secure"/>
+                     <interrupt id="ctimer0_irq" secure="Secure"/>
+                     <interrupt id="ctimer1_irq" secure="Secure"/>
+                     <interrupt id="ctimer2_irq" secure="Secure"/>
+                     <interrupt id="ctimer3_irq" secure="Secure"/>
+                     <interrupt id="ctimer4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm0_irq" secure="Secure"/>
+                     <interrupt id="flexcomm1_irq" secure="Secure"/>
+                     <interrupt id="flexcomm2_irq" secure="Secure"/>
+                     <interrupt id="flexcomm3_irq" secure="Secure"/>
+                     <interrupt id="flexcomm4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm5_irq" secure="Secure"/>
+                     <interrupt id="flexcomm6_irq" secure="Secure"/>
+                     <interrupt id="flexcomm7_irq" secure="Secure"/>
+                     <interrupt id="global_irq0" secure="Secure"/>
+                     <interrupt id="global_irq1" secure="Secure"/>
+                     <interrupt id="lspi_hs_irq" secure="Secure"/>
+                     <interrupt id="mailbox_irq" secure="Secure"/>
+                     <interrupt id="mrt_irq" secure="Secure"/>
+                     <interrupt id="os_event_irq" secure="Secure"/>
+                     <interrupt id="pin_int4" secure="Secure"/>
+                     <interrupt id="pin_int5" secure="Secure"/>
+                     <interrupt id="pin_int6" secure="Secure"/>
+                     <interrupt id="pin_int7" secure="Secure"/>
+                     <interrupt id="pin_irq0" secure="Secure"/>
+                     <interrupt id="pin_irq1" secure="Secure"/>
+                     <interrupt id="pin_irq2" secure="Secure"/>
+                     <interrupt id="pin_irq3" secure="Secure"/>
+                     <interrupt id="plu_irq" secure="Secure"/>
+                     <interrupt id="pq_irq" secure="Secure"/>
+                     <interrupt id="qddkey_irq" secure="Secure"/>
+                     <interrupt id="rtc_irq" secure="Secure"/>
+                     <interrupt id="sct_irq" secure="Secure"/>
+                     <interrupt id="sdio_irq" secure="Secure"/>
+                     <interrupt id="sdma0_irq" secure="Secure"/>
+                     <interrupt id="sdma1_irq" secure="Secure"/>
+                     <interrupt id="sec_hypervisor_call_irq" secure="Secure"/>
+                     <interrupt id="sec_int0" secure="Secure"/>
+                     <interrupt id="sec_int1" secure="Secure"/>
+                     <interrupt id="sec_vio_irq" secure="Secure"/>
+                     <interrupt id="sha_irq" secure="Secure"/>
+                     <interrupt id="sys_irq" secure="Secure"/>
+                     <interrupt id="usb0_irq" secure="Secure"/>
+                     <interrupt id="usb0_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_irq" secure="Secure"/>
+                     <interrupt id="usb1_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_utmi_irq" secure="Secure"/>
+                     <interrupt id="utick_irq" secure="Secure"/>
+                  </security>
+               </interrupts>
+               <ports>
+                  <port id="pio0">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+                  <port id="pio1">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+               </ports>
+            </ahb>
+            <saus>
+               <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false">
+                  <region start="0" size="268435456" security="ns" enabled="true" index="0"/>
+                  <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="2"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="3"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="4"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="5"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="6"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="7"/>
+               </sau>
+            </saus>
+            <global_options>
+               <option id="AIRCR_PRIS" value="no"/>
+               <option id="AIRCR_BFHFNMINS" value="no"/>
+               <option id="AIRCR_SYSRESETREQS" value="no"/>
+               <option id="SCR_SLEEPDEEPS" value="no"/>
+               <option id="SHCSR_SECUREFAULTENA" value="no"/>
+               <option id="CPACR_CP0" value="3"/>
+               <option id="CPACR_CP1" value="3"/>
+               <option id="CPACR_CP2" value="0"/>
+               <option id="CPACR_CP3" value="0"/>
+               <option id="CPACR_CP4" value="0"/>
+               <option id="CPACR_CP5" value="0"/>
+               <option id="CPACR_CP6" value="0"/>
+               <option id="CPACR_CP7" value="0"/>
+               <option id="CPACR_CP10" value="3"/>
+               <option id="CPACR_CP11" value="3"/>
+               <option id="NSACR_CP0" value="yes"/>
+               <option id="NSACR_CP1" value="yes"/>
+               <option id="NSACR_CP2" value="no"/>
+               <option id="NSACR_CP3" value="no"/>
+               <option id="NSACR_CP4" value="no"/>
+               <option id="NSACR_CP5" value="no"/>
+               <option id="NSACR_CP6" value="no"/>
+               <option id="NSACR_CP7" value="no"/>
+               <option id="NSACR_CP10" value="yes"/>
+               <option id="NSACR_CP11" value="yes"/>
+               <option id="CPPWR_SU0" value="no"/>
+               <option id="CPPWR_SUS0" value="no"/>
+               <option id="CPPWR_SU1" value="no"/>
+               <option id="CPPWR_SUS1" value="no"/>
+               <option id="CPPWR_SU2" value="no"/>
+               <option id="CPPWR_SUS2" value="no"/>
+               <option id="CPPWR_SU3" value="no"/>
+               <option id="CPPWR_SUS3" value="no"/>
+               <option id="CPPWR_SU4" value="no"/>
+               <option id="CPPWR_SUS4" value="no"/>
+               <option id="CPPWR_SU5" value="no"/>
+               <option id="CPPWR_SUS5" value="no"/>
+               <option id="CPPWR_SU6" value="no"/>
+               <option id="CPPWR_SUS6" value="no"/>
+               <option id="CPPWR_SU7" value="no"/>
+               <option id="CPPWR_SUS7" value="no"/>
+               <option id="CPPWR_SU10" value="no"/>
+               <option id="CPPWR_SUS10" value="no"/>
+               <option id="CPPWR_SU11" value="no"/>
+               <option id="CPPWR_SUS11" value="no"/>
+               <option id="SEC_GPIO_MASK0_LOCK" value="no"/>
+               <option id="SEC_GPIO_MASK1_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
+               <option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
+               <option id="CPU0_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU0_LOCK_NS_MPU" value="no"/>
+               <option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
+               <option id="CPU0_LOCK_S_MPU" value="no"/>
+               <option id="CPU0_LOCK_SAU" value="no"/>
+               <option id="CPU0_LOCK_REG_LOCK" value="no"/>
+               <option id="CPU1_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU1_LOCK_NS_MPU" value="no"/>
+               <option id="CPU1_LOCK_REG_LOCK" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/>
+            </global_options>
+            <mpus>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+            </mpus>
+         </functional_group>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index f46775b27..59f7d6329 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -2,9 +2,15 @@ set(MCU_VARIANT LPC55S69)
 set(MCU_CORE LPC55S69_cm33_core0)
 
 set(JLINK_DEVICE LPC55S69_M33_0)
+set(JLINK_OPTION "-USB 000727648789")
+
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
+# device highspeed, host fullspeed
+set(RHPORT_DEVICE 1)
+set(RHPORT_HOST 0)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
index e18d5bbad..3b81411a1 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h
@@ -36,20 +36,18 @@
  extern "C" {
 #endif
 
-// LED
-#define LED_PORT              1
-#define LED_PIN               6
+// LED: use red LED from generated pin_mux
+#define LED_PORT              BOARD_INITLEDSPINS_LED_RED_PORT
+#define LED_PIN               BOARD_INITLEDSPINS_LED_RED_PIN
 #define LED_STATE_ON          0
 
-// WAKE button
-#define BUTTON_PORT           1
-#define BUTTON_PIN            18
+// WAKE button: use S2 from generated pin_mux
+#define BUTTON_PORT           BOARD_INITBUTTONSPINS_S2_PORT
+#define BUTTON_PIN            BOARD_INITBUTTONSPINS_S2_PIN
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
 
 // XTAL
 #define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk
index 73edc88a9..e92c46f05 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk
@@ -1,9 +1,19 @@
 MCU_VARIANT = LPC55S69
 MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
+
+# device highspeed, host fullspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
 
 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0
 
+SRC_C += \
+	$(TOP)/$(BOARD_PATH)/board/clock_config.c \
+	$(TOP)/$(BOARD_PATH)/board/pin_mux.c \
+	$(TOP)/$(BOARD_PATH)/board/peripherals.c
+
+INC += $(TOP)/$(BOARD_PATH)/board
+
 JLINK_DEVICE = LPC55S69
 PYOCD_TARGET = LPC55S69
 
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c
new file mode 100644
index 000000000..99a738f18
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v18.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FXCOM0_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 144 MHz}
+- {id: USB0_clock.outFreq, value: 48 MHz}
+- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_PLL_USB_OUT, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV}
+- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0DIV.scale, value: '2'}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '18'}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2'}
+- {id: SYSCON.USB0CLKDIV.scale, value: '3'}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */
+
+    POWER_SetVoltageForFreq(144000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(144000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(18U),
+        .pllRate = 144000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #endif
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);               /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false);         /*!< Set USB0CLKDIV divider to value 3 */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+    CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK);                 /*!< Switch USB0_CLK to MAIN_CLK */
+    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to PLL0_DIV */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h
new file mode 100644
index 000000000..9112ede78
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK          0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK            0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK           0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK           0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK           0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK           0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK           0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK            0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK            0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK            0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK            0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK            0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK            0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK            0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK            0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK            0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK              0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK          0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK      0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK          0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK   0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK            0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK           0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK               0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK              0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK          0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK          0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK            12000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK             0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK              0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK          0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK             0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK               0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK        0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK          0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK         0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK         0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK         0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK         0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK         0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK          0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK          0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK          0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK          0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK          0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK          0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK          0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK          0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK          0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK            0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK        0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK    0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK        0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK          0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK         0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK             0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK            0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK        0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK        0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK          96000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK           0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK            0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK        0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK           0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK             0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK           0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK           100000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK             0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK         0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         144000000U  /*!< Core clock frequency: 144000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK           48000000UL     /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK           144000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK             48000000UL     /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK         16000000UL     /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c
new file mode 100644
index 000000000..890a20fc6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+functionalGroups:
+- name: BOARD_InitPeripherals_cm33_core0
+  UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1
+  called_from_default_init: true
+  selectedCore: cm33_core0
+- name: BOARD_InitPeripherals_cm33_core1
+  UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48
+  selectedCore: cm33_core1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system'
+- global_system_definitions:
+  - user_definitions: ''
+  - user_includes: ''
+  - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals_cm33_core0 functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DEBUG_UART initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'DEBUG_UART'
+- type: 'flexcomm_usart'
+- mode: 'polling'
+- custom_name_enabled: 'true'
+- type_id: 'flexcomm_usart_2.2.0'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'FLEXCOMM0'
+- config_sets:
+  - usartConfig_t:
+    - usartConfig:
+      - clockSource: 'FXCOMFunctionClock'
+      - clockSourceFreq: 'ClocksTool_DefaultInit'
+      - baudRate_Bps: '115200'
+      - syncMode: 'kUSART_SyncModeDisabled'
+      - parityMode: 'kUSART_ParityDisabled'
+      - stopBitCount: 'kUSART_OneStopBit'
+      - bitCountPerChar: 'kUSART_8BitsPerChar'
+      - loopback: 'false'
+      - txWatermark: 'kUSART_TxFifo0'
+      - rxWatermark: 'kUSART_RxFifo1'
+      - enableRx: 'true'
+      - enableTx: 'true'
+      - clockPolarity: 'kUSART_RxSampleOnFallingEdge'
+      - enableContinuousSCLK: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const usart_config_t DEBUG_UART_config = {
+  .baudRate_Bps = 115200UL,
+  .syncMode = kUSART_SyncModeDisabled,
+  .parityMode = kUSART_ParityDisabled,
+  .stopBitCount = kUSART_OneStopBit,
+  .bitCountPerChar = kUSART_8BitsPerChar,
+  .loopback = false,
+  .txWatermark = kUSART_TxFifo0,
+  .rxWatermark = kUSART_RxFifo1,
+  .enableRx = true,
+  .enableTx = true,
+  .enableMode32k = false,
+  .clockPolarity = kUSART_RxSampleOnFallingEdge,
+  .enableContinuousSCLK = false
+};
+
+static void DEBUG_UART_init(void) {
+  /* Reset FLEXCOMM device */
+  RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+  USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'NVIC'
+- config_sets:
+  - nvic:
+    - interrupt_table: []
+    - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals_cm33_core0(void)
+{
+  /* Initialize components */
+  DEBUG_UART_init();
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals_cm33_core0();
+}
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h
new file mode 100644
index 000000000..fc4d72c33
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_usart.h"
+#include "fsl_clock.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */
+/* Definition of peripheral ID */
+#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0)
+/* Definition of the clock source frequency */
+#define DEBUG_UART_CLOCK_SOURCE 48000000UL
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+extern const usart_config_t DEBUG_UART_config;
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals_cm33_core0(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c
new file mode 100644
index 000000000..979e7d065
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c
@@ -0,0 +1,860 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitDEBUG_UARTPins();
+    BOARD_InitUSBPins();
+    BOARD_InitLEDsPins();
+    BOARD_InitBUTTONsPins();
+    BOARD_InitPins_Core0();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitDEBUG_UARTPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX);
+
+    const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSWD_DEBUGPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSWD_DEBUGPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitSWD_DEBUGPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */
+                                    IOCON_PIO_FUNC6 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI |
+                                    /* Analog switch is open (disabled) */
+                                    IOCON_PIO_ASW_DI);
+    /* PORT0 PIN10 (coords: 21) is configured as SWO */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO);
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled) */
+                                           IOCON_PIO_ASW_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled), only for A0 version */
+                                           IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled) */
+                                          IOCON_PIO_ASW_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled), only for A0 version */
+                                          IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSBPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP}
+  - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM}
+  - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
+  - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
+  - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
+  - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp}
+  - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28,
+    mode: pullUp}
+  - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp}
+  - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSBPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitUSBPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */
+                                IOCON_PIO_FUNC7 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS);
+
+    IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][12] = ((IOCON->PIO[1][12] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][29] = ((IOCON->PIO[1][29] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][30] = ((IOCON->PIO[1][30] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true',
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitLEDsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t LED_BLUE_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_4 (pin 1)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
+
+    gpio_pin_config_t LED_RED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_6 (pin 5)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
+
+    gpio_pin_config_t LED_GREEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO1_7 (pin 9)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
+
+    const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */
+                               IOCON_PIO_FUNC0 |
+                               /* Selects pull-up function */
+                               IOCON_PIO_MODE_PULLUP |
+                               /* Standard mode, output slew rate control is enabled */
+                               IOCON_PIO_SLEW_STANDARD |
+                               /* Input function is not inverted */
+                               IOCON_PIO_INV_DI |
+                               /* Enables digital function */
+                               IOCON_PIO_DIGITAL_EN |
+                               /* Open drain is disabled */
+                               IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE);
+
+    const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */
+                              IOCON_PIO_FUNC0 |
+                              /* Selects pull-up function */
+                              IOCON_PIO_MODE_PULLUP |
+                              /* Standard mode, output slew rate control is enabled */
+                              IOCON_PIO_SLEW_STANDARD |
+                              /* Input function is not inverted */
+                              IOCON_PIO_INV_DI |
+                              /* Enables digital function */
+                              IOCON_PIO_DIGITAL_EN |
+                              /* Open drain is disabled */
+                              IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED);
+
+    const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */
+                                IOCON_PIO_FUNC0 |
+                                /* Selects pull-up function */
+                                IOCON_PIO_MODE_PULLUP |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBUTTONsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBUTTONsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitBUTTONsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t S1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_5 (pin 88)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config);
+
+    gpio_pin_config_t S3_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_9 (pin 10)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config);
+
+    gpio_pin_config_t S2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_18 (pin 64)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config);
+
+    const uint32_t S1 = (/* Pin is configured as PIO0_5 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1);
+
+    const uint32_t S2 = (/* Pin is configured as PIO1_18 */
+                         IOCON_PIO_FUNC0 |
+                         /* Selects pull-up function */
+                         IOCON_PIO_MODE_PULLUP |
+                         /* Standard mode, output slew rate control is enabled */
+                         IOCON_PIO_SLEW_STANDARD |
+                         /* Input function is not inverted */
+                         IOCON_PIO_INV_DI |
+                         /* Enables digital function */
+                         IOCON_PIO_DIGITAL_EN |
+                         /* Open drain is disabled */
+                         IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2);
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t S3 = (/* Pin is configured as PIO1_9 */
+                             IOCON_PIO_FUNC0 |
+                             /* Selects pull-up function */
+                             IOCON_PIO_MODE_PULLUP |
+                             /* Standard mode, output slew rate control is enabled */
+                             IOCON_PIO_SLEW_STANDARD |
+                             /* Input function is not inverted */
+                             IOCON_PIO_INV_DI |
+                             /* Enables digital function */
+                             IOCON_PIO_DIGITAL_EN |
+                             /* Open drain is disabled */
+                             IOCON_PIO_OPENDRAIN_DI |
+                             /* Analog switch is closed (enabled) */
+                             IOCON_PIO_ASW_EN);
+        /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */
+        IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3);
+    }
+    else
+    {
+        const uint32_t S3 = (/* Pin is configured as PIO1_9 */
+                             IOCON_PIO_FUNC0 |
+                             /* Selects pull-up function */
+                             IOCON_PIO_MODE_PULLUP |
+                             /* Standard mode, output slew rate control is enabled */
+                             IOCON_PIO_SLEW_STANDARD |
+                             /* Input function is not inverted */
+                             IOCON_PIO_INV_DI |
+                             /* Enables digital function */
+                             IOCON_PIO_DIGITAL_EN |
+                             /* Open drain is disabled */
+                             IOCON_PIO_OPENDRAIN_DI |
+                             /* Analog switch is closed (enabled), only for A0 version */
+                             IOCON_PIO_ASW_DIS_EN);
+        /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */
+        IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3);
+    }
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins_Core0:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins_Core0
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins_Core0(void)
+{
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitI2SPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled,
+    open_drain: disabled}
+  - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1,
+    identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitI2SPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitI2SPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */
+                                  IOCON_PIO_FUNC1 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI |
+                                  /* Analog switch is closed (enabled) */
+                                  IOCON_PIO_ASW_EN);
+    /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK);
+
+    const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS);
+
+    const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX);
+
+    const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */
+                                  IOCON_PIO_FUNC7 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK);
+
+    const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX);
+
+    const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+
+    const uint32_t MCLK = (/* Pin is configured as MCLK */
+                           IOCON_PIO_FUNC1 |
+                           /* No addition pin function */
+                           IOCON_PIO_MODE_INACT |
+                           /* Standard mode, output slew rate control is enabled */
+                           IOCON_PIO_SLEW_STANDARD |
+                           /* Input function is not inverted */
+                           IOCON_PIO_INV_DI |
+                           /* Enables digital function */
+                           IOCON_PIO_DIGITAL_EN |
+                           /* Open drain is disabled */
+                           IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN31 (coords: 91) is configured as MCLK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCELPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCELPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitACCELPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t ACCL_INTR_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_19 (pin 58)  */
+    GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config);
+
+    const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */
+                                IOCON_PIO_FUNC0 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI |
+                                /* Analog switch is open (disabled) */
+                                IOCON_PIO_ASW_DI);
+    /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h
new file mode 100644
index 000000000..3925c937a
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U)
+/* @} */
+
+/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_ASW_DIS_EN 0x00u    /*!<@brief Analog switch is closed (enabled), only for A0 version */
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC6 0x06u         /*!<@brief Selects pin function 6 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U)
+/* @} */
+
+/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U)
+/* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Enables digital function */
+#define IOCON_PIO_DIGITAL_EN 0x0100u
+/*!
+ * @brief Selects pin function 7 */
+#define IOCON_PIO_FUNC7 0x07u
+/*!
+ * @brief Input function is not inverted */
+#define IOCON_PIO_INV_DI 0x00u
+/*!
+ * @brief No addition pin function */
+#define IOCON_PIO_MODE_INACT 0x00u
+/*!
+ * @brief Open drain is disabled */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u
+/*!
+ * @brief Standard mode, output slew rate control is enabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_28_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 7. */
+#define PIO0_28_FUNC_ALT7 0x07u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_28_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_12_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_12_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_12_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_29_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_29_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_29_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_30_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_30_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_30_MODE_PULL_UP 0x02u
+
+/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS
+  @{ */
+#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U                   /*!<@brief PORT pin number */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U)      /*!<@brief PORT pin mask */
+                                                             /* @} */
+
+/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_RED_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_RED_PIN 6U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U)      /*!<@brief PORT pin mask */
+                                                            /* @} */
+
+/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DIS_EN 0x00u    /*!<@brief Analog switch is closed (enabled), only for A0 version */
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S1_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S1_PIN 5U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S2_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S2_PIN 18U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U)      /*!<@brief PORT pin mask */
+                                                           /* @} */
+
+/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_S3_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_S3_PIN 9U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U)      /*!<@brief PORT pin mask */
+                                                          /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC2 0x02u         /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_FUNC7 0x07u         /*!<@brief Selects pin function 7 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO
+  @{ */
+#define BOARD_INITI2SPINS_MCLK_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_MCLK_PIN 31U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
+#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake
index fd7cb6de6..bbaaf6648 100644
--- a/hw/bsp/lpc55/boards/mcu_link/board.cmake
+++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake
@@ -7,8 +7,6 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
-    CPU_LPC55S69JBD100_cm33_core0
-    # port 1 is highspeed
-    # BOARD_TUD_RHPORT=1
+    CPU_LPC55S69JBD64_cm33_core0
     )
 endfunction()
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h
index 1d71b3e79..d3c133f40 100644
--- a/hw/bsp/lpc55/boards/mcu_link/board.h
+++ b/hw/bsp/lpc55/boards/mcu_link/board.h
@@ -37,19 +37,17 @@
 #endif
 
 // LED
-#define LED_PORT              0
-#define LED_PIN               5
+#define LED_PORT              BOARD_INITLEDSPINS_LED_PORT
+#define LED_PIN               BOARD_INITLEDSPINS_LED_PIN
 #define LED_STATE_ON          0
 
 // WAKE button (Dummy, use unused pin
-#define BUTTON_PORT           0
-#define BUTTON_PIN            30
+#define BUTTON_PORT           BOARD_INITBUTTONSPINS_BUTTON_PORT
+#define BUTTON_PIN            BOARD_INITBUTTONSPINS_BUTTON_PIN
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_DEV              USART0
-#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
 
 // XTAL
 #define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.mk b/hw/bsp/lpc55/boards/mcu_link/board.mk
index ceb1d0ebc..4f686a88f 100644
--- a/hw/bsp/lpc55/boards/mcu_link/board.mk
+++ b/hw/bsp/lpc55/boards/mcu_link/board.mk
@@ -1,9 +1,16 @@
 MCU_VARIANT = LPC55S69
 MCU_CORE = LPC55S69_cm33_core0
-PORT ?= 1
+RHPORT_DEVICE ?= 1
 
 CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0
 
+SRC_C += \
+	$(TOP)/$(BOARD_PATH)/board/clock_config.c \
+	$(TOP)/$(BOARD_PATH)/board/pin_mux.c \
+	$(TOP)/$(BOARD_PATH)/board/peripherals.c
+
+INC += $(TOP)/$(BOARD_PATH)/board
+
 JLINK_DEVICE = LPC55S69
 PYOCD_TARGET = LPC55S69
 
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c
new file mode 100644
index 000000000..99a738f18
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v18.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: System_clock.outFreq, value: 100 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: FXCOM0_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 144 MHz}
+- {id: USB0_clock.outFreq, value: 48 MHz}
+- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: PLL1_Mode, value: Normal}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_PLL_USB_OUT, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV}
+- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0DIV.scale, value: '2'}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL1M_MULT.scale, value: '18'}
+- {id: SYSCON.PLL1_PDEC.scale, value: '2'}
+- {id: SYSCON.USB0CLKDIV.scale, value: '3'}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB}
+sources:
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */
+
+    POWER_SetVoltageForFreq(144000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(144000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up PLL1 */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U),
+        .pllndec = SYSCON_PLL1NDEC_NDIV(1U),
+        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
+        .pllmdec = SYSCON_PLL1MDEC_MDIV(18U),
+        .pllRate = 144000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */
+
+    /*!< Set up dividers */
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
+    #endif
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);               /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false);         /*!< Set USB0CLKDIV divider to value 3 */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+    CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK);                 /*!< Switch USB0_CLK to MAIN_CLK */
+    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to PLL0_DIV */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+#endif
+}
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h
new file mode 100644
index 000000000..9112ede78
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK          0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK            0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK           0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK           0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK           0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK           0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK           0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK            0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK            0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK            0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK            0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK            0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK            0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK            0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK            0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK            0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK              0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK          0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK      0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK          0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK   0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK            0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK           0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK               0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK              0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK          0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK          0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK            12000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK             0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK              0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK          0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK             0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK               0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK         96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK        0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK          0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK         0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK         0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK         0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK         0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK         0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK          0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK          0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK          0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK          0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK          0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK          0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK          0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK          0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK          0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK            0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK        0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK    0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK        0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL           /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK          0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK         0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK             0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK            0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK        0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK        0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK          96000000UL     /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK           0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK            0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK        0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK           0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK             0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK           0UL            /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK           100000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK             0UL            /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK         0UL            /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         144000000U  /*!< Core clock frequency: 144000000Hz */
+
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK         0UL            /* Clock consumers of ASYNCADC_clock output : ADC0 */
+#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK           0UL            /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK          0UL            /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK          0UL            /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK          0UL            /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK          0UL            /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK          0UL            /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK           48000000UL     /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK           0UL            /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK           0UL            /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK           0UL            /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK           0UL            /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK           0UL            /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK           0UL            /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */
+#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK           0UL            /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */
+#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK           0UL            /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */
+#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK             0UL            /* Clock consumers of MCLK_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK         0UL            /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK     0UL            /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */
+#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK         0UL            /* Clock consumers of PLUCLKIN_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL            /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK  0UL            /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */
+#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK           0UL            /* Clock consumers of RTC1HZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK          0UL            /* Clock consumers of RTC1KHZ_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK              0UL            /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK             0UL            /* Clock consumers of SDIO_clock output : SDIF */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK         0UL            /* Clock consumers of SYSTICK0_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK         0UL            /* Clock consumers of SYSTICK1_clock output : N/A */
+#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK           144000000UL    /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */
+#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK            0UL            /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK             48000000UL     /* Clock consumers of USB0_clock output : USB0, USBFSH */
+#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK         16000000UL     /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */
+#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK            0UL            /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK              0UL            /* Clock consumers of WDT_clock output : WWDT */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c
new file mode 100644
index 000000000..890a20fc6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+functionalGroups:
+- name: BOARD_InitPeripherals_cm33_core0
+  UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1
+  called_from_default_init: true
+  selectedCore: cm33_core0
+- name: BOARD_InitPeripherals_cm33_core1
+  UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48
+  selectedCore: cm33_core1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system'
+- global_system_definitions:
+  - user_definitions: ''
+  - user_includes: ''
+  - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+  - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals_cm33_core0 functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * DEBUG_UART initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'DEBUG_UART'
+- type: 'flexcomm_usart'
+- mode: 'polling'
+- custom_name_enabled: 'true'
+- type_id: 'flexcomm_usart_2.2.0'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'FLEXCOMM0'
+- config_sets:
+  - usartConfig_t:
+    - usartConfig:
+      - clockSource: 'FXCOMFunctionClock'
+      - clockSourceFreq: 'ClocksTool_DefaultInit'
+      - baudRate_Bps: '115200'
+      - syncMode: 'kUSART_SyncModeDisabled'
+      - parityMode: 'kUSART_ParityDisabled'
+      - stopBitCount: 'kUSART_OneStopBit'
+      - bitCountPerChar: 'kUSART_8BitsPerChar'
+      - loopback: 'false'
+      - txWatermark: 'kUSART_TxFifo0'
+      - rxWatermark: 'kUSART_RxFifo1'
+      - enableRx: 'true'
+      - enableTx: 'true'
+      - clockPolarity: 'kUSART_RxSampleOnFallingEdge'
+      - enableContinuousSCLK: 'false'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+const usart_config_t DEBUG_UART_config = {
+  .baudRate_Bps = 115200UL,
+  .syncMode = kUSART_SyncModeDisabled,
+  .parityMode = kUSART_ParityDisabled,
+  .stopBitCount = kUSART_OneStopBit,
+  .bitCountPerChar = kUSART_8BitsPerChar,
+  .loopback = false,
+  .txWatermark = kUSART_TxFifo0,
+  .rxWatermark = kUSART_RxFifo1,
+  .enableRx = true,
+  .enableTx = true,
+  .enableMode32k = false,
+  .clockPolarity = kUSART_RxSampleOnFallingEdge,
+  .enableContinuousSCLK = false
+};
+
+static void DEBUG_UART_init(void) {
+  /* Reset FLEXCOMM device */
+  RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+  USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE);
+}
+
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals_cm33_core0'
+- peripheral: 'NVIC'
+- config_sets:
+  - nvic:
+    - interrupt_table: []
+    - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals_cm33_core0(void)
+{
+  /* Initialize components */
+  DEBUG_UART_init();
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals_cm33_core0();
+}
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h
new file mode 100644
index 000000000..fc4d72c33
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+#include "fsl_reset.h"
+#include "fsl_usart.h"
+#include "fsl_clock.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */
+/* Definition of peripheral ID */
+#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0)
+/* Definition of the clock source frequency */
+#define DEBUG_UART_CLOCK_SOURCE 48000000UL
+
+/***********************************************************************************************************************
+ * Global variables
+ **********************************************************************************************************************/
+extern const usart_config_t DEBUG_UART_config;
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals_cm33_core0(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c
new file mode 100644
index 000000000..a673302e5
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c
@@ -0,0 +1,839 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: LPC55S69
+package_id: LPC55S69JBD100
+mcu_data: ksdk2_0
+processor_version: 25.09.10
+board: LPCXpresso55S69
+expansion_headers:
+- id: lpc_style_arduino
+  name: LPCXpresso V3 (Arduino compatible)
+  connectors:
+  - id: C1
+    name: P16
+    pins:
+    - {id: 8, name: 3.3V, external_signal_types: power_supply_3.3V}
+    - {id: 10, name: RESET, pin_num: '32', pin_signal: RESETN}
+    - {id: 12, name: 3.3V, external_signal_types: power_supply_3.3V}
+    - {id: 14, name: 5V, external_signal_types: power_supply_5V}
+    - {id: 16, name: GND, external_signal_types: ground}
+    - {id: 18, name: GND, external_signal_types: ground}
+    - {id: 20, name: 5V, external_signal_types: power_supply_5V}
+  - id: C2
+    name: P17
+    pins:
+    - {id: 1, name: D15, pin_num: '4', pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2}
+    - {id: 3, name: D14, pin_num: '30', pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3}
+    - {id: 5, name: 3.3V, external_signal_types: power_supply_3.3V}
+    - {id: 6, pin_num: '93', pin_signal: PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS}
+    - {id: 7, name: GND, external_signal_types: ground}
+    - {id: 8, pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5}
+    - {id: 9, name: D13, pin_num: '61', pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5}
+    - {id: 10, pin_num: '74', pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS}
+    - {id: 11, name: D12, pin_num: '62', pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6}
+    - {id: 12, pin_num: '90', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19}
+    - {id: 13, name: D11, pin_num: '60', pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26}
+    - {id: 14, pin_num: '76', pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21}
+    - {id: 15, name: D10, pin_num: '59', pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4}
+    - {id: 16, pin_num: '85', pin_signal: PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4}
+    - {id: 17, name: D9, pin_num: '31', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0}
+    - {id: 18, pin_num: '73', pin_signal: PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3}
+    - {id: 19, name: D8, pin_num: '24', pin_signal: PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4}
+    - {id: 20, pin_num: '2', pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N}
+  - id: C3
+    name: P18
+    pins:
+    - {id: 1, name: D7, pin_num: '10', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12}
+    - {id: 2, pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1}
+    - {id: 3, name: D6, pin_num: '40', pin_signal: PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3}
+    - {id: 4, pin_num: '57', pin_signal: PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D}
+    - {id: 5, name: D5, pin_num: '1', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A}
+    - {id: 6, pin_num: '77', pin_signal: PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN}
+    - {id: 7, name: D4-LED_GREEN, pin_num: '9', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4}
+    - {id: 8, pin_num: '42', pin_signal: PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5}
+    - {id: 10, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6}
+    - {id: 11, name: D2, pin_num: '22', pin_signal: PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2}
+    - {id: 12, pin_num: '82', pin_signal: PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2}
+    - {id: 13, name: D1, pin_num: '27', pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27}
+    - {id: 14, pin_num: '58', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF}
+    - {id: 15, name: D0, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6}
+    - {id: 16, pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0}
+    - {id: 17, pin_num: '87', pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD}
+    - {id: 18, pin_num: '68', pin_signal: PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5}
+    - {id: 19, pin_num: '43', pin_signal: PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N}
+    - {id: 20, pin_num: '56', pin_signal: PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C}
+  - id: C4
+    name: P19
+    pins:
+    - {id: 2, name: A0, pin_num: '14', pin_signal: PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8}
+    - {id: 4, name: A1, pin_num: '20', pin_signal: PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0}
+    - {id: 6, name: A2, pin_num: '54', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A}
+    - {id: 7, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0}
+    - {id: 8, name: A3, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0}
+    - {id: 9, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13}
+    - {id: 10, name: A4, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13}
+    - {id: 11, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14}
+    - {id: 12, name: A5, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14}
+pin_labels:
+- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED_RED}
+- {pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: 'S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1',
+  identifier: LED}
+- {pin_num: '11', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, label: 'U20[2]/SD0_D3', identifier: BUTTON}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitDEBUG_UARTPins();
+    BOARD_InitUSBPins();
+    BOARD_InitLEDsPins();
+    BOARD_InitBUTTONsPins();
+    BOARD_InitPins_Core0();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitDEBUG_UARTPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX);
+
+    const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
+                                    IOCON_PIO_FUNC1 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSWD_DEBUGPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSWD_DEBUGPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitSWD_DEBUGPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */
+                                    IOCON_PIO_FUNC6 |
+                                    /* No addition pin function */
+                                    IOCON_PIO_MODE_INACT |
+                                    /* Standard mode, output slew rate control is enabled */
+                                    IOCON_PIO_SLEW_STANDARD |
+                                    /* Input function is not inverted */
+                                    IOCON_PIO_INV_DI |
+                                    /* Enables digital function */
+                                    IOCON_PIO_DIGITAL_EN |
+                                    /* Open drain is disabled */
+                                    IOCON_PIO_OPENDRAIN_DI |
+                                    /* Analog switch is open (disabled) */
+                                    IOCON_PIO_ASW_DI);
+    /* PORT0 PIN10 (coords: 21) is configured as SWO */
+    IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO);
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled) */
+                                           IOCON_PIO_ASW_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */
+                                           IOCON_PIO_FUNC6 |
+                                           /* Selects pull-down function */
+                                           IOCON_PIO_MODE_PULLDOWN |
+                                           /* Standard mode, output slew rate control is enabled */
+                                           IOCON_PIO_SLEW_STANDARD |
+                                           /* Input function is not inverted */
+                                           IOCON_PIO_INV_DI |
+                                           /* Enables digital function */
+                                           IOCON_PIO_DIGITAL_EN |
+                                           /* Open drain is disabled */
+                                           IOCON_PIO_OPENDRAIN_DI |
+                                           /* Analog switch is closed (enabled), only for A0 version */
+                                           IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN11 (coords: 13) is configured as SWCLK */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK);
+    }
+
+    if (Chip_GetVersion()==1)
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled) */
+                                          IOCON_PIO_ASW_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+    else
+    {
+        const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */
+                                          IOCON_PIO_FUNC6 |
+                                          /* Selects pull-up function */
+                                          IOCON_PIO_MODE_PULLUP |
+                                          /* Standard mode, output slew rate control is enabled */
+                                          IOCON_PIO_SLEW_STANDARD |
+                                          /* Input function is not inverted */
+                                          IOCON_PIO_INV_DI |
+                                          /* Enables digital function */
+                                          IOCON_PIO_DIGITAL_EN |
+                                          /* Open drain is disabled */
+                                          IOCON_PIO_OPENDRAIN_DI |
+                                          /* Analog switch is closed (enabled), only for A0 version */
+                                          IOCON_PIO_ASW_DIS_EN);
+        /* PORT0 PIN12 (coords: 12) is configured as SWDIO */
+        IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO);
+    }
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSBPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP}
+  - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM}
+  - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22,
+    mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
+  - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
+  - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
+  - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp}
+  - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28,
+    mode: pullUp}
+  - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp}
+  - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSBPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitUSBPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */
+                                IOCON_PIO_FUNC7 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS);
+
+    IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][12] = ((IOCON->PIO[1][12] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][29] = ((IOCON->PIO[1][29] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */
+                         | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][30] = ((IOCON->PIO[1][30] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */
+                         | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4)
+
+                         /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                          * : Pull-up.
+                          * Pull-up resistor enabled. */
+                         | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT,
+    gpio_init_state: 'true', mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitLEDsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    gpio_pin_config_t LED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO0_5 (pin 88)  */
+    GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config);
+
+    IOCON->PIO[0][5] = ((IOCON->PIO[0][5] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT05 (pin 88) is configured as PIO0_5. */
+                        | IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0)
+
+                        /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                         * : Pull-up.
+                         * Pull-up resistor enabled. */
+                        | IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL));
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBUTTONsPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN}
+  - {pin_num: '11', peripheral: GPIO, signal: 'PIO1, 0', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, direction: INPUT, mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBUTTONsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitBUTTONsPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t BUTTON_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_0 (pin 11)  */
+    GPIO_PinInit(BOARD_INITBUTTONSPINS_BUTTON_GPIO, BOARD_INITBUTTONSPINS_BUTTON_PORT, BOARD_INITBUTTONSPINS_BUTTON_PIN, &BUTTON_config);
+
+    if (Chip_GetVersion()==1)
+    {
+        IOCON->PIO[1][0] = ((IOCON->PIO[1][0] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT10 (pin 11) is configured as PIO1_0. */
+                        | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0)
+
+                        /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                         * : Pull-up.
+                         * Pull-up resistor enabled. */
+                        | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL));
+    }
+    else
+    {
+        IOCON->PIO[1][0] = ((IOCON->PIO[1][0] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT10 (pin 11) is configured as PIO1_0. */
+                        | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0)
+
+                        /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                         * : Pull-up.
+                         * Pull-up resistor enabled. */
+                        | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL));
+    }
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins_Core0:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins_Core0
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitPins_Core0(void)
+{
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitI2SPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled,
+    open_drain: disabled}
+  - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1,
+    identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled}
+  - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N,
+    mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitI2SPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitI2SPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */
+                                  IOCON_PIO_FUNC1 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI |
+                                  /* Analog switch is closed (enabled) */
+                                  IOCON_PIO_ASW_EN);
+    /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK);
+
+    const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS);
+
+    const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC7 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX);
+
+    const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */
+                                  IOCON_PIO_FUNC7 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK);
+
+    const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX);
+
+    const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */
+                                 IOCON_PIO_FUNC2 |
+                                 /* Selects pull-up function */
+                                 IOCON_PIO_MODE_PULLUP |
+                                 /* Standard mode, output slew rate control is enabled */
+                                 IOCON_PIO_SLEW_STANDARD |
+                                 /* Input function is not inverted */
+                                 IOCON_PIO_INV_DI |
+                                 /* Enables digital function */
+                                 IOCON_PIO_DIGITAL_EN |
+                                 /* Open drain is disabled */
+                                 IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+
+    const uint32_t MCLK = (/* Pin is configured as MCLK */
+                           IOCON_PIO_FUNC1 |
+                           /* No addition pin function */
+                           IOCON_PIO_MODE_INACT |
+                           /* Standard mode, output slew rate control is enabled */
+                           IOCON_PIO_SLEW_STANDARD |
+                           /* Input function is not inverted */
+                           IOCON_PIO_INV_DI |
+                           /* Enables digital function */
+                           IOCON_PIO_DIGITAL_EN |
+                           /* Open drain is disabled */
+                           IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN31 (coords: 91) is configured as MCLK */
+    IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK);
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCELPins:
+- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp,
+    slew_rate: standard, invert: disabled, open_drain: disabled}
+  - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard,
+    invert: disabled, open_drain: disabled}
+  - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive,
+    slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCELPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitACCELPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO1 module */
+    CLOCK_EnableClock(kCLOCK_Gpio1);
+
+    gpio_pin_config_t ACCL_INTR_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO1_19 (pin 58)  */
+    GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config);
+
+    const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */
+                                IOCON_PIO_FUNC0 |
+                                /* No addition pin function */
+                                IOCON_PIO_MODE_INACT |
+                                /* Standard mode, output slew rate control is enabled */
+                                IOCON_PIO_SLEW_STANDARD |
+                                /* Input function is not inverted */
+                                IOCON_PIO_INV_DI |
+                                /* Enables digital function */
+                                IOCON_PIO_DIGITAL_EN |
+                                /* Open drain is disabled */
+                                IOCON_PIO_OPENDRAIN_DI |
+                                /* Analog switch is open (disabled) */
+                                IOCON_PIO_ASW_DI);
+    /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR);
+
+    const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL);
+
+    const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */
+                                  IOCON_PIO_FUNC5 |
+                                  /* Selects pull-up function */
+                                  IOCON_PIO_MODE_PULLUP |
+                                  /* Standard mode, output slew rate control is enabled */
+                                  IOCON_PIO_SLEW_STANDARD |
+                                  /* Input function is not inverted */
+                                  IOCON_PIO_INV_DI |
+                                  /* Enables digital function */
+                                  IOCON_PIO_DIGITAL_EN |
+                                  /* Open drain is disabled */
+                                  IOCON_PIO_OPENDRAIN_DI);
+    /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
+    IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h
new file mode 100644
index 000000000..3e14d6baf
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h
@@ -0,0 +1,393 @@
+/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U)
+/* @} */
+
+/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_ASW_DIS_EN 0x00u    /*!<@brief Analog switch is closed (enabled), only for A0 version */
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC6 0x06u         /*!<@brief Selects pin function 6 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U)
+/* @} */
+
+/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U)
+/* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+/*!
+ * @brief PORT peripheral base pointer */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U
+/*!
+ * @brief PORT pin number */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U
+/*!
+ * @brief PORT pin mask */
+#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U)
+/* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Enables digital function */
+#define IOCON_PIO_DIGITAL_EN 0x0100u
+/*!
+ * @brief Selects pin function 7 */
+#define IOCON_PIO_FUNC7 0x07u
+/*!
+ * @brief Input function is not inverted */
+#define IOCON_PIO_INV_DI 0x00u
+/*!
+ * @brief No addition pin function */
+#define IOCON_PIO_MODE_INACT 0x00u
+/*!
+ * @brief Open drain is disabled */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u
+/*!
+ * @brief Standard mode, output slew rate control is enabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_28_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 7. */
+#define PIO0_28_FUNC_ALT7 0x07u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_28_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_12_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_12_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_12_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_29_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_29_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_29_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_30_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 4. */
+#define PIO1_30_FUNC_ALT4 0x04u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_30_MODE_PULL_UP 0x02u
+
+/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS
+  @{ */
+#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U                   /*!<@brief PORT pin number */
+#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_5_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_5_FUNC_ALT0 0x00u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_5_MODE_PULL_UP 0x02u
+
+/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITLEDSPINS_LED_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 1U       /*!<@brief GPIO output initial state */
+#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define BOARD_INITLEDSPINS_LED_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITLEDSPINS_LED_PIN 5U                   /*!<@brief PORT pin number */
+#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                                        /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_0_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO1_0_FUNC_ALT0 0x00u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO1_0_MODE_PULL_UP 0x02u
+
+/*! @name PIO1_0 (number 11), U20[2]/SD0_D3
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITBUTTONSPINS_BUTTON_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */
+#define BOARD_INITBUTTONSPINS_BUTTON_PORT 1U                  /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITBUTTONSPINS_BUTTON_PIN 0U                   /*!<@brief PORT pin number */
+#define BOARD_INITBUTTONSPINS_BUTTON_PIN_MASK (1U << 0U)      /*!<@brief PORT pin mask */
+                                                              /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_EN 0x0400u      /*!<@brief Analog switch is closed (enabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC1 0x01u         /*!<@brief Selects pin function 1 */
+#define IOCON_PIO_FUNC2 0x02u         /*!<@brief Selects pin function 2 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_FUNC7 0x07u         /*!<@brief Selects pin function 7 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO
+  @{ */
+#define BOARD_INITI2SPINS_MCLK_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_MCLK_PIN 31U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U)      /*!<@brief PORT pin mask */
+                                                         /* @} */
+
+/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS
+  @{ */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN
+  @{ */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U                   /*!<@brief PORT pin number */
+#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U)      /*!<@brief PORT pin mask */
+                                                               /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#define IOCON_PIO_ASW_DI 0x00u        /*!<@brief Analog switch is open (disabled) */
+#define IOCON_PIO_DIGITAL_EN 0x0100u  /*!<@brief Enables digital function */
+#define IOCON_PIO_FUNC0 0x00u         /*!<@brief Selects pin function 0 */
+#define IOCON_PIO_FUNC5 0x05u         /*!<@brief Selects pin function 5 */
+#define IOCON_PIO_INV_DI 0x00u        /*!<@brief Input function is not inverted */
+#define IOCON_PIO_MODE_INACT 0x00u    /*!<@brief No addition pin function */
+#define IOCON_PIO_MODE_PULLUP 0x20u   /*!<@brief Selects pull-up function */
+#define IOCON_PIO_OPENDRAIN_DI 0x00u  /*!<@brief Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */
+
+/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD
+  @{ */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U)      /*!<@brief PORT pin mask */
+                                                                  /* @} */
+
+/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
+#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U                   /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U                   /*!<@brief PORT pin number */
+#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                                                /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex
new file mode 100644
index 000000000..c78dba808
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex
@@ -0,0 +1,1354 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>LPC55S69</processor>
+      <package>LPC55S69JBD100</package>
+      <board>LPCXpresso55S69</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33_core0">
+         <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
+         <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <custom_copyright>
+         <text>/*
+ * Copyright 2026 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+</text>
+         <enabled>true</enabled>
+      </custom_copyright>
+      <update_include_paths>true</update_include_paths>
+      <enable_parallel_routing>true</enable_parallel_routing>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="17.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>25.09.10</processor_version>
+            <pin_labels>
+               <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED_RED"/>
+               <pin_label pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5" label="S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1" identifier="LED"/>
+               <pin_label pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11" label="U20[2]/SD0_D3" identifier="BUTTON"/>
+            </pin_labels>
+            <expansion_headers>
+               <expansion_header id="lpc_style_arduino" name="LPCXpresso V3 (Arduino compatible)">
+                  <connectors>
+                     <connector id="C1" name="P16">
+                        <pins>
+                           <pin id="8" external_signal_types="power_supply_3.3V" name="3.3V"/>
+                           <pin id="10" pin_num="32" pin_signal="RESETN" name="RESET"/>
+                           <pin id="12" external_signal_types="power_supply_3.3V" name="3.3V"/>
+                           <pin id="14" external_signal_types="power_supply_5V" name="5V"/>
+                           <pin id="16" external_signal_types="ground" name="GND"/>
+                           <pin id="18" external_signal_types="ground" name="GND"/>
+                           <pin id="20" external_signal_types="power_supply_5V" name="5V"/>
+                        </pins>
+                     </connector>
+                     <connector id="C2" name="P17">
+                        <pins>
+                           <pin id="1" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2" name="D15"/>
+                           <pin id="3" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3" name="D14"/>
+                           <pin id="5" external_signal_types="power_supply_3.3V" name="3.3V"/>
+                           <pin id="6" pin_num="93" pin_signal="PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS"/>
+                           <pin id="7" external_signal_types="ground" name="GND"/>
+                           <pin id="8" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"/>
+                           <pin id="9" pin_num="61" pin_signal="PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5" name="D13"/>
+                           <pin id="10" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"/>
+                           <pin id="11" pin_num="62" pin_signal="PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6" name="D12"/>
+                           <pin id="12" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"/>
+                           <pin id="13" pin_num="60" pin_signal="PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26" name="D11"/>
+                           <pin id="14" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"/>
+                           <pin id="15" pin_num="59" pin_signal="PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4" name="D10"/>
+                           <pin id="16" pin_num="85" pin_signal="PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4"/>
+                           <pin id="17" pin_num="31" pin_signal="PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0" name="D9"/>
+                           <pin id="18" pin_num="73" pin_signal="PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3"/>
+                           <pin id="19" pin_num="24" pin_signal="PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4" name="D8"/>
+                           <pin id="20" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"/>
+                        </pins>
+                     </connector>
+                     <connector id="C3" name="P18">
+                        <pins>
+                           <pin id="1" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12" name="D7"/>
+                           <pin id="2" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1"/>
+                           <pin id="3" pin_num="40" pin_signal="PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3" name="D6"/>
+                           <pin id="4" pin_num="57" pin_signal="PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D"/>
+                           <pin id="5" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A" name="D5"/>
+                           <pin id="6" pin_num="77" pin_signal="PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN"/>
+                           <pin id="7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4" name="D4-LED_GREEN"/>
+                           <pin id="8" pin_num="42" pin_signal="PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5"/>
+                           <pin id="10" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6"/>
+                           <pin id="11" pin_num="22" pin_signal="PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2" name="D2"/>
+                           <pin id="12" pin_num="82" pin_signal="PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2"/>
+                           <pin id="13" pin_num="27" pin_signal="PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27" name="D1"/>
+                           <pin id="14" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"/>
+                           <pin id="15" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6" name="D0"/>
+                           <pin id="16" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"/>
+                           <pin id="17" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"/>
+                           <pin id="18" pin_num="68" pin_signal="PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5"/>
+                           <pin id="19" pin_num="43" pin_signal="PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N"/>
+                           <pin id="20" pin_num="56" pin_signal="PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C"/>
+                        </pins>
+                     </connector>
+                     <connector id="C4" name="P19">
+                        <pins>
+                           <pin id="2" pin_num="14" pin_signal="PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8" name="A0"/>
+                           <pin id="4" pin_num="20" pin_signal="PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0" name="A1"/>
+                           <pin id="6" pin_num="54" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A" name="A2"/>
+                           <pin id="7" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"/>
+                           <pin id="8" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0" name="A3"/>
+                           <pin id="9" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13"/>
+                           <pin id="10" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13" name="A4"/>
+                           <pin id="11" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14"/>
+                           <pin id="12" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14" name="A5"/>
+                        </pins>
+                     </connector>
+                  </connectors>
+               </expansion_header>
+            </expansion_headers>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSWD_DEBUGPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullDown"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DEBUG_SWD_SWO"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSBPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/>
+                  <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/>
+                  <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/>
+                  <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/>
+                  <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/>
+                  <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONsPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/>
+                  <pin peripheral="GPIO" signal="PIO1, 0" pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitPins_Core0">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitPins_Core1">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>cm33_core1</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitI2SPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0">
+                     <pin_features>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1">
+                     <pin_features>
+                        <pin_feature name="identifier" value="FC6_I2S_CLK"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="enabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitACCELPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2">
+                     <pin_features>
+                        <pin_feature name="mode" value="pullUp"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="standard"/>
+                        <pin_feature name="invert" value="disabled"/>
+                        <pin_feature name="open_drain" value="disabled"/>
+                        <pin_feature name="asw" value="disabled"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>25.09.10</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources/>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings/>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/>
+               </clock_settings>
+               <called_from_default_init>false</called_from_default_init>
+            </clock_configuration>
+            <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="PLL1_Mode" value="Normal" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/>
+                  <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/>
+                  <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/>
+                  <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/>
+                  <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/>
+                  <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.2.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data>true</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>25.09.10</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_i2c" quick_selection="QS_I2C_Master">
+                        <setting name="i2c_mode" value="kI2C_Master"/>
+                        <setting name="clockSource" value="FXCOMFunctionClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="i2c_master_config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="baudRate_Bps" value="100000"/>
+                           <setting name="enableTimeout" value="false"/>
+                           <setting name="timeout_Ms" value="35"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="usartConfig_t">
+                        <struct name="usartConfig">
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="syncMode" value="kUSART_SyncModeDisabled"/>
+                           <setting name="parityMode" value="kUSART_ParityDisabled"/>
+                           <setting name="stopBitCount" value="kUSART_OneStopBit"/>
+                           <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/>
+                           <setting name="loopback" value="false"/>
+                           <setting name="txWatermark" value="kUSART_TxFifo0"/>
+                           <setting name="rxWatermark" value="kUSART_RxFifo1"/>
+                           <setting name="enableRx" value="true"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/>
+                           <setting name="enableContinuousSCLK" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpc_gpio"/>
+                  </instance>
+                  <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+            <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+                  <setting name="global_init" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet">
+               <config_set_global name="global_enet"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="10.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+            <tool_options>
+               <option id="_output_type_" value="c_code"/>
+               <option id="_legacy_source_names_" value="yes"/>
+            </tool_options>
+         </tee_profile>
+         <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true">
+            <description></description>
+            <options/>
+            <ahb>
+               <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/>
+               <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/>
+               <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/>
+               <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/>
+               <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/>
+               <masters>
+                  <master id="HASH" security="ns_user"/>
+                  <master id="MCM33C" security="ns_user"/>
+                  <master id="MCM33S" security="ns_user"/>
+                  <master id="PQ" security="ns_user"/>
+                  <master id="SDIO" security="ns_user"/>
+                  <master id="SDMA0" security="ns_user"/>
+                  <master id="SDMA1" security="ns_user"/>
+                  <master id="USBFSD" security="ns_user"/>
+                  <master id="USBFSH" security="ns_user"/>
+               </masters>
+               <peripherals>
+                  <peripheral id="ADC0" security="s_priv"/>
+                  <peripheral id="AHB_SECURE_CTRL" security="s_priv"/>
+                  <peripheral id="ANACTRL" security="s_priv"/>
+                  <peripheral id="CASPER" security="s_priv"/>
+                  <peripheral id="CRC_ENGINE" security="s_priv"/>
+                  <peripheral id="CTIMER0" security="s_priv"/>
+                  <peripheral id="CTIMER1" security="s_priv"/>
+                  <peripheral id="CTIMER2" security="s_priv"/>
+                  <peripheral id="CTIMER3" security="s_priv"/>
+                  <peripheral id="CTIMER4" security="s_priv"/>
+                  <peripheral id="DBGMAILBOX" security="s_priv"/>
+                  <peripheral id="DMA0" security="s_priv"/>
+                  <peripheral id="DMA1" security="s_priv"/>
+                  <peripheral id="FLASH" security="s_priv"/>
+                  <peripheral id="FLEXCOMM0" security="s_priv"/>
+                  <peripheral id="FLEXCOMM1" security="s_priv"/>
+                  <peripheral id="FLEXCOMM2" security="s_priv"/>
+                  <peripheral id="FLEXCOMM3" security="s_priv"/>
+                  <peripheral id="FLEXCOMM4" security="s_priv"/>
+                  <peripheral id="FLEXCOMM5" security="s_priv"/>
+                  <peripheral id="FLEXCOMM6" security="s_priv"/>
+                  <peripheral id="FLEXCOMM7" security="s_priv"/>
+                  <peripheral id="GINT0" security="s_priv"/>
+                  <peripheral id="GINT1" security="s_priv"/>
+                  <peripheral id="GPIO" security="s_priv"/>
+                  <peripheral id="HASHCRYPT" security="s_priv"/>
+                  <peripheral id="INPUTMUX" security="s_priv"/>
+                  <peripheral id="IOCON" security="s_priv"/>
+                  <peripheral id="MAILBOX" security="s_priv"/>
+                  <peripheral id="MRT0" security="s_priv"/>
+                  <peripheral id="OSTIMER" security="s_priv"/>
+                  <peripheral id="PINT" security="s_priv"/>
+                  <peripheral id="PLU" security="s_priv"/>
+                  <peripheral id="PMC" security="s_priv"/>
+                  <peripheral id="POWERQUAD" security="s_priv"/>
+                  <peripheral id="PRINCE" security="s_priv"/>
+                  <peripheral id="PUF" security="s_priv"/>
+                  <peripheral id="RNG" security="s_priv"/>
+                  <peripheral id="RTC" security="s_priv"/>
+                  <peripheral id="SCT0" security="s_priv"/>
+                  <peripheral id="SDIF" security="s_priv"/>
+                  <peripheral id="SECGPIO" security="s_priv"/>
+                  <peripheral id="SECPINT" security="s_priv"/>
+                  <peripheral id="SPI8" security="s_priv"/>
+                  <peripheral id="SYSCON" security="s_priv"/>
+                  <peripheral id="SYSCTL" security="s_priv"/>
+                  <peripheral id="USB0" security="s_priv"/>
+                  <peripheral id="USBFSH" security="s_priv"/>
+                  <peripheral id="USBHSD" security="s_priv"/>
+                  <peripheral id="USBHSH" security="s_priv"/>
+                  <peripheral id="USBPHY" security="s_priv"/>
+                  <peripheral id="UTICK0" security="s_priv"/>
+                  <peripheral id="WWDT" security="s_priv"/>
+               </peripherals>
+               <interrupts>
+                  <masking>
+                     <interrupt id="acmp_capt_irq" masked="Masked"/>
+                     <interrupt id="adc_irq" masked="Masked"/>
+                     <interrupt id="casper_irq" masked="Masked"/>
+                     <interrupt id="ctimer0_irq" masked="Masked"/>
+                     <interrupt id="ctimer1_irq" masked="Masked"/>
+                     <interrupt id="ctimer2_irq" masked="Masked"/>
+                     <interrupt id="ctimer3_irq" masked="Masked"/>
+                     <interrupt id="ctimer4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm0_irq" masked="Masked"/>
+                     <interrupt id="flexcomm1_irq" masked="Masked"/>
+                     <interrupt id="flexcomm2_irq" masked="Masked"/>
+                     <interrupt id="flexcomm3_irq" masked="Masked"/>
+                     <interrupt id="flexcomm4_irq" masked="Masked"/>
+                     <interrupt id="flexcomm5_irq" masked="Masked"/>
+                     <interrupt id="flexcomm6_irq" masked="Masked"/>
+                     <interrupt id="flexcomm7_irq" masked="Masked"/>
+                     <interrupt id="global_irq0" masked="Masked"/>
+                     <interrupt id="global_irq1" masked="Masked"/>
+                     <interrupt id="lspi_hs_irq" masked="Masked"/>
+                     <interrupt id="mailbox_irq" masked="Masked"/>
+                     <interrupt id="mrt_irq" masked="Masked"/>
+                     <interrupt id="os_event_irq" masked="Masked"/>
+                     <interrupt id="pin_int4" masked="Masked"/>
+                     <interrupt id="pin_int5" masked="Masked"/>
+                     <interrupt id="pin_int6" masked="Masked"/>
+                     <interrupt id="pin_int7" masked="Masked"/>
+                     <interrupt id="pin_irq0" masked="Masked"/>
+                     <interrupt id="pin_irq1" masked="Masked"/>
+                     <interrupt id="pin_irq2" masked="Masked"/>
+                     <interrupt id="pin_irq3" masked="Masked"/>
+                     <interrupt id="plu_irq" masked="Masked"/>
+                     <interrupt id="pq_irq" masked="Masked"/>
+                     <interrupt id="qddkey_irq" masked="Masked"/>
+                     <interrupt id="rtc_irq" masked="Masked"/>
+                     <interrupt id="sct_irq" masked="Masked"/>
+                     <interrupt id="sdio_irq" masked="Masked"/>
+                     <interrupt id="sdma0_irq" masked="Masked"/>
+                     <interrupt id="sdma1_irq" masked="Masked"/>
+                     <interrupt id="sec_hypervisor_call_irq" masked="Masked"/>
+                     <interrupt id="sec_int0" masked="Masked"/>
+                     <interrupt id="sec_int1" masked="Masked"/>
+                     <interrupt id="sec_vio_irq" masked="Masked"/>
+                     <interrupt id="sha_irq" masked="Masked"/>
+                     <interrupt id="sys_irq" masked="Masked"/>
+                     <interrupt id="usb0_irq" masked="Masked"/>
+                     <interrupt id="usb0_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_irq" masked="Masked"/>
+                     <interrupt id="usb1_needclk_irq" masked="Masked"/>
+                     <interrupt id="usb1_utmi_irq" masked="Masked"/>
+                     <interrupt id="utick_irq" masked="Masked"/>
+                  </masking>
+                  <security>
+                     <interrupt id="acmp_capt_irq" secure="Secure"/>
+                     <interrupt id="adc_irq" secure="Secure"/>
+                     <interrupt id="casper_irq" secure="Secure"/>
+                     <interrupt id="ctimer0_irq" secure="Secure"/>
+                     <interrupt id="ctimer1_irq" secure="Secure"/>
+                     <interrupt id="ctimer2_irq" secure="Secure"/>
+                     <interrupt id="ctimer3_irq" secure="Secure"/>
+                     <interrupt id="ctimer4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm0_irq" secure="Secure"/>
+                     <interrupt id="flexcomm1_irq" secure="Secure"/>
+                     <interrupt id="flexcomm2_irq" secure="Secure"/>
+                     <interrupt id="flexcomm3_irq" secure="Secure"/>
+                     <interrupt id="flexcomm4_irq" secure="Secure"/>
+                     <interrupt id="flexcomm5_irq" secure="Secure"/>
+                     <interrupt id="flexcomm6_irq" secure="Secure"/>
+                     <interrupt id="flexcomm7_irq" secure="Secure"/>
+                     <interrupt id="global_irq0" secure="Secure"/>
+                     <interrupt id="global_irq1" secure="Secure"/>
+                     <interrupt id="lspi_hs_irq" secure="Secure"/>
+                     <interrupt id="mailbox_irq" secure="Secure"/>
+                     <interrupt id="mrt_irq" secure="Secure"/>
+                     <interrupt id="os_event_irq" secure="Secure"/>
+                     <interrupt id="pin_int4" secure="Secure"/>
+                     <interrupt id="pin_int5" secure="Secure"/>
+                     <interrupt id="pin_int6" secure="Secure"/>
+                     <interrupt id="pin_int7" secure="Secure"/>
+                     <interrupt id="pin_irq0" secure="Secure"/>
+                     <interrupt id="pin_irq1" secure="Secure"/>
+                     <interrupt id="pin_irq2" secure="Secure"/>
+                     <interrupt id="pin_irq3" secure="Secure"/>
+                     <interrupt id="plu_irq" secure="Secure"/>
+                     <interrupt id="pq_irq" secure="Secure"/>
+                     <interrupt id="qddkey_irq" secure="Secure"/>
+                     <interrupt id="rtc_irq" secure="Secure"/>
+                     <interrupt id="sct_irq" secure="Secure"/>
+                     <interrupt id="sdio_irq" secure="Secure"/>
+                     <interrupt id="sdma0_irq" secure="Secure"/>
+                     <interrupt id="sdma1_irq" secure="Secure"/>
+                     <interrupt id="sec_hypervisor_call_irq" secure="Secure"/>
+                     <interrupt id="sec_int0" secure="Secure"/>
+                     <interrupt id="sec_int1" secure="Secure"/>
+                     <interrupt id="sec_vio_irq" secure="Secure"/>
+                     <interrupt id="sha_irq" secure="Secure"/>
+                     <interrupt id="sys_irq" secure="Secure"/>
+                     <interrupt id="usb0_irq" secure="Secure"/>
+                     <interrupt id="usb0_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_irq" secure="Secure"/>
+                     <interrupt id="usb1_needclk_irq" secure="Secure"/>
+                     <interrupt id="usb1_utmi_irq" secure="Secure"/>
+                     <interrupt id="utick_irq" secure="Secure"/>
+                  </security>
+               </interrupts>
+               <ports>
+                  <port id="pio0">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+                  <port id="pio1">
+                     <pin_mask id="0" masked="Masked"/>
+                     <pin_mask id="1" masked="Masked"/>
+                     <pin_mask id="10" masked="Masked"/>
+                     <pin_mask id="11" masked="Masked"/>
+                     <pin_mask id="12" masked="Masked"/>
+                     <pin_mask id="13" masked="Masked"/>
+                     <pin_mask id="14" masked="Masked"/>
+                     <pin_mask id="15" masked="Masked"/>
+                     <pin_mask id="16" masked="Masked"/>
+                     <pin_mask id="17" masked="Masked"/>
+                     <pin_mask id="18" masked="Masked"/>
+                     <pin_mask id="19" masked="Masked"/>
+                     <pin_mask id="2" masked="Masked"/>
+                     <pin_mask id="20" masked="Masked"/>
+                     <pin_mask id="21" masked="Masked"/>
+                     <pin_mask id="22" masked="Masked"/>
+                     <pin_mask id="23" masked="Masked"/>
+                     <pin_mask id="24" masked="Masked"/>
+                     <pin_mask id="25" masked="Masked"/>
+                     <pin_mask id="26" masked="Masked"/>
+                     <pin_mask id="27" masked="Masked"/>
+                     <pin_mask id="28" masked="Masked"/>
+                     <pin_mask id="29" masked="Masked"/>
+                     <pin_mask id="3" masked="Masked"/>
+                     <pin_mask id="30" masked="Masked"/>
+                     <pin_mask id="31" masked="Masked"/>
+                     <pin_mask id="4" masked="Masked"/>
+                     <pin_mask id="5" masked="Masked"/>
+                     <pin_mask id="6" masked="Masked"/>
+                     <pin_mask id="7" masked="Masked"/>
+                     <pin_mask id="8" masked="Masked"/>
+                     <pin_mask id="9" masked="Masked"/>
+                  </port>
+               </ports>
+            </ahb>
+            <saus>
+               <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false">
+                  <region start="0" size="268435456" security="ns" enabled="true" index="0"/>
+                  <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="2"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="3"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="4"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="5"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="6"/>
+                  <region start="0" size="32" security="ns" enabled="false" index="7"/>
+               </sau>
+            </saus>
+            <global_options>
+               <option id="AIRCR_PRIS" value="no"/>
+               <option id="AIRCR_BFHFNMINS" value="no"/>
+               <option id="AIRCR_SYSRESETREQS" value="no"/>
+               <option id="SCR_SLEEPDEEPS" value="no"/>
+               <option id="SHCSR_SECUREFAULTENA" value="no"/>
+               <option id="CPACR_CP0" value="3"/>
+               <option id="CPACR_CP1" value="3"/>
+               <option id="CPACR_CP2" value="0"/>
+               <option id="CPACR_CP3" value="0"/>
+               <option id="CPACR_CP4" value="0"/>
+               <option id="CPACR_CP5" value="0"/>
+               <option id="CPACR_CP6" value="0"/>
+               <option id="CPACR_CP7" value="0"/>
+               <option id="CPACR_CP10" value="3"/>
+               <option id="CPACR_CP11" value="3"/>
+               <option id="NSACR_CP0" value="yes"/>
+               <option id="NSACR_CP1" value="yes"/>
+               <option id="NSACR_CP2" value="no"/>
+               <option id="NSACR_CP3" value="no"/>
+               <option id="NSACR_CP4" value="no"/>
+               <option id="NSACR_CP5" value="no"/>
+               <option id="NSACR_CP6" value="no"/>
+               <option id="NSACR_CP7" value="no"/>
+               <option id="NSACR_CP10" value="yes"/>
+               <option id="NSACR_CP11" value="yes"/>
+               <option id="CPPWR_SU0" value="no"/>
+               <option id="CPPWR_SUS0" value="no"/>
+               <option id="CPPWR_SU1" value="no"/>
+               <option id="CPPWR_SUS1" value="no"/>
+               <option id="CPPWR_SU2" value="no"/>
+               <option id="CPPWR_SUS2" value="no"/>
+               <option id="CPPWR_SU3" value="no"/>
+               <option id="CPPWR_SUS3" value="no"/>
+               <option id="CPPWR_SU4" value="no"/>
+               <option id="CPPWR_SUS4" value="no"/>
+               <option id="CPPWR_SU5" value="no"/>
+               <option id="CPPWR_SUS5" value="no"/>
+               <option id="CPPWR_SU6" value="no"/>
+               <option id="CPPWR_SUS6" value="no"/>
+               <option id="CPPWR_SU7" value="no"/>
+               <option id="CPPWR_SUS7" value="no"/>
+               <option id="CPPWR_SU10" value="no"/>
+               <option id="CPPWR_SUS10" value="no"/>
+               <option id="CPPWR_SU11" value="no"/>
+               <option id="CPPWR_SUS11" value="no"/>
+               <option id="SEC_GPIO_MASK0_LOCK" value="no"/>
+               <option id="SEC_GPIO_MASK1_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
+               <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
+               <option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
+               <option id="CPU0_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU0_LOCK_NS_MPU" value="no"/>
+               <option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
+               <option id="CPU0_LOCK_S_MPU" value="no"/>
+               <option id="CPU0_LOCK_SAU" value="no"/>
+               <option id="CPU0_LOCK_REG_LOCK" value="no"/>
+               <option id="CPU1_LOCK_NS_VTOR" value="no"/>
+               <option id="CPU1_LOCK_NS_MPU" value="no"/>
+               <option id="CPU1_LOCK_REG_LOCK" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
+               <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/>
+            </global_options>
+            <mpus>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+               <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
+                  <attributes>
+                     <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                     <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                     <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+                     <group index="3" id="3" memory_type="device" device="nGnRE"/>
+                     <group index="4" id="4" memory_type="device" device="nGnRE"/>
+                     <group index="5" id="5" memory_type="device" device="nGnRE"/>
+                     <group index="6" id="6" memory_type="device" device="nGnRE"/>
+                     <group index="7" id="7" memory_type="device" device="nGnRE"/>
+                  </attributes>
+                  <regions>
+                     <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/>
+                     <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/>
+                  </regions>
+               </mpu>
+            </mpus>
+         </functional_group>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index ad0e502b5..b5d097234 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -33,9 +33,12 @@
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_power.h"
-#include "fsl_iocon.h"
 #include "fsl_usart.h"
 
+#include "board/pin_mux.h"
+#include "board/clock_config.h"
+#include "board/peripherals.h"
+
 #ifdef NEOPIXEL_PIN
 #include "fsl_sctimer.h"
 #include "sct_neopixel.h"
@@ -45,23 +48,6 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN     0x0100u // Enables digital function
-#define IOCON_PIO_FUNC0          0x00u   // Selects pin function 0
-#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
-#define IOCON_PIO_FUNC4          0x04u   // Selects pin function 4
-#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
-#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
-#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
-#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
-#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
-#define IOCON_PIO_MODE_PULLUP    0x20u   /*!<@brief Selects pull-up function */
-
-#define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled
-#define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled
-#define IOCON_PIO_DIG_FUNC4_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) // Digital pin function 2 enabled
-#define IOCON_PIO_DIG_FUNC7_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) // Digital pin function 2 enabled
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -73,74 +59,12 @@ void USB1_IRQHandler(void) {
   tusb_int_handler(1, true);
 }
 
-/****************************************************************
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: System_clock.outFreq, value: 100 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
-- {id: ENABLE_CLKIN_ENA, value: Enabled}
-- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
-- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
-- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
-- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
-- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
-- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
-sources:
-- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
-- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
-******************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Set up the clock sources */
-    /*!< Configure FRO192M */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
-    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
-
-    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
-
-    /*!< Configure XTAL32M */
-    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
-    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
-    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
-    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
-    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
-
-    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
-
-    /*!< Set up PLL */
-    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
-    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
-    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
-        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
-        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
-        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
-        .pllRate = 100000000U,
-        .flags =  PLL_SETUPFLAG_WAITLOCK
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*< Set SystemCoreClock variable. */
-    SystemCoreClock = 100000000U;
-}
-
 void board_init(void) {
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
+  BOARD_InitBootPins();
+  BOARD_InitBootClocks();
+  BOARD_InitBootPeripherals();
 
-  // Init 100 MHz clock
-  BOARD_BootClockPLL100M();
+  board_led_write(0);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -155,54 +79,8 @@ void board_init(void) {
   NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  // Init all GPIO ports
-  GPIO_PortInit(GPIO, 0);
-  GPIO_PortInit(GPIO, 1);
-
-  // LED
-  IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-
-  board_led_write(0);
-
-#ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
-#endif
-
-  // Button
-  IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-#ifdef UART_DEV
-  // UART
-  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
-
-  // Enable UART when debug log is on
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
-  usart_config_t uart_config;
-  USART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx = true;
-  uart_config.enableRx = true;
-  USART_Init(UART_DEV, &uart_config, 12000000);
-#endif
-
 #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
-  /* PORT0 PIN22 configured as USB0_VBUS */
-  IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
   // Port0 is Full Speed
-
   NVIC_ClearPendingIRQ(USB0_IRQn);
   NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn);
 
@@ -227,36 +105,6 @@ void board_init(void) {
     /* enable USB Device clock */
     CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
   } else {
-    const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */
-                                         IOCON_PIO_FUNC4 |
-                                         /* Selects pull-up function */
-                                         IOCON_PIO_MODE_PULLUP |
-                                         /* Standard mode, output slew rate control is enabled */
-                                         IOCON_PIO_SLEW_STANDARD |
-                                         /* Input function is not inverted */
-                                         IOCON_PIO_INV_DI |
-                                         /* Enables digital function */
-                                         IOCON_PIO_DIGITAL_EN |
-                                         /* Open drain is disabled */
-                                         IOCON_PIO_OPENDRAIN_DI);
-    /* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */
-    IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config);
-
-    const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */
-                                         IOCON_PIO_FUNC7 |
-                                         /* Selects pull-up function */
-                                         IOCON_PIO_MODE_PULLUP |
-                                         /* Standard mode, output slew rate control is enabled */
-                                         IOCON_PIO_SLEW_STANDARD |
-                                         /* Input function is not inverted */
-                                         IOCON_PIO_INV_DI |
-                                         /* Enables digital function */
-                                         IOCON_PIO_DIGITAL_EN |
-                                         /* Open drain is disabled */
-                                         IOCON_PIO_OPENDRAIN_DI);
-    /* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */
-    IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config);
-
     CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U);
     USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
   }
@@ -274,18 +122,21 @@ void board_init(void) {
   RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
 
-  /* According to reference manual, device mode setting has to be set by access usb host register */
-  CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+  if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) {
+    /* According to reference manual, device mode setting has to be set by access usb host register */
+    CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
 
-  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
-  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+    USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
+    USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
 
-  CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+    CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+    /* enable USB Device clock */
+    CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
+  } else {
+    CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUnused, 0U);
+  }
 
-  /* enable USB Device clock */
   CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
-  CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
-  CLOCK_EnableClock(kCLOCK_UsbRam1);
 
   // Enable PHY support for Low speed device + LS via FS Hub
   USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
@@ -296,11 +147,9 @@ void board_init(void) {
   USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
   USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
 
-  // TX Timing
-//  uint32_t phytx = USBPHY->TX;
-//  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-//  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-//  USBPHY->TX = phytx;
+  // PHY Tx calibration
+  USBPHY->TX = ((USBPHY->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
+               (USBPHY_TX_D_CAL(0x05U) | USBPHY_TX_TXCAL45DP(0x0AU) | USBPHY_TX_TXCAL45DM(0x0AU)));
 
   ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
   ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
@@ -314,17 +163,6 @@ void board_init(void) {
 
 void board_led_write(bool state) {
   GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
 }
 
 uint32_t board_button_read(void) {
@@ -350,7 +188,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 1f18f9bad..2dc1c33f3 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -1,7 +1,8 @@
 include_guard()
 
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc/LPC5500)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
@@ -40,43 +41,60 @@ cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_
 # Startup & Linker script
 #------------------------------------
 if (NOT DEFINED LD_FILE_GNU)
-  set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  set(LD_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
 endif ()
 set(LD_FILE_Clang ${LD_FILE_GNU})
 
 if (NOT DEFINED STARTUP_FILE_GNU)
-  set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
 endif ()
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+if (NOT DEFINED LD_FILE_IAR)
+  set(LD_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+  set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s)
+endif ()
+
 #------------------------------------
 # Board Target
 #------------------------------------
 function(family_add_board BOARD_TARGET)
+  # Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69)
+  if (NOT DEFINED MCU_DRIVER_VARIANT)
+    set(MCU_DRIVER_VARIANT ${MCU_VARIANT})
+  endif ()
+
   add_library(${BOARD_TARGET} STATIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/peripherals.c
     # driver
-    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-    ${SDK_DIR}/drivers/common/fsl_common_arm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
+    ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${MCUX_DIR}/drivers/common/fsl_common_arm.c
+    ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    ${SDK_DIR}/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_reset.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${TOP}/lib/sct_neopixel
     # driver
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/flexcomm
-    ${SDK_DIR}/drivers/flexcomm/usart
-    ${SDK_DIR}/drivers/lpc_iocon
-    ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/sctimer
+    ${MCUX_DIR}/drivers/common
+    ${MCUX_DIR}/drivers/flexcomm
+    ${MCUX_DIR}/drivers/flexcomm/usart
+    ${MCUX_DIR}/drivers/lpc_iocon
+    ${MCUX_DIR}/drivers/lpc_gpio
+    ${MCUX_DIR}/drivers/sctimer
     # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/${MCU_VARIANT}
+    ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers
+    ${SDK_DIR}/periph
     ${CMSIS_DIR}/CMSIS/Core/Include
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
@@ -91,11 +109,13 @@ function(family_add_board BOARD_TARGET)
   # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
   if (RHPORT_DEVICE EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
       )
-  elseif (RHPORT_HOST EQUAL 1)
+  endif ()
+  if (RHPORT_HOST EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
+      CFG_TUH_USBIP_IP3516=1
       )
   endif ()
 
@@ -114,9 +134,19 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     ${TOP}/lib/sct_neopixel/sct_neopixel.c
     ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
-    ${TOP}/src/portable/ohci/ohci.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
+
+  if (RHPORT_HOST EQUAL 0)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/ohci/ohci.c
+      )
+  elseif (RHPORT_HOST EQUAL 1)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
+      )
+  endif ()
+
   target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
@@ -128,6 +158,8 @@ function(family_configure_example TARGET RTOS)
       "LINKER:--script=${LD_FILE_GNU}"
       --specs=nosys.specs --specs=nano.specs
       -nostartfiles
+      "LINKER:--defsym=__stack_size__=0x1000"
+      "LINKER:--defsym=__heap_size__=0"
       )
   elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
     target_link_options(${TARGET} PUBLIC
@@ -136,6 +168,8 @@ function(family_configure_example TARGET RTOS)
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
     target_link_options(${TARGET} PUBLIC
       "LINKER:--config=${LD_FILE_IAR}"
+      "LINKER:--config_def=__stack_size__=0x1000"
+      "LINKER:--config_def=__heap_size__=0"
       )
   endif ()
 
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index fadf852cd..2fc76ed50 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,28 +1,41 @@
 UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m33
-MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+MCUX_DIR = hw/mcu/nxp/mcuxsdk-core
+SDK_DIR = hw/mcu/nxp/mcux-devices-lpc
 
-# Default to Highspeed PORT1
-PORT ?= 1
+# Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69)
+MCU_DRIVER_VARIANT ?= $(MCU_VARIANT)
+
+# Default device port to USB1 highspeed, host to USB0 fullspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
 
 CFLAGS += \
   -flto \
   -D__STARTUP_CLEAR_BSS \
   -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-  -DBOARD_TUD_RHPORT=$(PORT) \
+  -DBOARD_TUD_RHPORT=$(RHPORT_DEVICE) \
+  -DBOARD_TUH_RHPORT=$(RHPORT_HOST) \
 
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
+# port 0 is fullspeed, port 1 is highspeed
+ifeq ($(RHPORT_DEVICE), 1)
   CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+  # Port1 controller can only access USB_SRAM
+  CFLAGS += -DCFG_TUD_MEM_SECTION='__attribute__((section("m_usb_global")))'
+else
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+endif
 
-  # LPC55 Highspeed Port1 can only write to USB_SRAM region
-  CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
+ifeq ($(RHPORT_HOST), 1)
+  CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+  CFLAGS += -DCFG_TUH_MEM_SECTION='__attribute__((section("m_usb_global")))'
+  CFLAGS += -DCFG_TUH_USBIP_IP3516=1
+	SRC_C += $(TOP)/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
 else
-  $(info "PORT0 Full Speed")
+  CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
 endif
 
 # mcu driver cause following warnings
@@ -31,33 +44,36 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal
 LDFLAGS_GCC += \
   -nostartfiles \
   --specs=nosys.specs --specs=nano.specs \
+  -Wl,--defsym=__stack_size__=0x1000 \
+  -Wl,--defsym=__heap_size__=0 \
 
 # All source paths should be relative to the top level.
-LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld
+LD_FILE ?= $(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
 
 SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_$(MCU_CORE).c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
-	lib/sct_neopixel/sct_neopixel.c
+	$(TOP)/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_clock.c \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_power.c \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_reset.c \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \
+	$(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \
+	$(TOP)/lib/sct_neopixel/sct_neopixel.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/sct_neopixel \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm/ \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
-	$(TOP)/$(SDK_DIR)/drivers/sctimer
+	$(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers \
+	$(TOP)/$(SDK_DIR)/LPC5500/periph \
+	$(TOP)/$(MCUX_DIR)/drivers/common \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \
+	$(TOP)/$(MCUX_DIR)/drivers/flexcomm/ \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \
+	$(TOP)/$(MCUX_DIR)/drivers/lpc_gpio \
+	$(TOP)/$(MCUX_DIR)/drivers/sctimer
 
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
+SRC_S += $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/maxim/family.c b/hw/bsp/maxim/family.c
index 7ad7d6ff9..6ef4c12c1 100644
--- a/hw/bsp/maxim/family.c
+++ b/hw/bsp/maxim/family.c
@@ -202,7 +202,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
index e6619992f..f0bf9510b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
@@ -1,4 +1,5 @@
 set(MCU_VARIANT MCXA153)
+set(MCU_FAMILY MCXA)
 set(MCU_CORE MCXA153)
 
 set(JLINK_DEVICE MCXA153_M33)
@@ -15,10 +16,10 @@ function(update_board TARGET)
     CFG_EXAMPLE_VIDEO_READONLY
     )
   target_sources(${TARGET} PRIVATE
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
     )
   target_include_directories(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board
+    ${SDK_DIR}/${MCU_FAMILY}/periph
     )
 endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
index 34558b43e..caa2e5a3b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
@@ -1,4 +1,5 @@
 MCU_VARIANT = MCXA153
+MCU_FAMILY = MCXA
 MCU_CORE = MCXA153
 PORT = 0
 
@@ -9,11 +10,11 @@ CFLAGS += \
 	-DCFG_EXAMPLE_VIDEO_READONLY
 
 SRC_C += \
-  ${BOARD_PATH}/board/clock_config.c \
-  ${BOARD_PATH}/board/pin_mux.c
+  ${BOARD_PATH}/clock_config.c \
+  ${BOARD_PATH}/pin_mux.c
 
 INC += \
-	$(TOP)/$(BOARD_PATH)/board
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
 
 JLINK_DEVICE = MCXA153
 PYOCD_TARGET = MCXA153
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
index 599110d7a..599110d7a 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h
index d609eb468..d609eb468 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
index 58b0f47e9..58b0f47e9 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
index 4a42f266d..4a42f266d 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
index a6aa6c2e4..0d8ec3229 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
@@ -1,4 +1,5 @@
 set(MCU_VARIANT MCXA156)
+set(MCU_FAMILY MCXA)
 set(MCU_CORE MCXA156)
 
 set(JLINK_DEVICE MCXA156_M33)
@@ -18,4 +19,7 @@ function(update_board TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
     )
+  target_include_directories(${TARGET} PUBLIC
+    ${SDK_DIR}/${MCU_FAMILY}/periph1
+    )
 endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
index d4a59b32a..9d24b5fab 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
@@ -1,4 +1,5 @@
 MCU_VARIANT = MCXA156
+MCU_FAMILY = MCXA
 MCU_CORE = MCXA156
 PORT = 0
 
@@ -7,6 +8,9 @@ CFLAGS += \
 	-DCPU_MCXA156VLH \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
 
+INC += \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph1
+
 JLINK_DEVICE = MCXA156
 PYOCD_TARGET = MCXA156
 
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
index 8c3280743..3bf7851bd 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
@@ -1,4 +1,5 @@
 set(MCU_VARIANT MCXN947)
+set(MCU_FAMILY MCXN)
 set(MCU_CORE MCXN947_cm33_core0)
 
 set(JLINK_DEVICE MCXN947_M33_0)
@@ -18,4 +19,7 @@ function(update_board TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
     )
+  target_include_directories(${TARGET} PUBLIC
+    ${SDK_DIR}/${MCU_FAMILY}/periph
+    )
 endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
index 22fefd79b..ee1c94f94 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
@@ -1,4 +1,5 @@
 MCU_VARIANT = MCXN947
+MCU_FAMILY = MCXN
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
@@ -7,6 +8,9 @@ CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
 
+INC += \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
+
 JLINK_DEVICE = MCXN947_M33_0
 PYOCD_TARGET = MCXN947
 
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index 8c3280743..3bf7851bd 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -1,4 +1,5 @@
 set(MCU_VARIANT MCXN947)
+set(MCU_FAMILY MCXN)
 set(MCU_CORE MCXN947_cm33_core0)
 
 set(JLINK_DEVICE MCXN947_M33_0)
@@ -18,4 +19,7 @@ function(update_board TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
     )
+  target_include_directories(${TARGET} PUBLIC
+    ${SDK_DIR}/${MCU_FAMILY}/periph
+    )
 endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
index 22fefd79b..ee1c94f94 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -1,4 +1,5 @@
 MCU_VARIANT = MCXN947
+MCU_FAMILY = MCXN
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
@@ -7,6 +8,9 @@ CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
 
+INC += \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
+
 JLINK_DEVICE = MCXN947_M33_0
 PYOCD_TARGET = MCXN947
 
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 3b91678b1..a3969c217 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -219,7 +219,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index d062cec16..89e2aadf2 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -1,7 +1,8 @@
 include_guard()
 
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-mcx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
@@ -26,46 +27,55 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
 # Startup & Linker script
 #------------------------------------
 if (NOT DEFINED LD_FILE_GNU)
-set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  set(LD_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
 endif ()
 set(LD_FILE_Clang ${LD_FILE_GNU})
+
 if (NOT DEFINED STARTUP_FILE_GNU)
-set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
 endif()
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+if (NOT DEFINED LD_FILE_IAR)
+  set(LD_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+  set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s)
+endif ()
+
 #------------------------------------
 # Board Target
 #------------------------------------
 function(family_add_board BOARD_TARGET)
   add_library(${BOARD_TARGET} STATIC
     # driver
-    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
-    ${SDK_DIR}/drivers/common/fsl_common_arm.c
-    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${MCUX_DIR}/drivers/gpio/fsl_gpio.c
+    ${MCUX_DIR}/drivers/common/fsl_common_arm.c
+    ${MCUX_DIR}/drivers/lpuart/fsl_lpuart.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c
     # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_reset.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMSIS_DIR}/CMSIS/Core/Include
-    ${SDK_DIR}/drivers/gpio/
-    ${SDK_DIR}/drivers/lpuart
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/port
+    ${MCUX_DIR}/drivers/gpio/
+    ${MCUX_DIR}/drivers/lpuart
+    ${MCUX_DIR}/drivers/common
+    ${MCUX_DIR}/drivers/port
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}
+    ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers
     )
 
   if (${FAMILY_MCUS} STREQUAL "MCXN9")
     target_sources(${BOARD_TARGET} PRIVATE
-      ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
+      ${MCUX_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
       )
     target_include_directories(${BOARD_TARGET} PUBLIC
-      ${SDK_DIR}/drivers/lpflexcomm
+      ${MCUX_DIR}/drivers/lpflexcomm
       )
   elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
   endif()
@@ -100,7 +110,8 @@ function(family_configure_example TARGET RTOS)
     target_link_options(${TARGET} PUBLIC
       "LINKER:--script=${LD_FILE_GNU}"
       --specs=nosys.specs --specs=nano.specs
-      #-nostartfiles
+      "LINKER:--defsym=__stack_size__=0x1000"
+      "LINKER:--defsym=__heap_size__=0"
       )
   elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
     target_link_options(${TARGET} PUBLIC
@@ -109,6 +120,8 @@ function(family_configure_example TARGET RTOS)
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
     target_link_options(${TARGET} PUBLIC
       "LINKER:--config=${LD_FILE_IAR}"
+      "LINKER:--config_def=__stack_size__=0x1000"
+      "LINKER:--config_def=__heap_size__=0"
       )
   endif ()
 
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 4321e654a..3d63eb238 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -1,7 +1,9 @@
 UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+MCUX_DIR = hw/mcu/nxp/mcuxsdk-core
+SDK_DIR = hw/mcu/nxp/mcux-devices-mcx
 
 # Default to Highspeed PORT1
 PORT ?= 1
@@ -13,10 +15,13 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls
 
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+  --specs=nosys.specs --specs=nano.specs \
+  -Wl,--defsym=__stack_size__=0x1000 \
+  -Wl,--defsym=__heap_size__=0 \
 
 # All source paths should be relative to the top level.
-LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+LD_FILE ?= $(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
 
 # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
 ifeq ($(PORT), 1)
@@ -30,17 +35,17 @@ else
 endif
 
 SRC_C += \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	${SDK_DIR}/drivers/gpio/fsl_gpio.c \
-	${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \
-	${SDK_DIR}/drivers/common/fsl_common_arm.c\
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(TOP)/$(MCUX_DIR)/drivers/gpio/fsl_gpio.c \
+	$(TOP)/$(MCUX_DIR)/drivers/lpuart/fsl_lpuart.c \
+	$(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \
 	hw/bsp/mcx/drivers/spc/fsl_spc.c
 
 # fsl_lpflexcomm for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
-	SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
+	SRC_C += $(MCUX_DIR)/drivers/lpflexcomm/fsl_lpflexcomm.c
 endif
 
 # fsl_spc for MCXNA15
@@ -50,15 +55,15 @@ endif
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/ \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/common\
-	$(TOP)/$(SDK_DIR)/drivers/gpio\
-	$(TOP)/$(SDK_DIR)/drivers/port\
+	$(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers \
+	$(TOP)/$(MCUX_DIR)/drivers/ \
+	$(TOP)/$(MCUX_DIR)/drivers/lpuart \
+	$(TOP)/$(MCUX_DIR)/drivers/lpflexcomm \
+	$(TOP)/$(MCUX_DIR)/drivers/common \
+	$(TOP)/$(MCUX_DIR)/drivers/gpio \
+	$(TOP)/$(MCUX_DIR)/drivers/port \
 	$(TOP)/hw/bsp/mcx/drivers/spc
 
-SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
+SRC_S += $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c
index 663c30818..330b01f6d 100644
--- a/hw/bsp/mm32/family.c
+++ b/hw/bsp/mm32/family.c
@@ -175,7 +175,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c
index 390a9915e..413ad7db6 100644
--- a/hw/bsp/msp430/family.c
+++ b/hw/bsp/msp430/family.c
@@ -102,10 +102,10 @@ static void SystemClock_Config(void)
 
   // VUSB enabled automatically.
   // Wait two milliseconds to stabilize, per manual recommendation.
-  uint32_t ms_elapsed = board_millis();
+  uint32_t ms_elapsed = tusb_time_millis_api();
   do
   {
-    while((board_millis() - ms_elapsed) < 2);
+    while((tusb_time_millis_api() - ms_elapsed) < 2);
   }while(!(USBPWRCTL & USBBGVBV));
 
   // USB uses XT2 (4 MHz) directly. Enable the PLL.
@@ -113,11 +113,11 @@ static void SystemClock_Config(void)
   USBPLLCTL |= (UPFDEN | UPLLEN);
 
   // Wait until PLL locks. Check every 2ms, per manual.
-  ms_elapsed = board_millis();
+  ms_elapsed = tusb_time_millis_api();
   do
   {
     USBPLLIR &= ~USBOOLIFG;
-    while((board_millis() - ms_elapsed) < 2);
+    while((tusb_time_millis_api() - ms_elapsed) < 2);
   }while(USBPLLIR & USBOOLIFG);
 
   USBKEYPID = 0;
@@ -207,7 +207,7 @@ void TIMER0_A0_ISR (void) {
   // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked.
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   uint32_t systick_mirror;
 
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 0e1b0528a..90eb945f4 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -202,7 +202,7 @@ void SysTick_Handler(void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index ee3ac61e2..04bfbf320 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -296,7 +296,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/nuc100_120/family.c b/hw/bsp/nuc100_120/family.c
index 752af2a56..cfe60121c 100644
--- a/hw/bsp/nuc100_120/family.c
+++ b/hw/bsp/nuc100_120/family.c
@@ -87,7 +87,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/nuc121_125/family.c b/hw/bsp/nuc121_125/family.c
index 089855207..dce5b4d62 100644
--- a/hw/bsp/nuc121_125/family.c
+++ b/hw/bsp/nuc121_125/family.c
@@ -86,7 +86,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/nuc126/family.c b/hw/bsp/nuc126/family.c
index f992fcab4..3343064e5 100644
--- a/hw/bsp/nuc126/family.c
+++ b/hw/bsp/nuc126/family.c
@@ -111,7 +111,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/nuc505/family.c b/hw/bsp/nuc505/family.c
index 00ed92310..f1a77e4a5 100644
--- a/hw/bsp/nuc505/family.c
+++ b/hw/bsp/nuc505/family.c
@@ -88,7 +88,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c
index da97f67a9..2bfc876e1 100644
--- a/hw/bsp/pic32mz/family.c
+++ b/hw/bsp/pic32mz/family.c
@@ -106,7 +106,7 @@ TU_ATTR_WEAK int board_uart_write(void const * buf, int len)
 }
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   // COUNTER is system clock (200MHz / 2 = 100MHz) convert to ms)
   return _CP0_GET_COUNT() / (100000000 / 1000);
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 1f75b47c1..f371e694b 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -169,7 +169,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index a51b3f758..adb58449d 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -370,7 +370,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx
   }else if (rx_buf == NULL) {
     ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes);
   }else {
-    ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes);
+    ret = spi_write_read_blocking(MAX3421_SPI, tx_buf, rx_buf, xfer_bytes);
   }
 
   return ret == (int) xfer_bytes;
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 1602e35eb..e31abe50b 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -98,6 +98,7 @@ target_sources(tinyusb_device_base INTERFACE
 		${TOP}/src/class/mtp/mtp_device.c
 		${TOP}/src/class/net/ecm_rndis_device.c
 		${TOP}/src/class/net/ncm_device.c
+		${TOP}/src/class/printer/printer_device.c
 		${TOP}/src/class/usbtmc/usbtmc_device.c
 		${TOP}/src/class/vendor/vendor_device.c
 		${TOP}/src/class/video/video_device.c
@@ -157,10 +158,12 @@ target_link_libraries(tinyusb_bsp INTERFACE
 # tinyusb_additions will hold our extra settings for examples
 add_library(tinyusb_additions INTERFACE)
 
+if (PICO_PLATFORM STREQUAL rp2040)
 target_compile_definitions(tinyusb_additions INTERFACE
 	PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
 	PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
-)
+	)
+endif ()
 
 if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
 	target_compile_definitions(tinyusb_additions INTERFACE
@@ -248,8 +251,10 @@ function(family_configure_target TARGET RTOS)
   family_flash_openocd(${TARGET})
 	family_flash_jlink(${TARGET})
 
-  # Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
+	# Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
+	family_add_bloaty(${TARGET})
   family_add_linkermap(${TARGET})
+  family_add_membrowse(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/rw61x/family.c b/hw/bsp/rw61x/family.c
index 265d5fcc0..fcc7fb262 100644
--- a/hw/bsp/rw61x/family.c
+++ b/hw/bsp/rw61x/family.c
@@ -128,7 +128,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 26ad4a6aa..e5b24bf69 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -248,7 +248,7 @@ void INT_Excep_CMT0_CMI0(void)
   ++system_ticks;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 66a319541..d5c2de05a 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -299,7 +299,7 @@ void INT_Excep_CMT0_CMI0(void)
   ++system_ticks;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c
index 6cbf02412..bccbac8ea 100644
--- a/hw/bsp/samd11/family.c
+++ b/hw/bsp/samd11/family.c
@@ -155,7 +155,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t tusb_time_millis_api(void)
 {
   return system_ticks;
 }
diff --git a/hw/bsp/samd2x_l2x/family.c b/hw/bsp/samd2x_l2x/family.c
index a2dc8a8d4..737219b6c 100644
--- a/hw/bsp/samd2x_l2x/family.c
+++ b/hw/bsp/samd2x_l2x/family.c
@@ -361,7 +361,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c
index 5a7105894..c008b9719 100644
--- a/hw/bsp/samd5x_e5x/family.c
+++ b/hw/bsp/samd5x_e5x/family.c
@@ -210,7 +210,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.cmake b/hw/bsp/same7x/boards/same70_qmtech/board.cmake
index 7937330e3..fc2071b3a 100644
--- a/hw/bsp/same7x/boards/same70_qmtech/board.cmake
+++ b/hw/bsp/same7x/boards/same70_qmtech/board.cmake
@@ -1,5 +1,8 @@
 set(JLINK_DEVICE ATSAME70N19B)
-set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same70n19b_flash.ld)
+
+# N19B and Q21B share the same vector table / startup code
+set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.mk b/hw/bsp/same7x/boards/same70_qmtech/board.mk
index 09ae98860..4ad8212a8 100644
--- a/hw/bsp/same7x/boards/same70_qmtech/board.mk
+++ b/hw/bsp/same7x/boards/same70_qmtech/board.mk
@@ -1,3 +1,6 @@
 CFLAGS += -D__SAME70N19B__
 
-JLINK_DEVICE = SAME70N19B
+LD_FILE = $(BOARD_PATH)/same70n19b_flash.ld
+STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c
+
+JLINK_DEVICE = ATSAME70N19B
diff --git a/hw/bsp/same7x/boards/same70_xplained/board.cmake b/hw/bsp/same7x/boards/same70_xplained/board.cmake
index 2350a4a28..f762464a6 100644
--- a/hw/bsp/same7x/boards/same70_xplained/board.cmake
+++ b/hw/bsp/same7x/boards/same70_xplained/board.cmake
@@ -2,6 +2,9 @@ set(JLINK_DEVICE ATSAME70Q21B)
 set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld)
 set(LD_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf)
 
+set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c)
+set(STARTUP_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/iar/startup_same70q21b.c)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     __SAME70Q21B__
diff --git a/hw/bsp/same7x/boards/same70_xplained/board.mk b/hw/bsp/same7x/boards/same70_xplained/board.mk
index ca23a9be5..231d5d770 100644
--- a/hw/bsp/same7x/boards/same70_xplained/board.mk
+++ b/hw/bsp/same7x/boards/same70_xplained/board.mk
@@ -1,3 +1,6 @@
 CFLAGS += -D__SAME70Q21B__
 
-JLINK_DEVICE = SAME70Q21B
+LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
+STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c
+
+JLINK_DEVICE = ATSAME70Q21B
diff --git a/hw/bsp/same7x/family.c b/hw/bsp/same7x/family.c
index 6feefa3b5..61c1792d1 100644
--- a/hw/bsp/same7x/family.c
+++ b/hw/bsp/same7x/family.c
@@ -42,56 +42,15 @@ static inline void board_vbus_set(uint8_t rhport, bool state);
 void _init(void);
 #include "board.h"
 
-#ifndef LED_STATE_ON
-  #define LED_STATE_ON 1
-#endif
-
-#ifndef LED_PORT_CLOCK
-  #define LED_PORT_CLOCK ID_PIOA
-#endif
-
-#ifndef BUTTON_PORT_CLOCK
-  #define BUTTON_PORT_CLOCK ID_PIOA
-#endif
-
-#ifndef UART_PORT_CLOCK
-  #define UART_PORT_CLOCK ID_USART1
-#endif
-
-#ifndef BOARD_USART
-  #define BOARD_USART USART1
-#endif
-
-#ifndef BOARD_UART_DESCRIPTOR
-  #define BOARD_UART_DESCRIPTOR edbg_com
-#endif
-
-#ifndef BOARD_UART_BUFFER
-  #define BOARD_UART_BUFFER edbg_com_buffer
-#endif
-
-#ifndef BUTTON_STATE_ACTIVE
-  #define BUTTON_STATE_ACTIVE 0
-#endif
-
-#ifndef UART_TX_FUNCTION
-  #define UART_TX_FUNCTION MUX_PB4D_USART1_TXD1
-#endif
-
-#ifndef UART_RX_FUNCTION
-  #define UART_RX_FUNCTION MUX_PA21A_USART1_RXD1
-#endif
-
 #ifndef UART_BUFFER_SIZE
   #define UART_BUFFER_SIZE 64
 #endif
 
 #define LED_STATE_OFF (1 - LED_STATE_ON)
 
-static struct usart_async_descriptor BOARD_UART_DESCRIPTOR;
-static uint8_t BOARD_UART_BUFFER[UART_BUFFER_SIZE];
+static struct usart_async_descriptor edbg_com;
+static uint8_t edbg_com_buffer[UART_BUFFER_SIZE];
 static volatile bool uart_busy = false;
-
 static void tx_complete_cb(const struct usart_async_descriptor *const io_descr) {
   (void) io_descr;
   uart_busy = false;
@@ -121,10 +80,10 @@ void board_init(void) {
   gpio_set_pin_function(UART_RX_PIN, UART_RX_FUNCTION);
   gpio_set_pin_function(UART_TX_PIN, UART_TX_FUNCTION);
 
-  usart_async_init(&BOARD_UART_DESCRIPTOR, BOARD_USART, BOARD_UART_BUFFER, sizeof(BOARD_UART_BUFFER), _usart_get_usart_async());
-  usart_async_set_baud_rate(&BOARD_UART_DESCRIPTOR, CFG_BOARD_UART_BAUDRATE);
-  usart_async_register_callback(&BOARD_UART_DESCRIPTOR, USART_ASYNC_TXC_CB, tx_complete_cb);
-  usart_async_enable(&BOARD_UART_DESCRIPTOR);
+  usart_async_init(&edbg_com, BOARD_USART, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
+  usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+  usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_complete_cb);
+  usart_async_enable(&edbg_com);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer (SystemCoreClock may not be correct after init)
@@ -181,10 +140,40 @@ int board_uart_write(void const *buf, int len) {
   while (uart_busy) {}
   uart_busy = true;
 
-  io_write(&BOARD_UART_DESCRIPTOR.io, buf, len);
+  io_write(&edbg_com.io, buf, len);
   return len;
 }
 
+// Read 128-bit unique ID via EFC STUI/SPUI commands
+// Must run from RAM since STUI remaps flash to the unique ID
+__attribute__((noinline)) TU_ATTR_SECTION(.ramfunc) static void read_unique_id(uint32_t uid[4]) {
+  // Wait for flash to be ready
+  while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {}
+
+  // Issue Start Read Unique Identifier command
+  EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_STUI;
+  while (EFC->EEFC_FSR & EEFC_FSR_FRDY) {}
+
+  // Read 128-bit unique ID from flash base address
+  const volatile uint32_t *flash = (const volatile uint32_t *) IFLASH_ADDR;
+  for (int i = 0; i < 4; i++) {
+    uid[i] = flash[i];
+  }
+
+  // Issue Stop Read Unique Identifier command
+  EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SPUI;
+  while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {}
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  const size_t uid_len = 16;
+  if (max_len < uid_len) {
+    return 0;
+  }
+  read_unique_id((uint32_t *)(uintptr_t) id);
+  return uid_len;
+}
+
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
@@ -192,7 +181,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/same7x/family.cmake b/hw/bsp/same7x/family.cmake
index fcfa9b583..63726a8e5 100644
--- a/hw/bsp/same7x/family.cmake
+++ b/hw/bsp/same7x/family.cmake
@@ -13,9 +13,7 @@ set(FAMILY_MCUS SAMX7X CACHE INTERNAL "")
 #------------------------------------
 # Startup & Linker script
 #------------------------------------
-set(STARTUP_FILE_GNU ${SDK_DIR}/same70b/gcc/gcc/startup_same70q21b.c)
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-set(STARTUP_FILE_IAR ${SDK_DIR}/same70b/iar/iar/startup_same70q21b.c)
 set(LD_FILE_Clang ${LD_FILE_GNU})
 
 #------------------------------------
@@ -48,14 +46,9 @@ function(family_add_board BOARD_TARGET)
 
   update_board(${BOARD_TARGET})
 
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      -Wno-error=unused-parameter
-      -Wno-error=cast-align
-      -Wno-error=redundant-decls
-      -Wno-error=cast-qual
-      )
-  endif()
+  if (TOOLCHAIN STREQUAL "gcc" OR TOOLCHAIN STREQUAL "clang")
+    set_target_properties(${BOARD_TARGET} PROPERTIES COMPILE_FLAGS -Wno-error=cast-qual)
+  endif ()
 endfunction()
 
 #------------------------------------
@@ -93,9 +86,11 @@ function(family_configure_example TARGET RTOS)
       )
   endif ()
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
-  set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
-    SKIP_LINTING ON
-    COMPILE_OPTIONS -w)
+    # ignore hal error
+    set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+      PROPERTIES
+      SKIP_LINTING ON
+      COMPILE_OPTIONS -w)
   endif()
 
   family_add_bin_hex(${TARGET})
diff --git a/hw/bsp/same7x/family.mk b/hw/bsp/same7x/family.mk
index c8fa74d71..19e119625 100644
--- a/hw/bsp/same7x/family.mk
+++ b/hw/bsp/same7x/family.mk
@@ -21,11 +21,9 @@ CFLAGS_SKIP += -Wcast-qual
 LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
 
 # All source paths should be relative to the top level.
-LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
-
 SRC_C += \
 	src/portable/microchip/samx7x/dcd_samx7x.c \
-	$(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
+	$(STARTUP_FILE) \
 	$(SDK_DIR)/same70b/gcc/system_same70q21b.c \
 	$(SDK_DIR)/hpl/core/hpl_init.c \
 	$(SDK_DIR)/hpl/usart/hpl_usart.c \
@@ -48,9 +46,6 @@ INC += \
 	$(TOP)/$(SDK_DIR)/hri \
 	$(TOP)/$(SDK_DIR)/CMSIS/Core/Include
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
-
 # For flash-jlink target
 flash: $(BUILD)/$(PROJECT).bin
 	edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/samg/family.c b/hw/bsp/samg/family.c
index 5c5fc3c14..b27134305 100644
--- a/hw/bsp/samg/family.c
+++ b/hw/bsp/samg/family.c
@@ -148,7 +148,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c
index e2ba47f45..e20c0ee15 100644
--- a/hw/bsp/stm32c0/family.c
+++ b/hw/bsp/stm32c0/family.c
@@ -173,7 +173,7 @@ void SysTick_Handler(void) {
   HAL_IncTick();
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index b99b0a8cc..5a35a3e50 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -160,7 +160,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 3147061cf..78a425453 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -148,12 +148,12 @@ void board_init(void) {
 #ifdef USB_CONNECT_PIN
 void dcd_disconnect(uint8_t rhport) {
   (void)rhport;
-  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, 1-USB_CONNECT_STATE);
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)(1 - USB_CONNECT_STATE));
 }
 
 void dcd_connect(uint8_t rhport) {
   (void)rhport;
-  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, USB_CONNECT_STATE);
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)USB_CONNECT_STATE);
 }
 #endif
 
@@ -202,7 +202,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c
index 8ea8ec5a5..f1fd4ddb2 100644
--- a/hw/bsp/stm32f2/family.c
+++ b/hw/bsp/stm32f2/family.c
@@ -31,12 +31,11 @@
 #include "stm32f2xx_hal.h"
 #include "bsp/board_api.h"
 #include "board.h"
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
 void OTG_FS_IRQHandler(void) {
-  tud_int_handler(0);
+  tusb_int_handler(0, true);
 }
 
 //--------------------------------------------------------------------+
@@ -105,9 +104,12 @@ void board_init(void) {
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+#if CFG_TUD_ENABLED
   // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = true;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -143,7 +145,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c
index 95bcc7882..fde1e9f6d 100644
--- a/hw/bsp/stm32f3/family.c
+++ b/hw/bsp/stm32f3/family.c
@@ -156,7 +156,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
index 11e976a42..2db42b98a 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -106,14 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if  (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h
deleted file mode 100644
index b892df3b6..000000000
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED   */
-/* #define HAL_DMA2D_MODULE_ENABLED   */
-/* #define HAL_ETH_MODULE_ENABLED   */
-/* #define HAL_NAND_MODULE_ENABLED   */
-/* #define HAL_NOR_MODULE_ENABLED   */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED   */
-/* #define HAL_SDRAM_MODULE_ENABLED   */
-/* #define HAL_HASH_MODULE_ENABLED   */
-/* #define HAL_I2C_MODULE_ENABLED   */
-/* #define HAL_I2S_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
-/* #define HAL_LTDC_MODULE_ENABLED   */
-/* #define HAL_RNG_MODULE_ENABLED   */
-/* #define HAL_RTC_MODULE_ENABLED   */
-/* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_MMC_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED   */
-/* #define HAL_TIM_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED   */
-/* #define HAL_IRDA_MODULE_ENABLED   */
-/* #define HAL_SMARTCARD_MODULE_ENABLED   */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED   */
-/* #define HAL_DSI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED   */
-/* #define HAL_DFSDM_MODULE_ENABLED   */
-/* #define HAL_LPTIM_MODULE_ENABLED   */
-/* #define HAL_EXTI_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE		      ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)   /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-/* Copied over manually- STM32Cube didn't generate these for some reason. */
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS           0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h
index 9583a924b..319d2336a 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.h
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -106,14 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if  (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h
deleted file mode 100644
index b892df3b6..000000000
--- a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf.h
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED   */
-/* #define HAL_DMA2D_MODULE_ENABLED   */
-/* #define HAL_ETH_MODULE_ENABLED   */
-/* #define HAL_NAND_MODULE_ENABLED   */
-/* #define HAL_NOR_MODULE_ENABLED   */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED   */
-/* #define HAL_SDRAM_MODULE_ENABLED   */
-/* #define HAL_HASH_MODULE_ENABLED   */
-/* #define HAL_I2C_MODULE_ENABLED   */
-/* #define HAL_I2S_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
-/* #define HAL_LTDC_MODULE_ENABLED   */
-/* #define HAL_RNG_MODULE_ENABLED   */
-/* #define HAL_RTC_MODULE_ENABLED   */
-/* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_MMC_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED   */
-/* #define HAL_TIM_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED   */
-/* #define HAL_IRDA_MODULE_ENABLED   */
-/* #define HAL_SMARTCARD_MODULE_ENABLED   */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_PCD_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED   */
-/* #define HAL_DSI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED   */
-/* #define HAL_DFSDM_MODULE_ENABLED   */
-/* #define HAL_LPTIM_MODULE_ENABLED   */
-/* #define HAL_EXTI_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE		      ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)   /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-/* Copied over manually- STM32Cube didn't generate these for some reason. */
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS           0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
index 8a3fe8409..b69ebbeaf 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -107,15 +109,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
-  if  (rhport == 0) {
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
deleted file mode 100644
index 16f081cfb..000000000
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
index effbf2be8..ebefeb988 100644
--- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOA,
@@ -106,15 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
deleted file mode 100644
index e24e782ea..000000000
--- a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
index 19a029768..bcfa6059a 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
@@ -46,6 +46,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOD,
@@ -114,14 +116,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
deleted file mode 100644
index e24e782ea..000000000
--- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
index d16db508f..f54807c2a 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
@@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld)
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32F411xE
+    HSE_VALUE=25000000
     )
 endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
index 61e5de70d..0faf6fe11 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -106,15 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
-  if  (rhport == 0) {
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
index 7af7ca47c..c45aba79b 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F411xE
+CFLAGS += -DSTM32F411xE -DHSE_VALUE=25000000
 
 # GCC
 SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
deleted file mode 100644
index 16f081cfb..000000000
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
index d7b02e79d..1a289dfb5 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOD,
@@ -111,14 +113,6 @@ static inline void board_clock_init(void) {
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Enable VBUS sense (B device) via pin PA9
-  if (rhport == 0) {
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
deleted file mode 100644
index e24e782ea..000000000
--- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
index d5146ae3c..0689dfe87 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
@@ -45,6 +45,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOE,
@@ -127,13 +129,6 @@ static inline void board_clock_init(void) {
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
deleted file mode 100644
index e24e782ea..000000000
--- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
index f7026ce61..be58f8ae7 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
@@ -45,6 +45,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -128,13 +130,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
deleted file mode 100644
index e24e782ea..000000000
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
-
-#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
-#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
-
-#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
-#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
index 9a348f33f..b1633b395 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
@@ -46,6 +46,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -117,14 +119,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
deleted file mode 100644
index 7bbd6b54f..000000000
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED      */
-/* #define HAL_CAN_MODULE_ENABLED      */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */
-/* #define HAL_CEC_MODULE_ENABLED      */
-/* #define HAL_CRYP_MODULE_ENABLED     */
-/* #define HAL_DAC_MODULE_ENABLED      */
-/* #define HAL_DCMI_MODULE_ENABLED     */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED    */
-/* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED     */
-/* #define HAL_NOR_MODULE_ENABLED      */
-/* #define HAL_PCCARD_MODULE_ENABLED   */
-/* #define HAL_SRAM_MODULE_ENABLED     */
-/* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED     */
-/* #define HAL_I2C_MODULE_ENABLED      */
-/* #define HAL_SMBUS_MODULE_ENABLED    */
-/* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */
-/* #define HAL_LTDC_MODULE_ENABLED     */
-/* #define HAL_DSI_MODULE_ENABLED      */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED      */
-/* #define HAL_RTC_MODULE_ENABLED      */
-/* #define HAL_SAI_MODULE_ENABLED      */
-/* #define HAL_SD_MODULE_ENABLED       */
-// #define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED      */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */
-/* #define HAL_IRDA_MODULE_ENABLED     */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED      */
-/* #define HAL_HCD_MODULE_ENABLED      */
-/* #define HAL_FMPI2C_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED  */
-/* #define HAL_DFSDM_MODULE_ENABLED    */
-/* #define HAL_LPTIM_MODULE_ENABLED    */
-/* #define HAL_MMC_MODULE_ENABLED      */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* LAN8742A_PHY_ADDRESS Address*/
-#define LAN8742A_PHY_ADDRESS           0U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-#define PHY_ISFR                        ((uint16_t)0x001DU)    /*!< PHY Interrupt Source Flag register Offset   */
-#define PHY_ISFR_INT4                   ((uint16_t)0x000BU)  /*!< PHY Link down inturrupt       */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 025f6a08c..665ea114a 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -180,11 +180,14 @@ void board_init(void) {
 #endif
 
 #if CFG_TUD_ENABLED
-  board_vbus_sense_init(BOARD_TUD_RHPORT);
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(BOARD_TUD_RHPORT, TUD_CFGID_DWC2, &cfg);
+  board_vbus_set(BOARD_TUD_RHPORT, false);
 #endif
 
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUD_RHPORT, true);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 }
 
@@ -248,7 +251,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index c3c41dc3f..f3e74ecea 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -71,6 +71,7 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
+	$(TOP)/hw/bsp/stm32$(ST_FAMILY) \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
index 35102c1f2..ca9641c68 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
@@ -41,7 +41,7 @@
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_HS_VBUS_SENSE     1
 
 #define PINID_LED      0
 #define PINID_BUTTON   1
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
index 2964ebada..f57ffb317 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
@@ -40,8 +40,8 @@
 #define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
 
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     0
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     1
 
 #define PINID_LED      0
 #define PINID_BUTTON   1
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index ac22c606f..ce9049abe 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -154,18 +154,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   //------------- rhport1: OTG_HS -------------//
 #ifdef USB_HS_PHYC
   // MCU with built-in HS PHY such as F723, F733, F730
@@ -178,9 +174,6 @@ void board_init(void) {
   GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
-  // Enable HS VBUS sense (B device) via pin PB13
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
   /* Configure OTG-HS ID pin */
   GPIO_InitStruct.Pin       = GPIO_PIN_13;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;
@@ -243,17 +236,16 @@ void board_init(void) {
   __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
   __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
 
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
 #endif
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
   // Turn on host vbus
 #if CFG_TUH_ENABLED
   board_vbus_set(BOARD_TUH_RHPORT, true);
@@ -320,7 +312,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index 4b175b0ec..b25897264 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -181,7 +181,7 @@ void SysTick_Handler(void) {
   HAL_IncTick();
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index d8afa0f95..2e13a1d4b 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -211,7 +211,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c
index fdb12e44f..1e8acd502 100644
--- a/hw/bsp/stm32h5/family.c
+++ b/hw/bsp/stm32h5/family.c
@@ -207,7 +207,7 @@ void SysTick_Handler(void) {
   HAL_IncTick();
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 96bfc24e1..d2f61a5ce 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -44,7 +44,7 @@
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_HS_VBUS_SENSE     1
 
 // USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
 #define ULPI_PINS \
@@ -120,13 +120,13 @@ static inline void SystemClock_Config(void) {
   // From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals
   // are shared with other peripherals. Trace CLK = PLL1R.
   RCC_OscInitStruct.PLL.PLLM = 5;
-  RCC_OscInitStruct.PLL.PLLN = 160;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 4;
-  RCC_OscInitStruct.PLL.PLLR = 6; // Trace clock is 400/6 = 66.67 MHz (larger than 50 MHz but work well)
+  RCC_OscInitStruct.PLL.PLLN      = 160; // May reduce to 100/200 Mhz when tracing to avoid overflowing trace buffer
+  RCC_OscInitStruct.PLL.PLLP      = 2;
+  RCC_OscInitStruct.PLL.PLLQ      = 4;
+  RCC_OscInitStruct.PLL.PLLR      = RCC_OscInitStruct.PLL.PLLN/10;  // Trace clock is limit to 50 Mhz to meet board requirement
+  RCC_OscInitStruct.PLL.PLLRGE    = RCC_PLL1VCIRANGE_2;
   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
   RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
 
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
index 0e5a4cc00..a2e11012f 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
@@ -193,8 +193,8 @@ Mcu.PinsNb=169
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H743XIHx
-MxCube.Version=6.10.0
-MxDb.Version=DB.6.0.100
+MxCube.Version=6.12.1
+MxDb.Version=DB.6.0.121
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
 NVIC.ForceEnableDMAVector=true
@@ -880,12 +880,12 @@ ProjectManager.CustomerFirmwarePackage=
 ProjectManager.DefaultFWLocation=true
 ProjectManager.DeletePrevious=true
 ProjectManager.DeviceId=STM32H743XIHx
-ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.2
 ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=false
+ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=2
 ProjectManager.MainLocation=Src
 ProjectManager.NoMain=false
@@ -933,8 +933,8 @@ RCC.DIVQ1Freq_Value=200000000
 RCC.DIVQ2Freq_Value=50390625
 RCC.DIVQ3=7
 RCC.DIVQ3Freq_Value=48000000
-RCC.DIVR1=6
-RCC.DIVR1Freq_Value=133333333.33333333
+RCC.DIVR1=8
+RCC.DIVR1Freq_Value=100000000
 RCC.DIVR2Freq_Value=50390625
 RCC.DIVR3Freq_Value=168000000
 RCC.EnbaleCSS=true
@@ -979,7 +979,7 @@ RCC.SYSCLKFreq_VALUE=400000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.Tim1OutputFreq_Value=200000000
 RCC.Tim2OutputFreq_Value=200000000
-RCC.TraceFreq_Value=133333333.33333333
+RCC.TraceFreq_Value=100000000
 RCC.USART16Freq_Value=100000000
 RCC.USART234578Freq_Value=100000000
 RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
index 0ab078319..32a8155c1 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
@@ -9,6 +9,10 @@
 **********************************************************************
 */
 void OnProjectLoad (void) {
+   Project.SetTraceSource ("Trace Pins");
+  Project.SetTraceTiming (100, 100, 100, 100);
+  Project.SetSWO (0);
+  Edit.SysVar (VAR_TRACE_CORE_CLOCK, 200000000);
   Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
   Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
   Project.AddSvdFile ("./STM32H743.svd");
@@ -18,12 +22,8 @@ void OnProjectLoad (void) {
   Project.SetTargetIF ("SWD");
   Project.SetTIFSpeed ("50 MHz");
 
-  Project.SetTraceSource ("Trace Pins");
-  Project.SetTracePortWidth (4);
-  // timing delay for trace pins in pico seconds, default is 2 nano seconds
-  Project.SetTraceTiming (100, 100, 100, 100);
-
   File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf");
+  // File.Open ("../../../../../../examples/cmake-build-stm32h743eval_host1/host/cdc_msc_hid/cdc_msc_hid.elf");
 }
 
 /*********************************************************************
diff --git a/hw/bsp/stm32h7/boards/stm32h747disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h747disco/board.cmake
new file mode 100644
index 000000000..8bce542a5
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h747disco/board.cmake
@@ -0,0 +1,23 @@
+set(MCU_VARIANT stm32h747xx)
+set(JLINK_DEVICE stm32h747xi_m7)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_CM7.icf)
+
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H747xx
+    HSE_VALUE=25000000
+    CORE_CM7
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h747disco/board.h b/hw/bsp/stm32h7/boards/stm32h747disco/board.h
new file mode 100644
index 000000000..458aa48b6
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h747disco/board.h
@@ -0,0 +1,169 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: STM32 H745 Discovery
+   url: https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// UART
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     1
+
+// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
+#define ULPI_PINS \
+  {GPIOA, GPIO_PIN_3 }, {GPIOA, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_0 }, {GPIOB, GPIO_PIN_1 }, \
+  {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \
+  {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11}
+
+#define PINID_LED      0
+#define PINID_BUTTON   1
+#define PINID_UART_TX  2
+#define PINID_UART_RX  3
+
+static board_pindef_t board_pindef[] = {
+  { // LED
+    .port = GPIOI,
+    .pin_init = { .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 0
+  },
+  { // Button
+    .port = GPIOC,
+    .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 },
+    .active_state = 1
+  },
+  { // UART TX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  },
+  { // UART RX
+    .port = GPIOA,
+    .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 },
+    .active_state = 0
+  }
+};
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
+
+  /*!< Supply configuration update enable */
+  /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
+  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+
+  /* The voltage scaling allows optimizing the power consumption when the
+     device is clocked below the maximum system frequency, to update the
+     voltage scaling value regarding system frequency refer to product
+     datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+  /* PLL1 for System Clock */
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 160;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure  bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
+  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /*activate CSI clock mondatory for I/O Compensation Cell*/
+  __HAL_RCC_CSI_ENABLE() ;
+
+  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
+  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+
+  /* Enables the I/O Compensation Cell */
+  HAL_EnableCompensationCell();
+}
+
+static inline void board_init2(void) {
+  // For this board does nothing
+}
+
+void board_vbus_set(uint8_t rhport, bool state) {
+  (void) rhport;
+  (void) state;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/stm32h747disco/board.mk b/hw/bsp/stm32h7/boards/stm32h747disco/board.mk
new file mode 100644
index 000000000..4b17246e2
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h747disco/board.mk
@@ -0,0 +1,15 @@
+# STM32H747I-DISCO uses OTG_FS
+# FIXME: Reset enumerates, un/replug USB plug does not enumerate
+MCU_VARIANT = stm32h747xx
+CFLAGS += -DSTM32H747xx -DCORE_CM7 -DHSE_VALUE=25000000
+
+# Default is FulSpeed port
+PORT ?= 0
+
+LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash_CM7.ld
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h747xi_m7
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 054d7855f..c94c2e755 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -139,6 +139,10 @@ void board_init(void) {
   #endif
 
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+  // Disable SysTick before kernel entry; _tx_initialize_low_level() will re-configure it
+  SysTick->CTRL &= ~1UL;
 #endif
 
   GPIO_InitTypeDef GPIO_InitStruct;
@@ -180,18 +184,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   //------------- USB HS -------------//
 #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
   // Despite being call USB2_OTG
@@ -216,28 +216,24 @@ void board_init(void) {
   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
   __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
 
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+  #if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
+  #endif
 #endif
 
   HAL_PWREx_EnableUSBVoltageDetector();
 
   board_init2(); // optional init
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
+  // Turn on host vbus
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUH_RHPORT, 1);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 
 }
@@ -303,10 +299,15 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+// Keep HAL_GetTick() working for HAL functions called from board_init()
+void osal_threadx_tick_cb(void) {
+  HAL_IncTick();
+}
 #endif
 
 void HardFault_Handler(void) {
diff --git a/hw/bsp/stm32h7/linker/stm32h747xx_flash_CM7.ld b/hw/bsp/stm32h7/linker/stm32h747xx_flash_CM7.ld
new file mode 100644
index 000000000..5b7fe4528
--- /dev/null
+++ b/hw/bsp/stm32h7/linker/stm32h747xx_flash_CM7.ld
@@ -0,0 +1,184 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**
+**  Abstract    : Linker script for STM32H7 series
+**                1024Kbytes FLASH and 192Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab :
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+  .ARM :
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
index 7b3456585..189c175dd 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
@@ -2,6 +2,8 @@ set(MCU_VARIANT stm32h7s3xx)
 set(JLINK_DEVICE stm32h7s3l8)
 
 set(LD_FILE_Clang ${LD_FILE_GNU})
+set(RHPORT_DEVICE 1)
+set(RHPORT_HOST 1)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
index 4fb72cce8..4b8564709 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
@@ -44,7 +44,7 @@
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
 
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
+#define OTG_FS_VBUS_SENSE     0
 #define OTG_HS_VBUS_SENSE     0
 
 #define PINID_LED      0
@@ -62,7 +62,7 @@ static board_pindef_t board_pindef[] = {
   { // Button
     .port = GPIOC,
     .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 },
-    .active_state = 1
+    .active_state = 0
   },
   { // UART TX
     .port = GPIOD,
diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c
index 784c92465..3bf75ba97 100644
--- a/hw/bsp/stm32h7rs/family.c
+++ b/hw/bsp/stm32h7rs/family.c
@@ -356,17 +356,14 @@ void board_init(void) {
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+#endif // vbus sense
 
-  // Enable VBUS sense (B device) via pin PM14
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device)
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
 #endif
 
   //------------- USB HS -------------//
@@ -382,33 +379,31 @@ void board_init(void) {
 
 #if OTG_HS_VBUS_SENSE
   // Configure VBUS Pin
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PM9
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+  GPIO_InitTypeDef GPIO_InitStruct2;
+  GPIO_InitStruct2.Pin = GPIO_PIN_8;
+  GPIO_InitStruct2.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct2.Pull = GPIO_NOPULL;
+  GPIO_InitStruct2.Alternate = GPIO_AF10_OTG_HS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct2);
+#endif
 
 #if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
-#else
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
 #endif
 
 #endif
-#endif
 
   board_init2();
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
+  // Turn on host vbus
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUH_RHPORT, 1);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 }
 
@@ -473,7 +468,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake
index 1fd1cb057..3b9dbf5cf 100644
--- a/hw/bsp/stm32h7rs/family.cmake
+++ b/hw/bsp/stm32h7rs/family.cmake
@@ -24,7 +24,7 @@ if (NOT DEFINED RHPORT_DEVICE)
   set(RHPORT_DEVICE 1)
 endif ()
 if (NOT DEFINED RHPORT_HOST)
-  set(RHPORT_HOST 1)
+  set(RHPORT_HOST 0)
 endif ()
 
 if (NOT DEFINED RHPORT_SPEED)
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index 6aeab1259..7fd076dbd 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -123,7 +123,8 @@ void board_init(void) {
 //--------------------------------------------------------------------+
 
 void board_led_write(bool state) {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void) {
@@ -168,7 +169,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
index 8c766d8ea..cf84d3e66 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_5
 #define UART_RX_PIN           GPIO_PIN_6
 
+#define VBUS_SENSE_EN         0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -128,15 +130,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
-  // Disable VBUS Sense and force device mode
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
index 607210cec..3b031e00f 100644
--- a/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
@@ -52,6 +52,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -145,12 +147,6 @@ static inline void board_clock_init(void)
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
index f522e7522..94978638e 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -129,12 +131,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
index c181f5d4a..f603ae855 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -129,12 +131,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index e69ae8e3b..c87b643b8 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -170,10 +170,16 @@ void board_init(void) {
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 #endif
 
-  /* Enable USB FS Clocks */
 #if defined(USB_OTG_FS)
+  /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-  board_vbus_sense_init();
+
+  #if CFG_TUD_ENABLED
+  /* Set Vbus sense */
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+  #endif
 #else
   __HAL_RCC_USB_CLK_ENABLE();
 #endif
@@ -225,7 +231,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake b/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
index e88efefb9..00efc974c 100644
--- a/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
+++ b/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT stm32n657xx)
-set(JLINK_DEVICE stm32n6xx)
+set(JLINK_DEVICE stm32n657x0)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
 
diff --git a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
index bbcad6340..8c2ec66dc 100644
--- a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
+++ b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
@@ -44,17 +44,16 @@ extern "C" {
 #define UART_DEV USART1
 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
 
-#define BOARD_TUD_RHPORT 1
-
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 1
+#define OTG_FS_VBUS_SENSE 0
+#define OTG_HS_VBUS_SENSE 0
 
 #define PINID_LED 0
 #define PINID_BUTTON 1
 #define PINID_UART_TX 2
 #define PINID_UART_RX 3
 #define PINID_TCPP0203_EN 4
+#define PINID_PWR_USB2 8
 
 static board_pindef_t board_pindef[] = {
     {// LED
@@ -77,21 +76,22 @@ static board_pindef_t board_pindef[] = {
      .port = GPIOA,
      .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
      .active_state = 0},
-    {
-        // I2C SCL for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    { // I2C SCL for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // I2C SDA for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SDA for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // INT for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    {// INT for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
     },
+    {// PWR for USB2
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    }
 };
 
 //--------------------------------------------------------------------+
@@ -262,9 +262,12 @@ static inline void board_init2(void) {
 }
 
 void board_vbus_set(uint8_t rhport, bool state) {
-  (void) state;
-  if (rhport == 1) {
-    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  if (rhport == 0) {
+    uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
+  } else if (rhport == 1) {
+    board_pindef_t *pindef = &board_pindef[PINID_PWR_USB2];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state ? GPIO_PIN_SET : GPIO_PIN_RESET);
   }
 }
 
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
index e88efefb9..e682cabcb 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
@@ -1,8 +1,15 @@
 set(MCU_VARIANT stm32n657xx)
-set(JLINK_DEVICE stm32n6xx)
+set(JLINK_DEVICE stm32n657x0)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
 
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32N657xx
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
index 33c68f7cf..5bdbaff3c 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
@@ -44,11 +44,9 @@ extern "C" {
 #define UART_DEV USART1
 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
 
-#define BOARD_TUD_RHPORT 1
-
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 1
+#define OTG_FS_VBUS_SENSE 0
+#define OTG_HS_VBUS_SENSE 0
 
 #define PINID_LED 0
 #define PINID_BUTTON 1
@@ -77,20 +75,17 @@ static board_pindef_t board_pindef[] = {
      .port = GPIOA,
      .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
      .active_state = 0},
-    {
-        // I2C SCL for TCPP0203
-        .port = GPIOB,
-        .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SCL for TCPP0203
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // I2C SDA for TCPP0203
-        .port = GPIOB,
-        .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SDA for TCPP0203
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // INT for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    {// INT for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
     },
 };
 
@@ -262,9 +257,9 @@ static inline void board_init2(void) {
 }
 
 void board_vbus_set(uint8_t rhport, bool state) {
-  (void) state;
-  if (rhport == 1) {
-    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  if (rhport == 0) {
+    uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
   }
 }
 
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
index 05717699c..efbb82611 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
@@ -1,9 +1,12 @@
 MCU_VARIANT = stm32n657xx
 CFLAGS += -DSTM32N657xx
-JLINK_DEVICE = stm32n6xx
+JLINK_DEVICE = stm32n657x0
 
 LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
 
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
 # flash target using on-board stlink
 flash: flash-stlink
 
diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c
index 567bb7294..4354616c3 100644
--- a/hw/bsp/stm32n6/family.c
+++ b/hw/bsp/stm32n6/family.c
@@ -48,7 +48,8 @@
 TU_ATTR_UNUSED static void Error_Handler(void) { }
 
 void HardFault_Handler(void);
-
+static void MPU_Config(void);
+static void SystemIsolation_Config(void);
 typedef struct {
   GPIO_TypeDef* port;
   GPIO_InitTypeDef pin_init;
@@ -87,20 +88,25 @@ static UART_HandleTypeDef UartHandle = {
 // Despite being call USB2_OTG_FS on some MCUs
 // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
 void USB2_OTG_HS_IRQHandler(void) {
-  tusb_int_handler(0, true);
+  tusb_int_handler(1, true);
 }
 
 // Despite being call USB1_OTG_HS on some MCUs
 // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
 void USB1_OTG_HS_IRQHandler(void) {
-  tusb_int_handler(1, true);
+  tusb_int_handler(0, true);
 }
 
 void board_init(void) {
-
   /* Enable BusFault and SecureFault handlers (HardFault is default) */
   SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
 
+  MPU_Config();
+  SystemIsolation_Config();
+
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
   HAL_PWREx_EnableVddA();
   HAL_PWREx_EnableVddIO2();
   HAL_PWREx_EnableVddIO3();
@@ -126,8 +132,6 @@ void board_init(void) {
   __HAL_RCC_GPIOP_CLK_ENABLE();
   __HAL_RCC_GPIOQ_CLK_ENABLE();
 
-  // HAL_ICACHE_Enable();
-
   for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
     HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
   }
@@ -155,7 +159,7 @@ void board_init(void) {
   HAL_UART_Init(&UartHandle);
 #endif
 
-
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
   __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
   __HAL_RCC_PWR_CLK_ENABLE();
   HAL_PWREx_EnableVddUSBVMEN();
@@ -196,11 +200,109 @@ void board_init(void) {
   /* Peripheral PHY clock enable */
   __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
 
-  board_init2();
+#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0
+  board_vbus_set(BOARD_TUH_RHPORT, 1);
+#endif
+#endif
+
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+  __HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWREx_EnableVddUSBVMEN();
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
+  HAL_PWREx_EnableVddUSB();
+
+  LL_AHB5_GRP1_ForceReset(0x00800000);
+  __HAL_RCC_USB2_OTG_HS_FORCE_RESET();
+  __HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET();
+
+  LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
+  LL_AHB5_GRP1_ReleaseReset(0x00800000);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
+
+  /* Required few clock cycles before accessing USB PHY Controller Registers */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  USB2_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
+
+  USB2_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
+                              (0x2 << 4)  |
+                              (0x1 << 2)  |
+                                0x1U;
+
+  __HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET();
+
+  /* Required few clock cycles before Releasing Reset */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  __HAL_RCC_USB2_OTG_HS_RELEASE_RESET();
+
+  /* Peripheral PHY clock enable */
+  __HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE();
 
-#if CFG_TUH_ENABLED
+#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1
   board_vbus_set(BOARD_TUH_RHPORT, 1);
 #endif
+#endif
+
+  board_init2();
+}
+
+static void MPU_Config(void)
+{
+  MPU_Region_InitTypeDef default_config = {0};
+  MPU_Attributes_InitTypeDef attr_config = {0};
+  uint32_t primask_bit = __get_PRIMASK();
+  __disable_irq();
+
+  /* disable the MPU */
+  HAL_MPU_Disable();
+
+  /* create an attribute configuration for the MPU */
+  attr_config.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
+  attr_config.Number = MPU_ATTRIBUTES_NUMBER0;
+
+  HAL_MPU_ConfigMemoryAttributes(&attr_config);
+
+  /* Create a non cacheable region */
+  /*Normal memory type, code execution allowed */
+  default_config.Enable = MPU_REGION_ENABLE;
+  default_config.Number = MPU_REGION_NUMBER0;
+  default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
+  default_config.LimitAddress =  __NON_CACHEABLE_SECTION_END;
+  default_config.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+  default_config.AccessPermission = MPU_REGION_ALL_RW;
+  default_config.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+  default_config.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
+  HAL_MPU_ConfigRegion(&default_config);
+
+  /* enable the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+  /* Exit critical section to lock the system and avoid any issue around MPU mechanisme */
+  __set_PRIMASK(primask_bit);
+}
+
+static void SystemIsolation_Config(void) {
+  /* set all required IPs as secure privileged */
+  __HAL_RCC_RIFSC_CLK_ENABLE();
+  RIMC_MasterConfig_t RIMC_master = {0};
+  RIMC_master.MasterCID = RIF_CID_1;
+  RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
+
+  /*RIMC configuration*/
+  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG1, &RIMC_master);
+  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG2, &RIMC_master);
+
+  /*RISUP configuration*/
+  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG1HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
+  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG2HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
 }
 
 //--------------------------------------------------------------------+
@@ -264,7 +366,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake
index 6c7aaea61..972138018 100644
--- a/hw/bsp/stm32n6/family.cmake
+++ b/hw/bsp/stm32n6/family.cmake
@@ -21,7 +21,7 @@ set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
 # Port & Speed Selection
 # ----------------------
 if (NOT DEFINED RHPORT_DEVICE)
-  set(RHPORT_DEVICE 1)
+  set(RHPORT_DEVICE 0)
 endif ()
 if (NOT DEFINED RHPORT_HOST)
   set(RHPORT_HOST 1)
@@ -68,6 +68,7 @@ function(family_add_board BOARD_TARGET)
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rif.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@@ -80,8 +81,8 @@ function(family_add_board BOARD_TARGET)
     BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
     BOARD_TUH_RHPORT=${RHPORT_HOST}
     BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
-    SEGGER_RTT_SECTION="noncacheable_buffer"
-    BUFFER_SIZE_UP=0x3000
+    SEGGER_RTT_SECTION=".noncacheable"
+    BUFFER_SIZE_UP=0x4000
     )
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk
index 45554e251..9fef533b1 100644
--- a/hw/bsp/stm32n6/family.mk
+++ b/hw/bsp/stm32n6/family.mk
@@ -12,7 +12,7 @@ CPU_CORE ?= cortex-m55
 # ----------------------
 # Port & Speed Selection
 # ----------------------
-RHPORT_DEVICE ?= 1
+RHPORT_DEVICE ?= 0
 RHPORT_HOST ?= 1
 
 ifndef RHPORT_DEVICE_SPEED
@@ -32,8 +32,8 @@ CFLAGS += \
 	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
 	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
 	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-	-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-	-DBUFFER_SIZE_UP=0x3000 \
+	-DSEGGER_RTT_SECTION="\".noncacheable\"" \
+	-DBUFFER_SIZE_UP=0x4000 \
 
 # GCC Flags
 CFLAGS_GCC += \
diff --git a/hw/bsp/stm32n6/setup_iar.mac b/hw/bsp/stm32n6/setup_iar.mac
new file mode 100644
index 000000000..b6f2bc97a
--- /dev/null
+++ b/hw/bsp/stm32n6/setup_iar.mac
@@ -0,0 +1,12 @@
+/* Called once after the target reset. */
+execUserReset()
+{
+    /* Re-load image as AIXRAM2 is erased after CPU reset */
+    __loadImage("$EXE_DIR$\\$TARGET_BNAME$.hex", 0, 0);
+
+    __restoreSoftwareBreakpoints();
+
+     #PC = __readMemory32(0x34180404, "Memory");
+
+     #SP = 0x341FFD00;
+}
diff --git a/hw/bsp/stm32n6/stm32n6.jdebug b/hw/bsp/stm32n6/stm32n6.jdebug
new file mode 100644
index 000000000..81490db5d
--- /dev/null
+++ b/hw/bsp/stm32n6/stm32n6.jdebug
@@ -0,0 +1,362 @@
+/*********************************************************************
+*                 (c) SEGGER Microcontroller GmbH                    *
+*                      The Embedded Experts                          *
+*                         www.segger.com                             *
+**********************************************************************
+
+File          :
+Created       : 31. Jan 2026 16:34
+Ozone Version : V3.40e
+*/
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  //
+  // Dialog-generated settings
+  //
+  Project.SetDevice ("STM32N657X0");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("4 MHz");
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M55F.svd");
+  //
+  // User settings
+  //
+  File.Open ("$(ProjectDir)/../../../examples/device/cdc_msc/build/stm32n6570dk/RelWithDebInfo/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*       OnStartupComplete
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//  //
+//  // Set up initial stack pointer
+//  //
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//  }
+//  //
+//  // Set up entry point PC
+//  //
+//  PC = Elf.GetEntryPointPC();
+//
+//  if (PC != 0xFFFFFFFF) {
+//    Target.SetReg("PC", PC);
+//  } else if (VectorTableAddr != 0xFFFFFFFF) {
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  } else {
+//    Util.Error("Project file error: failed to set entry point PC", 1);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  //_SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterProjectLoad
+*
+* Function description
+*   After Project load routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterProjectLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnDebugStartBreakSymbolReached
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the symbol to be breaked at during debug start. Optional.
+*
+**********************************************************************
+*/
+//void OnDebugStartBreakSymReached (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+	Debug.Download();
+  Debug.Halt();
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  //
+  // Set up initial stack pointer
+  //
+  SP = Target.ReadU32(VectorTableAddr);
+  if (SP != 0xFFFFFFFF) {
+    Target.SetReg("SP", SP);
+  }
+  //
+  // Set up entry point PC
+  //
+  PC = Elf.GetEntryPointPC();
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else {
+    Util.Error("Project script error: failed to set up entry point PC", 1);
+  }
+}
diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
index 00cb31159..49ca767fe 100644
--- a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
+++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
@@ -67,7 +67,7 @@
 /*#define HAL_PKA_MODULE_ENABLED      */
 /*#define HAL_PSSI_MODULE_ENABLED     */
 /*#define HAL_RAMCFG_MODULE_ENABLED   */
-/*#define HAL_RIF_MODULE_ENABLED      */
+#define HAL_RIF_MODULE_ENABLED
 /*#define HAL_RNG_MODULE_ENABLED      */
 /*#define HAL_RTC_MODULE_ENABLED      */
 /*#define HAL_SAI_MODULE_ENABLED      */
diff --git a/hw/bsp/stm32u0/family.c b/hw/bsp/stm32u0/family.c
index 50b513d8f..0f91d1f30 100644
--- a/hw/bsp/stm32u0/family.c
+++ b/hw/bsp/stm32u0/family.c
@@ -174,7 +174,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
index cf3f63ea5..c99743738 100644
--- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
@@ -55,6 +55,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -110,6 +112,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
index 0c3439b2c..eb2b63721 100644
--- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
@@ -110,6 +110,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
index b11f6a747..cce3e38b3 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -56,6 +56,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -111,6 +113,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
index be037b68a..b6b60f021 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -37,6 +37,8 @@ extern "C"
 {
 #endif
 
+#include "stm32u5xx_ll_tim.h"
+
 // LED GREEN
 #define LED_PORT GPIOC
 #define LED_PIN GPIO_PIN_7
@@ -55,6 +57,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_7
 #define UART_RX_PIN GPIO_PIN_8
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -110,6 +114,104 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+  /* ADC config */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+  PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  __HAL_RCC_ADC12_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  GPIO_InitStruct.Pin = GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  ADC_HandleTypeDef hadc1;
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_14B;
+  hadc1.Init.GainCompensation = 0;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  HAL_NVIC_EnableIRQ(ADC1_IRQn);
+
+  /* TIM1 init for TRGO */
+  __HAL_RCC_TIM1_CLK_ENABLE();
+  TIM_HandleTypeDef htim1;
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 159;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 999;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
+
+  HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
+  HAL_ADC_Start_IT(&hadc1);
+  HAL_TIM_Base_Start(&htim1);
+}
+
+void ADC1_IRQHandler(void) {
+  if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
+    /* Clear flag ADC group regular end of unitary conversion */
+    LL_ADC_ClearFlag_EOC(ADC1);
+    /* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
+     * with R1 = 330kOhm and R2 = 50kOhm
+     */
+    const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
+    if((ADC1->DR > threshold) && (USB_OTG_FS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
+      USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+    } else {
+      USB_OTG_FS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
+    }
+  }
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+  }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
index 0785fb36b..15106aee6 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -37,6 +37,8 @@ extern "C"
 {
 #endif
 
+#include "stm32u5xx_ll_tim.h"
+
 // LED GREEN
 #define LED_PORT GPIOC
 #define LED_PIN GPIO_PIN_7
@@ -55,11 +57,13 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static void SystemClock_Config(void) {
+static inline void SystemClock_Config(void) {
   RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
   RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
 
@@ -128,7 +132,7 @@ static void SystemClock_Config(void) {
   }
 }
 
-static void SystemPower_Config(void) {
+static inline void SystemPower_Config(void) {
   HAL_PWREx_EnableVddIO2();
 
   /*
@@ -141,7 +145,105 @@ static void SystemPower_Config(void) {
 /* USER CODE END PWR */
 }
 
+static inline void board_vbus_sense_init(void) {
+  /* ADC config */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+  PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  __HAL_RCC_ADC12_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  GPIO_InitStruct.Pin = GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  ADC_HandleTypeDef hadc1;
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_14B;
+  hadc1.Init.GainCompensation = 0;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
+
+  /* TIM1 init for TRGO */
+  __HAL_RCC_TIM1_CLK_ENABLE();
+  TIM_HandleTypeDef htim1;
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 159;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 999;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
+
+  HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
+  HAL_ADC_Start_IT(&hadc1);
+  HAL_TIM_Base_Start(&htim1);
+}
 
+void ADC1_2_IRQHandler(void) {
+  if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
+    /* Clear flag ADC group regular end of unitary conversion */
+    LL_ADC_ClearFlag_EOC(ADC1);
+    /* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
+     * with R1 = 330kOhm and R2 = 50kOhm
+     */
+    const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
+    if((ADC1->DR > threshold) && (USB_OTG_HS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
+      USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+      USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+    } else {
+      USB_OTG_HS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
+      USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
+    }
+  }
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+  }
+}
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 26d72d6a0..55ca25d58 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -179,18 +179,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  #else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
   #endif // vbus sense
 
+#if CFG_TUD_ENABLED
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
@@ -218,13 +214,15 @@ void board_init(void) {
   /*Configuring the SYSCFG registers OTG_HS PHY*/
   HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#if CFG_TUD_ENABLED
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 #endif // USB_OTG_FS
+
+  /* Non-standard VBus sense settings */
+  board_vbus_sense_init();
 }
 
 //--------------------------------------------------------------------+
@@ -272,7 +270,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 58dc63ae3..3d23c554d 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -45,6 +45,9 @@ function(family_add_board BOARD_TARGET)
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@@ -96,7 +99,7 @@ function(family_configure_example TARGET RTOS)
   endif ()
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
+    set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes -Wno-self-assign")
   endif ()
   set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
     SKIP_LINTING ON
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 47aed10a9..3dab8c610 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -16,6 +16,7 @@ CFLAGS_GCC += \
   -Wno-error=undef \
   -Wno-error=unused-parameter \
   -Wno-error=type-limits \
+  -Wno-self-assign \
 
 ifeq ($(TOOLCHAIN),gcc)
 CFLAGS_GCC += -Wno-error=maybe-uninitialized
@@ -35,11 +36,15 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c
 
 ifneq ($(filter stm32u545xx stm32u535xx,$(MCU_VARIANT)),)
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c \
 	src/portable/st/stm32_fsdev/fsdev_common.c
 else
 SRC_C += \
diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
index 87c3683de..5d95862f6 100644
--- a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
+++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
@@ -36,7 +36,7 @@
 
 #define HAL_MODULE_ENABLED
 
-/*#define HAL_ADC_MODULE_ENABLED */
+#define HAL_ADC_MODULE_ENABLED
 /*#define HAL_MDF_MODULE_ENABLED */
 /*#define HAL_COMP_MODULE_ENABLED */
 /*#define HAL_CORDIC_MODULE_ENABLED */
@@ -76,7 +76,7 @@
 /*#define HAL_SMBUS_MODULE_ENABLED */
 /*#define HAL_SPI_MODULE_ENABLED */
 /*#define HAL_SRAM_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
 /*#define HAL_TSC_MODULE_ENABLED */
 /*#define HAL_RAMCFG_MODULE_ENABLED */
 #define HAL_UART_MODULE_ENABLED
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index 153d10a09..de503c072 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -174,7 +174,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c
index 8dc6547ae..878355b48 100644
--- a/hw/bsp/stm32wba/family.c
+++ b/hw/bsp/stm32wba/family.c
@@ -172,17 +172,13 @@ void board_init(void) {
 
   // Configuring the SYSCFG registers OTG_HS PHY
   SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
-
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
-  #endif // USB_OTG_FS
+  #endif // USB_OTG_HS
 }
 
-void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); }
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
 
 uint32_t board_button_read(void) { return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE; }
 
@@ -205,7 +201,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) { return system_ticks; }
+uint32_t tusb_time_millis_api(void) { return system_ticks; }
 #endif
 
 void HardFault_Handler(void) { asm( "bkpt 1" ); }
diff --git a/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h
index 454b085e9..b4423e269 100644
--- a/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/tm4c/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,7 +44,13 @@
 
 // skip if included from IAR assembler
 #ifndef __IASMARM__
-  #include "TM4C123.h"
+  #ifdef TM4C123GH6PM
+    #include "TM4C123.h"
+  #elif TM4C1294NCPDT
+    #include "TM4C129.h"
+  #else
+      #error "Unknown TM4C device"
+  #endif
 #endif
 
 /* Cortex M23/M33 port configuration. */
diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
index c0ceb4cd8..fc0ab4c60 100644
--- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h
@@ -36,20 +36,26 @@
  extern "C" {
 #endif
 
+#include "TM4C123.h"
+
 #define BOARD_UART            UART0
 #define BOARD_UART_PORT       GPIOA
 
+#define BTN_PORT_CLK          5
 #define BOARD_BTN_PORT        GPIOF
 #define BOARD_BTN             4
 #define BOARD_BTN_Msk         (1u<<4)
 #define BUTTON_STATE_ACTIVE   0
 
+#define LED_PORT_CLK          5
 #define LED_PORT              GPIOF
 #define LED_PIN_RED           1
 #define LED_PIN_BLUE          2
 #define LED_PIN_GREEN         3
 #define LED_STATE_ON          1
 
+#define BOARD_LED_PIN         LED_PIN_BLUE
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
index 11e9608cc..3f06d8f03 100644
--- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
@@ -17,7 +17,7 @@ SECTIONS
     .text :
     {
         . = ALIGN(4) ;
-        *(.vectors)
+        KEEP(*(.vectors))
         *(.text)
         *(.text.*)
         *(.init)
diff --git a/hw/bsp/tm4c/boards/ek_tm4c1294xl/TM4C1294NC.icf b/hw/bsp/tm4c/boards/ek_tm4c1294xl/TM4C1294NC.icf
new file mode 100644
index 000000000..2dba41866
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c1294xl/TM4C1294NC.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x000FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2003FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x8000;
+define symbol __ICFEDIT_size_heap__     = 0x10000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.cmake b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.cmake
new file mode 100644
index 000000000..3e03b3f72
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_SUB_VARIANT 129)
+
+set(JLINK_DEVICE TM4C1294NCPDT)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/tm4c1294nc.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/TM4C1294NC.icf)
+
+set(OPENOCD_OPTION "-f board/ti_ek-tm4c1294xl.cfg")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    TM4C1294NCPDT
+    )
+endfunction()
diff --git a/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.h b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.h
new file mode 100644
index 000000000..4530e9430
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.h
@@ -0,0 +1,75 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: TM4C1294 LaunchPad
+   url: https://www.ti.com/tool/EK-TM4C1294XL
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "TM4C129.h"
+
+#define BOARD_UART            UART0
+#define BOARD_UART_PORT       GPIOA
+
+#define BTN_PORT_CLK          8
+#define BOARD_BTN_PORT        GPIOJ
+#define BOARD_BTN             0
+#define BOARD_BTN_Msk         (1u<<0)
+#define BUTTON_STATE_ACTIVE   0
+
+#define LED_PORT_CLK          12
+#define LED_PORT              GPION
+#define LED_PIN_1             1
+#define LED_PIN_2             0
+#define LED_STATE_ON          1
+
+#define BOARD_LED_PIN         LED_PIN_2
+
+#define GPIOA                 GPIOA_AHB
+#define GPIOB                 GPIOB_AHB
+#define GPIOC                 GPIOC_AHB
+#define GPIOD                 GPIOD_AHB
+#define GPIOE                 GPIOE_AHB
+#define GPIOF                 GPIOF_AHB
+#define GPIOG                 GPIOG_AHB
+#define GPIOH                 GPIOH_AHB
+#define GPIOI                 GPIOI_AHB
+#define GPIOJ                 GPIOJ_AHB
+
+#define GPIOA_Type            GPIOA_AHB_Type
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.mk b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.mk
new file mode 100644
index 000000000..b01977674
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c1294xl/board.mk
@@ -0,0 +1,16 @@
+MCU_SUB_VARIANT = 129
+
+CFLAGS += -DTM4C1294NCPDT
+
+LD_FILE_GCC = $(BOARD_PATH)/tm4c1294nc.ld
+LD_FILE_IAR = $(BOARD_PATH)/TM4C1294NC.icf
+
+# For flash-jlink target
+JLINK_DEVICE = TM4C1294NCPDT
+
+# flash using openocd
+OPENOCD_OPTION = -f board/ti_ek-tm4c1294xl.cfg
+
+UNIFLASH_OPTION = -c ${TOP}/${BOARD_PATH}/${BOARD}.ccxml -r 1
+
+flash: flash-openocd
diff --git a/hw/bsp/tm4c/boards/ek_tm4c1294xl/tm4c1294nc.ld b/hw/bsp/tm4c/boards/ek_tm4c1294xl/tm4c1294nc.ld
new file mode 100644
index 000000000..fa4ea4dc5
--- /dev/null
+++ b/hw/bsp/tm4c/boards/ek_tm4c1294xl/tm4c1294nc.ld
@@ -0,0 +1,66 @@
+ENTRY(Reset_Handler)
+
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000; /* required amount of stack */
+
+
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4) ;
+        _text = . ;
+        KEEP(*(.isr_vector))
+        *(.text)
+        *(.text.*)
+        *(.init)
+        *(.fini)
+        *(.rodata)
+        *(.rodata.*)
+        *(.ARM.exidx*)
+        _etext = . ;
+        . = ALIGN(4) ;
+    } >FLASH
+
+    .data : AT(ADDR(.text) + SIZEOF(.text))
+    {
+        _data = .;
+        . = ALIGN(4);
+        _ldata = LOADADDR (.data);
+        *(.data)
+        *(.data.*)
+        _edata = .;
+        . = ALIGN(4);
+
+    } >SRAM
+
+    .bss :
+    {
+        . = ALIGN(4) ;
+        _bss = .;
+        *(.bss)
+        *(.bss.*)
+        *(.COMMON)
+        _ebss = .;
+        . = ALIGN(4);
+    }>SRAM
+
+    /* User_heap_stack section, used to check that there is enough RAM left */
+    ._user_heap_stack :
+    {
+        . = ALIGN(8);
+        PROVIDE ( end = . );
+        PROVIDE ( _end = . );
+        . = . + _Min_Heap_Size;
+        . = . + _Min_Stack_Size;
+        . = ALIGN(8);
+    } >SRAM
+}
diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c
index ee1fa2a3c..503d0a8c9 100644
--- a/hw/bsp/tm4c/family.c
+++ b/hw/bsp/tm4c/family.c
@@ -2,7 +2,6 @@
    manufacturer: Texas Instruments
 */
 
-#include "TM4C123.h"
 #include "bsp/board_api.h"
 #include "board.h"
 
@@ -27,6 +26,9 @@ static void board_uart_init(void) {
   SYSCTL->RCGCUART |= (1 << 0);                // Enable the clock to UART0
   SYSCTL->RCGCGPIO |= (1 << 0);                // Enable the clock to GPIOA
 
+  while (!(SYSCTL->PRGPIO & (1 << 0))) {}      // Wait for the GPIOA clock to stabilize
+  while (!(SYSCTL->PRUART & (1 << 0))) {}      // Wait for the UART0 clock to stabilize
+
   GPIOA->AFSEL |= (1 << 1) | (1 << 0);         // Enable the alternate function on pin PA0 & PA1
   GPIOA->PCTL |= (1 << 0) | (1 << 4);          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
   GPIOA->DEN |= (1 << 0) | (1 << 1);           // Enable the digital functionality in PA0 and PA1
@@ -44,12 +46,26 @@ static void board_uart_init(void) {
   UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable
 }
 
-static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) {
-  /* Enable PortF Clock */
-  SYSCTL->RCGCGPIO |= (1 << 5);
+static void board_button_init(GPIOA_Type* port, uint8_t PinMsk) {
+  /* Enable Port Clock */
+  SYSCTL->RCGCGPIO |= (1 << BTN_PORT_CLK);
+
+  /* Let the clock stabilize */
+  while (!((SYSCTL->PRGPIO) & (1 << BTN_PORT_CLK))) {}
+
+  /* Port Digital Enable */
+  port->DEN |= PinMsk;
+
+  /* Set direction */
+  port->DIR &= ~PinMsk;
+}
+
+static void board_led_init(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) {
+  /* Enable Port Clock */
+  SYSCTL->RCGCGPIO |= (1 << LED_PORT_CLK);
 
   /* Let the clock stabilize */
-  while (!((SYSCTL->PRGPIO) & (1 << 5))) {}
+  while (!((SYSCTL->PRGPIO) & (1 << LED_PORT_CLK))) {}
 
   /* Port Digital Enable */
   port->DEN |= PinMsk;
@@ -71,7 +87,9 @@ static uint32_t ReadGPIOPin(GPIOA_Type* port, uint8_t pinMsk) {
 }
 
 void board_init(void) {
+#ifdef TM4C123_H
   SystemCoreClockUpdate();
+#endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -83,6 +101,7 @@ void board_init(void) {
   NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
+#ifdef TM4C123_H
   /* Reset USB */
   SYSCTL->SRCR2 |= (1u << 16);
 
@@ -99,7 +118,7 @@ void board_init(void) {
   /* USB IO Initialization */
   SYSCTL->RCGCGPIO |= (1u << 3);
 
-  /* Let the clock stabilize */
+    /* Let the clock stabilize */
   while (!(SYSCTL->PRGPIO & (1u << 3))) {}
 
   /* USB IOs to Analog Mode */
@@ -107,16 +126,43 @@ void board_init(void) {
   GPIOD->DEN &= ~((1u << 4) | (1u << 5));
   GPIOD->AMSEL |= ((1u << 4) | (1u << 5));
 
-  uint8_t leds = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
-  uint8_t dirmsk = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
+#else // TM4C129
+  /* Reset USB */
+  SYSCTL->SRUSB = 1;
 
-  /* Configure GPIO for board LED */
-  initialize_board_led(LED_PORT, leds, dirmsk);
+  for (volatile uint8_t i = 0; i < 20; i++) {}
+
+  SYSCTL->SRUSB = 0;
 
-  /* Configure GPIO for board switch */
-  GPIOF->DIR &= ~(1 << BOARD_BTN);
-  GPIOF->PUR |= (1 << BOARD_BTN);
-  GPIOF->DEN |= (1 << BOARD_BTN);
+  /* Open the USB clock gate */
+  SYSCTL->RCGCUSB = 1;
+
+  /* Let the clock stabilize */
+  while(!(SYSCTL->PRUSB & 1)) {}
+
+  /* USB IO Initialization */
+  SYSCTL->RCGCGPIO |= (1u << 10);
+
+  /* Let the clock stabilize */
+  while (!(SYSCTL->PRGPIO & (1u << 10))) {}
+
+  /* USB IOs to Analog Mode */
+  GPIOL->AFSEL &= ~((1u << 6) | (1u << 7));
+  GPIOL->DEN &= ~((1u << 6) | (1u << 7));
+  GPIOL->AMSEL |= ((1u << 6) | (1u << 7));
+
+  /* USB Clock Configuration */
+  USB0->CC = 0x207;
+#endif
+
+  uint8_t leds = 1 << BOARD_LED_PIN;
+  uint8_t dirmsk = 1 << BOARD_LED_PIN;
+
+  /* Configure GPIO for board button */
+  board_button_init(BOARD_BTN_PORT, BOARD_BTN_Msk);
+
+  /* Configure GPIO for board LED */
+  board_led_init(LED_PORT, leds, dirmsk);
 
   /* Initialize board UART */
   board_uart_init();
@@ -125,7 +171,7 @@ void board_init(void) {
 }
 
 void board_led_write(bool state) {
-  WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state);
+  WriteGPIOPin(LED_PORT, (1 << BOARD_LED_PIN), state);
 }
 
 uint32_t board_button_read(void) {
@@ -165,7 +211,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake
index 12f0448a3..41b8a597a 100644
--- a/hw/bsp/tm4c/family.cmake
+++ b/hw/bsp/tm4c/family.cmake
@@ -5,14 +5,14 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 set(MCU_VARIANT tm4c${MCU_SUB_VARIANT})
 set(MCU_VARIANT_UPPER TM4C${MCU_SUB_VARIANT})
 
-set(SDK_DIR ${TOP}/hw/mcu/ti/${MCU_VARIANT}xx)
+set(SDK_DIR ${TOP}/hw/mcu/ti/tm4c)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
 # toolchain set up
 set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS TM4C123 CACHE INTERNAL "")
+set(FAMILY_MCUS TM4C CACHE INTERNAL "")
 
 #------------------------------------
 # Startup & Linker script
@@ -20,7 +20,7 @@ set(FAMILY_MCUS TM4C123 CACHE INTERNAL "")
 set(LD_FILE_Clang ${LD_FILE_GNU})
 set(STARTUP_FILE_GNU ${SDK_DIR}/Source/GCC/${MCU_VARIANT}_startup.c)
 set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
+set(STARTUP_FILE_IAR ${SDK_DIR}/Source/IAR/${MCU_VARIANT}_startup.c)
 #------------------------------------
 # Board Target
 #------------------------------------
@@ -29,7 +29,7 @@ function(family_add_board BOARD_TARGET)
     ${SDK_DIR}/Source/system_${MCU_VARIANT_UPPER}.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
-    ${SDK_DIR}/Include/${MCU_VARIANT_UPPER}
+    ${SDK_DIR}/Include
     ${CMSIS_DIR}/CMSIS/Core/Include
     )
 
@@ -41,7 +41,7 @@ endfunction()
 #------------------------------------
 function(family_configure_example TARGET RTOS)
   family_configure_common(${TARGET} ${RTOS})
-  family_add_tinyusb(${TARGET} OPT_MCU_TM4C123)
+  family_add_tinyusb(${TARGET} OPT_MCU_TM4C${MCU_SUB_VARIANT})
 
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
@@ -71,13 +71,14 @@ function(family_configure_example TARGET RTOS)
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
     set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
+    set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
+      SKIP_LINTING ON
+      COMPILE_OPTIONS -w)
   endif ()
-  set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
-    SKIP_LINTING ON
-    COMPILE_OPTIONS -w)
 
   # Flashing
   family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
   family_flash_openocd(${TARGET})
   family_flash_uniflash(${TARGET})
 endfunction()
diff --git a/hw/bsp/tm4c/family.mk b/hw/bsp/tm4c/family.mk
index 76ae785b2..bc966d98e 100644
--- a/hw/bsp/tm4c/family.mk
+++ b/hw/bsp/tm4c/family.mk
@@ -4,11 +4,11 @@ CPU_CORE ?= cortex-m4
 MCU_VARIANT = tm4c${MCU_SUB_VARIANT}
 MCU_VARIANT_UPPER = TM4C${MCU_SUB_VARIANT}
 
-SDK_DIR = hw/mcu/ti/${MCU_VARIANT}xx
+SDK_DIR = hw/mcu/ti/tm4c
 
 CFLAGS += \
   -flto \
-  -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
+  -DCFG_TUSB_MCU=OPT_MCU_TM4C${MCU_SUB_VARIANT} \
   -uvectors \
 
 # mcu driver cause following warnings
@@ -18,7 +18,7 @@ LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/Include/${MCU_VARIANT_UPPER} \
+	$(TOP)/$(SDK_DIR)/Include \
 	$(TOP)/$(BOARD_PATH)
 
 SRC_C += \
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index 6fef53025..d0acd04cb 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -147,7 +147,7 @@ void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void) {
+uint32_t tusb_time_millis_api(void) {
   return system_ticks;
 }
 
diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c
index e2849fb10..5e824d5a5 100644
--- a/lib/networking/rndis_reports.c
+++ b/lib/networking/rndis_reports.c
@@ -44,7 +44,7 @@ static const uint8_t *const permanent_hwaddr = tud_network_mac_address;
 
 static usb_eth_stat_t usb_eth_stat = { 0, 0, 0, 0 };
 static uint32_t oid_packet_filter = 0x0000000;
-static rndis_state_t rndis_state;
+TU_ATTR_UNUSED static rndis_state_t rndis_state;
 
 static const uint32_t OIDSupportedList[] =
 {
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 48dc75e50..00f466007 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -19,6 +19,7 @@ function(tinyusb_sources_get OUTPUT_VAR)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/mtp/mtp_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/printer/printer_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f19c4a327..8f6dd7200 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -127,7 +127,7 @@ static bool     acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_
 static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
 static uint16_t ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
-static bool     ftdi_proccess_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer);
+static bool     ftdi_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer);
 static void     ftdi_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer);
 static bool     ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool     ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
@@ -216,82 +216,84 @@ typedef struct {
   #define DRIVER_NAME_DECLARE(_str)
 #endif
 
+// clang-format off
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
   {
-      .vid_pid_list           = NULL,
-      .vid_pid_count          = 0,
-      .open                   = acm_open,
-      .process_set_config     = acm_process_set_config,
-      .request_complete       = acm_internal_control_complete,
-      .set_control_line_state = acm_set_control_line_state,
-      .set_baudrate           = acm_set_line_coding,
-      .set_data_format        = acm_set_line_coding,
-      .set_line_coding        = acm_set_line_coding,
-      DRIVER_NAME_DECLARE("ACM")
+    .vid_pid_list           = NULL,
+    .vid_pid_count          = 0,
+    .open                   = acm_open,
+    .process_set_config     = acm_process_set_config,
+    .request_complete       = acm_internal_control_complete,
+    .set_control_line_state = acm_set_control_line_state,
+    .set_baudrate           = acm_set_line_coding,
+    .set_data_format        = acm_set_line_coding,
+    .set_line_coding        = acm_set_line_coding,
+    DRIVER_NAME_DECLARE("ACM")
   },
 
   #if CFG_TUH_CDC_FTDI
   {
-      .vid_pid_list           = ftdi_vid_pid_list,
-      .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
-      .open                   = ftdi_open,
-      .process_set_config     = ftdi_proccess_set_config,
-      .request_complete       = ftdi_internal_control_complete,
-      .set_control_line_state = ftdi_set_modem_ctrl,
-      .set_baudrate           = ftdi_set_baudrate,
-      .set_data_format        = ftdi_set_data_format,
-      .set_line_coding        = NULL, // 2 stage set line coding
-      DRIVER_NAME_DECLARE("FTDI")
+    .vid_pid_list           = ftdi_vid_pid_list,
+    .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
+    .open                   = ftdi_open,
+    .process_set_config     = ftdi_process_set_config,
+    .request_complete       = ftdi_internal_control_complete,
+    .set_control_line_state = ftdi_set_modem_ctrl,
+    .set_baudrate           = ftdi_set_baudrate,
+    .set_data_format        = ftdi_set_data_format,
+    .set_line_coding        = NULL, // 2 stage set line coding
+    DRIVER_NAME_DECLARE("FTDI")
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
   {
-      .vid_pid_list           = cp210x_vid_pid_list,
-      .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
-      .open                   = cp210x_open,
-      .process_set_config     = cp210x_process_set_config,
-      .request_complete       = cp210x_internal_control_complete,
-      .set_control_line_state = cp210x_set_modem_ctrl,
-      .set_baudrate           = cp210x_set_baudrate,
-      .set_data_format        = cp210x_set_data_format,
-      .set_line_coding        = NULL, // 2 stage set line coding
-      DRIVER_NAME_DECLARE("CP210x")
+    .vid_pid_list           = cp210x_vid_pid_list,
+    .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
+    .open                   = cp210x_open,
+    .process_set_config     = cp210x_process_set_config,
+    .request_complete       = cp210x_internal_control_complete,
+    .set_control_line_state = cp210x_set_modem_ctrl,
+    .set_baudrate           = cp210x_set_baudrate,
+    .set_data_format        = cp210x_set_data_format,
+    .set_line_coding        = NULL, // 2 stage set line coding
+    DRIVER_NAME_DECLARE("CP210x")
   },
   #endif
 
   #if CFG_TUH_CDC_CH34X
   {
-      .vid_pid_list           = ch34x_vid_pid_list,
-      .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
-      .open                   = ch34x_open,
-      .process_set_config     = ch34x_process_set_config,
-      .request_complete       = ch34x_internal_control_complete,
+    .vid_pid_list           = ch34x_vid_pid_list,
+    .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
+    .open                   = ch34x_open,
+    .process_set_config     = ch34x_process_set_config,
+    .request_complete       = ch34x_internal_control_complete,
 
-      .set_control_line_state = ch34x_set_modem_ctrl,
-      .set_baudrate           = ch34x_set_baudrate,
-      .set_data_format        = ch34x_set_data_format,
-      .set_line_coding        = NULL, // 2 stage set line coding
-      DRIVER_NAME_DECLARE("CH34x")
+    .set_control_line_state = ch34x_set_modem_ctrl,
+    .set_baudrate           = ch34x_set_baudrate,
+    .set_data_format        = ch34x_set_data_format,
+    .set_line_coding        = NULL, // 2 stage set line coding
+    DRIVER_NAME_DECLARE("CH34x")
   },
   #endif
 
   #if CFG_TUH_CDC_PL2303
   {
-      .vid_pid_list           = pl2303_vid_pid_list,
-      .vid_pid_count          = TU_ARRAY_SIZE(pl2303_vid_pid_list),
-      .open                   = pl2303_open,
-      .process_set_config     = pl2303_process_set_config,
-      .request_complete       = pl2303_internal_control_complete,
-      .set_control_line_state = pl2303_set_modem_ctrl,
-      .set_baudrate           = pl2303_set_line_coding,
-      .set_data_format        = pl2303_set_line_coding,
-      .set_line_coding        = pl2303_set_line_coding,
-      DRIVER_NAME_DECLARE("PL2303")
+    .vid_pid_list           = pl2303_vid_pid_list,
+    .vid_pid_count          = TU_ARRAY_SIZE(pl2303_vid_pid_list),
+    .open                   = pl2303_open,
+    .process_set_config     = pl2303_process_set_config,
+    .request_complete       = pl2303_internal_control_complete,
+    .set_control_line_state = pl2303_set_modem_ctrl,
+    .set_baudrate           = pl2303_set_line_coding,
+    .set_data_format        = pl2303_set_line_coding,
+    .set_line_coding        = pl2303_set_line_coding,
+    DRIVER_NAME_DECLARE("PL2303")
   }
   #endif
 };
+// clang-format on
 
 TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch");
 
@@ -761,7 +763,8 @@ uint16_t cdch_open(uint8_t rhport, uint8_t daddr, const tusb_desc_interface_t *i
       for (size_t i = 0; i < driver->vid_pid_count; i++) {
         if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) {
           const uint16_t drv_len = driver->open(daddr, itf_desc, max_len);
-          TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver->name, drv_len > 0 ? "OK" : "FAILED");
+          TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver->name,
+                     drv_len > 0 ? "OK" : "FAILED");
           return drv_len;
         }
       }
@@ -773,35 +776,16 @@ uint16_t cdch_open(uint8_t rhport, uint8_t daddr, const tusb_desc_interface_t *i
   return 0;
 }
 
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
-  tusb_control_request_t request;
-  request.wIndex = tu_htole16((uint16_t) itf_num);
-  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
-  cdch_interface_t *p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
-  TU_LOG_CDC(p_cdc, "set config");
-
-  // fake transfer to kick-off process_set_config()
-  tuh_xfer_t xfer;
-  xfer.daddr = daddr;
-  xfer.result = XFER_RESULT_SUCCESS;
-  xfer.setup = &request;
-  xfer.user_data = 0; // initial state 0
-  cdch_process_set_config(&xfer);
-
-  return true;
-}
-
 static void set_config_complete(cdch_interface_t *p_cdc, bool success) {
   if (success) {
     const uint8_t idx = get_idx_by_ptr(p_cdc);
-    p_cdc->mounted = true;
+    p_cdc->mounted    = true;
     tuh_cdc_mount_cb(idx);
     // Prepare for incoming data
     tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
   } else {
     // clear the interface entry
-    p_cdc->daddr = 0;
+    p_cdc->daddr            = 0;
     p_cdc->bInterfaceNumber = 0;
   }
 
@@ -810,6 +794,33 @@ static void set_config_complete(cdch_interface_t *p_cdc, bool success) {
   usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset);
 }
 
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
+  const uint8_t     idx   = tuh_cdc_itf_get_index(daddr, itf_num);
+  cdch_interface_t *p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  TU_LOG_CDC(p_cdc, "set config");
+
+  // fake transfer to kick-off process_set_config()
+  tusb_control_request_t request;
+  request.wIndex = tu_htole16((uint16_t)itf_num);
+
+  tuh_xfer_t xfer;
+  xfer.daddr       = daddr;
+  xfer.ep_addr     = 0;
+  xfer.result      = XFER_RESULT_SUCCESS;
+  xfer.setup       = &request;
+  xfer.complete_cb = NULL;
+  xfer.buffer      = NULL;
+  xfer.user_data   = 0; // initial state 0
+
+  const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid];
+  if (!driver->process_set_config(p_cdc, &xfer)) {
+    set_config_complete(p_cdc, false);
+  }
+
+  return true;
+}
+
 static void cdch_process_set_config(tuh_xfer_t *xfer) {
   cdch_interface_t *p_cdc = get_itf_by_xfer(xfer);
   TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,);
@@ -1215,22 +1226,14 @@ static uint16_t ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc,
   return drv_len;
 }
 
-static bool ftdi_proccess_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) {
+static bool ftdi_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
   const uintptr_t state = xfer->user_data;
   switch (state) {
     // from here sequence overtaken from Linux Kernel function ftdi_port_probe()
     case CONFIG_FTDI_DETERMINE_TYPE:
       // determine type
-      if (p_cdc->bInterfaceNumber == 0) {
-        TU_ASSERT(ftdi_determine_type(p_cdc));
-      } else {
-        // other interfaces have same type as interface 0
-        uint8_t const idx_itf0 = tuh_cdc_itf_get_index(xfer->daddr, 0);
-        cdch_interface_t const *p_cdc_itf0 = get_itf(idx_itf0);
-        TU_ASSERT(p_cdc_itf0);
-        p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type;
-      }
+      TU_ASSERT(ftdi_determine_type(p_cdc));
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_FTDI_WRITE_LATENCY:
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 36f9ffcf4..65332eae3 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -338,7 +338,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control
 
           default:
             if (stage == CONTROL_STAGE_SETUP) {
-              return reply_getstatus(rhport, request, _dfu_ctx.state, _dfu_ctx.status, 0);
+              return reply_getstatus(rhport, request, (dfu_state_t) _dfu_ctx.state, (dfu_status_t) _dfu_ctx.status, 0);
             }
             break;
         }
@@ -387,7 +387,7 @@ static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tus
       timeout = 0;
     }
 
-    return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
+    return reply_getstatus(rhport, request, next_state, (dfu_status_t) _dfu_ctx.status, timeout);
   } else if (stage == CONTROL_STAGE_ACK) {
     if (_dfu_ctx.flashing_in_progress) {
       _dfu_ctx.state = DFU_DNBUSY;
@@ -416,7 +416,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tus
       timeout = 0;
     }
 
-    return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
+    return reply_getstatus(rhport, request, next_state, (dfu_status_t) _dfu_ctx.status, timeout);
   } else if (stage == CONTROL_STAGE_ACK) {
     if (_dfu_ctx.flashing_in_progress) {
       _dfu_ctx.state = DFU_MANIFEST;
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 023a81595..a49cd725b 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -168,6 +168,108 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void *buffer, ui
   return total_read;
 }
 
+// Note: this function shares stream->buffer with tud_midi_n_stream_read().
+// Do not mix calls to both functions on the same interface.
+uint32_t tud_midi_n_demux_stream_read(uint8_t itf, uint8_t *p_cable_num, void *buffer, uint32_t bufsize) {
+  TU_VERIFY(p_cable_num != NULL && buffer != NULL && bufsize > 0, 0);
+
+  midid_interface_t    *p_midi = &_midid_itf[itf];
+  midi_driver_stream_t *stream = &p_midi->stream_read;
+  tu_edpt_stream_t     *ep_str = &p_midi->ep_stream.rx;
+
+  uint8_t  *buf8 = (uint8_t *)buffer;
+  uint32_t total_read = 0;
+
+  // Initialize to invalid cable so callers can detect "no data" even when
+  // the return value is 0.
+  *p_cable_num = 0xff;
+
+  // If there are leftover bytes from a previous partial read, return them first
+  if (stream->total > 0) {
+    *p_cable_num = (stream->buffer[0] >> 4) & 0x0f;
+    const uint8_t count = (uint8_t)tu_min32((uint32_t)(stream->total - stream->index), bufsize);
+    TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count));
+
+    total_read += count;
+    stream->index += count;
+    buf8 += count;
+    bufsize -= count;
+
+    if (stream->total == stream->index) {
+      stream->index = 0;
+      stream->total = 0;
+    }
+
+    if (bufsize == 0) {
+      return total_read;
+    }
+  }
+
+  while (bufsize > 0) {
+    // Peek at next packet header to get cable number without consuming
+    uint8_t one_byte;
+    if (!tu_edpt_stream_peek(ep_str, &one_byte)) {
+      break;
+    }
+
+    const uint8_t next_cable = (one_byte >> 4) & 0x0f;
+
+    // Stop if cable changed (covers both leftover-originated reads and
+    // freshly consumed packets — total_read > 0 in either case)
+    if (total_read > 0 && next_cable != *p_cable_num) {
+      break;
+    }
+    *p_cable_num = next_cable;
+
+    // Consume the packet
+    if (!tud_midi_n_packet_read(itf, stream->buffer)) {
+      break;
+    }
+
+    const uint8_t code_index = stream->buffer[0] & 0x0f;
+    uint8_t msg_bytes;
+
+    // MIDI 1.0 Table 4-1: Code Index Number Classifications
+    switch (code_index) {
+      case MIDI_CIN_MISC:
+      case MIDI_CIN_CABLE_EVENT:
+        // Reserved and unused, skip this packet
+        continue;
+
+      case MIDI_CIN_SYSEX_END_1BYTE:
+      case MIDI_CIN_1BYTE_DATA:
+        msg_bytes = 1;
+        break;
+
+      case MIDI_CIN_SYSCOM_2BYTE:
+      case MIDI_CIN_SYSEX_END_2BYTE:
+      case MIDI_CIN_PROGRAM_CHANGE:
+      case MIDI_CIN_CHANNEL_PRESSURE:
+        msg_bytes = 2;
+        break;
+
+      default:
+        msg_bytes = 3;
+        break;
+    }
+
+    const uint8_t count = (uint8_t)tu_min32((uint32_t)msg_bytes, bufsize);
+    TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1, count));
+
+    total_read += count;
+    buf8 += count;
+    bufsize -= count;
+
+    if (count < msg_bytes) {
+      // Output buffer full, save remaining for next call
+      stream->total = msg_bytes;
+      stream->index = count;
+    }
+  }
+
+  return total_read;
+}
+
 bool tud_midi_n_packet_read(uint8_t itf, uint8_t packet[4]) {
   midid_interface_t *p_midi = &_midid_itf[itf];
   tu_edpt_stream_t  *ep_str = &p_midi->ep_stream.rx;
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index ddbc2f9f0..b80ad544a 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -66,6 +66,13 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num);
 // Read byte stream (legacy)
 uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void *buffer, uint32_t bufsize);
 
+// Read byte stream with cable demultiplexing: returns the cable number of the
+// data that was read.  Reads from a single cable per call; stops when the next
+// packet belongs to a different cable so the caller can dispatch per-cable.
+// Note: shares internal state with tud_midi_n_stream_read(); do not mix both
+// on the same interface.
+uint32_t tud_midi_n_demux_stream_read(uint8_t itf, uint8_t *p_cable_num, void *buffer, uint32_t bufsize);
+
 // Write byte Stream (legacy)
 uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, const uint8_t *buffer, uint32_t bufsize);
 
@@ -97,6 +104,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_midi_stream_read(void *buffer,
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t
+tud_midi_demux_stream_read(uint8_t *p_cable_num, void *buffer, uint32_t bufsize) {
+  return tud_midi_n_demux_stream_read(0, p_cable_num, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t
 tud_midi_stream_write(uint8_t cable_num, const uint8_t *buffer, uint32_t bufsize) {
   return tud_midi_n_stream_write(0, cable_num, buffer, bufsize);
 }
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 15bfafc35..3766e3a25 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -646,7 +646,11 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
             break;
         }
 
-        TU_ASSERT(prepare_cbw(p_msc));
+        if (!usbd_edpt_stalled(rhport, p_msc->ep_out)) {
+          TU_ASSERT(prepare_cbw(p_msc));
+        } else {
+          p_msc->stage = MSC_STAGE_CMD;
+        }
       } else {
         // Any xfer ended here is considered unknown error, ignore it
         TU_LOG1("  Warning expect SCSI Status but received unknown data\r\n");
diff --git a/src/class/mtp/mtp_device.c b/src/class/mtp/mtp_device.c
index 4942a105a..59096e476 100644
--- a/src/class/mtp/mtp_device.c
+++ b/src/class/mtp/mtp_device.c
@@ -92,8 +92,9 @@ typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
-  uint8_t ep_event;
 
+  uint8_t ep_event;
+  uint8_t ep_sz_fs;
   // Bulk Only Transfer (BOT) Protocol
   uint8_t  phase;
 
@@ -194,42 +195,47 @@ static bool prepare_new_command(mtpd_interface_t* p_mtp) {
   return usbd_edpt_xfer(p_mtp->rhport, p_mtp->ep_out, _mtpd_epbuf.buf, CFG_TUD_MTP_EP_BUFSIZE, false);
 }
 
-static bool mtpd_data_xfer(mtp_container_info_t* p_container, uint8_t ep_addr) {
-  mtpd_interface_t* p_mtp = &_mtpd_itf;
+bool tud_mtp_data_send(mtp_container_info_t *p_container) {
+  mtpd_interface_t *p_mtp = &_mtpd_itf;
   if (p_mtp->phase == MTP_PHASE_COMMAND) {
     // 1st data block: header + payload
     p_mtp->phase = MTP_PHASE_DATA;
     p_mtp->xferred_len = 0;
+    p_mtp->total_len   = p_container->header->len;
 
-    if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
-      p_mtp->total_len = p_container->header->len;
-      p_container->header->type = MTP_CONTAINER_TYPE_DATA_BLOCK;
-      p_container->header->transaction_id = p_mtp->command.header.transaction_id;
-      p_mtp->io_header = *p_container->header; // save header for subsequent data
-    } else {
-      // OUT transfer: total length is at least max packet size
-      p_mtp->total_len = tu_max32(p_container->header->len, CFG_TUD_MTP_EP_BUFSIZE);
-    }
-  } else {
-    // subsequent data block: payload only
-    TU_ASSERT(p_mtp->phase == MTP_PHASE_DATA);
+    p_container->header->type           = MTP_CONTAINER_TYPE_DATA_BLOCK;
+    p_container->header->transaction_id = p_mtp->command.header.transaction_id;
+    p_mtp->io_header                    = *p_container->header; // save header for subsequent data
   }
 
-  const uint16_t xact_len = (uint16_t) tu_min32(p_mtp->total_len - p_mtp->xferred_len, CFG_TUD_MTP_EP_BUFSIZE);
+  const uint16_t xact_len = (uint16_t)tu_min32(p_mtp->total_len - p_mtp->xferred_len, CFG_TUD_MTP_EP_BUFSIZE);
+
+  TU_LOG_DRV("  MTP Data IN: xferred_len/total_len=%lu/%lu, xact_len=%u\r\n", p_mtp->xferred_len, p_mtp->total_len,
+             xact_len);
   if (xact_len) {
-    // already transferred all bytes in header's length. Application make an unnecessary extra call
-    TU_VERIFY(usbd_edpt_claim(p_mtp->rhport, ep_addr));
-    TU_ASSERT(usbd_edpt_xfer(p_mtp->rhport, ep_addr, _mtpd_epbuf.buf, xact_len, false));
+    TU_VERIFY(usbd_edpt_claim(p_mtp->rhport, p_mtp->ep_in));
+    TU_ASSERT(usbd_edpt_xfer(p_mtp->rhport, p_mtp->ep_in, _mtpd_epbuf.buf, xact_len, false));
   }
   return true;
 }
 
-bool tud_mtp_data_send(mtp_container_info_t* p_container) {
-  return mtpd_data_xfer(p_container, _mtpd_itf.ep_in);
-}
+bool tud_mtp_data_receive(mtp_container_info_t *p_container) {
+  mtpd_interface_t *p_mtp = &_mtpd_itf;
+  if (p_mtp->phase == MTP_PHASE_COMMAND) {
+    // 1st data block: header + payload
+    p_mtp->phase       = MTP_PHASE_DATA;
+    p_mtp->xferred_len = 0;
+    p_mtp->total_len   = p_container->header->len;
+  }
 
-bool tud_mtp_data_receive(mtp_container_info_t* p_container) {
-  return mtpd_data_xfer(p_container, _mtpd_itf.ep_out);
+  // up to buffer size since 1st packet (with header) may also contain payload
+  const uint16_t xact_len = CFG_TUD_MTP_EP_BUFSIZE;
+
+  TU_LOG_DRV("  MTP Data OUT: xferred_len/total_len=%lu/%lu, xact_len=%u\r\n", p_mtp->xferred_len, p_mtp->total_len,
+             xact_len);
+  TU_VERIFY(usbd_edpt_claim(p_mtp->rhport, p_mtp->ep_out));
+  TU_ASSERT(usbd_edpt_xfer(p_mtp->rhport, p_mtp->ep_out, _mtpd_epbuf.buf, xact_len, false));
+  return true;
 }
 
 bool tud_mtp_response_send(mtp_container_info_t* p_container) {
@@ -287,15 +293,20 @@ uint16_t mtpd_open(uint8_t rhport, tusb_desc_interface_t const* itf_desc, uint16
   p_mtp->itf_num = itf_desc->bInterfaceNumber;
 
   // Open interrupt IN endpoint
-  const tusb_desc_endpoint_t* ep_desc = (const tusb_desc_endpoint_t*) tu_desc_next(itf_desc);
-  TU_ASSERT(ep_desc->bDescriptorType == TUSB_DESC_ENDPOINT && ep_desc->bmAttributes.xfer == TUSB_XFER_INTERRUPT, 0);
-  TU_ASSERT(usbd_edpt_open(rhport, ep_desc), 0);
-  p_mtp->ep_event = ep_desc->bEndpointAddress;
+  const tusb_desc_endpoint_t* ep_desc_int = (const tusb_desc_endpoint_t*) tu_desc_next(itf_desc);
+  TU_ASSERT(ep_desc_int->bDescriptorType == TUSB_DESC_ENDPOINT && ep_desc_int->bmAttributes.xfer == TUSB_XFER_INTERRUPT, 0);
+  TU_ASSERT(usbd_edpt_open(rhport, ep_desc_int), 0);
+  p_mtp->ep_event = ep_desc_int->bEndpointAddress;
 
   // Open endpoint pair
-  TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(ep_desc), 2, TUSB_XFER_BULK, &p_mtp->ep_out, &p_mtp->ep_in), 0);
+  const tusb_desc_endpoint_t* ep_desc_bulk = (const tusb_desc_endpoint_t*) tu_desc_next(ep_desc_int);
+  TU_ASSERT(usbd_open_edpt_pair(rhport, (const uint8_t*)ep_desc_bulk, 2, TUSB_XFER_BULK, &p_mtp->ep_out, &p_mtp->ep_in), 0);
   TU_ASSERT(prepare_new_command(p_mtp), 0);
 
+  if (tud_speed_get() == TUSB_SPEED_FULL) {
+    p_mtp->ep_sz_fs = (uint8_t)tu_edpt_packet_size(ep_desc_bulk);
+  }
+
   return mtpd_itf_size;
 }
 
@@ -377,8 +388,8 @@ bool mtpd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
   mtp_generic_container_t* p_container = (mtp_generic_container_t*) _mtpd_epbuf.buf;
 
 #if CFG_TUSB_DEBUG >= CFG_TUD_MTP_LOG_LEVEL
-  tu_lookup_find(&_mtp_op_table, p_mtp->command.header.code);
-  TU_LOG_DRV("  MTP %s: %s phase\r\n", (const char *) tu_lookup_find(&_mtp_op_table, p_mtp->command.header.code),
+  const uint16_t code = (p_mtp->phase == MTP_PHASE_COMMAND) ? p_container->header.code : p_mtp->command.header.code;
+  TU_LOG_DRV("  MTP %s: %s phase\r\n", (const char *) tu_lookup_find(&_mtp_op_table, code),
     _mtp_phase_str[p_mtp->phase]);
 #endif
 
@@ -417,19 +428,35 @@ bool mtpd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     }
 
     case MTP_PHASE_DATA: {
-      const uint16_t bulk_mps = (tud_speed_get() == TUSB_SPEED_HIGH) ? 512 : 64;
       p_mtp->xferred_len += xferred_bytes;
       cb_data.total_xferred_bytes = p_mtp->xferred_len;
 
-      bool is_complete = false;
-      // complete if ZLP or short packet or total length reached
-      if (xferred_bytes == 0 || // ZLP
-          (xferred_bytes & (bulk_mps - 1)) || // short packet
-          p_mtp->xferred_len >= p_mtp->total_len) { // total length reached
-        is_complete = true;
+      const bool is_data_in = (ep_addr == p_mtp->ep_in);
+      // For IN endpoint, threshold is bulk max packet size
+      // For OUT endpoint, threshold is endpoint buffer size, since we always queue fixed size
+      uint16_t threshold;
+      if (is_data_in) {
+        threshold = (p_mtp->ep_sz_fs > 0) ? p_mtp->ep_sz_fs : 512; // full speed bulk if set
+      } else {
+        threshold = CFG_TUD_MTP_EP_BUFSIZE;
+      }
+
+      // Check completion: ZLP, short packet, or total length reached
+      const bool is_complete =
+        (xferred_bytes == 0 || xferred_bytes < threshold || p_mtp->xferred_len >= p_mtp->total_len);
+
+      TU_LOG_DRV("  MTP Data %s CB: xferred_bytes=%lu, xferred_len/total_len=%lu/%lu, is_complete=%d\r\n",
+                 is_data_in ? "IN" : "OUT", xferred_bytes, p_mtp->xferred_len, p_mtp->total_len, is_complete ? 1 : 0);
+
+      // Send/queue ZLP if packet is full-sized but transfer is complete
+      if (is_complete && xferred_bytes > 0 && !(xferred_bytes & (threshold - 1))) {
+        TU_LOG_DRV("  queue ZLP\r\n");
+        TU_VERIFY(usbd_edpt_claim(p_mtp->rhport, ep_addr));
+        TU_ASSERT(usbd_edpt_xfer(p_mtp->rhport, ep_addr, NULL, 0, false));
+        return true;
       }
 
-      if (ep_addr == p_mtp->ep_in) {
+      if (is_data_in) {
         // Data In
         if (is_complete) {
           cb_data.io_container.header->len = sizeof(mtp_container_header_t);
diff --git a/src/class/mtp/mtp_device.h b/src/class/mtp/mtp_device.h
index a33f1dc08..6cce7efbb 100644
--- a/src/class/mtp/mtp_device.h
+++ b/src/class/mtp/mtp_device.h
@@ -18,7 +18,7 @@
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN0
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  *
  * This file is part of the TinyUSB stack.
diff --git a/src/class/printer/printer.h b/src/class/printer/printer.h
new file mode 100644
index 000000000..09d1a8956
--- /dev/null
+++ b/src/class/printer/printer.h
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_PRINTER_H_
+#define TUSB_PRINTER_H_
+
+#include "common/tusb_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// Printer Class Specific Control Request
+typedef enum {
+  TUSB_PRINTER_REQUEST_GET_DEVICE_ID   = 0x00, ///< Get device ID
+  TUSB_PRINTER_REQUEST_GET_PORT_STATUS = 0x01, ///< Get port status
+  TUSB_PRINTER_REQUEST_SOFT_RESET      = 0x02, ///< Soft reset
+} tusb_printer_request_type_t;
+
+/// Printer Port Status (returned by GET_PORT_STATUS request)
+/// USB Printer Class spec 1.1, Section 4.2
+typedef union TU_ATTR_PACKED {
+  uint8_t status;
+  struct TU_ATTR_PACKED {
+    uint8_t reserved0   : 3; ///< Reserved (bits 0-2)
+    uint8_t not_error   : 1; ///< 1 = no error, 0 = error
+    uint8_t selected    : 1; ///< 1 = selected (online), 0 = not selected
+    uint8_t paper_empty : 1; ///< 1 = paper empty, 0 = paper not empty
+    uint8_t reserved6   : 2; ///< Reserved (bits 6-7)
+  } status_bm;
+} tusb_printer_port_status_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_printer_port_status_t) == 1, "size is not correct");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/class/printer/printer_device.c b/src/class/printer/printer_device.c
new file mode 100644
index 000000000..f5bb33795
--- /dev/null
+++ b/src/class/printer/printer_device.c
@@ -0,0 +1,329 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if (CFG_TUD_ENABLED && CFG_TUD_PRINTER)
+
+#include "device/usbd.h"
+#include "device/usbd_pvt.h"
+
+#include "printer_device.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+typedef struct {
+  uint8_t itf_num;
+
+  /*------------- From this point, data is not cleared by bus reset -------------*/
+
+  tu_edpt_stream_t rx_stream;
+  tu_edpt_stream_t tx_stream;
+
+  uint8_t rx_ff_buf[CFG_TUD_PRINTER_RX_BUFSIZE];
+  uint8_t tx_ff_buf[CFG_TUD_PRINTER_TX_BUFSIZE];
+} printer_interface_t;
+
+#define ITF_MEM_RESET_SIZE offsetof(printer_interface_t, rx_stream)
+
+#if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0
+typedef struct {
+  TUD_EPBUF_DEF(epout, CFG_TUD_PRINTER_EP_BUFSIZE);
+  TUD_EPBUF_DEF(epin, CFG_TUD_PRINTER_EP_BUFSIZE);
+} printer_epbuf_t;
+
+CFG_TUD_MEM_SECTION static printer_epbuf_t _printer_epbuf[CFG_TUD_PRINTER];
+#endif
+
+static printer_interface_t _printer_itf[CFG_TUD_PRINTER];
+
+//--------------------------------------------------------------------+
+// INTERNAL HELPERS
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t _find_itf(uint8_t ep_addr) {
+  for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) {
+    const printer_interface_t *p = &_printer_itf[i];
+    if (ep_addr == p->rx_stream.ep_addr || ep_addr == p->tx_stream.ep_addr) {
+      return i;
+    }
+  }
+  return TUSB_INDEX_INVALID_8;
+}
+
+//--------------------------------------------------------------------+
+// Weak stubs: invoked if no strong implementation is available
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_printer_rx_cb(uint8_t itf) {
+  (void)itf;
+}
+
+TU_ATTR_WEAK void tud_printer_tx_complete_cb(uint8_t itf) {
+  (void)itf;
+}
+
+TU_ATTR_WEAK void tud_printer_request_complete_cb(uint8_t itf, tusb_control_request_t const *request) {
+  (void)itf;
+  (void)request;
+}
+
+TU_ATTR_WEAK uint8_t const *tud_printer_get_device_id_cb(uint8_t itf) {
+  (void)itf;
+  return NULL;
+}
+
+TU_ATTR_WEAK uint8_t tud_printer_get_port_status_cb(uint8_t itf) {
+  (void)itf;
+  return 0x18; // not error, selected, paper not empty
+}
+
+TU_ATTR_WEAK void tud_printer_soft_reset_cb(uint8_t itf) {
+  (void)itf;
+}
+
+//--------------------------------------------------------------------+
+// READ API
+//--------------------------------------------------------------------+
+uint32_t tud_printer_n_read_available(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, 0);
+  return tu_edpt_stream_read_available(&_printer_itf[itf].rx_stream);
+}
+
+uint32_t tud_printer_n_read(uint8_t itf, void *buffer, uint32_t bufsize) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, 0);
+  return tu_edpt_stream_read(&_printer_itf[itf].rx_stream, buffer, bufsize);
+}
+
+bool tud_printer_n_peek(uint8_t itf, uint8_t *chr) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER);
+  return tu_edpt_stream_peek(&_printer_itf[itf].rx_stream, chr);
+}
+
+void tud_printer_n_read_flush(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, );
+  printer_interface_t *p = &_printer_itf[itf];
+  tu_edpt_stream_clear(&p->rx_stream);
+  tu_edpt_stream_read_xfer(&p->rx_stream);
+}
+
+//--------------------------------------------------------------------+
+// WRITE API
+//--------------------------------------------------------------------+
+uint32_t tud_printer_n_write(uint8_t itf, const void *buffer, uint32_t bufsize) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, 0);
+  return tu_edpt_stream_write(&_printer_itf[itf].tx_stream, buffer, bufsize);
+}
+
+uint32_t tud_printer_n_write_flush(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, 0);
+  return tu_edpt_stream_write_xfer(&_printer_itf[itf].tx_stream);
+}
+
+uint32_t tud_printer_n_write_available(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER, 0);
+  return tu_edpt_stream_write_available(&_printer_itf[itf].tx_stream);
+}
+
+bool tud_printer_n_write_clear(uint8_t itf) {
+  TU_VERIFY(itf < CFG_TUD_PRINTER);
+  tu_edpt_stream_clear(&_printer_itf[itf].tx_stream);
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// USBD-CLASS API
+//--------------------------------------------------------------------+
+void printerd_init(void) {
+  tu_memclr(_printer_itf, sizeof(_printer_itf));
+
+  for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) {
+    printer_interface_t *p = &_printer_itf[i];
+
+  #if CFG_TUD_EDPT_DEDICATED_HWFIFO
+    uint8_t *epout_buf = NULL;
+    uint8_t *epin_buf  = NULL;
+  #else
+    uint8_t *epout_buf = _printer_epbuf[i].epout;
+    uint8_t *epin_buf  = _printer_epbuf[i].epin;
+  #endif
+
+    tu_edpt_stream_init(&p->rx_stream, false, false, false,
+                        p->rx_ff_buf, CFG_TUD_PRINTER_RX_BUFSIZE,
+                        epout_buf, CFG_TUD_PRINTER_EP_BUFSIZE);
+
+    tu_edpt_stream_init(&p->tx_stream, false, true, true,
+                        p->tx_ff_buf, CFG_TUD_PRINTER_TX_BUFSIZE,
+                        epin_buf, CFG_TUD_PRINTER_EP_BUFSIZE);
+  }
+}
+
+bool printerd_deinit(void) {
+  for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) {
+    printer_interface_t *p = &_printer_itf[i];
+    tu_edpt_stream_deinit(&p->rx_stream);
+    tu_edpt_stream_deinit(&p->tx_stream);
+  }
+  return true;
+}
+
+void printerd_reset(uint8_t rhport) {
+  (void)rhport;
+
+  for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) {
+    printer_interface_t *p = &_printer_itf[i];
+    tu_memclr(p, ITF_MEM_RESET_SIZE);
+    tu_edpt_stream_close(&p->rx_stream);
+    tu_edpt_stream_close(&p->tx_stream);
+  }
+}
+
+uint16_t printerd_open(uint8_t rhport, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
+  TU_VERIFY(TUSB_CLASS_PRINTER == itf_desc->bInterfaceClass, 0);
+
+  // Find available interface slot
+  uint8_t const printer_id = _find_itf(0);
+  TU_ASSERT(printer_id < CFG_TUD_PRINTER, 0);
+  printer_interface_t *p = &_printer_itf[printer_id];
+
+  p->itf_num = itf_desc->bInterfaceNumber;
+
+  //------------- Endpoints -------------//
+  const uint8_t *p_desc   = (const uint8_t *)itf_desc;
+  const uint8_t *desc_end = p_desc + max_len;
+  uint16_t drv_len = sizeof(tusb_desc_interface_t);
+
+  p_desc = tu_desc_next(itf_desc);
+  for (uint8_t e = 0; e < itf_desc->bNumEndpoints; e++) {
+    TU_VERIFY(tu_desc_in_bounds(p_desc, desc_end), 0);
+    const tusb_desc_endpoint_t *desc_ep = (const tusb_desc_endpoint_t *)p_desc;
+    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer, 0);
+
+    TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
+
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+      tu_edpt_stream_open(&p->tx_stream, rhport, desc_ep);
+      tu_edpt_stream_clear(&p->tx_stream);
+    } else {
+      tu_edpt_stream_open(&p->rx_stream, rhport, desc_ep);
+      tu_edpt_stream_clear(&p->rx_stream);
+      TU_ASSERT(tu_edpt_stream_read_xfer(&p->rx_stream) > 0, 0);
+    }
+
+    drv_len += sizeof(tusb_desc_endpoint_t);
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  return drv_len;
+}
+
+bool printerd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t *request) {
+  TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE &&
+    request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
+
+  // GET_DEVICE_ID: wIndex = (interface_number << 8) | alt_setting
+  // GET_PORT_STATUS / SOFT_RESET: wIndex = interface_number
+  uint8_t itf_num;
+  if (TUSB_PRINTER_REQUEST_GET_DEVICE_ID == request->bRequest) {
+    itf_num = tu_u16_high(request->wIndex);
+  } else {
+    itf_num = tu_u16_low(request->wIndex);
+  }
+
+  // Find the printer instance index from the USB interface number
+  uint8_t itf = TUSB_INDEX_INVALID_8;
+  for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) {
+    if (_printer_itf[i].itf_num == itf_num) {
+      itf = i;
+      break;
+    }
+  }
+  TU_VERIFY(itf < CFG_TUD_PRINTER);
+
+  // https://www.usb.org/sites/default/files/usbprint11a021811.pdf
+  if (stage == CONTROL_STAGE_SETUP) {
+    switch (request->bRequest) {
+      case TUSB_PRINTER_REQUEST_GET_DEVICE_ID: {
+        const uint8_t *device_id = tud_printer_get_device_id_cb(itf);
+        TU_VERIFY(device_id);
+        const uint16_t total_len = (uint16_t)((device_id[0] << 8) | device_id[1]);
+        return tud_control_xfer(rhport, request, (void *)(uintptr_t)device_id, total_len);
+      }
+
+      case TUSB_PRINTER_REQUEST_GET_PORT_STATUS: {
+        static uint8_t port_status;
+        port_status = tud_printer_get_port_status_cb(itf);
+        return tud_control_xfer(rhport, request, &port_status, sizeof(port_status));
+      }
+
+      case TUSB_PRINTER_REQUEST_SOFT_RESET:
+        tud_printer_soft_reset_cb(itf);
+        tud_control_status(rhport, request);
+        return true;
+
+      default:
+        return false;
+    }
+  } else if (stage == CONTROL_STAGE_ACK) {
+    tud_printer_request_complete_cb(itf, request);
+  }
+
+  return true;
+}
+
+bool printerd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+  (void)rhport;
+  (void)result;
+
+  uint8_t const itf = _find_itf(ep_addr);
+  TU_ASSERT(itf < CFG_TUD_PRINTER);
+  printer_interface_t *p = &_printer_itf[itf];
+
+  // Received new data
+  if (ep_addr == p->rx_stream.ep_addr) {
+    tu_edpt_stream_read_xfer_complete(&p->rx_stream, xferred_bytes);
+
+    if (!tu_edpt_stream_empty(&p->rx_stream)) {
+      tud_printer_rx_cb(itf);
+    }
+
+    tu_edpt_stream_read_xfer(&p->rx_stream);
+  }
+
+  // Data sent to host
+  if (ep_addr == p->tx_stream.ep_addr) {
+    tud_printer_tx_complete_cb(itf);
+
+    if (0 == tu_edpt_stream_write_xfer(&p->tx_stream)) {
+      tu_edpt_stream_write_zlp_if_needed(&p->tx_stream, xferred_bytes);
+    }
+  }
+
+  return true;
+}
+
+#endif
diff --git a/src/class/printer/printer_device.h b/src/class/printer/printer_device.h
new file mode 100644
index 000000000..a6b7052cb
--- /dev/null
+++ b/src/class/printer/printer_device.h
@@ -0,0 +1,140 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2026 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_PRINTER_DEVICE_H_
+#define TUSB_PRINTER_DEVICE_H_
+
+#include "printer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Application API (Multiple Ports) i.e. CFG_TUD_PRINTER > 1
+//--------------------------------------------------------------------+
+
+// Get the number of bytes available for reading
+uint32_t tud_printer_n_read_available(uint8_t itf);
+
+// Read received bytes
+uint32_t tud_printer_n_read(uint8_t itf, void *buffer, uint32_t bufsize);
+
+// Get the number of bytes available for writing
+uint32_t tud_printer_n_write_available(uint8_t itf);
+
+// Clear the received FIFO
+void tud_printer_n_read_flush(uint8_t itf);
+
+// Get a byte from FIFO without removing it
+bool tud_printer_n_peek(uint8_t itf, uint8_t *ui8);
+
+// Write data to host
+uint32_t tud_printer_n_write(uint8_t itf, const void *buffer, uint32_t bufsize);
+
+// Force sending data in the TX FIFO
+uint32_t tud_printer_n_write_flush(uint8_t itf);
+
+// Clear the transmit FIFO
+bool tud_printer_n_write_clear(uint8_t itf);
+
+//--------------------------------------------------------------------+
+// Application API (Single Port)
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_read_available(void) {
+  return tud_printer_n_read_available(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write_available(void) {
+  return tud_printer_n_write_available(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_read(void *buffer, uint32_t bufsize) {
+  return tud_printer_n_read(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_printer_read_flush(void) {
+  tud_printer_n_read_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_printer_peek(uint8_t *ui8) {
+  return tud_printer_n_peek(0, ui8);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write(const void *buffer, uint32_t bufsize) {
+  return tud_printer_n_write(0, buffer, bufsize);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write_flush(void) {
+  return tud_printer_n_write_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_printer_write_clear(void) {
+  return tud_printer_n_write_clear(0);
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API (weak is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+void tud_printer_rx_cb(uint8_t itf);
+
+// Invoked when last write transfer is completed
+void tud_printer_tx_complete_cb(uint8_t itf);
+
+// Invoked when host requests device ID string (IEEE 1284).
+// Application returns pointer to device ID buffer (must remain valid until transfer completes).
+// First 2 bytes of returned buffer must contain big-endian length (including the 2 length bytes).
+const uint8_t *tud_printer_get_device_id_cb(uint8_t itf);
+
+// Invoked when host requests port status.
+uint8_t tud_printer_get_port_status_cb(uint8_t itf);
+
+// Invoked when host requests soft reset.
+void tud_printer_soft_reset_cb(uint8_t itf);
+
+// Invoked when a control request is completed (GET_DEVICE_ID, GET_PORT_STATUS, etc.)
+void tud_printer_request_complete_cb(uint8_t itf, tusb_control_request_t const *request);
+
+
+//--------------------------------------------------------------------+
+// Internal Class Driver API
+//--------------------------------------------------------------------+
+void     printerd_init(void);
+bool     printerd_deinit(void);
+void     printerd_reset(uint8_t rhport);
+uint16_t printerd_open(uint8_t rhport, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
+bool     printerd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t *request);
+bool     printerd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index b8e6fec6f..b917c8dc7 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -40,36 +40,33 @@ typedef struct {
   uint8_t rhport;
   uint8_t itf_num;
 
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
   /*------------- From this point, data is not cleared by bus reset -------------*/
-  struct {
-    tu_edpt_stream_t tx;
-    tu_edpt_stream_t rx;
-
-  #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
-    uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
-  #endif
-
-  #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
-    uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
+  tu_edpt_stream_t tx_stream;
+  tu_edpt_stream_t rx_stream;
+  uint8_t          tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
+  uint8_t          rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
+  #else
+  uint8_t  ep_in;
+  uint8_t  ep_out;
+  uint16_t ep_in_mps;
+  uint16_t ep_out_mps;
   #endif
-  } stream;
 } vendord_interface_t;
 
-#define ITF_MEM_RESET_SIZE (offsetof(vendord_interface_t, itf_num) + sizeof(((vendord_interface_t *)0)->itf_num))
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+    #define ITF_MEM_RESET_SIZE (offsetof(vendord_interface_t, itf_num) + TU_FIELD_SIZE(vendord_interface_t, itf_num))
+  #else
+    #define ITF_MEM_RESET_SIZE sizeof(vendord_interface_t)
+  #endif
 
 static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
-#if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 || CFG_TUD_VENDOR_RX_BUFSIZE == 0
+  // Skip local EP buffer if dedicated hw FIFO is supported or no fifo mode
+  #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 || !CFG_TUD_VENDOR_TXRX_BUFFERED
 typedef struct {
-    // Skip local EP buffer if dedicated hw FIFO is supported
-    #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 || CFG_TUD_VENDOR_RX_BUFSIZE == 0
   TUD_EPBUF_DEF(epout, CFG_TUD_VENDOR_EPSIZE);
-    #endif
-
-    // Skip local EP buffer if dedicated hw FIFO is supported
-    #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0
   TUD_EPBUF_DEF(epin, CFG_TUD_VENDOR_EPSIZE);
-    #endif
 } vendord_epbuf_t;
 
 CFG_TUD_MEM_SECTION static vendord_epbuf_t _vendord_epbuf[CFG_TUD_VENDOR];
@@ -78,7 +75,6 @@ CFG_TUD_MEM_SECTION static vendord_epbuf_t _vendord_epbuf[CFG_TUD_VENDOR];
 //--------------------------------------------------------------------+
 // Weak stubs: invoked if no strong implementation is available
 //--------------------------------------------------------------------+
-
 TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t idx, const uint8_t *buffer, uint32_t bufsize) {
   (void)idx;
   (void)buffer;
@@ -93,40 +89,44 @@ TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t idx, uint32_t sent_bytes) {
 //--------------------------------------------------------------------
 // Application API
 //--------------------------------------------------------------------
-
 bool tud_vendor_n_mounted(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return p_itf->stream.rx.ep_addr || p_itf->stream.tx.ep_addr;
+
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  return (p_itf->rx_stream.ep_addr != 0) || (p_itf->tx_stream.ep_addr != 0);
+  #else
+  return (p_itf->ep_out != 0) || (p_itf->ep_in != 0);
+  #endif
 }
 
 //--------------------------------------------------------------------+
 // Read API
 //--------------------------------------------------------------------+
-#if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
 uint32_t tud_vendor_n_available(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_read_available(&p_itf->stream.rx);
+  return tu_edpt_stream_read_available(&p_itf->rx_stream);
 }
 
 bool tud_vendor_n_peek(uint8_t idx, uint8_t *u8) {
   TU_VERIFY(idx < CFG_TUD_VENDOR);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_peek(&p_itf->stream.rx, u8);
+  return tu_edpt_stream_peek(&p_itf->rx_stream, u8);
 }
 
 uint32_t tud_vendor_n_read(uint8_t idx, void *buffer, uint32_t bufsize) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_read(&p_itf->stream.rx, buffer, bufsize);
+  return tu_edpt_stream_read(&p_itf->rx_stream, buffer, bufsize);
 }
 
 void tud_vendor_n_read_flush(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, );
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  tu_edpt_stream_clear(&p_itf->stream.rx);
-  tu_edpt_stream_read_xfer(&p_itf->stream.rx);
+  tu_edpt_stream_clear(&p_itf->rx_stream);
+  tu_edpt_stream_read_xfer(&p_itf->rx_stream);
 }
 #endif
 
@@ -134,9 +134,17 @@ void tud_vendor_n_read_flush(uint8_t idx) {
 bool tud_vendor_n_read_xfer(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_read_xfer(&p_itf->stream.rx);
+
+    #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  return tu_edpt_stream_read_xfer(&p_itf->rx_stream);
+
+    #else
+  // Non-FIFO mode
+  TU_VERIFY(usbd_edpt_claim(p_itf->rhport, p_itf->ep_out));
+  return usbd_edpt_xfer(p_itf->rhport, p_itf->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false);
+    #endif
 }
-#endif
+  #endif
 
 
 //--------------------------------------------------------------------+
@@ -145,26 +153,45 @@ bool tud_vendor_n_read_xfer(uint8_t idx) {
 uint32_t tud_vendor_n_write(uint8_t idx, const void *buffer, uint32_t bufsize) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_write(&p_itf->stream.tx, buffer, (uint16_t)bufsize);
+
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  return tu_edpt_stream_write(&p_itf->tx_stream, buffer, (uint16_t)bufsize);
+
+  #else
+  // non-fifo mode: direct transfer
+  TU_VERIFY(usbd_edpt_claim(p_itf->rhport, p_itf->ep_in), 0);
+  const uint32_t xact_len = tu_min32(bufsize, CFG_TUD_VENDOR_EPSIZE);
+  memcpy(_vendord_epbuf[idx].epin, buffer, xact_len);
+  TU_ASSERT(usbd_edpt_xfer(p_itf->rhport, p_itf->ep_in, _vendord_epbuf[idx].epin, (uint16_t)xact_len, false), 0);
+  return xact_len;
+  #endif
 }
 
-#if CFG_TUD_VENDOR_TX_BUFSIZE > 0
-uint32_t tud_vendor_n_write_flush(uint8_t idx) {
+uint32_t tud_vendor_n_write_available(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_write_xfer(&p_itf->stream.tx);
+
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  return tu_edpt_stream_write_available(&p_itf->tx_stream);
+
+  #else
+  // Non-FIFO mode
+  TU_VERIFY(p_itf->ep_in > 0, 0); // must be opened
+  return usbd_edpt_busy(p_itf->rhport, p_itf->ep_in) ? 0 : CFG_TUD_VENDOR_EPSIZE;
+  #endif
 }
 
-uint32_t tud_vendor_n_write_available(uint8_t idx) {
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+uint32_t tud_vendor_n_write_flush(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  return tu_edpt_stream_write_available(&p_itf->stream.tx);
+  return tu_edpt_stream_write_xfer(&p_itf->tx_stream);
 }
 
 bool tud_vendor_n_write_clear(uint8_t idx) {
   TU_VERIFY(idx < CFG_TUD_VENDOR, 0);
   vendord_interface_t *p_itf = &_vendord_itf[idx];
-  tu_edpt_stream_clear(&p_itf->stream.tx);
+  tu_edpt_stream_clear(&p_itf->tx_stream);
   return true;
 }
 #endif
@@ -175,48 +202,37 @@ bool tud_vendor_n_write_clear(uint8_t idx) {
 void vendord_init(void) {
   tu_memclr(_vendord_itf, sizeof(_vendord_itf));
 
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
-    vendord_interface_t* p_itf = &_vendord_itf[i];
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  for (uint8_t i = 0; i < CFG_TUD_VENDOR; i++) {
+    vendord_interface_t *p_itf = &_vendord_itf[i];
 
-  #if CFG_TUD_EDPT_DEDICATED_HWFIFO
-    #if CFG_TUD_VENDOR_RX_BUFSIZE == 0 // non-fifo rx still need ep buffer
-    uint8_t *epout_buf = _vendord_epbuf[i].epout;
-    #else
+    #if CFG_TUD_EDPT_DEDICATED_HWFIFO
     uint8_t *epout_buf = NULL;
-    #endif
-
-    uint8_t *epin_buf = NULL;
-  #else
+    uint8_t *epin_buf  = NULL;
+    #else
     uint8_t *epout_buf = _vendord_epbuf[i].epout;
     uint8_t *epin_buf  = _vendord_epbuf[i].epin;
-  #endif
-
-  #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
-    uint8_t *rx_ff_buf = p_itf->stream.rx_ff_buf;
-  #else
-    uint8_t *rx_ff_buf = NULL;
-  #endif
+    #endif
 
-    tu_edpt_stream_init(&p_itf->stream.rx, false, false, false, rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, epout_buf,
+    uint8_t *rx_ff_buf = p_itf->rx_ff_buf;
+    tu_edpt_stream_init(&p_itf->rx_stream, false, false, false, rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, epout_buf,
                         CFG_TUD_VENDOR_EPSIZE);
 
-  #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
-    uint8_t *tx_ff_buf = p_itf->stream.tx_ff_buf;
-  #else
-    uint8_t *tx_ff_buf = NULL;
-  #endif
-
-    tu_edpt_stream_init(&p_itf->stream.tx, false, true, false, tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, epin_buf,
+    uint8_t *tx_ff_buf = p_itf->tx_ff_buf;
+    tu_edpt_stream_init(&p_itf->tx_stream, false, true, false, tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, epin_buf,
                         CFG_TUD_VENDOR_EPSIZE);
   }
+  #endif
 }
 
 bool vendord_deinit(void) {
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
-    vendord_interface_t* p_itf = &_vendord_itf[i];
-    tu_edpt_stream_deinit(&p_itf->stream.rx);
-    tu_edpt_stream_deinit(&p_itf->stream.tx);
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+  for (uint8_t i = 0; i < CFG_TUD_VENDOR; i++) {
+    vendord_interface_t *p_itf = &_vendord_itf[i];
+    tu_edpt_stream_deinit(&p_itf->rx_stream);
+    tu_edpt_stream_deinit(&p_itf->tx_stream);
   }
+  #endif
   return true;
 }
 
@@ -227,11 +243,12 @@ void vendord_reset(uint8_t rhport) {
     vendord_interface_t* p_itf = &_vendord_itf[i];
     tu_memclr(p_itf, ITF_MEM_RESET_SIZE);
 
-    tu_edpt_stream_clear(&p_itf->stream.rx);
-    tu_edpt_stream_close(&p_itf->stream.rx);
-
-    tu_edpt_stream_clear(&p_itf->stream.tx);
-    tu_edpt_stream_close(&p_itf->stream.tx);
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+    tu_edpt_stream_clear(&p_itf->rx_stream);
+    tu_edpt_stream_close(&p_itf->rx_stream);
+    tu_edpt_stream_clear(&p_itf->tx_stream);
+    tu_edpt_stream_close(&p_itf->tx_stream);
+  #endif
   }
 }
 
@@ -241,13 +258,25 @@ static uint8_t find_vendor_itf(uint8_t ep_addr) {
     const vendord_interface_t *p_vendor = &_vendord_itf[idx];
     if (ep_addr == 0) {
       // find unused: require both ep == 0
-      if (p_vendor->stream.rx.ep_addr == 0 && p_vendor->stream.tx.ep_addr == 0) {
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+      if (p_vendor->rx_stream.ep_addr == 0 && p_vendor->tx_stream.ep_addr == 0) {
         return idx;
       }
-    } else if (ep_addr == p_vendor->stream.rx.ep_addr || ep_addr == p_vendor->stream.tx.ep_addr) {
-      return idx;
+  #else
+      if (p_vendor->ep_out == 0 && p_vendor->ep_in == 0) {
+        return idx;
+      }
+  #endif
     } else {
-      // nothing to do
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+      if (ep_addr == p_vendor->rx_stream.ep_addr || ep_addr == p_vendor->tx_stream.ep_addr) {
+        return idx;
+      }
+  #else
+      if (ep_addr == p_vendor->ep_out || ep_addr == p_vendor->ep_in) {
+        return idx;
+      }
+  #endif
     }
   }
   return 0xff;
@@ -273,28 +302,39 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t *desc_itf, uin
       const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
       TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
 
-      // open endpoint stream, skip if already opened (multiple IN/OUT endpoints)
+  #if CFG_TUD_VENDOR_TXRX_BUFFERED
+      // open endpoint stream
       if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
-        tu_edpt_stream_t *stream_tx = &p_vendor->stream.tx;
-        if (stream_tx->ep_addr == 0) {
-          tu_edpt_stream_open(stream_tx, rhport, desc_ep);
-          tu_edpt_stream_write_xfer(stream_tx); // flush pending data
-        }
+        tu_edpt_stream_t *tx_stream = &p_vendor->tx_stream;
+        tu_edpt_stream_open(tx_stream, rhport, desc_ep);
+        tu_edpt_stream_write_xfer(tx_stream); // flush pending data
       } else {
-        tu_edpt_stream_t *stream_rx = &p_vendor->stream.rx;
-        if (stream_rx->ep_addr == 0) {
-          tu_edpt_stream_open(stream_rx, rhport, desc_ep);
-  #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
-          TU_ASSERT(tu_edpt_stream_read_xfer(stream_rx) > 0, 0); // prepare for incoming data
-  #endif
-        }
+        tu_edpt_stream_t *rx_stream = &p_vendor->rx_stream;
+        tu_edpt_stream_open(rx_stream, rhport, desc_ep);
+    #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
+        TU_ASSERT(tu_edpt_stream_read_xfer(rx_stream) > 0, 0); // prepare for incoming data
+    #endif
+      }
+  #else
+      // Non-FIFO mode: store endpoint info
+      if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+        p_vendor->ep_in     = desc_ep->bEndpointAddress;
+        p_vendor->ep_in_mps = tu_edpt_packet_size(desc_ep);
+      } else {
+        p_vendor->ep_out     = desc_ep->bEndpointAddress;
+        p_vendor->ep_out_mps = tu_edpt_packet_size(desc_ep);
+    #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
+        // Prepare for incoming data
+        TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false), 0);
+    #endif
       }
+  #endif
     }
 
     p_desc = tu_desc_next(p_desc);
   }
 
-  return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf);
+  return (uint16_t)((uintptr_t)p_desc - (uintptr_t)desc_itf);
 }
 
 bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
@@ -304,34 +344,36 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
   TU_VERIFY(idx < CFG_TUD_VENDOR);
   vendord_interface_t *p_vendor = &_vendord_itf[idx];
 
-  if (ep_addr == p_vendor->stream.rx.ep_addr) {
-  #if CFG_TUD_VENDOR_RX_BUFSIZE
-    // Received new data: put into stream's fifo
-    tu_edpt_stream_read_xfer_complete(&p_vendor->stream.rx, xferred_bytes);
-  #endif
-
-    // invoke callback
-  #if CFG_TUD_VENDOR_RX_BUFSIZE == 0
-    tud_vendor_rx_cb(idx, p_vendor->stream.rx.ep_buf, xferred_bytes);
-  #else
+#if CFG_TUD_VENDOR_TXRX_BUFFERED
+  if (ep_addr == p_vendor->rx_stream.ep_addr) {
+    // Put received data to FIFO
+    tu_edpt_stream_read_xfer_complete(&p_vendor->rx_stream, xferred_bytes);
     tud_vendor_rx_cb(idx, NULL, 0);
-  #endif
-
-  #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
-    tu_edpt_stream_read_xfer(&p_vendor->stream.rx); // prepare next data
-  #endif
-  } else if (ep_addr == p_vendor->stream.tx.ep_addr) {
+    #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
+    tu_edpt_stream_read_xfer(&p_vendor->rx_stream); // prepare next data
+    #endif
+  } else if (ep_addr == p_vendor->tx_stream.ep_addr) {
     // Send complete
     tud_vendor_tx_cb(idx, (uint16_t)xferred_bytes);
 
-  #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
     // try to send more if possible
-    if (0 == tu_edpt_stream_write_xfer(&p_vendor->stream.tx)) {
+    if (0 == tu_edpt_stream_write_xfer(&p_vendor->tx_stream)) {
       // If there is no data left, a ZLP should be sent if xferred_bytes is multiple of EP Packet size and not zero
-      tu_edpt_stream_write_zlp_if_needed(&p_vendor->stream.tx, xferred_bytes);
+      tu_edpt_stream_write_zlp_if_needed(&p_vendor->tx_stream, xferred_bytes);
     }
-  #endif
   }
+  #else
+  if (ep_addr == p_vendor->ep_out) {
+    // Non-FIFO mode: invoke callback with buffer
+    tud_vendor_rx_cb(idx, _vendord_epbuf[idx].epout, xferred_bytes);
+    #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0
+    usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false);
+    #endif
+  } else if (ep_addr == p_vendor->ep_in) {
+    // Send complete
+    tud_vendor_tx_cb(idx, (uint16_t)xferred_bytes);
+  }
+  #endif
 
   return true;
 }
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index c3de4c49d..101765bb1 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -50,8 +50,14 @@ extern "C" {
   #define CFG_TUD_VENDOR_TX_BUFSIZE 64
 #endif
 
+// Vendor is buffered (FIFO mode) if both TX and RX buffers are configured
+// If either is 0, vendor operates in non-buffered (direct transfer) mode
+#ifndef CFG_TUD_VENDOR_TXRX_BUFFERED
+  #define CFG_TUD_VENDOR_TXRX_BUFFERED ((CFG_TUD_VENDOR_RX_BUFSIZE > 0) && (CFG_TUD_VENDOR_TX_BUFSIZE > 0))
+#endif
+
 // Application will manually schedule RX transfer. This can be useful when using with non-fifo (buffered) mode
-// i.e. CFG_TUD_VENDOR_RX_BUFSIZE = 0
+// i.e. CFG_TUD_VENDOR_TXRX_BUFFERED = 0
 #ifndef CFG_TUD_VENDOR_RX_MANUAL_XFER
   #define CFG_TUD_VENDOR_RX_MANUAL_XFER 0
 #endif
@@ -63,7 +69,8 @@ extern "C" {
 // Return whether the vendor interface is mounted
 bool tud_vendor_n_mounted(uint8_t idx);
 
-#if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+//------------- RX -------------//
+#if CFG_TUD_VENDOR_TXRX_BUFFERED
 // Return number of available bytes for reading
 uint32_t tud_vendor_n_available(uint8_t idx);
 
@@ -82,16 +89,17 @@ void tud_vendor_n_read_flush(uint8_t idx);
 bool tud_vendor_n_read_xfer(uint8_t idx);
 #endif
 
+//------------- TX -------------//
 // Write to TX FIFO. This can be buffered and not sent immediately unless buffered bytes >= USB endpoint size
 uint32_t tud_vendor_n_write(uint8_t idx, const void *buffer, uint32_t bufsize);
 
-#if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+// Return number of bytes available for writing in TX FIFO (or endpoint if non-buffered)
+uint32_t tud_vendor_n_write_available(uint8_t idx);
+
+#if CFG_TUD_VENDOR_TXRX_BUFFERED
 // Force sending buffered data, return number of bytes sent
 uint32_t tud_vendor_n_write_flush(uint8_t idx);
 
-// Return number of bytes available for writing in TX FIFO
-uint32_t tud_vendor_n_write_available(uint8_t idx);
-
 // Clear the transmit FIFO
 bool tud_vendor_n_write_clear(uint8_t idx);
 #endif
@@ -111,7 +119,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_mounted(void) {
   return tud_vendor_n_mounted(0);
 }
 
-#if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+#if CFG_TUD_VENDOR_TXRX_BUFFERED
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_available(void) {
   return tud_vendor_n_available(0);
 }
@@ -127,6 +135,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_read(void *buffer, uint3
 TU_ATTR_ALWAYS_INLINE static inline void tud_vendor_read_flush(void) {
   tud_vendor_n_read_flush(0);
 }
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_flush(void) {
+  return tud_vendor_n_write_flush(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_write_clear(void) {
+  return tud_vendor_n_write_clear(0);
+}
 #endif
 
 #if CFG_TUD_VENDOR_RX_MANUAL_XFER
@@ -143,20 +159,10 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_str(const char *st
   return tud_vendor_n_write_str(0, str);
 }
 
-#if CFG_TUD_VENDOR_TX_BUFSIZE > 0
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_flush(void) {
-  return tud_vendor_n_write_flush(0);
-}
-
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_available(void) {
   return tud_vendor_n_write_available(0);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_write_clear(void) {
-  return tud_vendor_n_write_clear(0);
-}
-#endif
-
 // backward compatible
 #define tud_vendor_flush() tud_vendor_write_flush()
 
@@ -165,8 +171,8 @@ TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_write_clear(void) {
 //--------------------------------------------------------------------+
 
 // Invoked when received new data.
-// - CFG_TUD_VENDOR_RX_BUFSIZE > 0; buffer and bufsize must not be used (both NULL,0) since data is in RX FIFO
-// - CFG_TUD_VENDOR_RX_BUFSIZE = 0: Buffer and bufsize are valid
+// - CFG_TUD_VENDOR_TXRX_BUFFERED = 1: buffer and bufsize must not be used (both NULL,0) since data is in RX FIFO
+// - CFG_TUD_VENDOR_TXRX_BUFFERED = 0: Buffer and bufsize are valid
 void tud_vendor_rx_cb(uint8_t idx, const uint8_t *buffer, uint32_t bufsize);
 
 // Invoked when tx transfer is finished
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index b2375def9..bbcfe45d5 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -70,6 +70,13 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubtype;
+  uint16_t wMaxTransferSize;
+} tusb_desc_cs_video_vc_ep_t;
+
 typedef union {
   struct TU_ATTR_PACKED {
     uint8_t bLength;
@@ -740,6 +747,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
   /* The end of the video control interface descriptor. */
   void const *end = _end_of_control_descriptor(vc);
   if (vc->std.bNumEndpoints != 0) {
+    /* Extend end to cover the standard endpoint and class-specific endpoint descriptors
+     * that follow wTotalLength */
+    end = (uint8_t const*)end + sizeof(tusb_desc_endpoint_t) + sizeof(tusb_desc_cs_video_vc_ep_t);
     /* Find the notification endpoint descriptor. */
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
     TU_ASSERT(cur < end);
@@ -780,6 +790,9 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   if (vc->std.bNumEndpoints != 0) {
     /* Support for 1 endpoint only. */
     TU_VERIFY(1 == vc->std.bNumEndpoints);
+    /* Extend end to cover the standard endpoint and class-specific endpoint descriptors
+     * that follow wTotalLength */
+    end = (uint8_t const*)end + sizeof(tusb_desc_endpoint_t) + sizeof(tusb_desc_cs_video_vc_ep_t);
     /* Find the notification endpoint descriptor. */
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
     TU_VERIFY(cur < end);
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index f14555e4f..2750bb2fb 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -99,8 +99,7 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
  * @param[in]   stm_idx       Destination streaming interface index
  * @param[out]  payload_buf   Payload storage buffer (target buffer for requested data)
  * @param[in]   payload_size  Size of payload_buf (requested data size)
- * @param[in]   offset        Current byte offset relative to given bufsize from tud_video_n_frame_xfer (framesize)
- * @return video_error_code_t */
+ * @param[in]   offset        Current byte offset relative to given bufsize from tud_video_n_frame_xfer (framesize)  */
 void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, tud_video_payload_request_t* request);
 
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a92435912..991ee18ff 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -30,11 +30,6 @@
 
 #define TU_FIFO_DBG 0
 
-// Suppress IAR warning
-// Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
-#if defined(__ICCARM__)
-#pragma diag_suppress = Pa082
-#endif
 
 #if OSAL_MUTEX_REQUIRED
 
@@ -110,8 +105,9 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
 }
 
 //--------------------------------------------------------------------+
-// Pull & Push
-// copy data to/from fifo without updating read/write pointers
+// Hardware FIFO API
+// Support different data access width and address increment scheme
+// Can support multiple i.e both 16 and 32-bit data access if needed
 //--------------------------------------------------------------------+
 #if CFG_TUSB_FIFO_HWFIFO_API
   #if CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE
@@ -122,18 +118,31 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
 
   #define HWFIFO_ADDR_NEXT(_hwfifo, _const) HWFIFO_ADDR_NEXT_N(_hwfifo, _const, CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE)
 
+//------------- Write -------------//
   #ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE
-static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
+TU_ATTR_ALWAYS_INLINE static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
+  (void)data_stride; // possible unused
     #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
-  if (data_stride == 4) {
+      #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
+  if (data_stride == 4)
+      #endif
+  {
     *((volatile uint32_t *)hwfifo) = tu_unaligned_read32(src);
   }
-  #endif
-  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
-  if (data_stride == 2) {
+    #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
+      #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 2
+  if (data_stride == 2)
+      #endif
+  {
     *((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
   }
-  #endif
+    #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+  *((volatile uint8_t *)hwfifo) = *(const uint8_t *)src;
+    #endif
 }
 
 // Copy from fifo to fixed address buffer (usually a tx register) with TU_FIFO_FIXED_ADDR_RW32 mode
@@ -147,7 +156,8 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, );
   }
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
   // 16-bit access is allowed for odd bytes
   if (len >= 2) {
     *((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
@@ -155,16 +165,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     len -= 2;
     HWFIFO_ADDR_NEXT_N(hwfifo, , 2);
   }
-    #endif
+      #endif
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
   // 8-bit access is allowed for odd bytes
   while (len > 0) {
     *((volatile uint8_t *)hwfifo) = *src++;
     len--;
     HWFIFO_ADDR_NEXT_N(hwfifo, , 1);
   }
-    #else
+      #else
 
   // Write odd bytes i.e 1 byte for 16 bit or 1-3 bytes for 32 bit
   if (len > 0) {
@@ -173,13 +183,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     stride_write(hwfifo, &tmp, data_stride);
     HWFIFO_ADDR_NEXT(hwfifo, );
   }
+      #endif
     #endif
 }
   #endif
 
+//------------- Read -------------//
   #ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_READ
-static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
+TU_ATTR_ALWAYS_INLINE static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
   (void)data_stride; // possible unused
+
     #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
       #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
   if (data_stride == 4)
@@ -197,6 +210,10 @@ static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t
     tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
   }
     #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+  *(uint8_t *)dest = *((const volatile uint8_t *)hwfifo);
+    #endif
 }
 
 void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, const tu_hwfifo_access_t *access_mode) {
@@ -209,7 +226,8 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, const);
   }
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
   // 16-bit access is allowed for odd bytes
   if (len >= 2) {
     tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
@@ -235,6 +253,7 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, const);
   }
     #endif
+    #endif
 }
   #endif
 
@@ -251,13 +270,17 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
     tu_hwfifo_read(hwfifo, ff_buf, n, access_mode);
   } else {
     // Wrap around case
-
+  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+    tu_hwfifo_read(hwfifo, ff_buf, lin_bytes, access_mode);     // linear part
+    HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_bytes);
+    tu_hwfifo_read(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
+  #else
     // Write full words to linear part of buffer
     const uint8_t  data_stride = access_mode->data_stride;
     const uint32_t odd_mask    = data_stride - 1;
     uint16_t       lin_even    = lin_bytes & ~odd_mask;
     tu_hwfifo_read(hwfifo, ff_buf, lin_even, access_mode);
-    HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_even);
+    HWFIFO_ADDR_NEXT_N(hwfifo, const, (lin_even / data_stride) * CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE);
     ff_buf += lin_even;
 
     // There could be odd 1 byte (16bit) or 1-3 bytes (32bit) before the wrap-around boundary
@@ -286,6 +309,7 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
     if (wrap_bytes > 0) {
       tu_hwfifo_read(hwfifo, ff_buf, wrap_bytes, access_mode);
     }
+  #endif
   }
 }
 
@@ -303,13 +327,17 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
     tu_hwfifo_write(hwfifo, ff_buf, n, access_mode);
   } else {
     // Wrap around case
-
+  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+    tu_hwfifo_write(hwfifo, ff_buf, lin_bytes, access_mode);     // linear part
+    HWFIFO_ADDR_NEXT_N(hwfifo, , lin_bytes);
+    tu_hwfifo_write(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
+  #else
     // Read full words from linear part
     const uint8_t  data_stride = access_mode->data_stride;
     const uint32_t odd_mask    = data_stride - 1;
-    uint16_t       lin_even = lin_bytes & ~odd_mask;
+    uint16_t       lin_even    = lin_bytes & ~odd_mask;
     tu_hwfifo_write(hwfifo, ff_buf, lin_even, access_mode);
-    HWFIFO_ADDR_NEXT_N(hwfifo, , lin_even);
+    HWFIFO_ADDR_NEXT_N(hwfifo, , (lin_even / data_stride) * CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE);
     ff_buf += lin_even;
 
     // There could be odd 1 byte (16bit) or 1-3 bytes (32bit) before the wrap-around boundary
@@ -338,10 +366,15 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
     if (wrap_bytes > 0) {
       tu_hwfifo_write(hwfifo, ff_buf, wrap_bytes, access_mode);
     }
+  #endif
   }
 }
 #endif
 
+//--------------------------------------------------------------------+
+// Pull & Push
+// copy data to/from fifo without updating read/write pointers
+//--------------------------------------------------------------------+
 // send n items to fifo WITHOUT updating write pointer
 static void ff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uint16_t wr_ptr) {
   uint16_t lin_bytes  = f->depth - wr_ptr;
@@ -458,7 +491,9 @@ uint16_t tu_fifo_peek_n_access_mode(tu_fifo_t *f, void *p_buffer, uint16_t n, ui
 // Read n items without removing it from the FIFO, correct read pointer if overflowed
 uint16_t tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n) {
   ff_lock(f->mutex_rd);
-  const uint16_t ret = tu_fifo_peek_n_access_mode(f, p_buffer, n, f->wr_idx, f->rd_idx, NULL);
+  const uint16_t wr_idx = f->wr_idx;
+  const uint16_t rd_idx = f->rd_idx;
+  const uint16_t ret = tu_fifo_peek_n_access_mode(f, p_buffer, n, wr_idx, rd_idx, NULL);
   ff_unlock(f->mutex_rd);
   return ret;
 }
@@ -468,7 +503,8 @@ uint16_t tu_fifo_read_n_access_mode(tu_fifo_t *f, void *buffer, uint16_t n, cons
   ff_lock(f->mutex_rd);
 
   // Peek the data: f->rd_idx might get modified in case of an overflow so we can not use a local variable
-  n         = tu_fifo_peek_n_access_mode(f, buffer, n, f->wr_idx, f->rd_idx, access_mode);
+  const uint16_t wr_idx = f->wr_idx;
+  n         = tu_fifo_peek_n_access_mode(f, buffer, n, wr_idx, f->rd_idx, access_mode);
   f->rd_idx = advance_index(f->depth, f->rd_idx, n);
 
   ff_unlock(f->mutex_rd);
@@ -595,7 +631,8 @@ static bool ff_peek_local(tu_fifo_t *f, void *buf, uint16_t wr_idx, uint16_t rd_
 bool tu_fifo_read(tu_fifo_t *f, void *buffer) {
   // Peek the data
   // f->rd_idx might get modified in case of an overflow so we can not use a local variable
-  const bool ret = ff_peek_local(f, buffer, f->wr_idx, f->rd_idx);
+  const uint16_t wr_idx = f->wr_idx;
+  const bool ret = ff_peek_local(f, buffer, wr_idx, f->rd_idx);
   if (ret) {
     ff_lock(f->mutex_rd);
     f->rd_idx = advance_index(f->depth, f->rd_idx, 1);
@@ -607,7 +644,9 @@ bool tu_fifo_read(tu_fifo_t *f, void *buffer) {
 
 // Read one item without removing it from the FIFO, correct read index if overflowed
 bool tu_fifo_peek(tu_fifo_t *f, void *p_buffer) {
-  return ff_peek_local(f, p_buffer, f->wr_idx, f->rd_idx);
+  const uint16_t wr_idx = f->wr_idx;
+  const uint16_t rd_idx = f->rd_idx;
+  return ff_peek_local(f, p_buffer, wr_idx, rd_idx);
 }
 
 // Write one element into the buffer
@@ -787,6 +826,6 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) {
   } else {
     info->linear.len  = f->depth - wr_ptr;
     info->wrapped.len = remain - info->linear.len; // Remaining length - n already was limited to remain or FIFO depth
-    info->wrapped.ptr = f->buffer;              // Always start of buffer
+    info->wrapped.ptr = f->buffer;                 // Always start of buffer
   }
 }
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 86ba59059..b31a0802e 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -120,9 +120,9 @@ typedef struct {
   uint8_t *buffer;              // buffer pointer
   uint16_t depth;               // max items
   bool     overwritable;        // overwritable when full
-  // 1 byte padding  here
+  // 1 byte padding here
 
-  volatile uint16_t wr_idx;     // write index TODO maybe can drop volatile
+  volatile uint16_t wr_idx;     // write index
   volatile uint16_t rd_idx;     // read index
 
 #if OSAL_MUTEX_REQUIRED
@@ -291,16 +291,22 @@ TU_ATTR_ALWAYS_INLINE static inline bool tu_fifo_empty(const tu_fifo_t *f) {
 
 // return number of items in fifo, capped to fifo's depth
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_count(const tu_fifo_t *f) {
-  return tu_min16(tu_ff_overflow_count(f->depth, f->wr_idx, f->rd_idx), f->depth);
+  const uint16_t wr_idx = f->wr_idx;
+  const uint16_t rd_idx = f->rd_idx;
+  return tu_min16(tu_ff_overflow_count(f->depth, wr_idx, rd_idx), f->depth);
 }
 
 // check if fifo is full
 TU_ATTR_ALWAYS_INLINE static inline bool tu_fifo_full(const tu_fifo_t *f) {
-  return tu_ff_overflow_count(f->depth, f->wr_idx, f->rd_idx) >= f->depth;
+  const uint16_t wr_idx = f->wr_idx;
+  const uint16_t rd_idx = f->rd_idx;
+  return tu_ff_overflow_count(f->depth, wr_idx, rd_idx) >= f->depth;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_remaining(const tu_fifo_t *f) {
-  return tu_ff_remaining_local(f->depth, f->wr_idx, f->rd_idx);
+  const uint16_t wr_idx = f->wr_idx;
+  const uint16_t rd_idx = f->rd_idx;
+  return tu_ff_remaining_local(f->depth, wr_idx, rd_idx);
 }
 
 #ifdef __cplusplus
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1a4e517b7..edc7ecc3e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -71,13 +71,24 @@
   #define TUP_DCD_ENDPOINT_MAX 5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC54)
+  #include "fsl_device_registers.h"
+
   // TODO USB0 has 5, USB1 has 6
   #define TUP_USBIP_IP3511
+
+  #if !defined(LPC54114_cm4_SERIES) && !defined(LPC54114_cm0plus_SERIES)
+    #define TUP_USBIP_IP3516
+    #define TUP_USBIP_OHCI
+    #define TUP_USBIP_OHCI_NXP
+    #define TUP_OHCI_RHPORTS     1 // 1 downstream port
+  #endif
+
   #define TUP_DCD_ENDPOINT_MAX 6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC55)
   // TODO USB0 has 5, USB1 has 6
   #define TUP_USBIP_IP3511
+  #define TUP_USBIP_IP3516
   #define TUP_USBIP_OHCI
   #define TUP_USBIP_OHCI_NXP
   #define TUP_OHCI_RHPORTS     1 // 1 downstream port
@@ -172,6 +183,10 @@
   #define TUP_RHPORT_HIGHSPEED 1
   #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
 
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_SAMX7X_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
+
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
   #define TUP_DCD_ENDPOINT_MAX 8
   #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
@@ -635,17 +650,7 @@
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 4
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
+#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405, OPT_MCU_AT32F423, OPT_MCU_AT32F425, OPT_MCU_AT32F435_437, OPT_MCU_AT32F45X)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 8
@@ -657,11 +662,6 @@
     #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
 //--------------------------------------------------------------------+
 // HPMicro
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index 10e12c2af..17ab267c3 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef TUSB_PRIVATE_H_
-#define TUSB_PRIVATE_H_
+#ifndef TUSB_PRIVATE_H
+#define TUSB_PRIVATE_H
 
 // Internal Helper used by Host and Device Stack
 
@@ -33,17 +33,11 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Configuration
-//--------------------------------------------------------------------+
+typedef void (*tusb_defer_func_t)(uintptr_t param);
 
-#if CFG_TUD_ENABLED && CFG_TUD_VENDOR && (CFG_TUD_VENDOR_TX_BUFSIZE == 0 || CFG_TUD_VENDOR_RX_BUFSIZE == 0)
-  #define CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED 1
-#endif
-
-#ifndef CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
-  #define CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED 0
-#endif
+ //--------------------------------------------------------------------+
+ // Configuration
+ //--------------------------------------------------------------------+
 
 #define TUP_USBIP_CONTROLLER_NUM 2
 extern tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM];
@@ -87,9 +81,8 @@ typedef struct {
 bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed);
 #else
 TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) {
-  (void)desc_ep;
   (void)speed;
-  return true;
+  return tu_edpt_packet_size(desc_ep) > 0;
 }
 #endif
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index d473e53e6..8a48a0f04 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -341,12 +341,10 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
   uint8_t  bDescriptorType    ; ///< DEVICE Descriptor Type.
   uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H).
-
   uint8_t  bDeviceClass       ; ///< Class code (assigned by the USB-IF).
   uint8_t  bDeviceSubClass    ; ///< Subclass code (assigned by the USB-IF).
   uint8_t  bDeviceProtocol    ; ///< Protocol code (assigned by the USB-IF).
   uint8_t  bMaxPacketSize0    ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64.
-
   uint16_t idVendor           ; ///< Vendor ID (assigned by the USB-IF).
   uint16_t idProduct          ; ///< Product ID (assigned by the manufacturer).
   uint16_t bcdDevice          ; ///< Device release number in binary-coded decimal.
@@ -554,7 +552,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) {
-  return (uint8_t) (num | (dir == TUSB_DIR_IN ? TUSB_DIR_IN_MASK : 0u));
+  return (uint8_t) (num | (dir == (uint8_t)TUSB_DIR_IN ? (uint8_t)TUSB_DIR_IN_MASK : 0u));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index c9e06361c..bd00b9d11 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -73,8 +73,13 @@
   #define TU_MESS_FAILED() do {} while (0)
 #endif
 
+// Custom defined application function
+#ifdef CFG_TUSB_DEBUG_BREAKPOINT
+  extern void CFG_TUSB_DEBUG_BREAKPOINT(void);
+  #define TU_BREAKPOINT() CFG_TUSB_DEBUG_BREAKPOINT()
+
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
     defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
   #define TU_BREAKPOINT() do {                                                                              \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1e21c667a..42903576c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -334,6 +334,19 @@ static const usbd_class_driver_t _usbd_driver[] = {
         .sof              = NULL
     },
     #endif
+
+    #if CFG_TUD_PRINTER
+    {
+        .name             = DRIVER_NAME("PRINTER"),
+        .init             = printerd_init,
+        .deinit           = printerd_deinit,
+        .reset            = printerd_reset,
+        .open             = printerd_open,
+        .control_xfer_cb  = printerd_control_xfer_cb,
+        .xfer_cb          = printerd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
@@ -585,7 +598,7 @@ bool tud_deinit(uint8_t rhport) {
   // Deinit device controller driver
   dcd_int_disable(rhport);
   dcd_disconnect(rhport);
-  TU_VERIFY(dcd_deinit(rhport));
+  TU_ASSERT(dcd_deinit(rhport));
 
   // Deinit class drivers
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
@@ -666,8 +679,14 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
     return;
   }
 
-  // Loop until there is no more events in the queue
-  while (1) {
+  // Loop until there are no more events in the queue or CFG_TUD_TASK_EVENTS_PER_RUN is reached
+  for (unsigned epr = 0;; epr++) {
+#if CFG_TUD_TASK_EVENTS_PER_RUN > 0
+    if (epr >= CFG_TUD_TASK_EVENTS_PER_RUN) {
+      TU_LOG_USBD("USBD event limit (" TU_XSTRING(CFG_TUD_TASK_EVENTS_PER_RUN) ") reached\r\n");
+      break;
+    }
+#endif
     dcd_event_t event;
     if (!osal_queue_receive(_usbd_q, &event, timeout_ms)) {
       return;
@@ -817,7 +836,9 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) {
     TU_LOG_USBD("  %s", tu_str_std_request[p_request->bRequest]);
-    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n");
+    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) {
+      TU_LOG_USBD("\r\n");
+    }
   }
 #endif
 
@@ -953,7 +974,25 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 
     //------------- Class/Interface Specific Request -------------//
     case TUSB_REQ_RCPT_INTERFACE: {
-      uint8_t const itf = tu_u16_low(p_request->wIndex);
+      uint8_t itf;
+      #if CFG_TUD_PRINTER
+      // Printer GET_DEVICE_ID has a weird wIndex = interface (high) | alt (low)
+      // attempt to interpret this as a printer request if matched
+      if (TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type &&
+          TUSB_DIR_IN == p_request->bmRequestType_bit.direction &&
+          TUSB_PRINTER_REQUEST_GET_DEVICE_ID == p_request->bRequest) {
+        itf = tu_u16_high(p_request->wIndex);
+        if (itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)) {
+          const usbd_class_driver_t * driver = get_driver(_usbd_dev.itf2drv[itf]);
+          if (driver != NULL && driver->control_xfer_cb == printerd_control_xfer_cb) {
+            if (invoke_class_control(rhport, driver, p_request)) {
+              return true;
+            }
+          }
+        }
+      }
+      #endif
+      itf = tu_u16_low(p_request->wIndex);
       TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
 
       usbd_class_driver_t const * driver = get_driver(_usbd_dev.itf2drv[itf]);
diff --git a/src/device/usbd.h b/src/device/usbd.h
index bd5a3c395..d3a6dccbb 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -41,8 +41,13 @@ enum {
 
 typedef struct {
   uint16_t bm_double_buffered; // bitmap of IN endpoints to be double buffered, only effective for bulk endpoints
+  bool vbus_sensing; // Vbus pin is used for device connection detection, mandatory for tud_umount_cb()
 } tud_configure_dwc2_t;
 
+  #ifndef CFG_TUD_CONFIGURE_DWC2_DEFAULT
+    #define CFG_TUD_CONFIGURE_DWC2_DEFAULT {.bm_double_buffered = 0, .vbus_sensing = CFG_TUD_VBUS_DETECT_HW}
+  #endif
+
 typedef union {
   tud_configure_dwc2_t dwc2;
 } tud_configure_param_t;
@@ -292,6 +297,19 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
+//--------------------------------------------------------------------+
+// Printer Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_PRINTER_DESC_LEN (9 + 7 + 7)  // one interface, two endpoints
+
+#define TUD_PRINTER_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \
+  /* Interface */\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_PRINTER, 1, 2, _stridx,\
+  /* Endpoint Out */\
+  7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+  /* Endpoint In */\
+  7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
 //--------------------------------------------------------------------+
 // MTP Descriptor Templates
@@ -819,7 +837,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
   /* Interface */ \
   9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_RT, _stridx, \
   /* Function */ \
-  9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
+  9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0110)
 
 //--------------------------------------------------------------------+
 // DFU Descriptor Templates
@@ -833,7 +851,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
 #define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \
   TU_XSTRCAT(TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \
   /* Function */ \
-  9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
+  9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0110)
 
 #define TUD_DFU_ALT(_itfnum, _alt, _stridx) \
   /* Interface */ \
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 36a7f5da5..47d672f9e 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -59,7 +59,7 @@ typedef enum {
   HCD_EVENT_XFER_COMPLETE,
 
   USBH_EVENT_FUNC_CALL, // Not an HCD event
-  HCD_EVENT_COUNT
+  HCD_EVENT_INVALID
 } hcd_eventid_t;
 
 typedef struct {
@@ -72,7 +72,6 @@ typedef struct {
     struct {
       uint8_t hub_addr;
       uint8_t hub_port;
-      uint8_t speed;
     } connection;
 
     // XFER_COMPLETE
diff --git a/src/host/hub.c b/src/host/hub.c
index 3baaff30f..7c6735ed4 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -48,7 +48,7 @@ typedef struct {
   uint8_t bNbrPorts;
   uint8_t bPwrOn2PwrGood_2ms; // port power on to good, in 2ms unit
   // uint16_t wHubCharacteristics;
-
+  bool mtt;
   hub_port_status_response_t port_status;
 } hub_interface_t;
 
@@ -218,23 +218,37 @@ bool hub_deinit(void) {
   return true;
 }
 
-uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
-  (void) rhport;
-
-  TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass &&
-            0              == itf_desc->bInterfaceSubClass, 0);
-  TU_VERIFY(itf_desc->bInterfaceProtocol <= 1, 0); // not support multiple TT yet
+uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
+  (void)rhport;
+  TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass && 0 == itf_desc->bInterfaceSubClass, 0);
 
-  const uint16_t drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
+  const uint16_t itf_ep_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
+  uint16_t       drv_len    = itf_ep_len;
   TU_ASSERT(drv_len <= max_len, 0);
 
+  hub_interface_t             *p_hub        = get_hub_itf(dev_addr);
+  const tusb_desc_interface_t *desc_itf_use = itf_desc; // interface to use for endpoint open
+
+  // Check device descriptor for MTT hub (bDeviceProtocol == 2)
+  // MTT hub has 2 alt settings: alt 0 is STT (protocol 1), alt 1 is MTT (protocol 2)
+  // Consume both alt settings and use alt setting 1 for endpoint
+  tusb_desc_device_t desc_dev;
+  if (tuh_descriptor_get_device_local(dev_addr, &desc_dev) && desc_dev.bDeviceProtocol == HUB_PROTOCOL_HIGH_SPEED_MTT) {
+    drv_len += itf_ep_len;
+    TU_ASSERT(drv_len <= max_len, 0);
+    const tusb_desc_interface_t *desc_alt1 = (const tusb_desc_interface_t *)((const uint8_t *)itf_desc + itf_ep_len);
+    TU_ASSERT(desc_alt1->bDescriptorType == TUSB_DESC_INTERFACE && desc_alt1->bInterfaceClass == TUSB_CLASS_HUB &&
+                desc_alt1->bInterfaceProtocol == HUB_PROTOCOL_HIGH_SPEED_MTT,
+              0);
+    p_hub->mtt   = true;
+    desc_itf_use = desc_alt1;
+  }
+
   // Interrupt Status endpoint
-  tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
-  TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
-            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
+  const tusb_desc_endpoint_t *desc_ep = (const tusb_desc_endpoint_t *)tu_desc_next(desc_itf_use);
+  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
   TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep), 0);
 
-  hub_interface_t* p_hub = get_hub_itf(dev_addr);
   p_hub->itf_num = itf_desc->bInterfaceNumber;
   p_hub->ep_in   = desc_ep->bEndpointAddress;
 
@@ -269,12 +283,27 @@ bool hub_edpt_status_xfer(uint8_t daddr) {
 //--------------------------------------------------------------------+
 static void config_set_port_power (tuh_xfer_t* xfer);
 static void config_port_power_complete (tuh_xfer_t* xfer);
+static void config_get_hub_descriptor(tuh_xfer_t* xfer);
 
 bool hub_set_config(uint8_t daddr, uint8_t itf_num) {
   hub_interface_t* p_hub = get_hub_itf(daddr);
   TU_ASSERT(itf_num == p_hub->itf_num);
-  hub_epbuf_t* p_epbuf = get_hub_epbuf(daddr);
 
+  if (p_hub->mtt) {
+    // Set Alternate Setting 1 for MTT hub
+    TU_ASSERT(tuh_interface_set(daddr, itf_num, 1, config_get_hub_descriptor, 0));
+  } else {
+    tuh_xfer_t xfer;
+    xfer.daddr     = daddr;
+    xfer.ep_addr   = 0;
+    xfer.user_data = 0;
+    config_get_hub_descriptor(&xfer);
+  }
+
+  return true;
+}
+
+static void config_get_hub_descriptor(tuh_xfer_t* xfer) {
   // Get Hub Descriptor
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -288,17 +317,11 @@ bool hub_set_config(uint8_t daddr, uint8_t itf_num) {
     .wLength  = sizeof(hub_desc_cs_t)
   };
 
-  tuh_xfer_t xfer = {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = p_epbuf->ctrl_buf,
-    .complete_cb = config_set_port_power,
-    .user_data    = 0
-  };
+  xfer->setup       = &request;
+  xfer->buffer      = get_hub_epbuf(xfer->daddr)->ctrl_buf;
+  xfer->complete_cb = config_set_port_power;
 
-  TU_ASSERT(tuh_control_xfer(&xfer));
-  return true;
+  TU_ASSERT(tuh_control_xfer(xfer), );
 }
 
 static void config_set_port_power (tuh_xfer_t* xfer) {
@@ -308,7 +331,7 @@ static void config_set_port_power (tuh_xfer_t* xfer) {
   hub_interface_t* p_hub = get_hub_itf(daddr);
   hub_epbuf_t* p_epbuf = get_hub_epbuf(daddr);
 
-  // only use number of ports in hub descriptor
+  // only use the number of ports in the hub descriptor
   hub_desc_cs_t const* desc_hub = (hub_desc_cs_t const*) p_epbuf->ctrl_buf;
   p_hub->bNbrPorts = desc_hub->bNbrPorts;
   p_hub->bPwrOn2PwrGood_2ms = desc_hub->bPwrOn2PwrGood;
diff --git a/src/host/hub.h b/src/host/hub.h
index d9750f8a5..8a7feda70 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -92,6 +92,13 @@ enum {
   HUB_CHARS_OVER_CURRENT_INDIVIDUAL = 1,
 };
 
+// Hub Interface Protocol (USB 2.0 spec Table 11-16)
+typedef enum {
+  HUB_PROTOCOL_FULL_SPEED     = 0, // Full speed hub
+  HUB_PROTOCOL_HIGH_SPEED_STT = 1, // Hi-speed hub with single TT
+  HUB_PROTOCOL_HIGH_SPEED_MTT = 2, // Hi-speed hub with multiple TTs
+} hub_protocol_t;
+
 typedef struct TU_ATTR_PACKED{
   uint8_t  bLength           ; ///< Size of descriptor
   uint8_t  bDescriptorType   ; ///< Other_speed_Configuration Type
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a725b7c8b..75df6bf60 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -104,10 +104,9 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr) {
 //--------------------------------------------------------------------+
 // Data Structure
 //--------------------------------------------------------------------+
-typedef struct {
-  tuh_bus_info_t bus_info;
 
-  // Device Descriptor
+// Device Descriptor (without bLength and bDescriptorType header)
+typedef struct TU_ATTR_PACKED {
   uint16_t bcdUSB;
   uint8_t  bDeviceClass;
   uint8_t  bDeviceSubClass;
@@ -120,6 +119,13 @@ typedef struct {
   uint8_t  iProduct;
   uint8_t  iSerialNumber;
   uint8_t  bNumConfigurations;
+} desc_device_noheader_t;
+
+TU_VERIFY_STATIC( sizeof(desc_device_noheader_t) == 16u, "size is not correct");
+
+typedef struct {
+  tuh_bus_info_t bus_info;
+  desc_device_noheader_t desc_device;
 
   // Device State
   struct TU_ATTR_PACKED {
@@ -169,6 +175,12 @@ static OSAL_SPINLOCK_DEF(_usbh_spin, usbh_int_set);
 OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
+  #if CFG_TUH_HUB
+// Deferred attachment queue, only needed when using hub
+OSAL_QUEUE_DEF(usbh_int_set, _usbh_daqdef, CFG_TUH_HUB, hcd_event_t);
+static osal_queue_t _usbh_daq;
+  #endif
+
 // Control transfers: since most controllers do not support multiple control transfers
 // on multiple devices concurrently and control transfers are not used much except for
 // enumeration, we will only execute control transfers one at a time.
@@ -184,11 +196,18 @@ typedef struct {
 } usbh_ctrl_xfer_info_t;
 
 typedef struct {
+  tusb_defer_func_t func;
+  uintptr_t         arg;
+  uint32_t          at_ms;
+} usbh_call_after_t;
+
+typedef struct {
   uint8_t controller_id;      // controller ID
   uint8_t enumerating_daddr;  // device address of the device being enumerated
   uint8_t attach_debouncing_bm;  // bitmask for roothub port attach debouncing
   tuh_bus_info_t dev0_bus;    // bus info for dev0 in enumeration
   usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer
+  usbh_call_after_t call_after;
 } usbh_data_t;
 
 static usbh_data_t _usbh_data = {
@@ -311,7 +330,8 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_class_driver_t const *get_driver(uint8_
 //--------------------------------------------------------------------+
 // Function Inline and Prototypes
 //--------------------------------------------------------------------+
-static bool enum_new_device(hcd_event_t* event);
+static void enum_new_device(hcd_event_t* event);
+static void enum_delay_async(uintptr_t state);
 static void process_remove_event(hcd_event_t *event);
 static void remove_device_tree(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
@@ -349,6 +369,15 @@ TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const ui
   return ret;
 }
 
+bool usbh_defer_func_ms_async(uint32_t ms, tusb_defer_func_t func, uintptr_t param) {
+  TU_ASSERT(_usbh_data.call_after.func == NULL);
+  TU_LOG_USBH("USBH schedule function after %u ms\r\n", (unsigned int)ms);
+  _usbh_data.call_after.func  = func;
+  _usbh_data.call_after.arg   = param;
+  _usbh_data.call_after.at_ms = tusb_time_millis_api() + ms;
+  return true;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void usbh_device_close(uint8_t rhport, uint8_t daddr) {
   hcd_device_close(rhport, daddr);
 
@@ -360,6 +389,10 @@ TU_ATTR_ALWAYS_INLINE static inline void usbh_device_close(uint8_t rhport, uint8
   // invalidate if enumerating
   if (daddr == _usbh_data.enumerating_daddr) {
     _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8;
+    // clear enum delay function of the device being removed
+    if (_usbh_data.call_after.func == enum_delay_async) {
+      _usbh_data.call_after.func = NULL;
+    }
   }
 }
 
@@ -386,10 +419,10 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = *pid = 0;
 
   usbh_device_t const *dev = get_device(dev_addr);
-  TU_VERIFY(dev && dev->addressed && dev->idVendor != 0);
+  TU_VERIFY(dev && dev->addressed && dev->desc_device.idVendor != 0);
 
-  *vid = dev->idVendor;
-  *pid = dev->idProduct;
+  *vid = dev->desc_device.idVendor;
+  *pid = dev->desc_device.idProduct;
 
   return true;
 }
@@ -400,18 +433,7 @@ bool tuh_descriptor_get_device_local(uint8_t daddr, tusb_desc_device_t* desc_dev
 
   desc_device->bLength = sizeof(tusb_desc_device_t);
   desc_device->bDescriptorType = TUSB_DESC_DEVICE;
-  desc_device->bcdUSB = dev->bcdUSB;
-  desc_device->bDeviceClass = dev->bDeviceClass;
-  desc_device->bDeviceSubClass = dev->bDeviceSubClass;
-  desc_device->bDeviceProtocol = dev->bDeviceProtocol;
-  desc_device->bMaxPacketSize0 = dev->bMaxPacketSize0;
-  desc_device->idVendor = dev->idVendor;
-  desc_device->idProduct = dev->idProduct;
-  desc_device->bcdDevice = dev->bcdDevice;
-  desc_device->iManufacturer = dev->iManufacturer;
-  desc_device->iProduct = dev->iProduct;
-  desc_device->iSerialNumber = dev->iSerialNumber;
-  desc_device->bNumConfigurations = dev->bNumConfigurations;
+  memcpy((uint8_t*) desc_device + offsetof(tusb_desc_device_t, bcdUSB), &dev->desc_device, sizeof(desc_device_noheader_t));
 
   return true;
 }
@@ -493,11 +515,17 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
     _usbh_q = osal_queue_create(&_usbh_qdef);
     TU_ASSERT(_usbh_q != NULL);
 
-#if OSAL_MUTEX_REQUIRED
+  #if CFG_TUH_HUB
+    // Deferred attachment queue
+    _usbh_daq = osal_queue_create(&_usbh_daqdef);
+    TU_ASSERT(_usbh_daq != NULL);
+  #endif
+
+  #if OSAL_MUTEX_REQUIRED
     // Init mutex
     _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
     TU_ASSERT(_usbh_mutex);
-#endif
+  #endif
 
     // Get application driver if available
     _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
@@ -538,7 +566,7 @@ bool tuh_deinit(uint8_t rhport) {
 
   // deinit host controller
   hcd_int_disable(rhport);
-  hcd_deinit(rhport);
+  TU_ASSERT(hcd_deinit(rhport));
   _usbh_data.controller_id = TUSB_INDEX_INVALID_8;
 
   // remove all devices on this rhport (hub_addr = 0, hub_port = 0)
@@ -558,11 +586,16 @@ bool tuh_deinit(uint8_t rhport) {
     osal_queue_delete(_usbh_q);
     _usbh_q = NULL;
 
-    #if OSAL_MUTEX_REQUIRED
+  #if CFG_TUH_HUB
+    osal_queue_delete(_usbh_daq);
+    _usbh_daq = NULL;
+  #endif
+
+  #if OSAL_MUTEX_REQUIRED
     // TODO make sure there is no task waiting on this mutex
     osal_mutex_delete(_usbh_mutex);
     _usbh_mutex = NULL;
-    #endif
+  #endif
   }
 
   return true;
@@ -570,9 +603,19 @@ bool tuh_deinit(uint8_t rhport) {
 
 bool tuh_task_event_ready(void) {
   if (!tuh_inited()) {
-    return false; // Skip if stack is not initialized
+    return false; // Skip if tusb stack is not initialized
   }
-  return !osal_queue_empty(_usbh_q);
+  if (!osal_queue_empty(_usbh_q)) {
+    return true;
+  }
+
+  #if CFG_TUH_HUB
+  if (!osal_queue_empty(_usbh_daq)) {
+    return true;
+  }
+  #endif
+
+  return false;
 }
 
 /* USB Host Driver task
@@ -592,45 +635,87 @@ bool tuh_task_event_ready(void) {
     @endcode
  */
 void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
-  (void) in_isr; // not implemented yet
-
   // Skip if stack is not initialized
   if (!tuh_inited()) {
     return;
   }
 
-  // Loop until there is no more events in the queue
-  while (1) {
+  (void) in_isr; // not implemented yet
+
+  // Loop until there are no more events in the queue or CFG_TUH_TASK_EVENTS_PER_RUN is reached
+  for (unsigned epr = 0;; epr++) {
+  #if CFG_TUH_TASK_EVENTS_PER_RUN > 0
+    if (epr >= CFG_TUH_TASK_EVENTS_PER_RUN) {
+      TU_LOG_USBH("USBH event limit (" TU_XSTRING(CFG_TUH_TASK_EVENTS_PER_RUN) ") reached\r\n");
+      break;
+    }
+  #endif
+
+    // Process call_after_ms function if ms is reached
+    tusb_defer_func_t after_cb = _usbh_data.call_after.func;
+    if (after_cb) {
+      int32_t remain_ms = (int32_t)(_usbh_data.call_after.at_ms - tusb_time_millis_api());
+      if (remain_ms <= 0) {
+        // delay expired, run callback now
+        TU_LOG_USBH("USBH invoke scheduled function\r\n");
+        _usbh_data.call_after.func = NULL;
+        after_cb(_usbh_data.call_after.arg);
+      }
+
+      // above after_cb() can re-schedule another function, we need to re-check and reduce timeout of
+      // the main event timeout to make sure we aren't blocking more than call_after remaining ms.
+      if (_usbh_data.call_after.func != NULL) {
+        remain_ms = (int32_t) (_usbh_data.call_after.at_ms - tusb_time_millis_api());
+        if (remain_ms <= 0) {
+          timeout_ms = 0; // expired already
+        } else if (timeout_ms > (uint32_t)remain_ms) {
+          timeout_ms = (uint32_t)remain_ms;
+        }
+      }
+    }
+
     hcd_event_t event;
-    if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; }
+
+  #if CFG_TUH_HUB
+    // Get deferred device attachments if none is enumerating
+    bool has_deferred_attach = false;
+    if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) {
+      // zero wait to avoid blocking the main event queue
+      has_deferred_attach = osal_queue_receive(_usbh_daq, &event, 0);
+    }
+
+    if (!has_deferred_attach) // skip event queue to process deferred attach
+  #endif
+    {
+      if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) {
+        return;
+      }
+    }
 
     switch (event.event_id) {
       case HCD_EVENT_DEVICE_ATTACH:
         // Should we miss the hub detach event due to high traffic, Or due to physical debouncing, some devices can
-        // cause multiple attaches (actually reset) without detach event.
+        // cause multiple attaches (actually reset) without a detached event.
         // Force remove currently mounted with the same bus info (rhport, hub addr, hub port) if exists
         process_remove_event(&event);
 
         // due to the shared control buffer, we must fully complete enumerating one device first.
-        // TODO better to have an separated queue for newly attached devices
         if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) {
           // New device attached and we are ready
           TU_LOG_USBH("[%u:] USBH Device Attach\r\n", event.rhport);
           _usbh_data.enumerating_daddr = 0; // enumerate new device with address 0
           enum_new_device(&event);
-        } else {
-          // currently enumerating another device
+        }
+  #if CFG_TUH_HUB
+        else {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
-          const bool is_empty = osal_queue_empty(_usbh_q);
-          queue_event(&event, in_isr);
-          if (is_empty) {
-            return; // Exit if this is the only event in the queue, otherwise we loop forever
-          }
+          TU_ASSERT(osal_queue_send(_usbh_daq, &event, in_isr), );
         }
+  #endif
         break;
 
       case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        TU_LOG_USBH("[%u:%u:%u] USBH Device Removed\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
         process_remove_event(&event);
         break;
 
@@ -703,10 +788,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
         break;
     }
 
-#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
-    // return if there is no more events, for application to run other background
-    if (osal_queue_empty(_usbh_q)) return;
-#endif
+    // allow to exit tuh_task() if there is no event in the next run
+    timeout_ms = 0;
   }
 }
 
@@ -764,10 +847,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
 
     while (result == XFER_RESULT_INVALID) {
       // Note: this can be called within an callback ie. part of tuh_task()
-      // therefore event with RTOS tuh_task() still need to be invoked
-      if (tuh_task_event_ready()) {
-        tuh_task();
-      }
+      // therefore even with RTOS tuh_task_ext() still need to be invoked
+      tuh_task_ext(0, false);
       // TODO probably some timeout to prevent hanged
     }
 
@@ -1064,7 +1145,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) {
 }
 
 bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) {
-  // HACK: some device incorrectly always report 512 bulk regardless of link speed, overwrite descriptor to force 64
+  // HACK: some device incorrectly always reports 512 bulk regardless of link speed, overwrite descriptor to force 64
   if (desc_ep->bmAttributes.xfer == TUSB_XFER_BULK && tu_edpt_packet_size(desc_ep) > 64 &&
       tuh_speed_get(dev_addr) == TUSB_SPEED_FULL) {
     TU_LOG1("  WARN: EP max packet size is 512 in fullspeed, force to 64\r\n");
@@ -1189,24 +1270,24 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
                                             tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   usbh_device_t const* dev = get_device(daddr);
-  TU_VERIFY(dev && dev->iManufacturer);
-  return tuh_descriptor_get_string(daddr, dev->iManufacturer, language_id, buffer, len, complete_cb, user_data);
+  TU_VERIFY(dev && dev->desc_device.iManufacturer);
+  return tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get product string descriptor
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                        tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
-  TU_VERIFY(dev && dev->iProduct);
-  return tuh_descriptor_get_string(daddr, dev->iProduct, language_id, buffer, len, complete_cb, user_data);
+  TU_VERIFY(dev && dev->desc_device.iProduct);
+  return tuh_descriptor_get_string(daddr, dev->desc_device.iProduct, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get serial string descriptor
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
-  TU_VERIFY(dev && dev->iSerialNumber);
-  return tuh_descriptor_get_string(daddr, dev->iSerialNumber, language_id, buffer, len, complete_cb, user_data);
+  TU_VERIFY(dev && dev->desc_device.iSerialNumber);
+  return tuh_descriptor_get_string(daddr, dev->desc_device.iSerialNumber, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get HID report descriptor
@@ -1417,10 +1498,10 @@ enum {                                      // USB 2.0 specs 7.1.7 for timing
 enum {
   ENUM_IDLE,
   ENUM_HUB_RERSET,
-  ENUM_HUB_GET_STATUS_AFTER_RESET,
+  ENUM_HUB_RESET_COMPLETE,
   ENUM_HUB_CLEAR_RESET,
+  ENUM_HUB_CLEAR_RESET_RETRY, // 2nd attempt waiting for hub reset
   ENUM_HUB_CLEAR_RESET_COMPLETE,
-
   ENUM_ADDR0_DEVICE_DESC,
   ENUM_SET_ADDR,
   ENUM_GET_DEVICE_DESC,
@@ -1439,138 +1520,175 @@ enum {
 };
 
 static uint8_t enum_get_new_address(bool is_hub);
-static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
-static void enum_full_complete(bool success);
-static void process_enumeration(tuh_xfer_t* xfer);
+static bool    enum_parse_configuration_desc(uint8_t dev_addr, const tusb_desc_configuration_t *desc_cfg);
+static void    enum_full_complete(bool success);
+static void    process_enumeration(tuh_xfer_t *xfer);
 
-// start a new enumeration process
-static bool enum_new_device(hcd_event_t* event) {
-  tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus;
-  dev0_bus->rhport = event->rhport;
-  dev0_bus->hub_addr = event->connection.hub_addr;
-  dev0_bus->hub_port = event->connection.hub_port;
+enum {
+  ENUM_AFTER_DEBOUNCING_DELAY,
+  ENUM_AFTER_RESET_ROOT_DELAY,
+  ENUM_AFTER_RESET_ROOT_POST_DELAY,
+  ENUM_AFTER_RESET_HUB_DELAY,
+  ENUM_AFTER_RESET_HUB_DELAY_RETRY,
+  ENUM_AFTER_RESET_RECOVERY_DELAY,
+  ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY,
+};
 
-  // wait until device connection is stable TODO non blocking
-  tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS);
+// process async delay in enumeration
+static void enum_delay_async(uintptr_t state) {
+  tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus;
+  switch (state) {
+    case ENUM_AFTER_DEBOUNCING_DELAY:
+  #if CFG_TUH_HUB
+      if (dev0_bus->hub_addr != 0) {
+        // connected via hub
+        TU_VERIFY(dev0_bus->hub_port != 0, );
+        TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration,
+                                      ENUM_HUB_RERSET), );
+      } else
+  #endif
+      {
+        // connected directly to roothub
+        _usbh_data.attach_debouncing_bm &= (uint8_t)~TU_BIT(dev0_bus->rhport); // clear roothub debouncing delay
+        if (!hcd_port_connect_status(dev0_bus->rhport)) {
+          TU_LOG_USBH("Device unplugged while debouncing\r\n");
+          enum_full_complete(false);
+          return;
+        }
+        hcd_port_reset(dev0_bus->rhport); // reset port
+        usbh_defer_func_ms_async(ENUM_RESET_ROOT_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_ROOT_DELAY);
+      }
+      break;
+
+    case ENUM_AFTER_RESET_ROOT_DELAY:
+      hcd_port_reset_end(dev0_bus->rhport);
+      usbh_defer_func_ms_async(ENUM_RESET_ROOT_POST_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_ROOT_POST_DELAY);
+      break;
+
+    case ENUM_AFTER_RESET_ROOT_POST_DELAY:
+      if (!hcd_port_connect_status(dev0_bus->rhport)) {
+        // device unplugged while delaying
+        enum_full_complete(false);
+        return;
+      }
 
-  if (dev0_bus->hub_addr == 0) {
-    // connected directly to roothub
-    // USB bus not active and frame number is not available yet.
-    // need to depend on tusb_time_millis_api() TODO non blocking
+      dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport);
+      TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]);
 
-    _usbh_data.attach_debouncing_bm &= (uint8_t) ~TU_BIT(dev0_bus->rhport); // clear roothub debouncing delay
+      // fake transfer to kick-off the enumeration process
+      tuh_xfer_t xfer;
+      xfer.daddr     = 0;
+      xfer.result    = XFER_RESULT_SUCCESS;
+      xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
+      process_enumeration(&xfer);
+      break;
 
-    if (!hcd_port_connect_status(dev0_bus->rhport)) {
-      TU_LOG_USBH("Device unplugged while debouncing\r\n");
-      enum_full_complete(false);
-      return true;
-    }
+  #if CFG_TUH_HUB
+    case ENUM_AFTER_RESET_HUB_DELAY:
+    case ENUM_AFTER_RESET_HUB_DELAY_RETRY:
+      // get status after reset complete to check for reset change
+      TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration,
+                                    state == ENUM_AFTER_RESET_HUB_DELAY ? ENUM_HUB_CLEAR_RESET
+                                                                        : ENUM_HUB_CLEAR_RESET_RETRY), );
+      break;
+  #endif
 
-    // reset device
-    hcd_port_reset(dev0_bus->rhport);
-    tusb_time_delay_ms_api(ENUM_RESET_ROOT_DELAY_MS);
-    hcd_port_reset_end(dev0_bus->rhport);
-    tusb_time_delay_ms_api(ENUM_RESET_ROOT_POST_DELAY_MS);
+    case ENUM_AFTER_RESET_RECOVERY_DELAY:
+      // TODO probably doesn't need to open/close each enumeration
+      if (!usbh_edpt_control_open(0, 8)) {
+        TU_LOG_USBH("Failed to open dev0's control endpoint\r\n");
+        enum_full_complete(false); // Stop enumeration gracefully
+        return;
+      }
+      // Get first 8 bytes of device descriptor for control endpoint size
+      TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(0, _usbh_epbuf.ctrl, 8, process_enumeration, ENUM_SET_ADDR), );
+      break;
 
-    if (!hcd_port_connect_status(dev0_bus->rhport)) {
-      // device unplugged while delaying
-      enum_full_complete(false);
-      return true;
+    case ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY: {
+      const uint8_t  new_addr = _usbh_data.enumerating_daddr;
+      usbh_device_t *new_dev  = get_device(new_addr);
+      TU_ASSERT(new_dev, );
+      if (!usbh_edpt_control_open(new_addr, new_dev->desc_device.bMaxPacketSize0)) {
+        TU_LOG_USBH("Failed to open new device's control endpoint\r\n");
+        clear_device(new_dev);
+        enum_full_complete(false);
+        return;
+      }
+      TU_LOG_USBH("Get Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), process_enumeration,
+                                          ENUM_GET_STRING_LANGUAGE_ID_LEN), );
+      break;
     }
 
-    dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport);
-    TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]);
-
-    // fake transfer to kick-off the enumeration process
-    tuh_xfer_t xfer;
-    xfer.daddr = 0;
-    xfer.result = XFER_RESULT_SUCCESS;
-    xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
-    process_enumeration(&xfer);
-  }
-  #if CFG_TUH_HUB
-  else {
-    // connected via hub
-    TU_VERIFY(dev0_bus->hub_port != 0);
-    TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL,
-                                  process_enumeration, ENUM_HUB_RERSET));
+    default:
+      break;
   }
-  #endif // hub
+}
 
-  return true;
+// start a new enumeration process
+static void enum_new_device(hcd_event_t *event) {
+  tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus;
+  dev0_bus->rhport         = event->rhport;
+  dev0_bus->hub_addr       = event->connection.hub_addr;
+  dev0_bus->hub_port       = event->connection.hub_port;
+  usbh_defer_func_ms_async(ENUM_DEBOUNCING_DELAY_MS, enum_delay_async, ENUM_AFTER_DEBOUNCING_DELAY);
 }
 
 // process device enumeration
-static void process_enumeration(tuh_xfer_t* xfer) {
-  // Retry a few times while enumerating since device can be unstable when starting up
-  static uint8_t failed_count = 0;
+static void process_enumeration(tuh_xfer_t *xfer) {
   if (XFER_RESULT_FAILED == xfer->result) {
-    enum {
-      ATTEMPT_COUNT_MAX = 3,
-      ATTEMPT_DELAY_MS = 100
-    };
-
-    // retry if not reaching max attempt
-    failed_count++;
-    bool retry = (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) && (failed_count < ATTEMPT_COUNT_MAX);
-    if (retry) {
-      tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit
-      TU_LOG_USBH("Enumeration attempt %u/%u\r\n", failed_count+1, ATTEMPT_COUNT_MAX);
-      retry = tuh_control_xfer(xfer);
-    }
-
-    if (!retry) {
-      enum_full_complete(false); // complete as failed
-    }
+    enum_full_complete(false); // failed to enum
     return;
   }
-  failed_count = 0;
 
-  uint8_t const daddr = xfer->daddr;
-  uintptr_t const state = xfer->user_data;
-  usbh_device_t* dev = get_device(daddr);
-  tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus;
+  const uint8_t   daddr    = xfer->daddr;
+  const uintptr_t state    = xfer->user_data;
+  usbh_device_t  *dev      = get_device(daddr);
+  tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus;
   if (daddr > 0) {
     TU_ASSERT(dev != NULL,);
   }
   uint16_t langid = 0x0409; // default is English
+  bool is_enum_failed = false;
 
   switch (state) {
-    #if CFG_TUH_HUB
+  #if CFG_TUH_HUB
     case ENUM_HUB_RERSET: {
       hub_port_status_response_t port_status;
       hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status);
 
       if (0 == port_status.status.connection) {
         TU_LOG_USBH("Device unplugged from hub while debouncing\r\n");
-        enum_full_complete(false);
-        return;
+        is_enum_failed = true;
+      } else {
+        TU_ASSERT(hub_port_reset(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration,
+                                 ENUM_HUB_RESET_COMPLETE), );
       }
-
-      TU_ASSERT(hub_port_reset(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_GET_STATUS_AFTER_RESET),);
       break;
     }
 
-    case ENUM_HUB_GET_STATUS_AFTER_RESET: {
-      tusb_time_delay_ms_api(ENUM_RESET_HUB_DELAY_MS); // wait for reset to take effect
-
-      // get status to check for reset change
-      TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET),);
+    case ENUM_HUB_RESET_COMPLETE:
+      // wait for reset to take effect
+      usbh_defer_func_ms_async(ENUM_RESET_HUB_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_HUB_DELAY);
       break;
-    }
 
-    case ENUM_HUB_CLEAR_RESET: {
+    case ENUM_HUB_CLEAR_RESET:
+    case ENUM_HUB_CLEAR_RESET_RETRY: {
       hub_port_status_response_t port_status;
       hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status);
 
       if (1 == port_status.change.reset) {
         // Acknowledge Port Reset Change
-        TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),);
+        TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration,
+                                              ENUM_HUB_CLEAR_RESET_COMPLETE), );
+      } else if (state == ENUM_HUB_CLEAR_RESET) {
+        // retry one more time if reset change not set yet
+        usbh_defer_func_ms_async(ENUM_RESET_HUB_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_HUB_DELAY_RETRY);
       } else {
-        // maybe retry if reset change not set but we need timeout to prevent infinite loop
-        // TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),);
+        // retry but still not set --> failed
+        is_enum_failed = true;
       }
-
       break;
     }
 
@@ -1580,70 +1698,50 @@ static void process_enumeration(tuh_xfer_t* xfer) {
 
       if (0 == port_status.status.connection) {
         TU_LOG_USBH("Device unplugged from hub (not addressed yet)\r\n");
-        enum_full_complete(false);
-        return;
+        is_enum_failed = true;
+        break;
       }
 
-      dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
-                        (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
-
+      dev0_bus->speed = (port_status.status.high_speed)  ? TUSB_SPEED_HIGH
+                        : (port_status.status.low_speed) ? TUSB_SPEED_LOW
+                                                         : TUSB_SPEED_FULL;
       TU_ATTR_FALLTHROUGH;
     }
-    #endif
-
-    case ENUM_ADDR0_DEVICE_DESC: {
-      tusb_time_delay_ms_api(ENUM_RESET_RECOVERY_DELAY_MS); // reset recovery
-
-      // TODO probably doesn't need to open/close each enumeration
-      uint8_t const addr0 = 0;
-      if (!usbh_edpt_control_open(addr0, 8)) {
-        // Stop enumeration gracefully
-        enum_full_complete(false);
-        TU_ASSERT(false,);
-      }
+  #endif
 
-      // Get first 8 bytes of device descriptor for control endpoint size
-      TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8,
-                                          process_enumeration, ENUM_SET_ADDR),);
+    case ENUM_ADDR0_DEVICE_DESC:
+      usbh_defer_func_ms_async(ENUM_RESET_RECOVERY_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_RECOVERY_DELAY);
       break;
-    }
 
     case ENUM_SET_ADDR: {
       const tusb_desc_device_t *desc_device = (const tusb_desc_device_t *) _usbh_epbuf.ctrl;
+      if (!(desc_device->bDescriptorType == TUSB_DESC_DEVICE && desc_device->bMaxPacketSize0 >= 8)) {
+        TU_LOG_USBH("Invalid Device descriptor\r\n");
+        is_enum_failed = true;
+        break;
+      }
+
       const uint8_t new_addr = enum_get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
       TU_ASSERT(new_addr != 0,);
 
       usbh_device_t* new_dev = get_device(new_addr);
       new_dev->bus_info = *dev0_bus;
       new_dev->connected = 1;
-      new_dev->bMaxPacketSize0 = desc_device->bMaxPacketSize0;
+      new_dev->desc_device.bMaxPacketSize0 = desc_device->bMaxPacketSize0;
 
-      TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC),);
+      TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC), );
       break;
     }
 
     case ENUM_GET_DEVICE_DESC: {
-      tusb_time_delay_ms_api(ENUM_SET_ADDRESS_RECOVERY_DELAY_MS); // set address recovery
-
-      const uint8_t new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
-      usbh_device_t* new_dev = get_device(new_addr);
-      TU_ASSERT(new_dev,);
-      new_dev->addressed = 1;
+      const uint8_t  new_addr = (uint8_t)tu_le16toh(xfer->setup->wValue);
+      usbh_device_t *new_dev  = get_device(new_addr);
+      TU_ASSERT(new_dev, );
+      new_dev->addressed           = 1;
       _usbh_data.enumerating_daddr = new_addr;
 
       usbh_device_close(dev0_bus->rhport, 0); // close dev0
-
-      if (!usbh_edpt_control_open(new_addr, new_dev->bMaxPacketSize0)) { // open new control endpoint
-        // Stop enumeration gracefully
-        clear_device(new_dev);
-        enum_full_complete(false);
-        TU_ASSERT(false,);
-      }
-
-      TU_LOG_USBH("Get Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t),
-                                          process_enumeration, ENUM_GET_STRING_LANGUAGE_ID_LEN),);
+      usbh_defer_func_ms_async(ENUM_SET_ADDRESS_RECOVERY_DELAY_MS, enum_delay_async, ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY);
       break;
     }
 
@@ -1653,18 +1751,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       // save the received device descriptor
       tusb_desc_device_t const *desc_device = (tusb_desc_device_t const *) _usbh_epbuf.ctrl;
 
-      dev->bcdUSB             = desc_device->bcdUSB;
-      dev->bDeviceClass       = desc_device->bDeviceClass;
-      dev->bDeviceSubClass    = desc_device->bDeviceSubClass;
-      dev->bDeviceProtocol    = desc_device->bDeviceProtocol;
-      dev->bMaxPacketSize0    = desc_device->bMaxPacketSize0;
-      dev->idVendor           = desc_device->idVendor;
-      dev->idProduct          = desc_device->idProduct;
-      dev->bcdDevice          = desc_device->bcdDevice;
-      dev->iManufacturer      = desc_device->iManufacturer;
-      dev->iProduct           = desc_device->iProduct;
-      dev->iSerialNumber      = desc_device->iSerialNumber;
-      dev->bNumConfigurations = desc_device->bNumConfigurations;
+      memcpy(&dev->desc_device, (const uint8_t*) desc_device + offsetof(tusb_desc_device_t, bcdUSB), sizeof(desc_device_noheader_t));
 
       tuh_enum_descriptor_device_cb(daddr, desc_device); // callback
       tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, 2,
@@ -1684,8 +1771,8 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       if (desc_langid->bLength >= 4) {
         langid = tu_le16toh(desc_langid->utf16le[0]); // previous request is langid
       }
-      if (dev->iManufacturer != 0) {
-        tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, 2,
+      if (dev->desc_device.iManufacturer != 0) {
+        tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, langid, _usbh_epbuf.ctrl, 2,
                                   process_enumeration, ENUM_GET_STRING_MANUFACTURER);
         break;
       }
@@ -1693,10 +1780,10 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     case ENUM_GET_STRING_MANUFACTURER: {
-      if (dev->iManufacturer != 0)  {
+      if (dev->desc_device.iManufacturer != 0)  {
         langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request
         const uint8_t str_len = xfer->buffer[0];
-        tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, str_len,
+        tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, langid, _usbh_epbuf.ctrl, str_len,
                                   process_enumeration, ENUM_GET_STRING_PRODUCT_LEN);
         break;
       }
@@ -1704,22 +1791,22 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     case ENUM_GET_STRING_PRODUCT_LEN: {
-      if (dev->iProduct != 0) {
+      if (dev->desc_device.iProduct != 0) {
         if (state == ENUM_GET_STRING_PRODUCT_LEN) {
           langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through
         }
         tuh_descriptor_get_string(
-            daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_PRODUCT);
+            daddr, dev->desc_device.iProduct, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_PRODUCT);
         break;
       }
       TU_ATTR_FALLTHROUGH;
     }
 
     case ENUM_GET_STRING_PRODUCT: {
-      if (dev->iProduct != 0) {
+      if (dev->desc_device.iProduct != 0) {
         langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request
         const uint8_t str_len = xfer->buffer[0];
-        tuh_descriptor_get_string(daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, str_len,
+        tuh_descriptor_get_string(daddr, dev->desc_device.iProduct, langid, _usbh_epbuf.ctrl, str_len,
                             process_enumeration, ENUM_GET_STRING_SERIAL_LEN);
         break;
       }
@@ -1727,22 +1814,22 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     case ENUM_GET_STRING_SERIAL_LEN: {
-      if (dev->iSerialNumber != 0) {
+      if (dev->desc_device.iSerialNumber != 0) {
         if (state == ENUM_GET_STRING_SERIAL_LEN) {
           langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through
         }
         tuh_descriptor_get_string(
-            daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_SERIAL);
+            daddr, dev->desc_device.iSerialNumber, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_SERIAL);
         break;
       }
       TU_ATTR_FALLTHROUGH;
     }
 
     case ENUM_GET_STRING_SERIAL: {
-      if (dev->iSerialNumber != 0) {
+      if (dev->desc_device.iSerialNumber != 0) {
         langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request
         const uint8_t str_len = xfer->buffer[0];
-        tuh_descriptor_get_string(daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, str_len,
+        tuh_descriptor_get_string(daddr, dev->desc_device.iSerialNumber, langid, _usbh_epbuf.ctrl, str_len,
                                   process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC);
         break;
       }
@@ -1781,7 +1868,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
         TU_ASSERT(tuh_configuration_set(daddr, config_idx+1u, process_enumeration, ENUM_CONFIG_DRIVER),);
       } else {
         config_idx++;
-        TU_ASSERT(config_idx < dev->bNumConfigurations,);
+        TU_ASSERT(config_idx < dev->desc_device.bNumConfigurations,);
         TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx);
         TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
                                                    process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
@@ -1793,11 +1880,12 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       TU_LOG_USBH("Device configured\r\n");
       dev->configured = 1;
 
-    #if CFG_TUH_HUB
+  #if CFG_TUH_HUB
+      // get next hub status now since device can be unplugged before set_configure() is complete
       if (_usbh_data.dev0_bus.hub_addr != 0) {
-        hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); // get next hub status
+        hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr);
       }
-    #endif
+  #endif
 
       // Parse configuration & set up drivers
       // driver_open() must not make any usb transfer
@@ -1812,9 +1900,13 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     default:
-      enum_full_complete(false); // stop enumeration if unknown state
+      is_enum_failed = true;
       break;
   }
+
+  if (is_enum_failed) {
+    enum_full_complete(false);
+  }
 }
 
 static uint8_t enum_get_new_address(bool is_hub) {
@@ -1835,6 +1927,12 @@ static uint8_t enum_get_new_address(bool is_hub) {
     }
   }
 
+#if CFG_TUH_HUB
+  if ( is_hub ) {
+    TU_LOG1("All addresses are occupied, try to increase CFG_TUH_HUB value.\r\n");
+  }
+#endif // CFG_TUH_HUB
+
   return 0; // invalid address
 }
 
@@ -1846,10 +1944,10 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat
 
   TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len);
 
-  // parse each interfaces
+  // parse all interfaces
   while (tu_desc_in_bounds(p_desc, desc_end)) {
     if (0 == tu_desc_len(p_desc)) {
-      // A zero length descriptor indicates that the device is off spec (e.g. wrong wTotalLength).
+      // A zero-length descriptor indicates that the device is off spec (e.g. wrong wTotalLength).
       // Parsed interfaces should still be usable
       TU_LOG_USBH("Encountered a zero-length descriptor after %" PRIu32 " bytes\r\n", (uint32_t)p_desc - (uint32_t)desc_cfg);
       break;
@@ -1865,7 +1963,7 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat
     // uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, (uint16_t)
     // (desc_end-p_desc)); TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
-    // Find driver for this interface
+    // Find a driver for this interface
     const uint16_t remaining_len = (uint16_t)(desc_end - p_desc);
     uint8_t        drv_id;
     for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
@@ -1913,7 +2011,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
     }
   }
 
-  // all interface are configured
+  // all interfaces are configured
   if (itf_num == CFG_TUH_INTERFACE_MAX) {
     enum_full_complete(true);
 
@@ -1928,16 +2026,17 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
 
 static void enum_full_complete(bool success) {
   (void)success;
-  // mark enumeration as complete
-  _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8;
+  TU_LOG_USBH("Enumeration complete: success = %u\r\n", success);
 
-#if CFG_TUH_HUB
+  _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; // mark enumeration as complete
+  _usbh_data.call_after.func = NULL;
+
+  #if CFG_TUH_HUB
   // Hub status is already requested in case of successful enumeration
-  if (_usbh_data.dev0_bus.hub_addr != 0 && !success) {
-    hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); // get next hub status
+  if (!success && _usbh_data.dev0_bus.hub_addr != 0) {
+    hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr);
   }
-#endif
-
+  #endif
 }
 
 #endif
diff --git a/src/host/usbh.h b/src/host/usbh.h
index d86efbcb2..143d36f8c 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -96,6 +96,7 @@ enum {
   TUH_CFGID_RPI_PIO_USB_CONFIGURATION = 100, // cfg_param: pio_usb_configuration_t
   TUH_CFGID_MAX3421 = 200,
   TUH_CFGID_FSDEV = 300,
+  TUH_CFGID_DWC2 = 400
 };
 
 typedef struct {
@@ -108,10 +109,15 @@ typedef struct {
   uint8_t max_nak; // max NAK per endpoint per frame to save CPU usage (0=unlimited)
 } tuh_configure_fsdev_t;
 
+typedef struct {
+  bool use_hs_phy; // Always use high-speed ULPI/UTMI phy even when working at full-speed
+} tuh_configure_dwc2_t;
+
 typedef union {
   // For TUH_CFGID_RPI_PIO_USB_CONFIGURATION use pio_usb_configuration_t
   tuh_configure_max3421_t max3421;
   tuh_configure_fsdev_t fsdev;
+  tuh_configure_dwc2_t dwc2;
 } tuh_configure_param_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 57428e3c5..adb6a8c44 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -68,8 +68,12 @@ uint8_t* usbh_get_enum_buf(void);
 
 void usbh_int_set(bool enabled);
 
+// Invoke this function later in tuh_task() by putting it into task queue
 void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
 
+// Schedules a function to be called after certain time asynchronously
+bool usbh_defer_func_ms_async(uint32_t ms, tusb_defer_func_t func, uintptr_t param);
+
 void usbh_spin_lock(bool in_isr);
 void usbh_spin_unlock(bool in_isr);
 
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 44521620f..4840463f3 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -65,6 +65,8 @@ typedef void (*osal_task_func_t)(void* param);
   #include "osal_rtx4.h"
 #elif CFG_TUSB_OS == OPT_OS_ZEPHYR
   #include "osal_zephyr.h"
+#elif CFG_TUSB_OS == OPT_OS_THREADX
+  #include "osal_threadx.h"
 #elif CFG_TUSB_OS == OPT_OS_CUSTOM
   #include "tusb_os_custom.h" // implemented by application
 #else
@@ -74,6 +76,8 @@ typedef void (*osal_task_func_t)(void* param);
 /*--------------------------------------------------------------------
   OSAL Porting API
   Should be implemented as static inline function in osal_port.h header
+   uint32_t osal_time_millis(void);
+
    void osal_spin_init(osal_spinlock_t *ctx);
    void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr)
    void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 9aeda4d01..db724179d 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -99,6 +99,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   vTaskDelay(pdMS_TO_TICKS(msec));
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return pdTICKS_TO_MS(xTaskGetTickCount());
+}
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
@@ -137,11 +141,12 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
   if (in_isr) {
-    if (TUP_MCU_MULTIPLE_CORE == 0) {
-      (void) ctx;
-      return; // single core MCU does not need to lock in ISR
-    }
+  #if TUP_MCU_MULTIPLE_CORE
     *ctx = taskENTER_CRITICAL_FROM_ISR();
+  #else
+    (void) ctx;
+    return; // single core MCU does not need to lock in ISR
+  #endif
   } else {
     taskENTER_CRITICAL();
   }
@@ -149,11 +154,12 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bo
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
   if (in_isr) {
-    if (TUP_MCU_MULTIPLE_CORE == 0) {
-      (void) ctx;
-      return; // single core MCU does not need to lock in ISR
-    }
+  #if TUP_MCU_MULTIPLE_CORE
     taskEXIT_CRITICAL_FROM_ISR(*ctx);
+  #else
+    (void) ctx;
+    return; // single core MCU does not need to lock in ISR
+  #endif
   } else {
     taskEXIT_CRITICAL();
   }
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index 6d51f8ec3..94124ca81 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -40,6 +40,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   os_time_delay( os_time_ms_to_ticks32(msec) );
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return os_time_ticks_to_ms32(os_time_get());
+}
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 6ab18ace8..7bf6029d6 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -31,6 +31,8 @@
 extern "C" {
 #endif
 
+// osal_time_millis() is not provided, tusb_time_millis_api() must be implemented by user application
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
@@ -184,7 +186,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   (void) msec; // not used, always behave as msec = 0
 
   qhdl->interrupt_set(false);
-  const bool success = tu_fifo_read_n(&qhdl->ff, data, qhdl->item_size);
+  const bool success = (tu_fifo_read_n(&qhdl->ff, data, qhdl->item_size) > 0);
   qhdl->interrupt_set(true);
 
   return success;
@@ -195,7 +197,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
     qhdl->interrupt_set(false);
   }
 
-  const bool success = tu_fifo_write_n(&qhdl->ff, data, qhdl->item_size);
+  const bool success = (tu_fifo_write_n(&qhdl->ff, data, qhdl->item_size) > 0);
 
   if (!in_isr) {
     qhdl->interrupt_set(true);
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 79b728e9a..6a0a21bb3 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -43,6 +43,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   sleep_ms(msec);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return to_ms_since_boot(get_absolute_time());
+}
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index a778f5425..f560281c5 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -42,6 +42,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   rt_thread_mdelay(msec);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return (uint32_t)((((uint64_t)rt_tick_get()) * 1000) / RT_TICK_PER_SECOND);
+}
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index 35860ddd5..e1930c96c 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -46,6 +46,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   os_dly_wait(lo);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return os_time_get();
+}
+
 TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) {
   if (msec == OSAL_TIMEOUT_WAIT_FOREVER) {
     return 0xFFFF;
diff --git a/src/osal/osal_threadx.h b/src/osal/osal_threadx.h
new file mode 100644
index 000000000..6bcf9c5ab
--- /dev/null
+++ b/src/osal/osal_threadx.h
@@ -0,0 +1,201 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_OSAL_THREADX_H_
+#define TUSB_OSAL_THREADX_H_
+
+// ThreadX Headers
+#include "tx_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) {
+  if ( msec == TX_WAIT_FOREVER ) {
+    return TX_WAIT_FOREVER;
+  }
+  if ( msec == 0 ) {
+    return 0;
+  }
+
+  uint32_t ticks = msec * TX_TIMER_TICKS_PER_SECOND  / 1000;
+
+  // TX_TIMER_TICKS_PER_SECOND is less than 1000 and 1 tick > 1 ms
+  // we still need to delay at least 1 tick
+  if ( ticks == 0 ) {
+    ticks = 1;
+  }
+
+  return ticks;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return (uint32_t)((uint64_t) tx_time_get() * 1000u / TX_TIMER_TICKS_PER_SECOND);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
+  tx_thread_sleep(_osal_ms2tick(msec));
+}
+
+//--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+//--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef struct {
+  void (* interrupt_set)(bool);
+} osal_spinlock_t;
+
+// For SMP, spinlock must be locked by hardware, cannot just use interrupt
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name = { .interrupt_set = _int_set }
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+ if (!in_isr) {
+   ctx->interrupt_set(false);
+ }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+ if (!in_isr) {
+   ctx->interrupt_set(true);
+ }
+}
+
+
+//--------------------------------------------------------------------+
+// Binary Semaphore API (act)
+//--------------------------------------------------------------------+
+// Note: semaphores are not used in tinyusb for now, and their API has not been tested
+
+typedef TX_SEMAPHORE osal_semaphore_def_t, * osal_semaphore_t;
+
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
+  tx_semaphore_create(semdef, TX_NULL, 0);
+  return semdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t sem_hdl) {
+  (void) sem_hdl;
+  return TX_SUCCESS == tx_semaphore_delete(sem_hdl);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  (void) in_isr;
+  return TX_SUCCESS == tx_semaphore_put(sem_hdl);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
+  return TX_SUCCESS == tx_semaphore_get(sem_hdl, _osal_ms2tick(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
+  (void) sem_hdl;
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API
+//--------------------------------------------------------------------+
+typedef TX_MUTEX osal_mutex_def_t, *osal_mutex_t;
+
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
+  if (TX_SUCCESS == tx_mutex_create(mdef, mdef->tx_mutex_name, TX_NO_INHERIT)) {
+  	return mdef;
+  } else {
+    return NULL;
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
+  return TX_SUCCESS == tx_mutex_get(mutex_hdl, _osal_ms2tick(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
+  return TX_SUCCESS == tx_mutex_put(mutex_hdl);
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+
+typedef TX_QUEUE osal_queue_def_t, * osal_queue_t;
+
+// _int_set is not used with an RTOS _usbd_qdef
+
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)    \
+static _type _name##_buf[_depth];                         \
+osal_queue_def_t _name = {                                \
+		.tx_queue_name         = (CHAR*)(uintptr_t)#_name,                  \
+		.tx_queue_message_size = (sizeof(_type) + 3) / 4, \
+		.tx_queue_capacity     = _depth,                  \
+		.tx_queue_start        = (ULONG *) _name##_buf }
+
+
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
+  return TX_SUCCESS ==
+           tx_queue_create(qdef, qdef->tx_queue_name, qdef->tx_queue_message_size, qdef->tx_queue_start, qdef->tx_queue_capacity * qdef->tx_queue_message_size * 4)
+		   ? qdef : 0;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
+  return 0 == tx_queue_receive(qhdl, data, _osal_ms2tick(msec));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+  return 0 == tx_queue_send(qhdl, (VOID *)(uintptr_t) data, in_isr ? TX_NO_WAIT : TX_WAIT_FOREVER);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
+  ULONG enqueued;
+  tx_queue_info_get(qhdl, 0, &enqueued, 0, 0, 0, 0);
+  return enqueued == 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h
index 91f225f79..900ac786c 100644
--- a/src/osal/osal_zephyr.h
+++ b/src/osal/osal_zephyr.h
@@ -35,6 +35,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   k_msleep(msec);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) {
+  return k_uptime_get_32();
+}
+
 //--------------------------------------------------------------------+
 // Spinlock API
 //--------------------------------------------------------------------+
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 178eec419..c22aea887 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -47,10 +47,10 @@ static const ci_hs_controller_t _ci_controller[] =
 
 #define CI_HS_REG(_port)        ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
 
-#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
-#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
+#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
 
-#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
-#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum)
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 2bba32ada..9ed75ffd9 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -285,6 +285,23 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
   return true;
 }
 
+bool dcd_deinit(uint8_t rhport) {
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+
+  // disable all interrupt
+  dcd_reg->USBINTR = 0;
+
+  // unattach from bus
+  dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
+
+  // flush all endpoints
+  while (dcd_reg->ENDPTPRIME) {}
+  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
+  while (dcd_reg->ENDPTFLUSH) {}
+
+  return true;
+}
+
 void dcd_int_enable(uint8_t rhport) {
   CI_DCD_INT_ENABLE(rhport);
 }
@@ -371,7 +388,7 @@ TU_ATTR_ALWAYS_INLINE static inline void ep_ctrl_mask(volatile uint32_t *epctrl,
                                                       uint32_t or_mask) {
   uint32_t value = *epctrl;
   if (and_mask != 0) {
-    value &= (dir == TUSB_DIR_OUT) ? and_mask : (and_mask << 16u);
+    value &= (dir == TUSB_DIR_OUT) ? (and_mask | 0xFFFF0000u) : ((and_mask << 16u) | 0x0000FFFFu);
   }
   if (or_mask != 0) {
     value |= (dir == TUSB_DIR_OUT) ? or_mask : (or_mask << 16u);
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 29ce0cd7f..c0d14fe57 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -93,21 +93,25 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
   hcd_reg->USBCMD |= USBCMD_RESET;
   while (hcd_reg->USBCMD & USBCMD_RESET) {}
 
-  // Set mode to device, must be set immediately after reset
+  // Set mode to host, must be set immediately after reset
   #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
   // LPC18XX/43XX need to set VBUS Power Select to HIGH
-  // RHPORT1 is fullspeed only (need external PHY for Highspeed)
   hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) {
-    hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
-  }
   #else
   hcd_reg->USBMODE = USBMODE_CM_HOST;
   #endif
 
+  #if !TUH_OPT_HIGH_SPEED
+  hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  #endif
+
   return ehci_init(rhport, (uint32_t)&hcd_reg->CAPLENGTH, (uint32_t)&hcd_reg->USBCMD);
 }
 
+bool hcd_deinit(uint8_t rhport) {
+  return ehci_deinit(rhport);
+}
+
 void hcd_int_enable(uint8_t rhport) {
   CI_HCD_INT_ENABLE(rhport);
 }
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 9b2cf98be..03c3b91fd 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -411,17 +411,22 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   return true;
 }
 
-#if 0
-static void ehci_stop(uint8_t rhport) {
+bool ehci_deinit(uint8_t rhport) {
   (void) rhport;
 
   ehci_registers_t* regs = ehci_data.regs;
+
+  // Disable all the interrupt
+  regs->inten  = 0;
+
+  // Disable schedules
   regs->command_bm.run_stop = 0;
 
   // USB Spec: controller has to stop within 16 uframe = 2 frames
   while( regs->status_bm.hc_halted == 0 ) {}
+
+  return true;
 }
-#endif
 
 //--------------------------------------------------------------------+
 // Endpoint API
diff --git a/src/portable/ehci/ehci_api.h b/src/portable/ehci/ehci_api.h
index 79fbe702a..e9018639f 100644
--- a/src/portable/ehci/ehci_api.h
+++ b/src/portable/ehci/ehci_api.h
@@ -38,6 +38,9 @@
 // Initialize EHCI driver
 bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg);
 
+// De-initialize EHCI driver
+bool ehci_deinit(uint8_t rhport);
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 3827be318..d329285e9 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -32,12 +32,6 @@
 #define MUSB_DEBUG 2
 #define MUSB_REGS(rhport)   ((musb_regs_t*) MUSB_BASES[rhport])
 
-#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
-/* GCC warns that an address may be unaligned, even though
- * the target CPU has the capability for unaligned memory access. */
-_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
-#endif
-
 #include "musb_type.h"
 #include "device/dcd.h"
 
@@ -73,7 +67,10 @@ typedef struct TU_ATTR_PACKED
 
 typedef struct
 {
-  tusb_control_request_t setup_packet;
+  union {
+    tusb_control_request_t setup_packet;
+    uint32_t setup_buffer[2];
+  };
   uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
   int8_t       status_out;
   pipe_state_t pipe0;
@@ -174,10 +171,8 @@ static void process_setup_packet(uint8_t rhport) {
   musb_regs_t* musb_regs = MUSB_REGS(rhport);
 
   // Read setup packet
-  uint32_t *p = (void*)&_dcd.setup_packet;
-  volatile uint32_t *fifo_ptr = &musb_regs->fifo[0];
-  p[0] = *fifo_ptr;
-  p[1] = *fifo_ptr;
+  _dcd.setup_buffer[0] = musb_regs->fifo[0];
+  _dcd.setup_buffer[1] = musb_regs->fifo[0];
 
   _dcd.pipe0.buf       = NULL;
   _dcd.pipe0.length    = 0;
@@ -194,14 +189,13 @@ static void process_setup_packet(uint8_t rhport) {
   }
 }
 
-static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr)
-{
+static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) {
   unsigned epnum = tu_edpt_number(ep_addr);
   unsigned epnum_minus1 = epnum - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
   const unsigned rem  = pipe->remaining;
 
-  if (!rem) {
+  if (rem == 0 && pipe->length > 0) {
     pipe->buf = NULL;
     return true;
   }
@@ -218,7 +212,7 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr)
       tu_hwfifo_write_from_fifo(fifo_ptr, (tu_fifo_t *)buf, len, NULL);
     } else {
       tu_hwfifo_write(fifo_ptr, buf, len, NULL);
-      pipe->buf       = buf + len;
+      pipe->buf       = (uint8_t*)buf + len;
     }
     pipe->remaining = rem - len;
   }
@@ -249,7 +243,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr)
       tu_hwfifo_read_to_fifo(fifo_ptr, (tu_fifo_t *)buf, len, NULL);
     } else {
       tu_hwfifo_read(fifo_ptr, buf, len, NULL);
-      pipe->buf       = buf + len;
+      pipe->buf       = (uint8_t*)buf + len;
     }
     pipe->remaining = rem - len;
   }
diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h
index d17e836ee..68e89d77d 100644
--- a/src/portable/mentor/musb/musb_ti.h
+++ b/src/portable/mentor/musb/musb_ti.h
@@ -35,7 +35,10 @@
   #include "TM4C123.h"
   #define FIFO0_WORD FIFO0
   #define FIFO1_WORD FIFO1
-//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
+#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
+  #include "TM4C129.h"
+  #define FIFO0_WORD FIFOA
+  #define FIFO1_WORD FIFOB
 #elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
   #include "msp.h"
 #else
diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h
index 4e448c0ed..b2f6492fa 100644
--- a/src/portable/mentor/musb/musb_type.h
+++ b/src/portable/mentor/musb/musb_type.h
@@ -147,7 +147,7 @@ typedef struct TU_ATTR_PACKED {
 
 TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct");
 
-typedef struct TU_ATTR_PACKED {
+typedef struct {
   //------------- Common -------------//
   __IO uint8_t  faddr;             // 0x00: FADDR
   union {
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index b0a053c01..6da1e9778 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -1,133 +1,117 @@
 /*
-* The MIT License (MIT)
-*
-* Copyright (c) 2018, hathach (tinyusb.org)
-* Copyright (c) 2021, HiFiPhile
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-* THE SOFTWARE.
-*
-* This file is part of the TinyUSB stack.
-*/
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright (c) 2021, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
 
 #include "tusb_option.h"
 
 #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
 
-#include "device/dcd.h"
-#include "sam.h"
-#include "common_usb_regs.h"
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#ifndef USE_SOF
-#  define USE_SOF         0
-#endif
-
-// Dual bank can improve performance, but need 2 times bigger packet buffer
-// As SAM7x has only 4KB packet buffer, use with caution !
-// Enable in FS mode as packets are smaller
-#ifndef USE_DUAL_BANK
-#  if TUD_OPT_HIGH_SPEED
-#    define USE_DUAL_BANK   0
-#  else
-#    define USE_DUAL_BANK   1
-#  endif
-#endif
+  #include "device/dcd.h"
+  #include "sam.h"
+  #include "samx7x_common.h"
+  //--------------------------------------------------------------------+
+  // MACRO TYPEDEF CONSTANT ENUM DECLARATION
+  //--------------------------------------------------------------------+
 
-#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])FIFO_RAM_ADDR)[(ep)])
+  // Dual bank can improve performance, but need 2 times bigger packet buffer
+  // As SAM7x has only 4KB packet buffer, use with caution !
+  // Enable in FS mode as packets are smaller
+  #ifndef USE_DUAL_BANK
+    #if TUD_OPT_HIGH_SPEED
+      #define USE_DUAL_BANK 0
+    #else
+      #define USE_DUAL_BANK 1
+    #endif
+  #endif
 
-// DMA Channel Transfer Descriptor
-typedef struct {
-  volatile uint32_t next_desc;
-  volatile uint32_t buff_addr;
-  volatile uint32_t chnl_ctrl;
-  uint32_t padding;
-} dma_desc_t;
+  #define EP_GET_FIFO_PTR(ep, scale)                                                            \
+    (((TU_XSTRCAT(TU_STRCAT(uint, scale), _t)(*)[0x8000 / ((scale) / 8)]) FIFO_RAM_ADDR)[(ep)])
 
 // Transfer control context
 typedef struct {
-  uint8_t * buffer;
-  uint16_t total_len;
-  uint16_t queued_len;
-  uint16_t max_packet_size;
-  uint8_t interval;
-  tu_fifo_t * fifo;
+  uint8_t   *buffer;
+  uint16_t   total_len;
+  uint16_t   queued_len;
+  uint16_t   max_packet_size;
+  uint8_t    interval;
+  tu_fifo_t *fifo;
 } xfer_ctl_t;
 
 static tusb_speed_t get_speed(void);
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
-
-// DMA descriptors shouldn't be placed in ITCM !
-CFG_TUD_MEM_SECTION static dma_desc_t dma_desc[6];
+static void         dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix);
 
 static xfer_ctl_t xfer_status[EP_MAX];
 
-static const tusb_desc_endpoint_t ep0_desc =
-{
+static const tusb_desc_endpoint_t ep0_desc = {
   .bEndpointAddress = 0x00,
   .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
 };
 
-TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size)
-{
-  if (SCB->CCR & SCB_CCR_DC_Msk)
-  {
-    SCB_CleanInvalidateDCache_by_Addr(addr, size);
-  }
-  else
-  {
-    __DSB();
-    __ISB();
-  }
+  #if CFG_TUD_MEM_DCACHE_ENABLE
+bool dcd_dcache_clean(const void *addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return samx7x_dcache_clean(addr, data_size);
 }
+
+bool dcd_dcache_invalidate(const void *addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return samx7x_dcache_invalidate(addr, data_size);
+}
+
+bool dcd_dcache_clean_invalidate(const void *addr, uint32_t data_size) {
+  TU_VERIFY(addr && data_size);
+  return samx7x_dcache_clean_invalidate(addr, data_size);
+}
+  #endif
 //------------------------------------------------------------------
 // Device API
 //------------------------------------------------------------------
 
 // Initialize controller to device mode
-bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
-  (void) rh_init;
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
+  (void)rh_init;
   dcd_connect(rhport);
   return true;
 }
 
 // Enable device interrupt
-void dcd_int_enable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
+void dcd_int_enable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_EnableIRQ((IRQn_Type)ID_USBHS);
 }
 
 // Disable device interrupt
-void dcd_int_disable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
+void dcd_int_disable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_DisableIRQ((IRQn_Type)ID_USBHS);
 }
 
 // Receive Set Address request, mcu port must also include status IN response
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  (void) dev_addr;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void)dev_addr;
   // DCD can only set address after status for this request is complete
   // do it at dcd_edpt0_status_complete()
 
@@ -136,30 +120,26 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 }
 
 // Wake up host
-void dcd_remote_wakeup (uint8_t rhport)
-{
-  (void) rhport;
+void dcd_remote_wakeup(uint8_t rhport) {
+  (void)rhport;
   USB_REG->DEVCTRL |= DEVCTRL_RMWKUP;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
+void dcd_connect(uint8_t rhport) {
+  (void)rhport;
   dcd_int_disable(rhport);
   // Enable the USB controller in device mode
   USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE;
-  while (!(USB_REG->SR & SR_CLKUSABLE));
-#if TUD_OPT_HIGH_SPEED
+  while (!(USB_REG->SR & SR_CLKUSABLE))
+    ;
+  #if TUD_OPT_HIGH_SPEED
   USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF;
-#else
+  #else
   USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER;
-#endif
+  #endif
   // Enable the End Of Reset, Suspend & Wakeup interrupts
   USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES);
-#if USE_SOF
-  USB_REG->DEVIER = DEVIER_SOFES;
-#endif
   // Clear the End Of Reset, SOF & Wakeup interrupts
   USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC);
   // Manually set the Suspend Interrupt
@@ -173,15 +153,15 @@ void dcd_connect(uint8_t rhport)
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
+void dcd_disconnect(uint8_t rhport) {
+  (void)rhport;
   dcd_int_disable(rhport);
   // Disable all endpoints
   USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos);
   // Unfreeze USB clock
   USB_REG->CTRL &= ~CTRL_FRZCLK;
-  while (!(USB_REG->SR & SR_CLKUSABLE));
+  while (!(USB_REG->SR & SR_CLKUSABLE))
+    ;
   // Clear all the pending interrupts
   USB_REG->DEVICR = DEVICR_Msk;
   // Disable all interrupts
@@ -189,127 +169,106 @@ void dcd_disconnect(uint8_t rhport)
   // Detach the device
   USB_REG->DEVCTRL |= DEVCTRL_DETACH;
   // Disable the device address
-  USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD);
+  USB_REG->DEVCTRL &= ~(DEVCTRL_ADDEN | DEVCTRL_UADD);
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
+void dcd_sof_enable(uint8_t rhport, bool en) {
+  (void)rhport;
+  if (en) {
+    USB_REG->DEVIER = DEVIER_SOFES;
+  } else {
+    USB_REG->DEVIDR = DEVIDR_SOFEC;
+  }
 }
 
-static tusb_speed_t get_speed(void)
-{
+static tusb_speed_t get_speed(void) {
   switch (USB_REG->SR & SR_SPEED) {
-  case SR_SPEED_FULL_SPEED:
-  default:
-    return TUSB_SPEED_FULL;
-  case SR_SPEED_HIGH_SPEED:
-    return TUSB_SPEED_HIGH;
-  case SR_SPEED_LOW_SPEED:
-    return TUSB_SPEED_LOW;
+    case SR_SPEED_FULL_SPEED:
+    default:
+      return TUSB_SPEED_FULL;
+    case SR_SPEED_HIGH_SPEED:
+      return TUSB_SPEED_HIGH;
+    case SR_SPEED_LOW_SPEED:
+      return TUSB_SPEED_LOW;
   }
 }
 
-static void dcd_ep_handler(uint8_t ep_ix)
-{
+static void dcd_ep_handler(uint8_t ep_ix) {
   uint32_t int_status = USB_REG->DEVEPTISR[ep_ix];
   int_status &= USB_REG->DEVEPTIMR[ep_ix];
 
-  uint16_t count = (USB_REG->DEVEPTISR[ep_ix] &
-                    DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos;
-  xfer_ctl_t *xfer = &xfer_status[ep_ix];
+  uint16_t    count = (USB_REG->DEVEPTISR[ep_ix] & DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos;
+  xfer_ctl_t *xfer  = &xfer_status[ep_ix];
 
-  if (ep_ix == 0U)
-  {
+  if (ep_ix == 0U) {
     static uint8_t ctrl_dir;
 
-    if (int_status & DEVEPTISR_CTRL_RXSTPI)
-    {
+    if (int_status & DEVEPTISR_CTRL_RXSTPI) {
       ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos;
       // Setup packet should always be 8 bytes. If not, ignore it, and try again.
-      if (count == 8)
-      {
-        uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
+      if (count == 8) {
+        uint8_t *ptr = EP_GET_FIFO_PTR(0, 8);
         dcd_event_setup_received(0, ptr, true);
       }
       // Ack and disable SETUP interrupt
       USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC;
       USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC;
     }
-    if (int_status & DEVEPTISR_RXOUTI)
-    {
-      uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
+    if (int_status & DEVEPTISR_RXOUTI) {
+      uint8_t *ptr = EP_GET_FIFO_PTR(0, 8);
 
-      if (count && xfer->total_len)
-      {
+      if (count && xfer->total_len) {
         uint16_t remain = xfer->total_len - xfer->queued_len;
-        if (count > remain)
-        {
+        if (count > remain) {
           count = remain;
         }
-        if (xfer->buffer)
-        {
+        if (xfer->buffer) {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-        } else
-        {
-          tu_fifo_write_n(xfer->fifo, ptr, count);
+        } else {
+          tu_hwfifo_read_to_fifo(ptr, xfer->fifo, count, NULL);
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
       // Acknowledge the interrupt
       USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC;
-      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-      {
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
         // RX COMPLETE
         dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
         USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC;
         // Re-enable SETUP interrupt
-        if (ctrl_dir == 1)
-        {
+        if (ctrl_dir == 1) {
           USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
         }
       }
     }
-    if (int_status & DEVEPTISR_TXINI)
-    {
+    if (int_status & DEVEPTISR_TXINI) {
       // Disable the interrupt
       USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC;
-      if ((xfer->total_len != xfer->queued_len))
-      {
+      if ((xfer->total_len != xfer->queued_len)) {
         // TX not complete
         dcd_transmit_packet(xfer, 0);
-      } else
-      {
+      } else {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
         // Re-enable SETUP interrupt
-        if (ctrl_dir == 0)
-        {
+        if (ctrl_dir == 0) {
           USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
         }
       }
     }
-  } else
-  {
-    if (int_status & DEVEPTISR_RXOUTI)
-    {
-      if (count && xfer->total_len)
-      {
+  } else {
+    if (int_status & DEVEPTISR_RXOUTI) {
+      if (count && xfer->total_len) {
         uint16_t remain = xfer->total_len - xfer->queued_len;
-        if (count > remain)
-        {
+        if (count > remain) {
           count = remain;
         }
-        uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
-        if (xfer->buffer)
-        {
+        uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8);
+        if (xfer->buffer) {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
         } else {
-          tu_fifo_write_n(xfer->fifo, ptr, count);
+          tu_hwfifo_read_to_fifo(ptr, xfer->fifo, count, NULL);
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
@@ -317,8 +276,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
       // Acknowledge the interrupt
       USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC;
-      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-      {
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
         // RX COMPLETE
         dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
@@ -326,16 +284,13 @@ static void dcd_ep_handler(uint8_t ep_ix)
         // Though the host could still send, we don't know.
       }
     }
-    if (int_status & DEVEPTISR_TXINI)
-    {
+    if (int_status & DEVEPTISR_TXINI) {
       // Acknowledge the interrupt
       USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC;
-      if ((xfer->total_len != xfer->queued_len))
-      {
+      if ((xfer->total_len != xfer->queued_len)) {
         // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
-      } else
-      {
+      } else {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
@@ -345,45 +300,40 @@ static void dcd_ep_handler(uint8_t ep_ix)
   }
 }
 
-static void dcd_dma_handler(uint8_t ep_ix)
-{
+static void dcd_dma_handler(uint8_t ep_ix) {
   uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS;
-  if (status & DEVDMASTATUS_CHANN_ENB)
-  {
+  if (status & DEVDMASTATUS_CHANN_ENB) {
     return; // Ignore EOT_STA interrupt
   }
   // Disable DMA interrupt
   USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1);
 
-  xfer_ctl_t *xfer = &xfer_status[ep_ix];
-  uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos);
-  if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
-  {
+  xfer_ctl_t *xfer  = &xfer_status[ep_ix];
+  uint16_t    count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos);
+  if (USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else
-  {
+  } else {
+    dcd_dcache_invalidate(xfer->buffer, count);
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
 }
 
-void dcd_int_handler(uint8_t rhport)
-{
-  (void) rhport;
+void dcd_int_handler(uint8_t rhport) {
+  (void)rhport;
   uint32_t int_status = USB_REG->DEVISR;
   int_status &= USB_REG->DEVIMR;
   // End of reset interrupt
-  if (int_status & DEVISR_EORST)
-  {
+  if (int_status & DEVISR_EORST) {
     // Unfreeze USB clock
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while(!(USB_REG->SR & SR_CLKUSABLE));
+    while (!(USB_REG->SR & SR_CLKUSABLE))
+      ;
     // Reset all endpoints
-    for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
-    {
+    for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) {
       USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix);
-      USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + ep_ix));
+      USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + ep_ix));
     }
-    dcd_edpt_open (0, &ep0_desc);
+    dcd_edpt_open(0, &ep0_desc);
     USB_REG->DEVICR = DEVICR_EORSTC;
     USB_REG->DEVICR = DEVICR_WAKEUPC;
     USB_REG->DEVICR = DEVICR_SUSPC;
@@ -392,10 +342,10 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_reset(rhport, get_speed(), true);
   }
   // End of Wakeup interrupt
-  if (int_status & DEVISR_WAKEUP)
-  {
+  if (int_status & DEVISR_WAKEUP) {
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while (!(USB_REG->SR & SR_CLKUSABLE));
+    while (!(USB_REG->SR & SR_CLKUSABLE))
+      ;
     USB_REG->DEVICR = DEVICR_WAKEUPC;
     USB_REG->DEVIDR = DEVIDR_WAKEUPEC;
     USB_REG->DEVIER = DEVIER_SUSPES;
@@ -403,11 +353,11 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
   // Suspend interrupt
-  if (int_status & DEVISR_SUSP)
-  {
+  if (int_status & DEVISR_SUSP) {
     // Unfreeze USB clock
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while (!(USB_REG->SR & SR_CLKUSABLE));
+    while (!(USB_REG->SR & SR_CLKUSABLE))
+      ;
     USB_REG->DEVICR = DEVICR_SUSPC;
     USB_REG->DEVIDR = DEVIDR_SUSPEC;
     USB_REG->DEVIER = DEVIER_WAKEUPES;
@@ -415,29 +365,21 @@ void dcd_int_handler(uint8_t rhport)
 
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
-#if USE_SOF
-  if(int_status & DEVISR_SOF)
-  {
+  if (int_status & DEVISR_SOF) {
     USB_REG->DEVICR = DEVICR_SOFC;
 
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
-#endif
   // Endpoints interrupt
-  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
-  {
-    if (int_status & (DEVISR_PEP_0 << ep_ix))
-    {
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
+    if (int_status & (DEVISR_PEP_0 << ep_ix)) {
       dcd_ep_handler(ep_ix);
     }
   }
   // Endpoints DMA interrupt
-  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
-  {
-    if (EP_DMA_SUPPORT(ep_ix))
-    {
-      if (int_status & (DEVISR_DMA_1 << (ep_ix - 1)))
-      {
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
+    if (EP_DMA_SUPPORT(ep_ix)) {
+      if (int_status & (DEVISR_DMA_1 << (ep_ix - 1))) {
         dcd_dma_handler(ep_ix);
       }
     }
@@ -449,35 +391,29 @@ void dcd_int_handler(uint8_t rhport)
 //--------------------------------------------------------------------+
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
-  (void) rhport;
+void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t *request) {
+  (void)rhport;
 
   if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-        request->bRequest == TUSB_REQ_SET_ADDRESS )
-  {
-    uint8_t const dev_addr = (uint8_t) request->wValue;
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) {
+    const uint8_t dev_addr = (uint8_t)request->wValue;
 
     USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN;
   }
 }
 
 // Configure endpoint's registers according to descriptor
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
-  uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
-  uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc);
-  tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
-  uint8_t fifoSize = 0;                       // FIFO size
-  uint16_t defaultEndpointSize = 8;           // Default size of Endpoint
+bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
+  (void)rhport;
+  const uint8_t          epnum               = tu_edpt_number(ep_desc->bEndpointAddress);
+  const uint8_t          dir                 = tu_edpt_dir(ep_desc->bEndpointAddress);
+  const uint16_t         epMaxPktSize        = tu_edpt_packet_size(ep_desc);
+  const tusb_xfer_type_t eptype              = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
+  uint8_t                fifoSize            = 0; // FIFO size
+  uint16_t               defaultEndpointSize = 8; // Default size of Endpoint
   // Find upper 2 power number of epMaxPktSize
-  if (epMaxPktSize)
-  {
-    while (defaultEndpointSize < epMaxPktSize)
-    {
+  if (epMaxPktSize) {
+    while (defaultEndpointSize < epMaxPktSize) {
       fifoSize++;
       defaultEndpointSize <<= 1;
     }
@@ -485,121 +421,94 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   xfer_status[epnum].max_packet_size = epMaxPktSize;
 
   USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum);
-  USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + epnum));
+  USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + epnum));
 
-  if (epnum == 0)
-  {
+  if (epnum == 0) {
     // Enable the control endpoint - Endpoint 0
     USB_REG->DEVEPT |= DEVEPT_EPEN0;
     // Configure the Endpoint 0 configuration register
-    USB_REG->DEVEPTCFG[0] =
-      (
-       (fifoSize << DEVEPTCFG_EPSIZE_Pos)            |
-       (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos)   |
-       (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
-       DEVEPTCFG_ALLOC
-       );
+    USB_REG->DEVEPTCFG[0] = ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) |
+                             (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | DEVEPTCFG_ALLOC);
     USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS;
     USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC;
-    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK))
-    {
+    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK)) {
       // Endpoint configuration is successful
       USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
       // Enable Endpoint 0 Interrupts
       USB_REG->DEVIER = DEVIER_PEP_0;
       return true;
-    } else
-    {
+    } else {
       // Endpoint configuration is not successful
       return false;
     }
-  } else
-  {
+  } else {
     // Enable the endpoint
     USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
     // and enable the interrupt. CLear the data toggle.
     // AUTOSW is needed for DMA ack !
     USB_REG->DEVEPTCFG[epnum] =
-      (
-       (fifoSize << DEVEPTCFG_EPSIZE_Pos)            |
-       (eptype  << DEVEPTCFG_EPTYPE_Pos)             |
-       (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
-       DEVEPTCFG_AUTOSW |
-       ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos)
-       );
-    if (eptype == TUSB_XFER_ISOCHRONOUS)
-    {
+      ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | (eptype << DEVEPTCFG_EPTYPE_Pos) |
+       (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | DEVEPTCFG_AUTOSW | ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos));
+    if (eptype == TUSB_XFER_ISOCHRONOUS) {
       USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS;
     }
-#if USE_DUAL_BANK
-    if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
-    {
+  #if USE_DUAL_BANK
+    if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) {
       USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK;
     }
-#endif
+  #endif
     USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC;
     USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS;
     USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
-    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK))
-    {
+    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK)) {
       USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
       return true;
-    } else
-    {
+    } else {
       // Endpoint configuration is not successful
       return false;
     }
   }
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
+void dcd_edpt_close_all(uint8_t rhport) {
+  (void)rhport;
   // TODO implement dcd_edpt_close_all()
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
-  (void) rhport;
-  (void) ep_addr;
-  (void) largest_packet_size;
+  (void)rhport;
+  (void)ep_addr;
+  (void)largest_packet_size;
   return false;
 }
 
-bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) {
-  (void) rhport;
-  (void) desc_ep;
+bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *desc_ep) {
+  (void)rhport;
+  (void)desc_ep;
   return false;
 }
 
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
-{
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix) {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
-  if (len)
-  {
-    if (len > xfer->max_packet_size)
-    {
+  if (len) {
+    if (len > xfer->max_packet_size) {
       len = xfer->max_packet_size;
     }
-    uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
-    if(xfer->buffer)
-    {
+    uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8);
+    if (xfer->buffer) {
       memcpy(ptr, xfer->buffer + xfer->queued_len, len);
-    }
-    else
-    {
-      tu_fifo_read_n(xfer->fifo, ptr, len);
+    } else {
+      tu_hwfifo_write_from_fifo(ptr, xfer->fifo, len, NULL);
     }
     __DSB();
     __ISB();
     xfer->queued_len = (uint16_t)(xfer->queued_len + len);
   }
-  if (ep_ix == 0U)
-  {
+  if (ep_ix == 0U) {
     // Control endpoint: clear the interrupt flag to send the data
     USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
-  } else
-  {
+  } else {
     // Other endpoint types: clear the FIFO control flag to send the data
     USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
   }
@@ -607,59 +516,36 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool is_isr)
-{
-  (void) is_isr;
-  (void) rhport;
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool is_isr) {
+  (void)is_isr;
+  (void)rhport;
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  const uint8_t dir   = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = &xfer_status[epnum];
+  xfer_ctl_t *xfer = &xfer_status[epnum];
 
-  xfer->buffer = buffer;
-  xfer->total_len = total_bytes;
+  xfer->buffer     = buffer;
+  xfer->total_len  = total_bytes;
   xfer->queued_len = 0;
-  xfer->fifo = NULL;
+  xfer->fifo       = NULL;
 
-  if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
-  {
-    // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
-    // address to 32-byte boundaries.
-    CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
+  if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) {
     uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos;
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
     } else {
       udd_dma_ctrl |= DEVDMACONTROL_END_B_EN;
+      dcd_dcache_clean(xfer->buffer, total_bytes);
     }
     USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer;
     udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB;
-    // Disable IRQs to have a short sequence
-    // between read of EOT_STA and DMA enable
-    uint32_t irq_state = __get_PRIMASK();
-    __disable_irq();
-    if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
-    {
-      USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl;
-      USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
-      __set_PRIMASK(irq_state);
-      return true;
-    }
-    __set_PRIMASK(irq_state);
-
-    // Here a ZLP has been received
-    // and the DMA transfer must be not started.
-    // It is the end of transfer
-    return false;
-  } else
-  {
-    if (dir == TUSB_DIR_OUT)
-    {
+    USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl;
+    USB_REG->DEVIER                          = DEVIER_DMA_1 << (epnum - 1);
+  } else {
+    if (dir == TUSB_DIR_OUT) {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else
-    {
-      dcd_transmit_packet(xfer,epnum);
+    } else {
+      dcd_transmit_packet(xfer, epnum);
     }
   }
   return true;
@@ -669,112 +555,43 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes, bool is_isr)
-{
-  (void) is_isr;
-  (void) rhport;
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes, bool is_isr) {
+  (void)is_isr;
+  (void)rhport;
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  const uint8_t dir   = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = &xfer_status[epnum];
-  if(epnum == 0x80)
-    xfer = &xfer_status[EP_MAX];
+  xfer_ctl_t *xfer = &xfer_status[epnum];
 
-  xfer->buffer = NULL;
-  xfer->total_len = total_bytes;
+  xfer->buffer     = NULL;
+  xfer->total_len  = total_bytes;
   xfer->queued_len = 0;
-  xfer->fifo = ff;
-
-  if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
-  {
-    tu_fifo_buffer_info_t info;
-    uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB;
-    uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT;
-    if (dir == TUSB_DIR_OUT)
-    {
-      tu_fifo_get_write_info(ff, &info);
-      udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
-      udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
-    } else {
-      tu_fifo_get_read_info(ff, &info);
-      if(info.wrapped.len == 0)
-      {
-        udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN;
-      }
-      udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN;
-    }
-
-    // Clean invalidate cache of linear part
-    CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.linear.ptr, 4), info.linear.len + 31);
-
-    USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.linear.ptr;
-    if (info.wrapped.len)
-    {
-      // Clean invalidate cache of wrapped part
-      CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.wrapped.ptr, 4), info.wrapped.len + 31);
+  xfer->fifo       = ff;
 
-      dma_desc[epnum - 1].next_desc = 0;
-      dma_desc[epnum - 1].buff_addr = (uint32_t)info.wrapped.ptr;
-      dma_desc[epnum - 1].chnl_ctrl =
-        udd_dma_ctrl_wrap | (info.wrapped.len << DEVDMACONTROL_BUFF_LENGTH_Pos);
-      // Clean cache of wrapped DMA descriptor
-      CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
-
-      udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
-      USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
-    } else {
-      udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT;
-    }
-    udd_dma_ctrl_lin |= (info.linear.len << DEVDMACONTROL_BUFF_LENGTH_Pos);
-    // Disable IRQs to have a short sequence
-    // between read of EOT_STA and DMA enable
-    uint32_t irq_state = __get_PRIMASK();
-    __disable_irq();
-    if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
-    {
-      USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin;
-      USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
-      __set_PRIMASK(irq_state);
-      return true;
-    }
-    __set_PRIMASK(irq_state);
-
-    // Here a ZLP has been received
-    // and the DMA transfer must be not started.
-    // It is the end of transfer
-    return false;
-  } else
-  {
-    if (dir == TUSB_DIR_OUT)
-    {
-      USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else
-    {
-      dcd_transmit_packet(xfer,epnum);
-    }
+  if (dir == TUSB_DIR_OUT) {
+    USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
+  } else {
+    dcd_transmit_packet(xfer, epnum);
   }
   return true;
 }
 
 // Stall endpoint
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void)rhport;
+  const uint8_t epnum       = tu_edpt_number(ep_addr);
   USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS;
   // Re-enable SETUP interrupt
-  if (epnum == 0)
-  {
+  if (epnum == 0) {
     USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
   }
 }
 
 // clear stall, data toggle is also reset to DATA0
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+  (void)rhport;
+  const uint8_t epnum       = tu_edpt_number(ep_addr);
   USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
-  USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS;
+  USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS;
 }
 #endif
diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/samx7x_common.h
index db4a81e0e..5e3c20c0f 100644
--- a/src/portable/microchip/samx7x/common_usb_regs.h
+++ b/src/portable/microchip/samx7x/samx7x_common.h
@@ -1,4 +1,4 @@
- /*
+/*
 * The MIT License (MIT)
 *
 * Copyright (c) 2019 Microchip Technology Inc.
@@ -2098,7 +2098,72 @@ typedef struct
 #define FIFO_RAM_ADDR     0xA0100000u
 
 // Errata: The DMA feature is not available for Pipe/Endpoint 7
-#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6 && CFG_TUD_SAMX7X_DMA_ENABLE)
+
+//------------- DCache -------------//
+#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
+
+typedef struct {
+  uintptr_t start;
+  uintptr_t end;
+} mem_region_t;
+
+// Can be used to define additional uncached regions
+#ifndef CFG_SAMX7X_MEM_UNCACHED_REGIONS
+#define CFG_SAMX7X_MEM_UNCACHED_REGIONS
+#endif
+
+static mem_region_t uncached_regions[] = {
+  // DTCM
+  {.start = 0x20000000, .end = 0x203fffff},
+  CFG_SAMX7X_MEM_UNCACHED_REGIONS
+};
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
+  if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) {
+    size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT;
+  }
+  return size;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
+  if (0 == (SCB->CCR & SCB_CCR_DC_Msk)) {
+    return false; // D-Cache is disabled
+  }
+  for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
+    if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_clean(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+#endif
 
 #else // TODO : SAM3U
 
diff --git a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
new file mode 100644
index 000000000..c9810f51c
--- /dev/null
+++ b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
@@ -0,0 +1,821 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 HiFiPhile (Zixun LI)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_IP3516)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "host/hcd.h"
+#include "host/usbh.h"
+#include "hcd_lpc_ip3516.h"
+
+#if TU_CHECK_MCU(OPT_MCU_LPC55, OPT_MCU_LPC54)
+  #include "fsl_device_registers.h"
+#else
+  #error "Unsupported MCUs"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+#if TU_CHECK_MCU(OPT_MCU_LPC54)
+  #define ATLPTD ATL_PTD_BASE_ADDR
+  #define INTPTD INT_PTD_BASE_ADDR
+  #define ISOPTD ISO_PTD_BASE_ADDR
+  #define ATLPTDD ATL_PTD_DONE_MAP
+  #define INTPTDD INT_PTD_DONE_MAP
+  #define ISOPTDD ISO_PTD_DONE_MAP
+  #define ATLPTDS ATL_PTD_SKIP_MAP
+  #define INTPTDS INT_PTD_SKIP_MAP
+  #define ISOPTDS ISO_PTD_SKIP_MAP
+  #define DATAPAYLOAD DATA_PAYLOAD_BASE_ADDR
+  #define LASTPTD LAST_PTD_INUSE
+
+  #define USBHSH_ATLPTD_ATL_BASE_MASK USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK
+  #define USBHSH_INTPTD_INT_BASE_MASK USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK
+  #define USBHSH_ISOPTD_ISO_BASE_MASK USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK
+
+  #define USBHSH_DATAPAYLOAD_DAT_BASE_MASK USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK
+
+  #define USBHSH_LASTPTD_ATL_LAST USBHSH_LAST_PTD_INUSE_ATL_LAST
+  #define USBHSH_LASTPTD_INT_LAST USBHSH_LAST_PTD_INUSE_INT_LAST
+  #define USBHSH_LASTPTD_ISO_LAST USBHSH_LAST_PTD_INUSE_ISO_LAST
+#endif
+
+#define USBHSH_PORTSC1_W1C_MASK (USBHSH_PORTSC1_CSC_MASK | USBHSH_PORTSC1_PEDC_MASK | USBHSH_PORTSC1_OCC_MASK)
+
+#define IP3516_PSPD_LOW   0
+#define IP3516_PSPD_FULL  1
+#define IP3516_PSPD_HIGH  2
+
+//--------------------------------------------------------------------+
+// Proprietary Transfer Descriptor
+//--------------------------------------------------------------------+
+
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(1024) static ip3516_ptd_t _ptd;
+
+static struct {
+  uint32_t uframe_number;
+  uint32_t uframe_length;
+  bool attached; // Track attachment state to avoid duplicate events, sometimes high-speed disconnection detector is not reliable
+} _hcd_data;
+
+//--------------------------------------------------------------------+
+// Helper Functions
+//--------------------------------------------------------------------+
+
+static inline bool is_ptd_free(const ptd_ctrl1_t ctrl1) {
+  return ctrl1.mps == 0;
+}
+
+static inline bool is_xfer_async(tusb_xfer_type_t xfer_type) {
+  return (xfer_type == TUSB_XFER_CONTROL || xfer_type == TUSB_XFER_BULK);
+}
+
+static inline void ptd_clear_state(ptd_state_t *state) {
+  ptd_state_t local = {.value = 0};
+  local.ep_type     = state->ep_type;     // preserve ep_type
+  local.token       = state->token;       // preserve token
+  local.data_toggle = state->data_toggle; // preserve data_toggle
+  *state            = local;
+}
+
+static inline uint8_t ptd_find_free(tusb_xfer_type_t xfer_type) {
+  uint8_t  max_count;
+  intptr_t ptd_array;
+
+  switch (xfer_type) {
+    case TUSB_XFER_CONTROL:
+    case TUSB_XFER_BULK:
+      max_count = IP3516_ATL_NUM;
+      ptd_array = (intptr_t)&_ptd.atl;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      max_count = IP3516_PTL_NUM;
+      ptd_array = (intptr_t)&_ptd.intr;
+      break;
+
+    case TUSB_XFER_ISOCHRONOUS:
+      max_count = IP3516_PTL_NUM;
+      ptd_array = (intptr_t)&_ptd.iso;
+      break;
+
+    default:
+      return TUSB_INDEX_INVALID_8;
+  }
+
+  for (uint8_t i = 0; i < max_count; i++) {
+    // For ATL: stride is sizeof(ip3516_atl_t) = 16 bytes = 4 words
+    // For PTL: stride is sizeof(ip3516_ptl_t) = 32 bytes = 8 words
+    uint8_t      stride = is_xfer_async(xfer_type) ? sizeof(ip3516_atl_t) : sizeof(ip3516_ptl_t);
+    ptd_ctrl1_t *ctrl1  = (ptd_ctrl1_t *)(ptd_array + i * stride);
+
+    if (is_ptd_free(*ctrl1)) {
+      return i;
+    }
+  }
+
+  return TUSB_INDEX_INVALID_8; // No free PTD found
+}
+
+// Close all PTDs associated with a specific device address
+static void close_ptds_by_device(uint8_t dev_addr, intptr_t ptd_array, uint8_t max_count, uint8_t stride,
+                                 volatile uint32_t *skip_reg) {
+
+  uint32_t skip_mask = 0;
+
+  for (uint8_t i = 0; i < max_count; i++) {
+    intptr_t     ptd_ptr   = ptd_array + i * stride;
+    ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1));
+    ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2));
+
+    if (!is_ptd_free(*ptd_ctrl1) && ptd_ctrl2->dev_addr == dev_addr) {
+      *skip_reg |= (1 << i);
+      skip_mask |= (1 << i);
+    }
+  }
+
+  if (skip_mask) {
+    // Wait 1 uframe for PTDs to be inactive (with timeout)
+    uint32_t start_uframe =
+      (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT;
+    uint32_t timeout = 10000;
+    while (((USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT) ==
+           start_uframe && timeout > 0) {
+      timeout--;
+    }
+
+    // Clear PTDs
+    for (uint8_t i = 0; i < max_count; i++) {
+      if (skip_mask & (1 << i)) {
+        intptr_t ptd_ptr = ptd_array + i * stride;
+        tu_memclr((void *)ptd_ptr, stride);
+      }
+    }
+
+    // Clear skip bits
+    *skip_reg &= ~skip_mask;
+  }
+}
+
+// Check if a PTD matches the given endpoint criteria
+static bool ptd_matches(intptr_t ptd_ptr, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
+  ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1));
+  if (is_ptd_free(*ptd_ctrl1)) {
+    return false;
+  }
+
+  ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2));
+  if (ptd_ctrl2->dev_addr != dev_addr || ptd_ctrl2->ep_num != ep_num) {
+    return false;
+  }
+
+  ptd_state_t *ptd_state  = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+  bool         is_control = (ptd_state->ep_type == TUSB_XFER_CONTROL);
+
+  // For control endpoint, match both IN and OUT directions
+  if (is_control) {
+    return true;
+  }
+
+  if (ep_dir == TUSB_DIR_IN && ptd_state->token == IP3516_PTD_TOKEN_IN) {
+    return true;
+  }
+
+  if (ep_dir == TUSB_DIR_OUT && ptd_state->token == IP3516_PTD_TOKEN_OUT) {
+    return true;
+  }
+
+  return false;
+}
+
+// Find and close a specific PTD
+static bool find_and_close_ptd(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir, intptr_t ptd_array, uint8_t max_count,
+                               uint8_t stride, volatile uint32_t *skip_reg) {
+  for (uint8_t i = 0; i < max_count; i++) {
+    intptr_t ptd_ptr = ptd_array + i * stride;
+    if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) {
+      if (skip_reg) {
+        *skip_reg |= (1 << i);
+
+        // Wait 1 uframe for PTD to be inactive (with timeout)
+        uint32_t start_uframe =
+          (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT;
+        uint32_t timeout = 10000;
+        while (((USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT) ==
+               start_uframe && timeout > 0) {
+          timeout--;
+        }
+
+        // Just clear state
+        ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1));
+        ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+        ptd_clear_state(ptd_state);
+        ptd_ctrl1->valid = 0;
+
+        *skip_reg &= ~(1 << i);
+      } else {
+        // Clear PTD
+        tu_memclr((void *)ptd_ptr, stride);
+      }
+      return true;
+    }
+  }
+  return false;
+}
+
+// Find an opened PTD
+static intptr_t find_opened_ptd(uint8_t dev_addr, uint8_t ep_addr) {
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+
+  // Search in ATL
+  for (uint8_t i = 0; i < IP3516_ATL_NUM; i++) {
+    intptr_t ptd_ptr = (intptr_t)&_ptd.atl[i];
+    if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) {
+      return ptd_ptr;
+    }
+  }
+
+  // Search in INT
+  for (uint8_t i = 0; i < IP3516_PTL_NUM; i++) {
+    intptr_t ptd_ptr = (intptr_t)&_ptd.intr[i];
+    if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) {
+      return ptd_ptr;
+    }
+  }
+
+  // Search in ISO
+  for (uint8_t i = 0; i < IP3516_PTL_NUM; i++) {
+    intptr_t ptd_ptr = (intptr_t)&_ptd.iso[i];
+    if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) {
+      return ptd_ptr;
+    }
+  }
+
+  return 0;
+}
+
+static bool edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen, bool is_setup) {
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+
+  intptr_t ptd_ptr = find_opened_ptd(dev_addr, ep_addr);
+  TU_ASSERT(ptd_ptr != 0);
+
+  ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1));
+  ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2));
+  ptd_data_t  *ptd_data  = (ptd_data_t *)(ptd_ptr + offsetof(ip3516_atl_t, data));
+  ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+
+  // Setup data buffer and length
+  ptd_data->data_addr = (uint32_t)(uintptr_t)buffer & IP3516_PTD_DATA_ADDR_MASK;
+  ptd_data->xfer_len  = buflen;
+
+  // Clear previous state
+  ptd_clear_state(ptd_state);
+
+  // Set token for EP0
+  if (ep_num == 0) {
+    if (is_setup) {
+      ptd_state->token       = IP3516_PTD_TOKEN_SETUP;
+      ptd_state->data_toggle = 0;
+    } else {
+      ptd_state->token       = (ep_dir == TUSB_DIR_IN) ? IP3516_PTD_TOKEN_IN : IP3516_PTD_TOKEN_OUT;
+      ptd_state->data_toggle = 1;
+    }
+  }
+
+  // Interrupt split transfer needs to be relaunched manually if NAKed
+  if (ptd_ctrl2->split && ptd_state->ep_type == TUSB_XFER_INTERRUPT) {
+    ptd_ctrl2->reload  = 0x0f;
+    ptd_state->nak_cnt = 0x0f;
+  }
+
+  // Activate PTD
+  ptd_ctrl1->valid  = 1;
+  ptd_state->active = 1;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) {
+  (void)rh_init;
+  (void)rhport;
+
+  // Reset controller
+  USBHSH->USBCMD |= USBHSH_USBCMD_HCRESET_MASK;
+  while (USBHSH->USBCMD & USBHSH_USBCMD_HCRESET_MASK) {}
+
+  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK;
+
+  tu_memclr(&_ptd, sizeof(_ptd));
+  tu_varclr(&_hcd_data);
+
+  // Set base addresses
+  USBHSH->ATLPTD      = (uint32_t)&_ptd.atl & USBHSH_ATLPTD_ATL_BASE_MASK;
+  USBHSH->INTPTD      = (uint32_t)&_ptd.intr & USBHSH_INTPTD_INT_BASE_MASK;
+  USBHSH->ISOPTD      = (uint32_t)&_ptd.iso & USBHSH_ISOPTD_ISO_BASE_MASK;
+  USBHSH->DATAPAYLOAD = (uint32_t)&_ptd & USBHSH_DATAPAYLOAD_DAT_BASE_MASK;
+
+  // Turn on power switch
+  if (USBHSH->HCSPARAMS & USBHSH_HCSPARAMS_PPC_MASK) {
+    USBHSH->PORTSC1 |= USBHSH_PORTSC1_PP_MASK;
+  }
+
+  // Get frame list size
+  uint32_t fls = (USBHSH->USBCMD & USBHSH_USBCMD_FLS_MASK) >> USBHSH_USBCMD_FLS_SHIFT;
+  _hcd_data.uframe_length = 8192 >> fls;
+
+  // Clear pending interrupts
+  USBHSH->USBSTS = 0xFFFFFFFF;
+
+  // Enable interrupts
+  USBHSH->USBINTR = USBHSH_USBINTR_ATL_IRQ_E_MASK | USBHSH_USBINTR_INT_IRQ_E_MASK | USBHSH_USBINTR_ISO_IRQ_E_MASK |
+                    USBHSH_USBINTR_PCDE_MASK | USBHSH_USBINTR_FLRE_MASK;
+
+
+  // Enable all PTDs
+  USBHSH->LASTPTD = USBHSH_LASTPTD_ATL_LAST(IP3516_ATL_NUM - 1) | USBHSH_LASTPTD_INT_LAST(IP3516_PTL_NUM - 1) |
+                    USBHSH_LASTPTD_ISO_LAST(IP3516_PTL_NUM - 1);
+
+  // Enable controller
+  USBHSH->USBCMD = USBHSH_USBCMD_ATL_EN_MASK | USBHSH_USBCMD_INT_EN_MASK | USBHSH_USBCMD_ISO_EN_MASK | USBHSH_USBCMD_RS_MASK;
+
+  return true;
+}
+
+// Enable USB interrupt
+void hcd_int_enable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_EnableIRQ(USB1_IRQn);
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void)rhport;
+  NVIC_DisableIRQ(USB1_IRQn);
+}
+
+bool hcd_deinit(uint8_t rhport) {
+  (void)rhport;
+
+  // Disable interrupts
+  USBHSH->USBINTR = 0;
+  USBHSH->USBSTS = 0xFFFFFFFF;
+
+  // Disable controller
+  USBHSH->USBCMD &= ~(USBHSH_USBCMD_ATL_EN_MASK | USBHSH_USBCMD_INT_EN_MASK | USBHSH_USBCMD_ISO_EN_MASK | USBHSH_USBCMD_RS_MASK);
+
+  // Turn off power switch
+  if (USBHSH->HCSPARAMS & USBHSH_HCSPARAMS_PPC_MASK) {
+    USBHSH->PORTSC1 &= ~USBHSH_PORTSC1_PP_MASK;
+  }
+
+  // Connect PHY to device mode
+  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK | USBHSH_PORTMODE_DEV_ENABLE_MASK;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void)rhport;
+  uint32_t status = USBHSH->PORTSC1 & ~USBHSH_PORTSC1_W1C_MASK;
+  USBHSH->PORTSC1 = status | USBHSH_PORTSC1_PR_MASK;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void)rhport;
+  uint32_t status = USBHSH->PORTSC1 & ~USBHSH_PORTSC1_W1C_MASK;
+  USBHSH->PORTSC1 = status & ~USBHSH_PORTSC1_PR_MASK;
+  while (USBHSH->PORTSC1 & USBHSH_PORTSC1_PR_MASK) {}
+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+  uint32_t pspd = (USBHSH->PORTSC1 & USBHSH_PORTSC1_PSPD_MASK) >> USBHSH_PORTSC1_PSPD_SHIFT;
+  if (pspd == IP3516_PSPD_HIGH) {
+    // enable phy disconnection for high speed
+    USBPHY->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
+  }
+#endif
+}
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void)rhport;
+  return (USBHSH->PORTSC1 & USBHSH_PORTSC1_CCS_MASK) ? true : false;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void)rhport;
+  uint32_t pspd = (USBHSH->PORTSC1 & USBHSH_PORTSC1_PSPD_MASK) >> USBHSH_PORTSC1_PSPD_SHIFT;
+  switch (pspd) {
+    case IP3516_PSPD_LOW:
+      return TUSB_SPEED_LOW;
+    case IP3516_PSPD_FULL:
+      return TUSB_SPEED_FULL;
+    case IP3516_PSPD_HIGH:
+      return TUSB_SPEED_HIGH;
+    default:
+      return TUSB_SPEED_INVALID;
+  }
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void)rhport;
+  uint32_t uframe = (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT;
+  uframe &= (_hcd_data.uframe_length - 1);
+  return (uframe + _hcd_data.uframe_number) >> 3;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void)rhport;
+
+  close_ptds_by_device(dev_addr, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t), &USBHSH->ATLPTDS);
+  close_ptds_by_device(dev_addr, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), &USBHSH->INTPTDS);
+  close_ptds_by_device(dev_addr, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), &USBHSH->ISOPTDS);
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+static inline intptr_t get_ptd_from_index(tusb_xfer_type_t xfer_type, uint8_t ptd_index) {
+  if (is_xfer_async(xfer_type)) {
+    return (intptr_t)&_ptd.atl[ptd_index];
+  } else {
+    if (xfer_type == TUSB_XFER_INTERRUPT) {
+      return (intptr_t)&_ptd.intr[ptd_index];
+    } else {
+      return (intptr_t)&_ptd.iso[ptd_index];
+    }
+  }
+}
+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc) {
+  (void)rhport;
+
+  const uint8_t          ep_num    = tu_edpt_number(ep_desc->bEndpointAddress);
+  const tusb_xfer_type_t xfer_type = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
+
+  tuh_bus_info_t bus_info;
+  tuh_bus_info_get(dev_addr, &bus_info);
+
+  // Find a free PTD
+  uint8_t ptd_index = ptd_find_free(xfer_type);
+  TU_ASSERT(ptd_index != TUSB_INDEX_INVALID_8);
+
+  // Configure PTD
+  intptr_t              ptd_ptr = get_ptd_from_index(xfer_type, ptd_index);
+  volatile ptd_ctrl1_t *ctrl1   = (volatile ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1));
+  volatile ptd_ctrl2_t *ctrl2   = (volatile ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2));
+  volatile ptd_data_t  *data    = (volatile ptd_data_t *)(ptd_ptr + offsetof(ip3516_atl_t, data));
+  volatile ptd_state_t *state   = (volatile ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+
+  // Initialize PTD fields
+  ctrl1->mps  = ep_desc->wMaxPacketSize;
+  ctrl1->mult = 1;
+
+  ctrl2->dev_addr = dev_addr;
+  ctrl2->ep_num   = ep_num;
+  ctrl2->speed    = bus_info.speed == TUSB_SPEED_LOW ? 2 : 0;
+  ctrl2->hub_addr = bus_info.hub_addr;
+  ctrl2->hub_port = bus_info.hub_port;
+  ctrl2->split    = (hcd_port_speed_get(rhport) == TUSB_SPEED_HIGH) && (bus_info.speed != TUSB_SPEED_HIGH) ? 1 : 0;
+
+  data->intr = 1;
+
+  state->ep_type = (uint32_t)xfer_type;
+  state->token   = tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN ? IP3516_PTD_TOKEN_IN : IP3516_PTD_TOKEN_OUT;
+
+  if (!is_xfer_async(xfer_type)) {
+    ip3516_ptl_t *ptd = (ip3516_ptl_t *)ptd_ptr;
+
+    uint32_t uframe_interval;
+    if (bus_info.speed == TUSB_SPEED_HIGH) {
+      uframe_interval = 1 << (ep_desc->bInterval - 1);
+    } else {
+      uframe_interval = ep_desc->bInterval << 3;
+      // round down to nearest power of 2
+      uframe_interval = 1 << tu_log2(uframe_interval);
+    }
+    uframe_interval = tu_min32(uframe_interval, IP3516_MAX_UFRAME);
+
+    // uframe_active is an 8-bit mask, where each bit corresponds to a micro-frame within a 1ms frame.
+    // A '1' indicates the endpoint should be polled in that micro-frame.
+    // For example:
+    // Interval 1 (poll every u-frame) -> mask is 0b11111111 (0xFF)
+    // Interval 2 (poll every 2nd u-frame, e.g., 0, 2, 4, 6) -> mask is 0b10101010 (0xAA)
+    // Interval 4 (poll every 4th u-frame, e.g., 0, 4) -> mask is 0b10001000 (0x88)
+    // Interval 8 (poll every 8th u-frame, e.g., 0) -> mask is 0b10000000 (0x80)
+    switch (uframe_interval) {
+      case 1:
+        ptd->status.uframe_active = 0xFF;
+        break;
+      case 2:
+        ptd->status.uframe_active = 0xAA;
+        break;
+      case 4:
+        ptd->status.uframe_active = 0x11;
+        break;
+      case 8:
+        ptd->status.uframe_active = 0x01;
+        break;
+      default:
+        // For intervals > 8, we poll once per frame (every 8 u-frames) and use ctrl1.uframe to skip frames.
+        ptd->status.uframe_active = 0x01;
+        if (uframe_interval >= 16) {
+          ctrl1->uframe = tu_log2(uframe_interval) - 3;
+        }
+        break;
+    }
+
+    if (ctrl2->split) {
+      // 11.18.1 Best Case Full-Speed Budget
+      //
+      // A microframe of time allows at most 187.5 raw bytes of signaling on a full-speed bus.
+      // The best case full-speed budget assumes that 188 full-speed bytes occur in each microframe.
+      //
+      // A 1 ms frame subdivided into microframes of budget time:
+      //
+      // Microframes            Y_0   Y_1   Y_2   Y_3   Y_4   Y_5   Y_6   Y_7
+      // Max wire time          187.5 187.5 187.5 187.5 187.5 187.5 32
+      // Best case wire budget  188   188   188   188   188   188   29
+      //
+      // 11.18.4  Host Split Transaction Scheduling Requirements
+      //
+      // 1. The host must never schedule a start-split in microframe Y_6.
+      // 2. For isochronous OUT full-speed transactions, for each microframe in which the transaction is
+      // budgeted, the host must schedule a 188 (or the remaining data size) data byte start-split transaction.
+      // For isochronous IN and interrupt IN/OUT full-/low-speed transactions, a single start-split must be
+      // scheduled in the microframe before the transaction is budgeted to start on the full-/low-speed bus.
+      // 3. For isochronous OUT full-speed transactions, the host must never schedule a complete-split. The
+      // TT response to a complete-split for an isochronous OUT is undefined.
+      //    For interrupt IN/OUT full-/low-speed transactions, the host must schedule a complete-split
+      // transaction in each of the two microframes following the first microframe in which the full-/low-
+      // speed transaction is budgeted.  An additional complete-split must also be scheduled in the third
+      // following microframe unless the full-/low-speed transaction was budgeted to start in microframe Y_6
+      //    For isochronous IN full-speed transactions, for each microframe in which the full-speed transaction
+      // is budgeted, a complete-split must be scheduled for each following microframe.
+      // Also, determine the last microframe in which a complete-split is scheduled, call it L.
+      // If L is less than Y_6, schedule additional complete-splits in microframe L+1 and L+2.
+      // If L is equal to Y_6, schedule one complete-split in microframe Y_7.
+      //
+      // TODO: Implement budget check scheduling
+      // Otherwise, it may cause bus contention with other split transfers
+      // Here we simply start interrupt transfers for Y_0 and Y1 and isochronous transfers for Y_2
+      if (xfer_type == TUSB_XFER_ISOCHRONOUS) {
+        const uint8_t    ss_slot = 2; // Start-split slot
+        const uint8_t    slots   = (ep_desc->wMaxPacketSize + 187) / 188;
+        const tusb_dir_t ep_dir  = tu_edpt_dir(ep_desc->bEndpointAddress);
+        if (ep_dir == TUSB_DIR_IN) {
+          if (ep_desc->wMaxPacketSize > 192) {
+            ctrl1->mps = 192;
+          }
+          ptd->status.uframe_active = 1 << ss_slot;
+          for (uint8_t i = 0; i < slots; i++) {
+            ptd->iso_in_0.uframe_complete |= 1 << (2 + ss_slot + i);
+          }
+          // Schedule additional complete-splits if needed
+          uint8_t last_complete = ss_slot + slots + 1;
+          if (last_complete < 6) {
+            ptd->iso_in_0.uframe_complete |= 1 << (ss_slot + last_complete + 1);
+            ptd->iso_in_0.uframe_complete |= 1 << (ss_slot + last_complete + 2);
+          } else if (last_complete == 6) {
+            ptd->iso_in_0.uframe_complete |= 1 << 7;
+          }
+        } else {
+          if (ep_desc->wMaxPacketSize > 188) {
+            ctrl1->mps = 188;
+          }
+          for (uint8_t i = 0; i < slots; i++) {
+            ptd->status.uframe_active |= 1 << (ss_slot + i);
+          }
+        }
+      } else {
+        // Start-split slot, jigging to avoid bus contention: EP odd -> Y_1, EP even -> Y_0
+        const uint8_t ss_slot     = ep_num & 0x01;
+        ptd->status.uframe_active = 1 << ss_slot;
+        // Complete-split slots: next 3 u-frames
+        ptd->iso_in_0.uframe_complete = 0x1c << ss_slot;
+      }
+    }
+  }
+
+  return true;
+}
+
+// Close an opened endpoint
+bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void)rhport;
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+
+  // Search in ATL
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t), NULL)) {
+    return true;
+  }
+
+  // Search in INT
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), NULL)) {
+    return true;
+  }
+
+  // Search in ISO
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), NULL)) {
+    return true;
+  }
+
+  return false;
+}
+
+// Submit a transfer on an endpoint
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
+  (void)rhport;
+
+  return edpt_xfer(dev_addr, ep_addr, buffer, buflen, false);
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void)rhport;
+
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = tu_edpt_dir(ep_addr);
+
+  // Search in ATL
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t),
+                         &USBHSH->ATLPTDS)) {
+    return true;
+  }
+
+  // Search in INT
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t),
+                         &USBHSH->INTPTDS)) {
+    return true;
+  }
+
+  // Search in ISO
+  if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t),
+                         &USBHSH->ISOPTDS)) {
+    return true;
+  }
+
+  return false;
+}
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) {
+  (void)rhport;
+
+  return edpt_xfer(dev_addr, 0x00, (uint8_t *)(uintptr_t)setup_packet, 8, true);
+}
+
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void)rhport;
+
+  intptr_t ptd_ptr = find_opened_ptd(dev_addr, ep_addr);
+  TU_ASSERT(ptd_ptr != 0);
+
+  ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+  ptd_clear_state(ptd_state);
+  ptd_state->data_toggle = 0; // reset data toggle to DATA0
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Interrupt Handler
+//--------------------------------------------------------------------+
+
+// Handle port status change event
+static inline void handle_port_status_change(uint8_t rhport) {
+  const uint32_t status = USBHSH->PORTSC1;
+
+  if (status & USBHSH_PORTSC1_CSC_MASK) {
+    if (status & USBHSH_PORTSC1_CCS_MASK && !_hcd_data.attached) {
+      _hcd_data.attached = true;
+      hcd_event_device_attach(rhport, true);
+    } else {
+      _hcd_data.attached = false;
+      hcd_event_device_remove(rhport, true);
+  #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
+      // disable phy disconnection for high speed
+      USBPHY->CTRL &= ~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
+  #endif
+    }
+  }
+
+  USBHSH->PORTSC1 |= status & USBHSH_PORTSC1_W1C_MASK;
+}
+
+// Handle PTD done interrupt
+static inline void handle_ptd_done(uint32_t done_status, intptr_t ptd_array, bool is_async) {
+  uint8_t max_count = is_async ? IP3516_ATL_NUM : IP3516_PTL_NUM;
+  uint8_t stride    = is_async ? sizeof(ip3516_atl_t) : sizeof(ip3516_ptl_t);
+
+  for (uint8_t i = 0; i < max_count; i++) {
+    if (done_status & (1 << i)) {
+      intptr_t     ptd_ptr   = ptd_array + i * stride;
+      ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2));
+      ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state));
+
+      xfer_result_t result;
+      if (ptd_state->halt) {
+        result = XFER_RESULT_STALLED;
+      } else if (ptd_state->error || ptd_state->babble) {
+        result = XFER_RESULT_FAILED;
+      } else {
+        result = XFER_RESULT_SUCCESS;
+      }
+
+      uint8_t ep_addr = ptd_ctrl2->ep_num | (ptd_state->token == IP3516_PTD_TOKEN_IN ? 0x80 : 0x00);
+
+      hcd_event_xfer_complete(ptd_ctrl2->dev_addr, ep_addr, ptd_state->xferred_len, result, true);
+    }
+  }
+}
+
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void)in_isr;
+
+  uint32_t int_status = USBHSH->USBSTS;
+  USBHSH->USBSTS      = int_status; // clear interrupt status
+
+  // Port Change Detect
+  if (int_status & USBHSH_USBSTS_PCD_MASK) {
+    handle_port_status_change(rhport);
+  }
+
+  // Frame List Rollover
+  if (int_status & USBHSH_USBSTS_FLR_MASK) {
+    _hcd_data.uframe_number += _hcd_data.uframe_length;
+  }
+
+  // ATL done
+  if (int_status & USBHSH_USBSTS_ATL_IRQ_MASK) {
+    uint32_t done_status = USBHSH->ATLPTDD;
+    handle_ptd_done(done_status, (intptr_t)&_ptd.atl, true);
+    USBHSH->ATLPTDD = done_status;
+  }
+
+  // INT done
+  if (int_status & USBHSH_USBSTS_INT_IRQ_MASK) {
+    uint32_t done_status = USBHSH->INTPTDD;
+    handle_ptd_done(done_status, (intptr_t)&_ptd.intr, false);
+    USBHSH->INTPTDD = done_status;
+  }
+
+  // ISO done
+  if (int_status & USBHSH_USBSTS_ISO_IRQ_MASK) {
+    uint32_t done_status = USBHSH->ISOPTDD;
+    handle_ptd_done(done_status, (intptr_t)&_ptd.iso, false);
+    USBHSH->ISOPTDD = done_status;
+  }
+}
+
+#endif
diff --git a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h
new file mode 100644
index 000000000..5214c18ae
--- /dev/null
+++ b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h
@@ -0,0 +1,188 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 HiFiPhile (Zixun LI)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_HCD_IP3516_H_
+#define TUSB_HCD_IP3516_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// IP3516 CONFIGURATION & CONSTANTS
+//--------------------------------------------------------------------+
+
+#define IP3516_ATL_NUM 32
+#define IP3516_PTL_NUM 32
+
+#define IP3516_PTD_TOKEN_OUT 0x00U
+#define IP3516_PTD_TOKEN_IN 0x01U
+#define IP3516_PTD_TOKEN_SETUP 0x02U
+
+#define IP3516_PTD_EPTYPE_OUT 0x00U
+#define IP3516_PTD_EPTYPE_IN 0x01U
+#define IP3516_PTD_EPTYPE_SETUP 0x02U
+
+#define IP3516_PTD_MAX_TRANSFER_LENGTH 0x7FFFU
+
+#define IP3516_PTD_DATA_ADDR_MASK 0xFFFFU
+
+#define IP3516_MAX_UFRAME (1UL << 8)
+
+#define IP3516_PERIODIC_TRANSFER_GAP (3U)
+#define IP3516_ISO_MULTIPLE_TRANSFER (8U)
+
+
+//--------------------------------------------------------------------+
+// IP3516 PTD Data Structure
+//--------------------------------------------------------------------+
+
+// Control Word 1
+typedef union {
+  uint32_t value;
+  struct {
+    uint32_t valid    : 1;
+    uint32_t next_ptd : 5;
+    uint32_t          : 1;
+    uint32_t jump     : 1;
+    uint32_t uframe   : 8;
+    uint32_t mps      : 11;
+    uint32_t          : 1;
+    uint32_t mult     : 2;
+    uint32_t          : 2;
+  };
+} ptd_ctrl1_t;
+
+TU_VERIFY_STATIC(sizeof(ptd_ctrl1_t) == 4, "size is not correct");
+
+// Control Word 2
+typedef union {
+  uint32_t value;
+  struct {
+    uint32_t ep_num   : 4;
+    uint32_t dev_addr : 7;
+    uint32_t split    : 1;
+    uint32_t reload   : 4;
+    uint32_t speed    : 2;
+    uint32_t hub_port : 7;
+    uint32_t hub_addr : 7;
+  };
+} ptd_ctrl2_t;
+
+TU_VERIFY_STATIC(sizeof(ptd_ctrl2_t) == 4, "size is not correct");
+
+// Data Word
+typedef union {
+  uint32_t value;
+  struct {
+    uint32_t xfer_len  : 15;
+    uint32_t intr      : 1;
+    uint32_t data_addr : 16;
+  };
+} ptd_data_t;
+
+TU_VERIFY_STATIC(sizeof(ptd_data_t) == 4, "size is not correct");
+
+// State Word
+typedef union {
+  uint32_t value;
+  struct {
+    uint32_t xferred_len    : 15;
+    uint32_t token          : 2;
+    uint32_t ep_type        : 2;
+    uint32_t nak_cnt        : 4;
+    uint32_t err_cnt        : 2;
+    uint32_t data_toggle    : 1;
+    uint32_t ping           : 1;
+    uint32_t start_complete : 1;
+    uint32_t error          : 1;
+    uint32_t babble         : 1;
+    uint32_t halt           : 1;
+    uint32_t active         : 1;
+  };
+} ptd_state_t;
+
+TU_VERIFY_STATIC(sizeof(ptd_state_t) == 4, "size is not correct");
+
+// Status Word
+typedef union {
+  uint32_t value;
+  struct {
+    uint32_t uframe_active : 8;
+    uint32_t iso_status0   : 3;
+    uint32_t iso_status1   : 3;
+    uint32_t iso_status2   : 3;
+    uint32_t iso_status3   : 3;
+    uint32_t iso_status4   : 3;
+    uint32_t iso_status5   : 3;
+    uint32_t iso_status6   : 3;
+    uint32_t iso_status7   : 3;
+  };
+} ptd_status_t;
+
+TU_VERIFY_STATIC(sizeof(ptd_status_t) == 4, "size is not correct");
+
+// ATL (Asynchronous Transfer List) structure
+typedef volatile struct {
+  ptd_ctrl1_t ctrl1;
+  ptd_ctrl2_t ctrl2;
+  ptd_data_t  data;
+  ptd_state_t state;
+} ip3516_atl_t;
+
+TU_VERIFY_STATIC(sizeof(ip3516_atl_t) == 16, "size is not correct");
+
+// PTL (Periodic Transfer List) structure
+typedef volatile struct {
+  ptd_ctrl1_t  ctrl1;
+  ptd_ctrl2_t  ctrl2;
+  ptd_data_t   data;
+  ptd_state_t  state;
+  ptd_status_t status;
+  union {
+    uint32_t value;
+    struct {
+      uint32_t uframe_complete : 8;
+      uint32_t spl_iso_in_0    : 24;
+    };
+  } iso_in_0;
+  uint32_t iso_in_1;
+  uint32_t iso_in_2;
+} ip3516_ptl_t;
+
+TU_VERIFY_STATIC(sizeof(ip3516_ptl_t) == 32, "size is not correct");
+
+// Proprietary Transfer Descriptor
+typedef struct {
+  ip3516_ptl_t intr[IP3516_PTL_NUM];
+  ip3516_ptl_t iso[IP3516_PTL_NUM];
+  ip3516_atl_t atl[IP3516_ATL_NUM];
+} ip3516_ptd_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TUSB_HCD_IP3516_H_ */
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 5ca093506..4b248d9e6 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -243,7 +243,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
        OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
 
   OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;
-  OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated.
+  OHCI_REG->frame_interval ^= (1ul << 31); //Must toggle when frame_interval is updated.
   OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval
 
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
@@ -557,6 +557,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   (void) rhport;
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
+  TU_ASSERT(p_ed);
 
   ohci_ed_word2_t td_head = p_ed->td_head;
   td_head.toggle = 0; // reset data toggle
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 15852f29f..240e6c727 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -39,122 +39,103 @@
 #include "device/dcd.h"
 
 // Current implementation force vbus detection as always present, causing device think it is always plugged into host.
-// Therefore it cannot detect disconnect event, mistaken it as suspend.
+// Therefore, it cannot detect disconnect event, mistaken it as suspend.
 // Note: won't work if change to 0 (for now)
-#define FORCE_VBUS_DETECT   1
+  #define FORCE_VBUS_DETECT 1
+
+  #define USB_INTS_ERROR_BITS                                                                 \
+    (USB_INTS_ERROR_DATA_SEQ_BITS | USB_INTS_ERROR_BIT_STUFF_BITS | USB_INTS_ERROR_CRC_BITS | \
+     USB_INTS_ERROR_RX_OVERFLOW_BITS | USB_INTS_ERROR_RX_TIMEOUT_BITS)
 
 /*------------------------------------------------------------------*/
 /* Low level controller
  *------------------------------------------------------------------*/
-// Init these in dcd_init
-static uint8_t* next_buffer_ptr;
+// HW buffer pointer from USB buffer space (max 3840 bytes)
+static uint8_t *hw_buffer_ptr;
 
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
 static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 
-// SOF may be used by remote wakeup as RESUME, this indicate whether SOF is actually used by usbd
+// SOF may be used by remote wakeup as RESUME, this indicates whether SOF is actually used by usbd
 static bool _sof_enable = false;
 
-TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir) {
-  return &hw_endpoints[num][dir];
-}
-
-TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) {
-  uint8_t num = tu_edpt_number(ep_addr);
-  tusb_dir_t dir = tu_edpt_dir(ep_addr);
-  return hw_endpoint_get_by_num(num, dir);
-}
-
-// Allocate from the USB buffer space (max 3840 bytes)
-static void hw_endpoint_alloc(struct hw_endpoint* ep, size_t size) {
-  // round up size to multiple of 64
-  size = tu_round_up(ep->wMaxPacketSize, 64);
-
-  // double buffered Bulk endpoint
-  if (ep->transfer_type == TUSB_XFER_BULK) {
-    size *= 2u;
-  }
-
-  // assign buffer
-  ep->hw_data_buf = next_buffer_ptr;
-  next_buffer_ptr += size;
-
-  hard_assert(next_buffer_ptr < usb_dpram->epx_data + sizeof(usb_dpram->epx_data));
-  pico_info("  Allocated %d bytes (0x%p)\r\n", size,  ep->hw_data_buf);
+TU_ATTR_ALWAYS_INLINE static inline hw_endpoint_t *hw_endpoint_get(uint8_t epnum, tusb_dir_t dir) {
+  return &hw_endpoints[epnum][dir];
 }
 
-// Enable endpoint
-TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_enable(struct hw_endpoint* ep) {
-  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | hw_data_offset(ep->hw_data_buf);
-  *ep->endpoint_control = reg;
+TU_ATTR_ALWAYS_INLINE static inline hw_endpoint_t *hw_endpoint_get_by_addr(uint8_t ep_addr) {
+  const uint8_t    num = tu_edpt_number(ep_addr);
+  const tusb_dir_t dir = tu_edpt_dir(ep_addr);
+  return hw_endpoint_get(num, dir);
 }
 
 // main processing for dcd_edpt_iso_activate
-static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
-
-  const uint8_t num = tu_edpt_number(ep_addr);
-  const tusb_dir_t dir = tu_edpt_dir(ep_addr);
-
-  ep->ep_addr = ep_addr;
-
-  // For device, IN is a tx transfer and OUT is an rx transfer
-  ep->rx = (dir == TUSB_DIR_OUT);
-
-  ep->next_pid = 0u;
+static void hw_endpoint_init(hw_endpoint_t *ep, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
+  ep->ep_addr        = ep_addr;
+  ep->next_pid       = 0u;
   ep->wMaxPacketSize = wMaxPacketSize;
-  ep->transfer_type = transfer_type;
-
-  // Every endpoint has a buffer control register in dpram
-  if (dir == TUSB_DIR_IN) {
-    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
-  } else {
-    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
-  }
 
   // Clear existing buffer control state
-  *ep->buffer_control = 0;
-
-  if (num == 0) {
-    // EP0 has no endpoint control register because the buffer offsets are fixed
-    ep->endpoint_control = NULL;
+  io_rw_32 *buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+  *buf_ctrl_reg          = 0;
 
+  // allocated hw buffer
+  const uint8_t epnum = tu_edpt_number(ep_addr);
+  if (epnum == 0) {
     // Buffer offset is fixed (also double buffered)
     ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
   } else {
-    // Set the endpoint control register (starts at EP1, hence num-1)
-    if (dir == TUSB_DIR_IN) {
-      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
-    } else {
-      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
+    // round up size to multiple of 64
+    uint16_t size = (uint16_t)tu_round_up(wMaxPacketSize, 64);
+
+    // double buffered Bulk endpoint
+    if (transfer_type == TUSB_XFER_BULK) {
+      size *= 2u;
+
+  #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+      if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
+        ep->e15_bulk_in = true;
+      }
+  #endif
     }
+
+    // assign buffer
+    ep->hw_data_buf = hw_buffer_ptr;
+    hw_buffer_ptr += size;
+
+    hard_assert(hw_buffer_ptr < usb_dpram->epx_data + sizeof(usb_dpram->epx_data));
+    pico_info("  Allocated %d bytes (0x%p)\r\n", size, ep->hw_data_buf);
   }
 }
 
-// Init, allocate buffer and enable endpoint
-static void hw_endpoint_open(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
-  hw_endpoint_init(ep_addr, wMaxPacketSize, transfer_type);
-  const uint8_t num = tu_edpt_number(ep_addr);
-  if (num != 0) {
-    // EP0 is already enabled
-    hw_endpoint_alloc(ep, ep->wMaxPacketSize);
-    hw_endpoint_enable(ep);
+static void hw_endpoint_enable(hw_endpoint_t *ep, uint8_t transfer_type) {
+  io_rw_32 *ctrl_reg = hwep_ctrl_reg_device(ep);
+  // Set endpoint control register to enable (EP0 has no endpoint control register)
+  if (ctrl_reg != NULL) {
+    const uint32_t ctrl_value =
+      EP_CTRL_ENABLE_BITS | ((uint32_t)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | hw_data_offset(ep->hw_data_buf);
+    *ctrl_reg = ctrl_value;
   }
 }
 
-static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
-  hw_endpoint_xfer_start(ep, buffer, total_bytes);
+// Init and enable endpoint
+static void hw_endpoint_open(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
+  const uint8_t    epnum = tu_edpt_number(ep_addr);
+  const tusb_dir_t dir   = tu_edpt_dir(ep_addr);
+  hw_endpoint_t   *ep    = hw_endpoint_get(epnum, dir);
+
+  hw_endpoint_init(ep, ep_addr, wMaxPacketSize, transfer_type);
+  hw_endpoint_enable(ep, transfer_type);
 }
 
 static void hw_endpoint_abort_xfer(struct hw_endpoint* ep) {
   // Abort any pending transfer
+  const uint8_t  dir        = (uint8_t)tu_edpt_dir(ep->ep_addr);
+  const uint8_t  epnum      = tu_edpt_number(ep->ep_addr);
+  const uint32_t abort_mask = TU_BIT((epnum << 1) | (dir ? 0 : 1));
+
   // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1).
   // Which means we are not guaranteed to safely abort pending transfer on B0 and B1.
-  const uint8_t dir = tu_edpt_dir(ep->ep_addr);
-  const uint8_t epnum = tu_edpt_number(ep->ep_addr);
-  const uint32_t abort_mask = TU_BIT((epnum << 1) | (dir ? 0 : 1));
   if (rp2040_chip_version() >= 2) {
     usb_hw_set->abort = abort_mask;
     while ((usb_hw->abort_done & abort_mask) != abort_mask) {}
@@ -165,7 +146,8 @@ static void hw_endpoint_abort_xfer(struct hw_endpoint* ep) {
     buf_ctrl |= USB_BUF_CTRL_DATA1_PID;
   }
 
-  _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
+  io_rw_32 *buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+  hwbuf_ctrl_set(buf_ctrl_reg, buf_ctrl);
   hw_endpoint_reset_transfer(ep);
 
   if (rp2040_chip_version() >= 2) {
@@ -174,7 +156,7 @@ static void hw_endpoint_abort_xfer(struct hw_endpoint* ep) {
   }
 }
 
-static void __tusb_irq_path_func(hw_handle_buff_status)(void) {
+static void __tusb_irq_path_func(handle_hw_buff_status)(void) {
   uint32_t remaining_buffers = usb_hw->buf_status;
   pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
   uint bit = 1u;
@@ -184,12 +166,13 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) {
       usb_hw_clear->buf_status = bit;
 
       // IN transfer for even i, OUT transfer for odd i
-      struct hw_endpoint* ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN);
+      const uint8_t    epnum = i >> 1u;
+      const tusb_dir_t dir   = (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN;
+      hw_endpoint_t   *ep    = hw_endpoint_get(epnum, dir);
 
-      // Continue xfer
-      bool done = hw_endpoint_xfer_continue(ep);
+      const bool done = hw_endpoint_xfer_continue(ep);
       if (done) {
-        // Notify
+        // Notify usbd
         const uint16_t xferred_len = ep->xferred_len;
         hw_endpoint_reset_transfer(ep);
         dcd_event_xfer_complete(0, ep->ep_addr, xferred_len, XFER_RESULT_SUCCESS, true);
@@ -204,7 +187,7 @@ TU_ATTR_ALWAYS_INLINE static inline void reset_ep0(void) {
   // If we have finished this transfer on EP0 set pid back to 1 for next
   // setup transfer. Also clear a stall in case
   for (uint8_t dir = 0; dir < 2; dir++) {
-    struct hw_endpoint* ep = hw_endpoint_get_by_num(0, dir);
+    struct hw_endpoint *ep = hw_endpoint_get(0, dir);
     ep->next_pid = 1u;
     if (ep->active) {
       hw_endpoint_abort_xfer(ep); // Abort any pending transfer per USB specs
@@ -223,11 +206,11 @@ static void __tusb_irq_path_func(reset_non_control_endpoints)(void) {
   tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2 * sizeof(hw_endpoint_t));
 
   // reclaim buffer space
-  next_buffer_ptr = &usb_dpram->epx_data[0];
+  hw_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
 static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
-  uint32_t const status = usb_hw->ints;
+  const uint32_t status  = usb_hw->ints;
   uint32_t handled = 0;
 
   if (status & USB_INTF_DEV_SOF_BITS) {
@@ -240,27 +223,26 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
     e15_last_sof = time_us_32();
 
     for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) {
-      struct hw_endpoint* ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
+      struct hw_endpoint *ep = hw_endpoint_get(i, TUSB_DIR_IN);
 
       // Active Bulk IN endpoint requires SOF
-      if ((ep->transfer_type == TUSB_XFER_BULK) && ep->active) {
+      if (ep->e15_bulk_in && ep->active) {
         keep_sof_alive = true;
 
         hw_endpoint_lock_update(ep, 1);
-
-        // Deferred enable?
         if (ep->pending) {
           ep->pending = 0;
           hw_endpoint_start_next_buffer(ep);
         }
-
         hw_endpoint_lock_update(ep, -1);
       }
     }
 #endif
 
     // disable SOF interrupt if it is used for RESUME in remote wakeup
-    if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+    if (!keep_sof_alive && !_sof_enable) {
+      usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+    }
 
     dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
   }
@@ -269,7 +251,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
   // before closing the EP, the events will be delivered in same order.
   if (status & USB_INTS_BUFF_STATUS_BITS) {
     handled |= USB_INTS_BUFF_STATUS_BITS;
-    hw_handle_buff_status();
+    handle_hw_buff_status();
   }
 
   if (status & USB_INTS_SETUP_REQ_BITS) {
@@ -287,15 +269,12 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
 #if FORCE_VBUS_DETECT == 0
   // Since we force VBUS detect On, device will always think it is connected and
   // couldn't distinguish between disconnect and suspend
-  if (status & USB_INTS_DEV_CONN_DIS_BITS)
-  {
+  if (status & USB_INTS_DEV_CONN_DIS_BITS) {
     handled |= USB_INTS_DEV_CONN_DIS_BITS;
 
-    if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
-    {
+    if (usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS) {
       // Connected: nothing to do
-    }else
-    {
+    } else {
       // Disconnected
       dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
     }
@@ -315,10 +294,12 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
     usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
-#if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
+  #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
     // Only run enumeration workaround if pull up is enabled
-    if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) rp2040_usb_device_enumeration_fix();
-#endif
+    if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) {
+      rp2040_usb_device_enumeration_fix();
+    }
+  #endif
   }
 
   /* Note from pico datasheet 4.1.2.6.4 (v1.2)
@@ -346,13 +327,6 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
   }
 }
 
-#define USB_INTS_ERROR_BITS ( \
-    USB_INTS_ERROR_DATA_SEQ_BITS      |  \
-    USB_INTS_ERROR_BIT_STUFF_BITS     |  \
-    USB_INTS_ERROR_CRC_BITS           |  \
-    USB_INTS_ERROR_RX_OVERFLOW_BITS   |  \
-    USB_INTS_ERROR_RX_TIMEOUT_BITS)
-
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
@@ -369,9 +343,9 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version());
 
   // Reset hardware to default state
-  rp2040_usb_init();
+  rp2usb_init();
 
-#if FORCE_VBUS_DETECT
+  #if FORCE_VBUS_DETECT
   // Force VBUS detect so the device thinks it is plugged into a host
   usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 #endif
@@ -425,12 +399,11 @@ void dcd_int_disable(__unused uint8_t rhport) {
   irq_set_enabled(USBCTRL_IRQ, false);
 }
 
-void dcd_set_address(__unused uint8_t rhport, __unused uint8_t dev_addr) {
-  assert(rhport == 0);
-
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void)dev_addr;
   // Can't set device address in hardware until status xfer has complete
   // Send 0len complete response on EP0 IN
-  hw_endpoint_xfer(0x80, NULL, 0);
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0, false);
 }
 
 void dcd_remote_wakeup(__unused uint8_t rhport) {
@@ -475,7 +448,6 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
-
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
   (void) rhport;
 
@@ -489,7 +461,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* req
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
   (void) rhport;
   const uint8_t xfer_type = desc_edpt->bmAttributes.xfer;
-  TU_VERIFY(xfer_type != TUSB_XFER_ISOCHRONOUS);
   hw_endpoint_open(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), xfer_type);
   return true;
 }
@@ -497,56 +468,65 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
 // New API: Allocate packet buffer used by ISO endpoints
 // Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
-  (void) rhport;
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
-  hw_endpoint_init(ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS);
-  hw_endpoint_alloc(ep, largest_packet_size);
+  (void)rhport;
+  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_init(ep, ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS);
   return true;
 }
 
 // New API: Configure and enable an ISO endpoint according to descriptor
-bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
-  (void) rhport;
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_desc->bEndpointAddress);
+bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) {
+  (void)rhport;
+  const uint8_t       epnum = tu_edpt_number(ep_desc->bEndpointAddress);
+  const tusb_dir_t    dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
+  struct hw_endpoint *ep    = hw_endpoint_get(epnum, dir);
   TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and allocated previously
 
   if (ep->active) {
     hw_endpoint_abort_xfer(ep); // abort any pending transfer
   }
-
   ep->wMaxPacketSize = ep_desc->wMaxPacketSize;
-  hw_endpoint_enable(ep);
+
+  hw_endpoint_enable(ep, TUSB_XFER_ISOCHRONOUS);
   return true;
 }
 
 void dcd_edpt_close_all(uint8_t rhport) {
   (void) rhport;
-
   // may need to use EP Abort
   reset_non_control_endpoints();
 }
 
-bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes, bool is_isr) {
-  (void) is_isr;
-  assert(rhport == 0);
-  hw_endpoint_xfer(ep_addr, buffer, total_bytes);
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool is_isr) {
+  (void)rhport;
+  (void)is_isr;
+  hw_endpoint_t *ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_xfer_start(ep, buffer, NULL, total_bytes);
+  return true;
+}
+
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes, bool is_isr) {
+  (void)rhport;
+  (void)is_isr;
+  hw_endpoint_t *ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_xfer_start(ep, NULL, ff, total_bytes);
   return true;
 }
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
-  (void) rhport;
+  (void)rhport;
+  const uint8_t    epnum = tu_edpt_number(ep_addr);
+  const tusb_dir_t dir   = tu_edpt_dir(ep_addr);
+  hw_endpoint_t   *ep    = hw_endpoint_get(epnum, dir);
 
-  if (tu_edpt_number(ep_addr) == 0) {
+  if (epnum == 0) {
     // A stall on EP0 has to be armed so it can be cleared on the next setup packet
-    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS
-                                                                     : USB_EP_STALL_ARM_EP0_OUT_BITS;
+    usb_hw_set->ep_stall_arm = (dir == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
   }
 
-  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
-
-  // stall and clear current pending buffer
-  // may need to use EP_ABORT
-  _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL);
+  // stall and clear current pending buffer, may need to use EP_ABORT
+  io_rw_32 *buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+  hwbuf_ctrl_set(buf_ctrl_reg, USB_BUF_CTRL_STALL);
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
@@ -557,7 +537,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
 
     // clear stall also reset toggle to DATA0, ready for next transfer
     ep->next_pid = 0;
-    _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL);
+    io_rw_32 *buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+    hwbuf_ctrl_clear_mask(buf_ctrl_reg, USB_BUF_CTRL_STALL);
   }
 }
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index cd8c905d5..06c0ce340 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -62,34 +62,33 @@ enum {
                   USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS
 };
 
-static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
-{
+static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr) {
   uint8_t num = tu_edpt_number(ep_addr);
-  if ( num == 0 ) return &epx;
+  if (num == 0) {
+    return &epx;
+  }
 
-  for ( uint32_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
-  {
+  for (uint32_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) {
     struct hw_endpoint *ep = &ep_pool[i];
-    if ( ep->configured && (ep->dev_addr == dev_addr) && (ep->ep_addr == ep_addr) ) return ep;
+    if (ep->configured && (ep->dev_addr == dev_addr) && (ep->ep_addr == ep_addr)) {
+      return ep;
+    }
   }
 
   return NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void) {
   return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr) {
   // If this device is different to the speed of the root device
   // (i.e. is a low speed device on a full speed hub) then need pre
   return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
-static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
-{
+static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result) {
   // Mark transfer as done before we tell the tinyusb stack
   uint8_t dev_addr = ep->dev_addr;
   uint8_t ep_addr = ep->ep_addr;
@@ -98,47 +97,28 @@ static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_
   hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
-static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
-{
+static void __tusb_irq_path_func(handle_hwbuf_status_bit)(uint bit, struct hw_endpoint *ep) {
   usb_hw_clear->buf_status = bit;
-  // EP may have been stalled?
-  assert(ep->active);
-  bool done = hw_endpoint_xfer_continue(ep);
-  if ( done )
-  {
+  const bool done          = hw_endpoint_xfer_continue(ep);
+  if (done) {
     hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
   }
 }
 
-static void __tusb_irq_path_func(hw_handle_buff_status)(void)
-{
-  uint32_t remaining_buffers = usb_hw->buf_status;
-  pico_trace("buf_status 0x%08lx\n", remaining_buffers);
+static void __tusb_irq_path_func(handle_hwbuf_status)(void) {
+  uint32_t buf_status = usb_hw->buf_status;
+  pico_trace("buf_status 0x%08lx\n", buf_status);
 
   // Check EPX first
-  uint bit = 0b1;
-  if ( remaining_buffers & bit )
-  {
-    remaining_buffers &= ~bit;
+  uint32_t bit = 1u;
+  if (buf_status & bit) {
+    buf_status &= ~bit;
     struct hw_endpoint * ep = &epx;
-
-    uint32_t ep_ctrl = *ep->endpoint_control;
-    if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS )
-    {
-      TU_LOG(3, "Double Buffered: ");
-    }
-    else
-    {
-      TU_LOG(3, "Single Buffered: ");
-    }
-    TU_LOG_HEX(3, ep_ctrl);
-
-    _handle_buff_status_bit(bit, ep);
+    handle_hwbuf_status_bit(bit, ep);
   }
 
   // Check "interrupt" (asynchronous) endpoints for both IN and OUT
-  for ( uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++ )
-  {
+  for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && buf_status; i++) {
     // EPX is bit 0 & 1
     // IEP1 IN  is bit 2
     // IEP1 OUT is bit 3
@@ -147,20 +127,17 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
     // IEP3 IN  is bit 6
     // IEP3 OUT is bit 7
     // etc
-    for ( uint j = 0; j < 2; j++ )
-    {
+    for (uint j = 0; j < 2; j++) {
       bit = 1 << (i * 2 + j);
-      if ( remaining_buffers & bit )
-      {
-        remaining_buffers &= ~bit;
-        _handle_buff_status_bit(bit, &ep_pool[i]);
+      if (buf_status & bit) {
+        buf_status &= ~bit;
+        handle_hwbuf_status_bit(bit, &ep_pool[i]);
       }
     }
   }
 
-  if ( remaining_buffers )
-  {
-    panic("Unhandled buffer %d\n", remaining_buffers);
+  if (buf_status) {
+    panic("Unhandled buffer %d\n", buf_status);
   }
 }
 
@@ -220,7 +197,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   {
     handled |= USB_INTS_BUFF_STATUS_BITS;
     TU_LOG(2, "Buffer complete\r\n");
-    hw_handle_buff_status();
+    handle_hwbuf_status();
   }
 
   if ( status & USB_INTS_TRANS_COMPLETE_BITS )
@@ -240,9 +217,8 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   if ( status & USB_INTS_ERROR_DATA_SEQ_BITS )
   {
     usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
-    TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n",
-           tu_u32_low16(*epx.buffer_control),
-           tu_u32_high16(*epx.buffer_control));
+    TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(*hwbuf_ctrl_reg_host(&epx)),
+           tu_u32_high16(*hwbuf_ctrl_reg_host(&epx)));
     panic("Data Seq Error \n");
   }
 
@@ -266,7 +242,7 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
     ep = &ep_pool[i];
     if ( !ep->configured )
     {
-      // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
+      // Will be configured by hw_endpoint_init / hw_endpoint_allocate
       ep->interrupt_num = (uint8_t) (i - 1);
       return ep;
     }
@@ -274,41 +250,31 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
   return ep;
 }
 
-static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
-{
-  struct hw_endpoint * ep = NULL;
+static hw_endpoint_t *hw_endpoint_allocate(uint8_t transfer_type) {
+  hw_endpoint_t *ep = NULL;
 
-  if ( transfer_type != TUSB_XFER_CONTROL )
-  {
+  if (transfer_type == TUSB_XFER_CONTROL) {
+    ep              = &epx;
+    ep->hw_data_buf = &usbh_dpram->epx_data[0];
+  } else {
     // Note: even though datasheet name these "Interrupt" endpoints. These are actually
     // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
     ep = _next_free_interrupt_ep();
     pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
     assert(ep);
-    ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
-    ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
     // 0 for epx (double buffered): TODO increase to 1024 for ISO
     // 2x64 for intep0
     // 3x64 for intep1
     // etc
     ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
   }
-  else
-  {
-    ep = &epx;
-    ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
-    ep->endpoint_control = &usbh_dpram->epx_ctrl;
-    ep->hw_data_buf = &usbh_dpram->epx_data[0];
-  }
 
   return ep;
 }
 
-static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
-{
+static void hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize,
+                             uint8_t transfer_type, uint8_t bmInterval) {
   // Already has data buffer, endpoint control, and buffer control allocated at this point
-  assert(ep->endpoint_control);
-  assert(ep->buffer_control);
   assert(ep->hw_data_buf);
 
   uint8_t const num = tu_edpt_number(ep_addr);
@@ -317,49 +283,41 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
   ep->ep_addr = ep_addr;
   ep->dev_addr = dev_addr;
 
-  // For host, IN to host == RX, anything else rx == false
-  ep->rx = (dir == TUSB_DIR_IN);
-
   // Response to a setup packet on EP0 starts with pid of 1
   ep->next_pid = (num == 0 ? 1u : 0u);
   ep->wMaxPacketSize = wMaxPacketSize;
-  ep->transfer_type = transfer_type;
 
-  pico_trace("hw_endpoint_init dev %d ep %02X xfer %d\n", ep->dev_addr, ep->ep_addr, ep->transfer_type);
+  pico_trace("hw_endpoint_init dev %d ep %02X xfer %d\n", ep->dev_addr, ep->ep_addr, transfer_type);
   pico_trace("dev %d ep %02X setup buffer @ 0x%p\n", ep->dev_addr, ep->ep_addr, ep->hw_data_buf);
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
   // Bits 0-5 should be 0
   assert(!(dpram_offset & 0b111111));
 
   // Fill in endpoint control register with buffer offset
-  uint32_t ep_reg = EP_CTRL_ENABLE_BITS
-                    | EP_CTRL_INTERRUPT_PER_BUFFER
-                    | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
-                    | dpram_offset;
-  if ( bmInterval )
-  {
-    ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+  uint32_t ctrl_value = EP_CTRL_ENABLE_BITS | EP_CTRL_INTERRUPT_PER_BUFFER |
+                        ((uint32_t)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+  if (bmInterval) {
+    ctrl_value |= (uint32_t)((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
   }
-  *ep->endpoint_control = ep_reg;
-  pico_trace("endpoint control (0x%p) <- 0x%lx\n", ep->endpoint_control, ep_reg);
+
+  io_rw_32 *ctrl_reg = hwep_ctrl_reg_host(ep);
+  *ctrl_reg          = ctrl_value;
+  pico_trace("endpoint control (0x%p) <- 0x%lx\n", ctrl_reg, ctrl_value);
   ep->configured = true;
 
-  if ( ep != &epx )
-  {
+  if (ep != &epx) {
     // Endpoint has its own addr_endp and interrupt bits to be setup!
     // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
     // - device address
     // - endpoint number / direction
     // - preamble
-    uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
+    uint32_t reg = (uint32_t)(dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
 
-    if ( dir == TUSB_DIR_OUT )
-    {
+    if (dir == TUSB_DIR_OUT) {
       reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
     }
 
-    if ( need_pre(dev_addr) )
-    {
+    if (need_pre(dev_addr)) {
       reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
     }
     usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
@@ -367,8 +325,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     // Finally, enable interrupt that endpoint
     usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
 
-    // If it's an interrupt endpoint we need to set up the buffer control
-    // register
+    // If it's an interrupt endpoint we need to set up the buffer control register
   }
 }
 
@@ -382,7 +339,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   assert(rhport == 0);
 
   // Reset any previous state
-  rp2040_usb_init();
+  rp2usb_init();
 
   // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
   usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
@@ -466,8 +423,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
   // reset epx if it is currently active with unplugged device
   if (epx.configured && epx.active && epx.dev_addr == dev_addr) {
     epx.configured = false;
-    *epx.endpoint_control = 0;
-    *epx.buffer_control = 0;
+    *hwep_ctrl_reg_host(&epx)  = 0;
+    *hwbuf_ctrl_reg_host(&epx) = 0;
     hw_endpoint_reset_transfer(&epx);
   }
 
@@ -482,54 +439,41 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 
         // unconfigure the endpoint
         ep->configured = false;
-        *ep->endpoint_control = 0;
-        *ep->buffer_control = 0;
+        *hwep_ctrl_reg_host(ep)  = 0;
+        *hwbuf_ctrl_reg_host(ep) = 0;
         hw_endpoint_reset_transfer(ep);
       }
     }
   }
 }
 
-uint32_t hcd_frame_number(uint8_t rhport)
-{
-  (void) rhport;
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void)rhport;
   return usb_hw->sof_rd;
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  assert(rhport == 0);
+void hcd_int_enable(uint8_t rhport) {
+  (void)rhport;
   irq_set_enabled(USBCTRL_IRQ, true);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
-  (void) rhport;
+void hcd_int_disable(uint8_t rhport) {
+  (void)rhport;
   // todo we should check this is disabling from the correct core; note currently this is never called
-  assert(rhport == 0);
   irq_set_enabled(USBCTRL_IRQ, false);
 }
 
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
-
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc) {
+  (void)rhport;
   pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
-
-  // Allocated differently based on if it's an interrupt endpoint or not
-  struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+  hw_endpoint_t *ep = hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
   TU_ASSERT(ep);
 
-  _hw_endpoint_init(ep,
-                    dev_addr,
-                    ep_desc->bEndpointAddress,
-                    tu_edpt_packet_size(ep_desc),
-                    ep_desc->bmAttributes.xfer,
-                    ep_desc->bInterval);
+  hw_endpoint_init(ep, dev_addr, ep_desc->bEndpointAddress, tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer,
+                   ep_desc->bInterval);
 
   return true;
 }
@@ -539,13 +483,12 @@ bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
   return false; // TODO not implemented yet
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
   (void) rhport;
 
   pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
 
-  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  const uint8_t    ep_num = tu_edpt_number(ep_addr);
   tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
 
   // Get appropriate ep. Either EPX or interrupt endpoint
@@ -557,20 +500,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   assert(!ep->active);
 
   // Control endpoint can change direction 0x00 <-> 0x80
-  if ( ep_addr != ep->ep_addr )
-  {
+  if (ep_addr != ep->ep_addr) {
     assert(ep_num == 0);
 
     // Direction has flipped on endpoint control so re init it but with same properties
-    _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
+    hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, TUSB_XFER_CONTROL, 0);
   }
 
   // If a normal transfer (non-interrupt) then initiate using
   // sie ctrl registers. Otherwise, interrupt ep registers should
   // already be configured
-  if ( ep == &epx )
-  {
-    hw_endpoint_xfer_start(ep, buffer, buflen);
+  if (ep == &epx) {
+    hw_endpoint_xfer_start(ep, buffer, NULL, buflen);
 
     // That has set up buffer control, endpoint control etc
     // for host we have to initiate the transfer
@@ -585,9 +526,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS;
     busy_wait_at_least_cycles(12);
     usb_hw->sie_ctrl = flags;
-  }else
-  {
-    hw_endpoint_xfer_start(ep, buffer, buflen);
+  } else {
+    hw_endpoint_xfer_start(ep, buffer, NULL, buflen);
   }
 
   return true;
@@ -611,14 +551,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   }
 
   // Configure EP0 struct with setup info for the trans complete
-  struct hw_endpoint * ep = _hw_endpoint_allocate( (uint8_t) TUSB_XFER_CONTROL);
+  hw_endpoint_t *ep = hw_endpoint_allocate((uint8_t)TUSB_XFER_CONTROL);
   TU_ASSERT(ep);
 
   // EPX should be inactive
   assert(!ep->active);
 
   // EP0 out
-  _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
+  hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
   assert(ep->configured);
 
   ep->remaining_len = 8;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 9d0bd762d..3b65f57a4 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -35,34 +35,35 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPE
 //--------------------------------------------------------------------+
-static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep);
+static void sync_xfer(hw_endpoint_t *ep);
 
-#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-  static bool e15_is_bulkin_ep(struct hw_endpoint* ep);
-  static bool e15_is_critical_frame_period(struct hw_endpoint* ep);
-#else
-  #define e15_is_bulkin_ep(x)             (false)
-  #define e15_is_critical_frame_period(x) (false)
-#endif
-
-// if usb hardware is in host mode
-TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) {
-  return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
-}
+  #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+static bool e15_is_critical_frame_period(struct hw_endpoint *ep);
+  #else
+    #define e15_is_critical_frame_period(x) (false)
+  #endif
 
 //--------------------------------------------------------------------+
 // Implementation
 //--------------------------------------------------------------------+
 // Provide own byte by byte memcpy as not all copies are aligned
-static void unaligned_memcpy(void *dst, const void *src, size_t n) {
-  uint8_t *dst_byte = (uint8_t*)dst;
-  const uint8_t *src_byte = (const uint8_t*)src;
+static void unaligned_memcpy(uint8_t *dst, const uint8_t *src, size_t n) {
   while (n--) {
-    *dst_byte++ = *src_byte++;
+    *dst++ = *src++;
   }
 }
 
-void rp2040_usb_init(void) {
+void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, const tu_hwfifo_access_t *access_mode) {
+  (void)access_mode;
+  unaligned_memcpy((uint8_t *)(uintptr_t)hwfifo, src, len);
+}
+
+void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, const tu_hwfifo_access_t *access_mode) {
+  (void)access_mode;
+  unaligned_memcpy(dest, (const uint8_t *)(uintptr_t)hwfifo, len);
+}
+
+void rp2usb_init(void) {
   // Reset usb controller
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
@@ -93,35 +94,38 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint* ep) {
   ep->user_buf = 0;
 }
 
-void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint* ep, uint32_t and_mask,
-                                                               uint32_t or_mask) {
-  uint32_t value = 0;
+void __tusb_irq_path_func(hwbuf_ctrl_update)(io_rw_32 *buf_ctrl_reg, uint32_t and_mask, uint32_t or_mask) {
+  const bool is_host = rp2usb_is_host_mode();
+  uint32_t   value    = 0;
+  uint32_t   buf_ctrl = *buf_ctrl_reg;
 
   if (and_mask) {
-    value = *ep->buffer_control & and_mask;
+    value = buf_ctrl & and_mask;
   }
 
   if (or_mask) {
     value |= or_mask;
     if (or_mask & USB_BUF_CTRL_AVAIL) {
-      if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
-        panic("ep %02X was already available", ep->ep_addr);
+      if (buf_ctrl & USB_BUF_CTRL_AVAIL) {
+        panic("buf_ctrl @ 0x%lX already available", (uintptr_t)buf_ctrl_reg);
       }
-      *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
-      // 4.1.2.5.1 Con-current access: 12 cycles (should be good for 48*12Mhz = 576Mhz) after write to buffer control
+      *buf_ctrl_reg = value & ~USB_BUF_CTRL_AVAIL;
+
+      // Section 4.1.2.7.1 (rp2040) / 12.7.3.7.1 (rp2350) Concurrent access:  after write to buffer control, we need to
+      // wait at least 1/48 mhz (usb clock), 12 cycles should be good for 48*12Mhz = 576Mhz.
       // Don't need delay in host mode as host is in charge
-      if (!is_host_mode()) {
+      if (!is_host) {
         busy_wait_at_least_cycles(12);
       }
     }
   }
 
-  *ep->buffer_control = value;
+  *buf_ctrl_reg = value;
 }
 
-// prepare buffer, return buffer control
-static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
-  uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+// prepare buffer, move data if tx, return buffer control
+static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id, bool is_rx) {
+  const uint16_t buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
   ep->remaining_len = (uint16_t) (ep->remaining_len - buflen);
 
   uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
@@ -130,10 +134,18 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep,
   buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
   ep->next_pid ^= 1u;
 
-  if (!ep->rx) {
-    // Copy data from user buffer to hw buffer
-    unaligned_memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
-    ep->user_buf += buflen;
+  if (!is_rx) {
+    if (buflen) {
+      // Copy data from user buffer/fifo to hw buffer
+      uint8_t *hw_buf = ep->hw_data_buf + buf_id * 64;
+      if (ep->is_xfer_fifo) {
+        // not in sram, may mess up timing with E15 workaround
+        tu_hwfifo_write_from_fifo(hw_buf, ep->user_fifo, buflen, NULL);
+      } else {
+        unaligned_memcpy(hw_buf, ep->user_buf, buflen);
+        ep->user_buf += buflen;
+      }
+    }
 
     // Mark as full
     buf_ctrl |= USB_BUF_CTRL_FULL;
@@ -146,52 +158,75 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep,
     buf_ctrl |= USB_BUF_CTRL_LAST;
   }
 
-  if (buf_id) buf_ctrl = buf_ctrl << 16;
+  if (buf_id) {
+    buf_ctrl = buf_ctrl << 16;
+  }
 
   return buf_ctrl;
 }
 
 // Prepare buffer control register value
 void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep) {
-  uint32_t ep_ctrl = *ep->endpoint_control;
+  const tusb_dir_t dir = tu_edpt_dir(ep->ep_addr);
+  bool      is_rx;
+  bool      is_host = false;
+  io_rw_32 *ep_ctrl_reg;
+  io_rw_32 *buf_ctrl_reg;
+
+  #if CFG_TUH_ENABLED
+  is_host = rp2usb_is_host_mode();
+  if (is_host) {
+    buf_ctrl_reg = hwbuf_ctrl_reg_host(ep);
+    ep_ctrl_reg  = hwep_ctrl_reg_host(ep);
+    is_rx        = (dir == TUSB_DIR_IN);
+  } else
+  #endif
+  {
+    buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+    ep_ctrl_reg  = hwep_ctrl_reg_device(ep);
+    is_rx        = (dir == TUSB_DIR_OUT);
+  }
 
   // always compute and start with buffer 0
-  uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
+  uint32_t buf_ctrl = prepare_ep_buffer(ep, 0, is_rx) | USB_BUF_CTRL_SEL;
 
-  // For now: skip double buffered for OUT endpoint in Device mode, since
-  // host could send < 64 bytes and cause short packet on buffer0
-  // NOTE: this could happen to Host mode IN endpoint
-  // Also, Host mode "interrupt" endpoint hardware is only single buffered,
-  // NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
-  bool const is_host = is_host_mode();
-  bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
-                            (is_host && tu_edpt_number(ep->ep_addr) != 0);
+  // EP0 has no endpoint control register, also usbd only schedule 1 packet at a time (single buffer)
+  if (ep_ctrl_reg != NULL) {
+    uint32_t ep_ctrl = *ep_ctrl_reg;
 
-  if (ep->remaining_len && !force_single) {
-    // Use buffer 1 (double buffered) if there is still data
-    // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
+    // For now: skip double buffered for RX e.g OUT endpoint in Device mode, since host could send < 64 bytes and cause
+    // short packet on buffer0
+    // NOTE: this could happen to Host mode IN endpoint Also, Host mode "interrupt" endpoint hardware is only single
+    // buffered,
+    // NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
+    const bool force_single = (!is_host && is_rx) || (is_host && tu_edpt_number(ep->ep_addr) != 0);
 
-    buf_ctrl |= prepare_ep_buffer(ep, 1);
+    if (ep->remaining_len && !force_single) {
+      // Use buffer 1 (double buffered) if there is still data
+      // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
 
-    // Set endpoint control double buffered bit if needed
-    ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
-    ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
-  } else {
-    // Single buffered since 1 is enough
-    ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
-    ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
-  }
+      buf_ctrl |= prepare_ep_buffer(ep, 1, is_rx);
 
-  *ep->endpoint_control = ep_ctrl;
+      // Set endpoint control double buffered bit if needed
+      ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
+      ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
+    } else {
+      // Single buffered since 1 is enough
+      ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+      ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+    }
+
+    *ep_ctrl_reg = ep_ctrl;
+  }
 
   TU_LOG(3, "  Prepare BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // Finally, write to buffer_control which will trigger the transfer
   // the next time the controller polls this dpram address
-  _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
+  hwbuf_ctrl_set(buf_ctrl_reg, buf_ctrl);
 }
 
-void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t total_len) {
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, tu_fifo_t *ff, uint16_t total_len) {
   hw_endpoint_lock_update(ep, 1);
 
   if (ep->active) {
@@ -204,15 +239,25 @@ void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t to
   ep->remaining_len = total_len;
   ep->xferred_len = 0;
   ep->active = true;
-  ep->user_buf = buffer;
 
-  if (e15_is_bulkin_ep(ep)) {
+  if (ff != NULL) {
+    ep->user_fifo    = ff;
+    ep->is_xfer_fifo = true;
+  } else {
+    ep->user_buf     = buffer;
+    ep->is_xfer_fifo = false;
+  }
+
+  #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  if (ep->e15_bulk_in) {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
   }
 
   if (e15_is_critical_frame_period(ep)) {
-    ep->pending = 1;
-  } else {
+    ep->pending = 1; // skip transfer if we are in critical frame period
+  } else
+  #endif
+  {
     hw_endpoint_start_next_buffer(ep);
   }
 
@@ -220,31 +265,37 @@ void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t to
 }
 
 // sync endpoint buffer and return transferred bytes
-static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
-  uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  if (buf_id) buf_ctrl = buf_ctrl >> 16;
+static uint16_t __tusb_irq_path_func(sync_ep_buffer)(hw_endpoint_t *ep, io_rw_32 *buf_ctrl_reg, uint8_t buf_id,
+                                                     bool is_rx) {
+  uint32_t buf_ctrl = *buf_ctrl_reg;
+  if (buf_id) {
+    buf_ctrl = buf_ctrl >> 16;
+  }
 
-  uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
+  const uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
 
-  if (!ep->rx) {
+  if (!is_rx) {
     // We are continuing a transfer here. If we are TX, we have successfully
     // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
-
-    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
   } else {
     // If we have received some data, so can increase the length
     // we have received AFTER we have copied it to the user buffer at the appropriate offset
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
-    unaligned_memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
-    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
-    ep->user_buf += xferred_bytes;
+    uint8_t *hw_buf = ep->hw_data_buf + buf_id * 64;
+    if (ep->is_xfer_fifo) {
+      // not in sram, may mess up timing with E15 workaround
+      tu_hwfifo_read_to_fifo(hw_buf, ep->user_fifo, xferred_bytes, NULL);
+    } else {
+      unaligned_memcpy(ep->user_buf, hw_buf, xferred_bytes);
+      ep->user_buf += xferred_bytes;
+    }
   }
+  ep->xferred_len += xferred_bytes;
 
   // Short packet
   if (xferred_bytes < ep->wMaxPacketSize) {
-    pico_trace("  Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
@@ -252,21 +303,38 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uin
   return xferred_bytes;
 }
 
-static void __tusb_irq_path_func(_hw_endpoint_xfer_sync)(struct hw_endpoint* ep) {
-  // Update hw endpoint struct with info from hardware
-  // after a buff status interrupt
+// Update hw endpoint struct with info from hardware after a buff status interrupt
+static void __tusb_irq_path_func(sync_xfer)(hw_endpoint_t *ep) {
+  // const uint8_t    ep_num  = tu_edpt_number(ep->ep_addr);
+  const tusb_dir_t dir     = tu_edpt_dir(ep->ep_addr);
 
-  uint32_t __unused buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+  io_rw_32 *buf_ctrl_reg;
+  io_rw_32 *ep_ctrl_reg;
+  bool      is_rx;
 
-  // always sync buffer 0
-  uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
+  #if CFG_TUH_ENABLED
+  const bool is_host = rp2usb_is_host_mode();
+  if (is_host) {
+    buf_ctrl_reg = hwbuf_ctrl_reg_host(ep);
+    ep_ctrl_reg  = hwep_ctrl_reg_host(ep);
+    is_rx        = (dir == TUSB_DIR_IN);
+  } else
+  #endif
+  {
+    buf_ctrl_reg = hwbuf_ctrl_reg_device(ep);
+    ep_ctrl_reg  = hwep_ctrl_reg_device(ep);
+    is_rx        = (dir == TUSB_DIR_OUT);
+  }
+
+  TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(*buf_ctrl_reg),
+         tu_u32_high16(*buf_ctrl_reg));
+  uint16_t buf0_bytes = sync_ep_buffer(ep, buf_ctrl_reg, 0, is_rx); // always sync buffer 0
 
   // sync buffer 1 if double buffered
-  if ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) {
+  if (ep_ctrl_reg != NULL && (*ep_ctrl_reg) & EP_CTRL_DOUBLE_BUFFERED_BITS) {
     if (buf0_bytes == ep->wMaxPacketSize) {
       // sync buffer 1 if not short packet
-      sync_ep_buffer(ep, 1);
+      sync_ep_buffer(ep, buf_ctrl_reg, 1, is_rx);
     } else {
       // short packet on buffer 0
       // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example
@@ -287,7 +355,8 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync)(struct hw_endpoint* ep)
       ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
       ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
 
-      _hw_endpoint_buffer_control_set_value32(ep, 0);
+      io_rw_32 *buf_ctrl_reg = is_host ? hwbuf_ctrl_reg_host(ep) : hwbuf_ctrl_reg_device(ep);
+      hwbuf_ctrl_set(buf_ctrl_reg, 0);
 
       usb_hw->abort &= ~TU_BIT(ep_id);
 
@@ -307,8 +376,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
     panic("Can't continue xfer on inactive ep %02X", ep->ep_addr);
   }
 
-  // Update EP struct from hardware state
-  _hw_endpoint_xfer_sync(ep);
+  sync_xfer(ep); // Update EP struct from hardware state
 
   // Now we have synced our state with the hardware. Is there more data to transfer?
   // If we are done then notify tinyusb
@@ -318,9 +386,12 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
     hw_endpoint_lock_update(ep, -1);
     return true;
   } else {
+  #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
     if (e15_is_critical_frame_period(ep)) {
       ep->pending = 1;
-    } else {
+    } else
+  #endif
+    {
       hw_endpoint_start_next_buffer(ep);
     }
   }
@@ -335,6 +406,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
 //--------------------------------------------------------------------+
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+// E15 is fixed with RP2350
 
 /* Don't mark IN buffers as available during the last 200us of a full-speed
    frame. This avoids a situation seen with the USB2.0 hub on a Raspberry
@@ -354,16 +426,12 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
 
 volatile uint32_t e15_last_sof = 0;
 
-// check if Errata 15 is needed for this endpoint i.e device bulk-in
-static bool __tusb_irq_path_func(e15_is_bulkin_ep)(struct hw_endpoint* ep) {
-  return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
-          ep->transfer_type == TUSB_XFER_BULK);
-}
-
 // check if we need to apply Errata 15 workaround : i.e
 // Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
 static bool __tusb_irq_path_func(e15_is_critical_frame_period)(struct hw_endpoint* ep) {
-  TU_VERIFY(e15_is_bulkin_ep(ep));
+  if (!ep->e15_bulk_in) {
+    return false;
+  }
 
   /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
    * The device state machine cannot recover from receiving an incorrect PID
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index d4d29a816..c03dc34b2 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -1,29 +1,44 @@
 #ifndef RP2040_COMMON_H_
 #define RP2040_COMMON_H_
 
-#if defined(RP2040_USB_HOST_MODE) && defined(RP2040_USB_DEVICE_MODE)
-#error TinyUSB device and host mode not supported at the same time
-#endif
-
-#include "common/tusb_common.h"
-
 #include "pico.h"
 #include "hardware/structs/usb.h"
 #include "hardware/irq.h"
 #include "hardware/resets.h"
 #include "hardware/timer.h"
 
-#if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX)
-#define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
+#include "common/tusb_common.h"
+#include "osal/osal.h"
+#include "common/tusb_fifo.h"
+
+#if defined(RP2040_USB_HOST_MODE) && defined(RP2040_USB_DEVICE_MODE)
+  #error TinyUSB device and host mode not supported at the same time
+#endif
+
+// E5 and E15 only apply to RP2040
+#if defined(PICO_RP2040) && PICO_RP2040 == 1
+  // RP2040 E5: USB device fails to exit RESET state on busy USB bus.
+  #if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX)
+    #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
+  #endif
+
+  // RP2040 E15: USB Device controller will hang if certain bus errors occur during an IN transfer.
+  #if defined(PICO_RP2040_USB_DEVICE_UFRAME_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX)
+    #define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX PICO_RP2040_USB_DEVICE_UFRAME_FIX
+  #endif
+#endif
+
+#ifndef TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
+  #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX 0
 #endif
 
-#if defined(PICO_RP2040_USB_DEVICE_UFRAME_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX)
-#define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX PICO_RP2040_USB_DEVICE_UFRAME_FIX
+#ifndef TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  #define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX 0
 #endif
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-#undef PICO_RP2040_USB_FAST_IRQ
-#define PICO_RP2040_USB_FAST_IRQ 1
+  #undef PICO_RP2040_USB_FAST_IRQ
+  #define PICO_RP2040_USB_FAST_IRQ 1
 #endif
 
 #ifndef PICO_RP2040_USB_FAST_IRQ
@@ -36,6 +51,9 @@
 #define __tusb_irq_path_func(x) x
 #endif
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 #define usb_hw_set    ((usb_hw_t *) hw_set_alias_untyped(usb_hw))
 #define usb_hw_clear  ((usb_hw_t *) hw_clear_alias_untyped(usb_hw))
 
@@ -43,63 +61,48 @@
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)
 
 // Hardware information per endpoint
-typedef struct hw_endpoint
-{
-    // Is this a valid struct
-    bool configured;
-
-    // Transfer direction (i.e. IN is rx for host but tx for device)
-    // allows us to common up transfer functions
-    bool rx;
-
-    uint8_t ep_addr;
-    uint8_t next_pid;
-
-    // Endpoint control register
-    io_rw_32 *endpoint_control;
-
-    // Buffer control register
-    io_rw_32 *buffer_control;
-
-    // Buffer pointer in usb dpram
-    uint8_t *hw_data_buf;
-
-    // User buffer in main memory
-    uint8_t *user_buf;
-
-    // Current transfer information
-    uint16_t remaining_len;
-    uint16_t xferred_len;
+typedef struct hw_endpoint {
+  uint8_t ep_addr;
+  uint8_t next_pid;
+  bool    active;       // transferring data
+  bool    is_xfer_fifo; // transfer using fifo
 
-    // Data needed from EP descriptor
-    uint16_t wMaxPacketSize;
-
-    // Endpoint is in use
-    bool active;
-
-    // Interrupt, bulk, etc
-    uint8_t transfer_type;
-
-    // Transfer scheduled but not active
-    uint8_t pending;
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  bool    e15_bulk_in; // Errata15 device bulk in
+  uint8_t pending;     // Transfer scheduled but not active
+#endif
 
 #if CFG_TUH_ENABLED
-    // Only needed for host
-    uint8_t dev_addr;
-
-    // If interrupt endpoint
-    uint8_t interrupt_num;
+  bool    configured;    // Is this a valid struct
+  uint8_t dev_addr;
+  uint8_t interrupt_num; // for host interrupt endpoints
 #endif
 
+  uint16_t wMaxPacketSize;
+  uint8_t *hw_data_buf; // Buffer pointer in usb dpram
+
+  // transfer info
+  union {
+    uint8_t   *user_buf; // User buffer in main memory
+    tu_fifo_t *user_fifo;
+  };
+  uint16_t remaining_len;
+  uint16_t xferred_len;
+
 } hw_endpoint_t;
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
 extern volatile uint32_t e15_last_sof;
 #endif
 
-void rp2040_usb_init(void);
+void rp2usb_init(void);
+
+// if usb hardware is in host mode
+TU_ATTR_ALWAYS_INLINE static inline bool rp2usb_is_host_mode(void) {
+  return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
+}
 
-void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, tu_fifo_t *ff, uint16_t total_len);
 bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
 void hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
@@ -110,34 +113,60 @@ TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_lock_update(__unused struct
   //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
 }
 
-void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
+// #if CFG_TUD_ENABLED
+TU_ATTR_ALWAYS_INLINE static inline io_rw_32 *hwep_ctrl_reg_device(struct hw_endpoint *ep) {
+  uint8_t const epnum = tu_edpt_number(ep->ep_addr);
+  const uint8_t dir   = (uint8_t)tu_edpt_dir(ep->ep_addr);
+  if (epnum == 0) {
+    // EP0 has no endpoint control register because the buffer offsets are fixed and always enabled
+    return NULL;
+  }
+  return (dir == TUSB_DIR_IN) ? &usb_dpram->ep_ctrl[epnum - 1].in : &usb_dpram->ep_ctrl[epnum - 1].out;
+}
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep)
-{
-  return *ep->buffer_control;
+TU_ATTR_ALWAYS_INLINE static inline io_rw_32 *hwbuf_ctrl_reg_device(struct hw_endpoint *ep) {
+  const uint8_t epnum = tu_edpt_number(ep->ep_addr);
+  const uint8_t dir   = (uint8_t)tu_edpt_dir(ep->ep_addr);
+  return (dir == TUSB_DIR_IN) ? &usb_dpram->ep_buf_ctrl[epnum].in : &usb_dpram->ep_buf_ctrl[epnum].out;
 }
+// #endif
 
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value)
-{
-  _hw_endpoint_buffer_control_update32(ep, 0, value);
+#if CFG_TUH_ENABLED
+TU_ATTR_ALWAYS_INLINE static inline io_rw_32 *hwep_ctrl_reg_host(struct hw_endpoint *ep) {
+  if (tu_edpt_number(ep->ep_addr) == 0) {
+    return &usbh_dpram->epx_ctrl;
+  }
+  return &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value)
-{
-  _hw_endpoint_buffer_control_update32(ep, ~value, value);
+TU_ATTR_ALWAYS_INLINE static inline io_rw_32 *hwbuf_ctrl_reg_host(struct hw_endpoint *ep) {
+  if (tu_edpt_number(ep->ep_addr) == 0) {
+    return &usbh_dpram->epx_buf_ctrl;
+  }
+  return &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
 }
+#endif
 
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value)
-{
-  _hw_endpoint_buffer_control_update32(ep, ~value, 0);
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+void hwbuf_ctrl_update(io_rw_32 *buf_ctrl_reg, uint32_t and_mask, uint32_t or_mask);
+
+TU_ATTR_ALWAYS_INLINE static inline void hwbuf_ctrl_set(io_rw_32 *buf_ctrl_reg, uint32_t value) {
+  hwbuf_ctrl_update(buf_ctrl_reg, 0, value);
 }
 
-static inline uintptr_t hw_data_offset (uint8_t *buf)
-{
-  // Remove usb base from buffer pointer
-  return (uintptr_t) buf ^ (uintptr_t) usb_dpram;
+TU_ATTR_ALWAYS_INLINE static inline void hwbuf_ctrl_set_mask(io_rw_32 *buf_ctrl_reg, uint32_t value) {
+  hwbuf_ctrl_update(buf_ctrl_reg, ~value, value);
 }
 
-extern const char *ep_dir_string[];
+TU_ATTR_ALWAYS_INLINE static inline void hwbuf_ctrl_clear_mask(io_rw_32 *buf_ctrl_reg, uint32_t value) {
+  hwbuf_ctrl_update(buf_ctrl_reg, ~value, 0);
+}
+
+static inline uintptr_t hw_data_offset(uint8_t *buf) {
+  // Remove usb base from buffer pointer
+  return (uintptr_t)buf ^ (uintptr_t)usb_dpram;
+}
 
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 22a9e4af8..a6abc6244 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -833,7 +833,7 @@ void dcd_int_disable(uint8_t rhport) {
   fsdev_int_disable(rhport);
 }
 
-  #if defined(USB_BCDR_DPPU) || defined(SYSCFG_PMC_USB_PU)
+  #if defined(USB_BCDR_DPPU) || defined(SYSCFG_PMC_USB_PU) || defined(EXTEN_USBD_PU_EN)
 void dcd_connect(uint8_t rhport) {
   fsdev_connect(rhport);
 }
diff --git a/src/portable/st/stm32_fsdev/fsdev_common.h b/src/portable/st/stm32_fsdev/fsdev_common.h
index c53e345b0..b749a92ff 100644
--- a/src/portable/st/stm32_fsdev/fsdev_common.h
+++ b/src/portable/st/stm32_fsdev/fsdev_common.h
@@ -63,23 +63,21 @@ TU_VERIFY_STATIC(FSDEV_BTABLE_BASE % 8 == 0, "BTABLE base must be aligned to 8 b
 
 // CFG_TUSB_FSDEV_PMA_SIZE is PMA buffer size in bytes.
 // - 512-byte devices, access with a stride of two words (use every other 16-bit address)
-// - 1024-byte devices, access with a stride of one word (use every 16-bit address)
+// - 1024-byte devices, access with a stride of one word (use every 16-bit address) or 32-bit address
 // - 2048-byte devices, access with 32-bit address
-
-// For purposes of accessing the packet
-#if CFG_TUSB_FSDEV_PMA_SIZE == 512
-  // 1x16 bit / word access scheme
-  #define FSDEV_PMA_STRIDE  2
-  #define pma_access_scheme TU_ATTR_ALIGNED(4)
-#elif CFG_TUSB_FSDEV_PMA_SIZE == 1024
-  // 2x16 bit / word access scheme
-  #define FSDEV_PMA_STRIDE 1
-  #define pma_access_scheme
-#elif CFG_TUSB_FSDEV_PMA_SIZE == 2048
+#if CFG_TUSB_FSDEV_PMA_SIZE == 2048 || TU_CHECK_MCU(OPT_MCU_STM32U0)
   // 32 bit access scheme
   #define FSDEV_BUS_32BIT
   #define FSDEV_PMA_STRIDE 1
   #define pma_access_scheme
+#elif CFG_TUSB_FSDEV_PMA_SIZE == 1024
+  // 2x16 bit / word access scheme
+  #define FSDEV_PMA_STRIDE 1
+  #define pma_access_scheme
+#elif CFG_TUSB_FSDEV_PMA_SIZE == 512
+  // 1x16 bit / word access scheme
+  #define FSDEV_PMA_STRIDE  2
+  #define pma_access_scheme TU_ATTR_ALIGNED(4)
 #endif
 
 // The fsdev_bus_t type can be used for both register and PMA access necessities
diff --git a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c
index acdeccf6d..1813ef70b 100644
--- a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c
@@ -223,9 +223,13 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
+  // Clear pending interrupts
+  // Normally no interrupts should be pending here since we just reset the core,
+  // but device mode suspend needs to cleared by WKUP flag
+  FSDEV_REG->ISTR = 0;
+
   // Enable interrupts for host mode
-  FSDEV_REG->CNTR |= USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SOFM | USB_CNTR_SUSPM |
-                     USB_CNTR_WKUPM | USB_CNTR_ERRM | USB_CNTR_PMAOVRM;
+  FSDEV_REG->CNTR |= USB_CNTR_DCON | USB_CNTR_CTRM | USB_CNTR_SOFM | USB_CNTR_ERRM | USB_CNTR_PMAOVRM;
 
   // Initialize port state
   _hcd_data.connected = false;
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index b413121a5..9fac0bc1c 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -36,9 +36,6 @@
 #include <device/dcd.h>
 #include "musb_def.h"
 
-//#include "bsp/board_api.h"
-extern uint32_t board_millis(void); // TODO remove
-
 typedef uint32_t u32;
 typedef uint16_t u16;
 typedef uint8_t u8;
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 44f7137f9..8685ec6dc 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -77,9 +77,7 @@ CFG_TUD_MEM_SECTION static struct {
   TUD_EPBUF_DEF(setup_packet, 8);
 } _dcd_usbbuf;
 
-static tud_configure_dwc2_t _tud_cfg = {
-  .bm_double_buffered = 0
-};
+static tud_configure_dwc2_t _tud_cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
   #if TU_CHECK_MCU(OPT_MCU_GD32VF103)
@@ -444,14 +442,14 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   tu_memclr(&_dcd_data, sizeof(_dcd_data));
 
   // Core Initialization
-  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
+  const bool is_hs_phy = dwc2_core_is_highspeed_phy(dwc2, TUD_OPT_HIGH_SPEED);
   const bool is_dma = dma_device_enabled(dwc2);
-  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+  TU_ASSERT(dwc2_core_init(rhport, is_hs_phy, is_dma));
 
   //------------- 7.1 Device Initialization -------------//
   // Set device max speed
   uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
-  if (is_highspeed) {
+  if (is_hs_phy) {
     // dcfg Highspeed's mask is 0
 
     // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
@@ -472,13 +470,16 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   // Force device mode
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
-  // Clear A override, force B Valid
-  dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+  // OTG Ctrl
+  uint32_t gotgctl = dwc2->gotgctl & ~GOTGCTL_AVALOEN; // Clear A-override
+  if (!_tud_cfg.vbus_sensing) {
+    gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;     // force B Valid if not sensing VBus
+  }
+  dwc2->gotgctl = gotgctl;
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32N6
-  // No hardware detection of Vbus B-session is available on the STM32N6
-  dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
-#endif
+  #ifdef TUP_USBIP_DWC2_STM32
+  dwc2_stm32_gccfg_cfg(dwc2, _tud_cfg.vbus_sensing, false);
+  #endif
 
   // Enable required interrupts
   dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
@@ -491,6 +492,12 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   return true;
 }
 
+bool dcd_deinit(uint8_t rhport) {
+  dcd_disconnect(rhport);
+  dwc2_core_deinit(rhport);
+  return true;
+}
+
 void dcd_int_enable(uint8_t rhport) {
   dwc2_dcd_int_enable(rhport);
 }
@@ -526,34 +533,38 @@ void dcd_remote_wakeup(uint8_t rhport) {
 }
 
 void dcd_connect(uint8_t rhport) {
-  (void) rhport;
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
 #ifdef TUP_USBIP_DWC2_ESP32
-  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
-  conf.pad_pull_override = 0;
-  conf.dp_pullup = 0;
-  conf.dp_pulldown = 0;
-  conf.dm_pullup = 0;
-  conf.dm_pulldown = 0;
-  USB_WRAP.otg_conf = conf;
+  // On ESP32-P4 HS PHY, do not write to USB_WRAP register which belongs to FS PHY
+  if (rhport == 0) {
+    usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+    conf.pad_pull_override = 0;
+    conf.dp_pullup = 0;
+    conf.dp_pulldown = 0;
+    conf.dm_pullup = 0;
+    conf.dm_pulldown = 0;
+    USB_WRAP.otg_conf = conf;
+  }
 #endif
 
   dwc2->dctl &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport) {
-  (void) rhport;
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
 #ifdef TUP_USBIP_DWC2_ESP32
-  usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
-  conf.pad_pull_override = 1;
-  conf.dp_pullup = 0;
-  conf.dp_pulldown = 1;
-  conf.dm_pullup = 0;
-  conf.dm_pulldown = 1;
-  USB_WRAP.otg_conf = conf;
+  // On ESP32-P4 HS PHY, do not write to USB_WRAP register which belongs to FS PHY
+  if (rhport == 0) {
+    usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+    conf.pad_pull_override = 1;
+    conf.dp_pullup = 0;
+    conf.dp_pulldown = 1;
+    conf.dm_pullup = 0;
+    conf.dm_pulldown = 1;
+    USB_WRAP.otg_conf = conf;
+  }
 #endif
 
   dwc2->dctl |= DCTL_SDIS;
@@ -780,7 +791,7 @@ static void handle_bus_reset(uint8_t rhport) {
     dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
   }
 
-  dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
+  dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_OEPINT | GINTMSK_IEPINT | GINTMSK_IISOIXFRM;
 }
 
 static void handle_enum_done(uint8_t rhport) {
@@ -1180,6 +1191,7 @@ void dcd_int_handler(uint8_t rhport) {
     const uint32_t otg_int = dwc2->gotgint;
 
     if (otg_int & GOTGINT_SEDET) {
+      dwc2->gintmsk &= ~GINTMSK_OTGINT;
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h
index 513495eb1..fa6d10c12 100644
--- a/src/portable/synopsys/dwc2/dwc2_at32.h
+++ b/src/portable/synopsys/dwc2/dwc2_at32.h
@@ -61,6 +61,11 @@
   #define OTG1_FIFO_SIZE           1280
   #define OTG1_IRQn                OTGFS1_IRQn
   #define DWC2_OTG1_REG_BASE       0x50000000UL
+#elif CFG_TUSB_MCU == OPT_MCU_AT32F45X
+  #include <at32f45x.h>
+  #define OTG1_FIFO_SIZE           1280
+  #define OTG1_IRQn                OTGFS1_IRQn
+  #define DWC2_OTG1_REG_BASE       0x50000000UL
 #endif
 
 #ifdef __cplusplus
@@ -107,6 +112,12 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_
   }
 }
 
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
+  (void) hs_phy_type;
+  dwc2->stm32_gccfg &= ~(STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN);
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
   (void) dwc2;
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index df6d4a852..00842bba2 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -73,6 +73,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   // nothing to do
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index a7e6188df..33eabaeab 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -39,14 +39,11 @@ static void reset_core(dwc2_regs_t* dwc2) {
   while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {
   }
 
-  // load gsnpsid (it is not readable after reset is asserted)
-  const uint32_t gsnpsid = dwc2->gsnpsid;
-
-  // reset core
-  dwc2->grstctl |= GRSTCTL_CSRST;
+  const uint32_t gsnpsid = dwc2->gsnpsid; // preload gsnpsid which is not readable while resetting
+  dwc2->grstctl |= GRSTCTL_CSRST; // reset core
 
   if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
-    // prior v4.20a: CSRST is self-clearing and the core clears this bit after all the necessary logic is reset in
+    // prior v4.20a: CSRST is self-clearing, and the core clears this bit after all the necessary logic is reset in
     // the core, which can take several clocks, depending on the current state of the core. Once this bit has been
     // cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay).
     while (dwc2->grstctl & GRSTCTL_CSRST) {}
@@ -60,6 +57,7 @@ static void reset_core(dwc2_regs_t* dwc2) {
   while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE
 }
 
+// Dedicated FS PHY is internal with a clock 48Mhz.
 static void phy_fs_init(dwc2_regs_t* dwc2) {
   TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
 
@@ -86,6 +84,12 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
   dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
 }
 
+/* dwc2 has 2 highspeed PHYs options
+ * - UTMI+ is internal highspeed PHY, can be clocked at 30 Mhz (8-bit) or 60 Mhz (16-bit).
+ * - ULPI is external highspeed PHY, clocked at 60Mhz with 8-bit interface.
+ *
+ * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
+ */
 static void phy_hs_init(dwc2_regs_t* dwc2) {
   uint32_t gusbcfg = dwc2->gusbcfg;
   const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
@@ -179,32 +183,20 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
 //--------------------------------------------------------------------
 //
 //--------------------------------------------------------------------
-bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
-  (void)dwc2;
-#if CFG_TUD_ENABLED
-  if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
-    return false;
-  }
-#endif
-#if CFG_TUH_ENABLED
-  if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
-    return false;
-  }
-#endif
+bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy) {
+  const dwc2_ghwcfg2_t ghwcfg2    = {.value = dwc2->ghwcfg2};
+  const bool           has_hs_phy = (ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED);
 
-  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
-  return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
+  if (prefer_hs_phy) {
+    return has_hs_phy;
+  } else {
+    const bool has_fs_phy = (ghwcfg2.fs_phy_type != GHWCFG2_FSPHY_NOT_SUPPORTED);
+    // false if has fs phy, otherwise true since hs phy is the only available phy
+    return !has_fs_phy && has_hs_phy;
+  }
 }
 
-/* dwc2 has several PHYs option
- * - UTMI+ is internal highspeed PHY, clock can be 30 Mhz (8-bit) or 60 Mhz (16-bit)
- * - ULPI is external highspeed PHY, clock is 60Mhz with only 8-bit interface
- * - Dedicated FS PHY is internal with clock 48Mhz.
- *
- * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
- *
-*/
-bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
+bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // Check Synopsys ID register, failed if controller clock/power is not enabled
@@ -213,7 +205,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
   // disable global interrupt
   dwc2->gahbcfg &= ~GAHBCFG_GINT;
 
-  if (is_highspeed) {
+  if (is_hs_phy) {
     phy_hs_init(dwc2);
   } else {
     phy_fs_init(dwc2);
@@ -251,6 +243,24 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
   return true;
 }
 
+void dwc2_core_deinit(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Disable global interrupt
+  dwc2->gahbcfg &= ~GAHBCFG_GINT;
+
+  // Reset core: this also flushes FIFOs and clears all interrupt registers
+  reset_core(dwc2);
+
+  // Stop PHY clock and gate HCLK for power saving (per databook chapter 14)
+  dwc2->pcgcctl |= PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK;
+
+  // MCU-specific PHY deinit (disable PHY power)
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  const uint8_t hs_phy_type = (dwc2->gusbcfg & GUSBCFG_PHYSEL) ? GHWCFG2_HSPHY_NOT_SUPPORTED : ghwcfg2.hs_phy_type;
+  dwc2_phy_deinit(dwc2, hs_phy_type);
+}
+
 // void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) {
 //   (void) in_isr;
 //   dwc2_regs_t * const dwc2 = DWC2_REG(rhport);
diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h
index 428304ba9..9f28ab2e0 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.h
+++ b/src/portable/synopsys/dwc2/dwc2_common.h
@@ -42,6 +42,7 @@
 // - _dwc2_controller[]: array of controllers
 // - DWC2_EP_MAX: largest EP counts of all controllers
 // - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+// - dwc2_phy_deinit(dwc2, hs_phy_type): phy deinit to disable PHY power, only deinit the phy used by core
 // - dwc2_dcd_int_enable/dwc2_dcd_int_disable
 // - dwc2_remote_wakeup_delay
 
@@ -84,8 +85,10 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
   return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
 }
 
-bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role);
-bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma);
+// check if highspeed phy should be used
+bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy);
+bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma);
+void dwc2_core_deinit(uint8_t rhport);
 void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr);
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h
index 0e3570cbb..e1cb7c769 100644
--- a/src/portable/synopsys/dwc2/dwc2_efm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_efm32.h
@@ -72,6 +72,14 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   USB->ROUTE = USB_ROUTE_PHYPEN;
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // Disable PHY pin
+  USB->ROUTE = 0;
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index a4e0d1770..ff9f216bd 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -121,6 +121,13 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
 
 }
 
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+  // PHY managed by ESP-IDF
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 0375fffe4..ccbf93a76 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -85,6 +85,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   // nothing to do
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index f655e4dba..f83007b8c 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -1,58 +1,58 @@
-|                            | AT32 F405 FS   | AT32 F405 HS   | AT32 F415   | BCM2711 (Pi4)   | EFM32GG      | ESP32-S2/S3   | ESP32-P4     | nRF54        | ST F207/F407/411/429 FS   | ST F407/429 HS   | ST F412/76x FS   | ST F723/L4P5 FS   | ST F723 HS   | ST F76x HS   | ST H743/H750   | ST L476 FS   | ST U5A5/H7RS/N6 HS   | XMC4500      | GD32VF103   |
-|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------|
-| GUID                       | 0x00002000     | 0x00000000     | 0x00001000  | 0x2708A000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00000000   | 0x00001200                | 0x00001100       | 0x00002000       | 0x00003000        | 0x00003100   | 0x00002100   | 0x00002300     | 0x00002000   | 0x00005000           | 0x00AEC000   | 0x00001000  |
-| GSNPSID                    | 0x4F54400A     | 0x4F54400A     | 0x4F54400A  | 0x4F54280A      | 0x4F54330A   | 0x4F54400A    | 0x4F54400A   | 0x4F54430A   | 0x4F54281A                | 0x4F54281A       | 0x4F54320A       | 0x4F54330A        | 0x4F54330A   | 0x4F54320A   | 0x4F54330A     | 0x4F54310A   | 0x4F54411A           | 0x4F54292A   | 0x00000000  |
-| - specs version            | 4.00a          | 4.00a          | 4.00a       | 2.80a           | 3.30a        | 4.00a         | 4.00a        | 4.30a        | 2.81a                     | 2.81a            | 3.20a            | 3.30a             | 3.30a        | 3.20a        | 3.30a          | 3.10a        | 4.11a                | 2.92a        | 0.00W       |
-| GHWCFG1                    | 0x00000000     | 0x00000000     | 0x00000000  | 0x00000000      | 0x00000000   | 0x00000000    | 0x00000000   | 0xAA555000   | 0x00000000                | 0x00000000       | 0x00000000       | 0x00000000        | 0x00000000   | 0x00000000   | 0x00000000     | 0x00000000   | 0x00000000           | 0x00000000   | 0x00000000  |
-| GHWCFG2                    | 0x228FDD00     | 0x229FDDD0     | 0x228DCD00  | 0x228DDD50      | 0x228F5910   | 0x224DD930    | 0x215FFFD0   | 0x228BFC72   | 0x229DCD20                | 0x229ED590       | 0x229ED520       | 0x229ED520        | 0x229FE1D0   | 0x229FE190   | 0x229FE190     | 0x229ED520   | 0x228FE052           | 0x228F5930   | 0x00000000  |
-| - op_mode                  | HNP SRP        | HNP SRP        | HNP SRP     | HNP SRP         | HNP SRP      | HNP SRP       | HNP SRP      | noHNP noSRP  | HNP SRP                   | HNP SRP          | HNP SRP          | HNP SRP           | HNP SRP      | HNP SRP      | HNP SRP        | HNP SRP      | noHNP noSRP          | HNP SRP      | HNP SRP     |
-| - arch                     | Slave only     | DMA internal   | Slave only  | DMA internal    | DMA internal | DMA internal  | DMA internal | DMA internal | Slave only                | DMA internal     | Slave only       | Slave only        | DMA internal | DMA internal | DMA internal   | Slave only   | DMA internal         | DMA internal | Slave only  |
-| - single_point             | hub            | hub            | hub         | hub             | hub          | n/a           | hub          | n/a          | n/a                       | hub              | n/a              | n/a               | hub          | hub          | hub            | n/a          | hub                  | n/a          | hub         |
-| - hs_phy_type              | n/a            | UTMI+/ULPI     | n/a         | UTMI+           | n/a          | n/a           | UTMI+/ULPI   | UTMI+        | n/a                       | ULPI             | n/a              | n/a               | UTMI+/ULPI   | ULPI         | ULPI           | n/a          | UTMI+                | n/a          | n/a         |
-| - fs_phy_type              | Dedicated      | Dedicated      | Dedicated   | Dedicated       | Dedicated    | Dedicated     | Shared ULPI  | n/a          | Dedicated                 | Dedicated        | Dedicated        | Dedicated         | Dedicated    | Dedicated    | Dedicated      | Dedicated    | n/a                  | Dedicated    | n/a         |
-| - num_dev_ep               | 7              | 7              | 3           | 7               | 6            | 6             | 15           | 15           | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8                    | 6            | 0           |
-| - num_host_ch              | 15             | 15             | 7           | 7               | 13           | 7             | 15           | 15           | 7                         | 11               | 11               | 11                | 15           | 15           | 15             | 11           | 15                   | 13           | 0           |
-| - period_channel_support   | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - enable_dynamic_fifo      | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - mul_proc_intrpt          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - reserved21               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - nptx_q_depth             | 8              | 8              | 8           | 8               | 8            | 4             | 4            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 2           |
-| - ptx_q_depth              | 8              | 8              | 8           | 8               | 8            | 8             | 4            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 2           |
-| - token_q_depth            | 8              | 8              | 8           | 8               | 8            | 8             | 8            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 8            | 0           |
-| - otg_enable_ic_usb        | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| GHWCFG3                    | 0x020004E8     | 0x03F006E8     | 0x020004E8  | 0x0FF000E8      | 0x01F204E8   | 0x00C804B5    | 0x03805EB5   | 0x0BEAC0E8   | 0x020001E8                | 0x03F403E8       | 0x0200D1E8       | 0x0200D1E8        | 0x03EED2E8   | 0x03EED2E8   | 0x03B8D2E8     | 0x0200D1E8   | 0x03B882E8           | 0x027A01E5   | 0x00000000  |
-| - xfer_size_width          | 8              | 8              | 8           | 8               | 8            | 5             | 5            | 8            | 8                         | 8                | 8                | 8                 | 8            | 8            | 8              | 8            | 8                    | 5            | 0           |
-| - packet_size_width        | 6              | 6              | 6           | 6               | 6            | 3             | 3            | 6            | 6                         | 6                | 6                | 6                 | 6            | 6            | 6              | 6            | 6                    | 6            | 0           |
-| - otg_enable               | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - i2c_enable               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 1                         | 1                | 1                | 1                 | 0            | 0            | 0              | 1            | 0                    | 1            | 0           |
-| - vendor_ctrl_itf          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 1                | 0                | 0                 | 1            | 1            | 1              | 0            | 1                    | 0            | 0           |
-| - optional_feature_removed | 1              | 1              | 1           | 0               | 1            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - synch_reset              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - otg_adp_support          | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - otg_enable_hsic          | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - battery_charger_support  | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 0            | 0           |
-| - lpm_mode                 | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 0            | 0           |
-| - dfifo_depth              | 512            | 1008           | 512         | 4080            | 498          | 200           | 896          | 3050         | 512                       | 1012             | 512              | 512               | 1006         | 1006         | 952            | 512          | 952                  | 634          | 0           |
-| GHWCFG4                    | 0x1FF0A020     | 0x1FF0A020     | 0x0000000F  | 0x1FF00020      | 0x1BF08030   | 0xD3F0A030    | 0xDFF1A030   | 0x1E10AA60   | 0x0FF08030                | 0x17F00030       | 0x17F08030       | 0x17F08030        | 0x23F00030   | 0x23F00030   | 0xE3F00030     | 0x17F08030   | 0xE2103E30           | 0xDBF08030   | 0x00000000  |
-| - num_dev_period_in_ep     | 0              | 0              | 15          | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - partial_powerdown        | 0              | 0              | 0           | 0               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - ahb_freq_min             | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - hibernation              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - extended_hibernation     | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - reserved8                | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - enhanced_lpm_support1    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - service_interval_flow    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - ipg_isoc_support         | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - acg_support              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - enhanced_lpm_support     | 1              | 1              | 0           | 0               | 0            | 1             | 1            | 1            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 1                    | 0            | 0           |
-| - phy_data_width           | 8/16 bit       | 8/16 bit       | 8 bit       | 8 bit           | 8/16 bit     | 8/16 bit      | 8/16 bit     | 8/16 bit     | 8/16 bit                  | 8 bit            | 8/16 bit         | 8/16 bit          | 8 bit        | 8 bit        | 8 bit          | 8/16 bit     | 8 bit                | 8/16 bit     | 8 bit       |
-| - ctrl_ep_num              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 0              | 0            | 0                    | 0            | 0           |
-| - iddg_filter              | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - vbus_valid_filter        | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - a_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - b_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - session_end_filter       | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 0                    | 1            | 0           |
-| - dedicated_fifos          | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                         | 1                | 1                | 1                 | 1            | 1            | 1              | 1            | 1                    | 1            | 0           |
-| - num_dev_in_eps           | 7              | 7              | 0           | 7               | 6            | 4             | 7            | 7            | 3                         | 5                | 5                | 5                 | 8            | 8            | 8              | 5            | 8                    | 6            | 0           |
-| - dma_desc_enable          | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1                    | 1            | 0           |
-| - dma_desc_dynamic         | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                         | 0                | 0                | 0                 | 0            | 0            | 1              | 0            | 1                    | 1            | 0           |
+|                            | AT32 F405 FS   | AT32 F405 HS   | AT32 F415   | BCM2711 (Pi4)   | EFM32GG      | ESP32-S2/S3   | ESP32-P4     | nRF54        | ST F407/429 HS   | ST F207/F407/411/429 FS   | ST L476 FS   | ST F412/76x FS   | ST F76x HS   | ST H743/H750   | ST F723/L4P5 FS   | ST F723 HS   | ST H7RS FS   | ST U5A5/H7RS/N6 HS   | XMC4500      | GD32VF103   |
+|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:-----------------|:--------------------------|:-------------|:-----------------|:-------------|:---------------|:------------------|:-------------|:-------------|:---------------------|:-------------|:------------|
+| GUID                       | 0x00002000     | 0x00000000     | 0x00001000  | 0x2708A000      | 0x00000000   | 0x00000000    | 0x00000000   | 0x00000000   | 0x00001100       | 0x00001200                | 0x00002000   | 0x00002000       | 0x00002100   | 0x00002300     | 0x00003000        | 0x00003100   | 0x00004000   | 0x00005000           | 0x00AEC000   | 0x00001000  |
+| GSNPSID                    | 0x4F54400A     | 0x4F54400A     | 0x4F54400A  | 0x4F54280A      | 0x4F54330A   | 0x4F54400A    | 0x4F54400A   | 0x4F54430A   | 0x4F54281A       | 0x4F54281A                | 0x4F54310A   | 0x4F54320A       | 0x4F54320A   | 0x4F54330A     | 0x4F54330A        | 0x4F54330A   | 0x4F54411A   | 0x4F54411A           | 0x4F54292A   | 0x00000000  |
+| - specs version            | 4.00a          | 4.00a          | 4.00a       | 2.80a           | 3.30a        | 4.00a         | 4.00a        | 4.30a        | 2.81a            | 2.81a                     | 3.10a        | 3.20a            | 3.20a        | 3.30a          | 3.30a             | 3.30a        | 4.11a        | 4.11a                | 2.92a        | 0.00W       |
+| GHWCFG1                    | 0x00000000     | 0x00000000     | 0x00000000  | 0x00000000      | 0x00000000   | 0x00000000    | 0x00000000   | 0xAA555000   | 0x00000000       | 0x00000000                | 0x00000000   | 0x00000000       | 0x00000000   | 0x00000000     | 0x00000000        | 0x00000000   | 0x00000000   | 0x00000000           | 0x00000000   | 0x00000000  |
+| GHWCFG2                    | 0x228FDD00     | 0x229FDDD0     | 0x228DCD00  | 0x228DDD50      | 0x228F5910   | 0x224DD930    | 0x215FFFD0   | 0x228BFC72   | 0x229ED590       | 0x229DCD20                | 0x229ED520   | 0x229ED520       | 0x229FE190   | 0x229FE190     | 0x229ED520        | 0x229FE1D0   | 0x229ED522   | 0x228FE052           | 0x228F5930   | 0x00000000  |
+| - op_mode                  | HNP SRP        | HNP SRP        | HNP SRP     | HNP SRP         | HNP SRP      | HNP SRP       | HNP SRP      | noHNP noSRP  | HNP SRP          | HNP SRP                   | HNP SRP      | HNP SRP          | HNP SRP      | HNP SRP        | HNP SRP           | HNP SRP      | noHNP noSRP  | noHNP noSRP          | HNP SRP      | HNP SRP     |
+| - arch                     | Slave only     | DMA internal   | Slave only  | DMA internal    | DMA internal | DMA internal  | DMA internal | DMA internal | DMA internal     | Slave only                | Slave only   | Slave only       | DMA internal | DMA internal   | Slave only        | DMA internal | Slave only   | DMA internal         | DMA internal | Slave only  |
+| - single_point             | hub            | hub            | hub         | hub             | hub          | n/a           | hub          | n/a          | hub              | n/a                       | n/a          | n/a              | hub          | hub            | n/a               | hub          | n/a          | hub                  | n/a          | hub         |
+| - hs_phy_type              | n/a            | UTMI+/ULPI     | n/a         | UTMI+           | n/a          | n/a           | UTMI+/ULPI   | UTMI+        | ULPI             | n/a                       | n/a          | n/a              | ULPI         | ULPI           | n/a               | UTMI+/ULPI   | n/a          | UTMI+                | n/a          | n/a         |
+| - fs_phy_type              | Dedicated      | Dedicated      | Dedicated   | Dedicated       | Dedicated    | Dedicated     | Shared ULPI  | n/a          | Dedicated        | Dedicated                 | Dedicated    | Dedicated        | Dedicated    | Dedicated      | Dedicated         | Dedicated    | Dedicated    | n/a                  | Dedicated    | n/a         |
+| - num_dev_ep               | 7              | 7              | 3           | 7               | 6            | 6             | 15           | 15           | 5                | 3                         | 5            | 5                | 8            | 8              | 5                 | 8            | 5            | 8                    | 6            | 0           |
+| - num_host_ch              | 15             | 15             | 7           | 7               | 13           | 7             | 15           | 15           | 11               | 7                         | 11           | 11               | 15           | 15             | 11                | 15           | 11           | 15                   | 13           | 0           |
+| - period_channel_support   | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - enable_dynamic_fifo      | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - mul_proc_intrpt          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 0                    | 0            | 0           |
+| - reserved21               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - nptx_q_depth             | 8              | 8              | 8           | 8               | 8            | 4             | 4            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 2           |
+| - ptx_q_depth              | 8              | 8              | 8           | 8               | 8            | 8             | 4            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 2           |
+| - token_q_depth            | 8              | 8              | 8           | 8               | 8            | 8             | 8            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 8            | 0           |
+| - otg_enable_ic_usb        | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| GHWCFG3                    | 0x020004E8     | 0x03F006E8     | 0x020004E8  | 0x0FF000E8      | 0x01F204E8   | 0x00C804B5    | 0x03805EB5   | 0x0BEAC0E8   | 0x03F403E8       | 0x020001E8                | 0x0200D1E8   | 0x0200D1E8       | 0x03EED2E8   | 0x03B8D2E8     | 0x0200D1E8        | 0x03EED2E8   | 0x020081E8   | 0x03B882E8           | 0x027A01E5   | 0x00000000  |
+| - xfer_size_width          | 8              | 8              | 8           | 8               | 8            | 5             | 5            | 8            | 8                | 8                         | 8            | 8                | 8            | 8              | 8                 | 8            | 8            | 8                    | 5            | 0           |
+| - packet_size_width        | 6              | 6              | 6           | 6               | 6            | 3             | 3            | 6            | 6                | 6                         | 6            | 6                | 6            | 6              | 6                 | 6            | 6            | 6                    | 6            | 0           |
+| - otg_enable               | 1              | 1              | 1           | 1               | 1            | 1             | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - i2c_enable               | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 1                | 1                         | 1            | 1                | 0            | 0              | 1                 | 0            | 1            | 0                    | 1            | 0           |
+| - vendor_ctrl_itf          | 0              | 1              | 0           | 0               | 0            | 0             | 1            | 0            | 1                | 0                         | 0            | 0                | 1            | 1              | 0                 | 1            | 0            | 1                    | 0            | 0           |
+| - optional_feature_removed | 1              | 1              | 1           | 0               | 1            | 1             | 1            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - synch_reset              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - otg_adp_support          | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 0            | 0           |
+| - otg_enable_hsic          | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - battery_charger_support  | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 1            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 0            | 0           |
+| - lpm_mode                 | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                | 0                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 0            | 0           |
+| - dfifo_depth              | 512            | 1008           | 512         | 4080            | 498          | 200           | 896          | 3050         | 1012             | 512                       | 512          | 512              | 1006         | 952            | 512               | 1006         | 512          | 952                  | 634          | 0           |
+| GHWCFG4                    | 0x1FF0A020     | 0x1FF0A020     | 0x0000000F  | 0x1FF00020      | 0x1BF08030   | 0xD3F0A030    | 0xDFF1A030   | 0x1E10AA60   | 0x17F00030       | 0x0FF08030                | 0x17F08030   | 0x17F08030       | 0x23F00030   | 0xE3F00030     | 0x17F08030        | 0x23F00030   | 0x1610B230   | 0xE2103E30           | 0xDBF08030   | 0x00000000  |
+| - num_dev_period_in_ep     | 0              | 0              | 15          | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - partial_powerdown        | 0              | 0              | 0           | 0               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - ahb_freq_min             | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - hibernation              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - extended_hibernation     | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - reserved8                | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - enhanced_lpm_support1    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - service_interval_flow    | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 1                    | 0            | 0           |
+| - ipg_isoc_support         | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 1                    | 0            | 0           |
+| - acg_support              | 0              | 0              | 0           | 0               | 0            | 0             | 0            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - enhanced_lpm_support     | 1              | 1              | 0           | 0               | 0            | 1             | 1            | 1            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 1            | 1                    | 0            | 0           |
+| - phy_data_width           | 8/16 bit       | 8/16 bit       | 8 bit       | 8 bit           | 8/16 bit     | 8/16 bit      | 8/16 bit     | 8/16 bit     | 8 bit            | 8/16 bit                  | 8/16 bit     | 8/16 bit         | 8 bit        | 8 bit          | 8/16 bit          | 8 bit        | 8/16 bit     | 8 bit                | 8/16 bit     | 8 bit       |
+| - ctrl_ep_num              | 0              | 0              | 0           | 0               | 0            | 0             | 1            | 0            | 0                | 0                         | 0            | 0                | 0            | 0              | 0                 | 0            | 0            | 0                    | 0            | 0           |
+| - iddg_filter              | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - vbus_valid_filter        | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - a_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - b_valid_filter           | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - session_end_filter       | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 0            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 0            | 0                    | 1            | 0           |
+| - dedicated_fifos          | 1              | 1              | 0           | 1               | 1            | 1             | 1            | 1            | 1                | 1                         | 1            | 1                | 1            | 1              | 1                 | 1            | 1            | 1                    | 1            | 0           |
+| - num_dev_in_eps           | 7              | 7              | 0           | 7               | 6            | 4             | 7            | 7            | 5                | 3                         | 5            | 5                | 8            | 8              | 5                 | 8            | 5            | 8                    | 6            | 0           |
+| - dma_desc_enable          | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                | 0                         | 0            | 0                | 0            | 1              | 0                 | 0            | 0            | 1                    | 1            | 0           |
+| - dma_desc_dynamic         | 0              | 0              | 0           | 0               | 0            | 1             | 1            | 0            | 0                | 0                         | 0            | 0                | 0            | 1              | 0                 | 0            | 0            | 1                    | 1            | 0           |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index 8fbbc00a0..e6601f482 100755
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -16,14 +16,16 @@ dwc2_reg_value = {
     'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
     'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
     'nRF54': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60],
-    'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+    # ST sort by GUID
     'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
+    'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+    'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
     'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
-    'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
-    'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
     'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
     'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
-    'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+    'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
+    'ST H7RS FS': [0x4000, 0x4F54411A, 0, 0x229ED522, 0x20081E8, 0x1610B230],
     'ST U5A5/H7RS/N6 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
     'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
     'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
diff --git a/src/portable/synopsys/dwc2/dwc2_nrf.h b/src/portable/synopsys/dwc2/dwc2_nrf.h
index b93571f16..51f2d684f 100644
--- a/src/portable/synopsys/dwc2/dwc2_nrf.h
+++ b/src/portable/synopsys/dwc2/dwc2_nrf.h
@@ -52,6 +52,12 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
   (void)hs_phy_type;
 }
 
+// MCU specific PHY deinit, disable PHY power
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  (void)dwc2;
+  (void)hs_phy_type;
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   (void)dwc2;
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 516eb021b..259ad21b9 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -85,8 +85,11 @@ extern "C" {
   #define EP_MAX_HS       9
   #define EP_FIFO_SIZE_HS 4096
 
-  #define USB_OTG_HS_PERIPH_BASE    USB1_OTG_HS_BASE
-  #define OTG_HS_IRQn               USB1_OTG_HS_IRQn
+  #define USB_OTG_FS_PERIPH_BASE    USB1_OTG_HS_BASE
+  #define OTG_FS_IRQn               USB1_OTG_HS_IRQn
+
+  #define USB_OTG_HS_PERIPH_BASE    USB2_OTG_HS_BASE
+  #define OTG_HS_IRQn               USB2_OTG_HS_IRQn
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
@@ -261,6 +264,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   }
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
+    // Disable on-chip FS PHY
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+  } else {
+    // Disable HS PHY
+    #ifdef USB_HS_PHYC
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PHYHSEN;
+    // Disable PLL and LDO
+    USB_HS_PHYC->USB_HS_PHYC_PLL &= ~USB_HS_PHYC_PLL_PLLEN;
+    USB_HS_PHYC->USB_HS_PHYC_LDO &= ~USB_HS_PHYC_LDO_ENABLE;
+    #endif
+  }
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   // used to set turnaround time for fullspeed, nothing to do in highspeed mode
@@ -300,6 +319,66 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   }
 }
 
+//------------- GCCFG configuration -------------//
+static inline void dwc2_stm32_gccfg_cfg(dwc2_regs_t* dwc2, bool vbus_sensing, bool is_host) {
+  if (is_host) {
+    vbus_sensing = false;
+  }
+
+  uint32_t gccfg = dwc2->stm32_gccfg;
+  if (dwc2->guid < 0x2000) {
+    // use VBUSASEN/VBUSBSEN/NOVBUSSENS bits
+    if (is_host) {
+      gccfg &= ~(STM32_GCCFG_NOVBUSSENS | STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
+    } else {
+      if (vbus_sensing) {
+        gccfg &= ~STM32_GCCFG_NOVBUSSENS;
+        gccfg |= STM32_GCCFG_VBUSBSEN;
+      } else {
+        gccfg |= STM32_GCCFG_NOVBUSSENS;
+        gccfg &= ~(STM32_GCCFG_VBUSBSEN | STM32_GCCFG_VBUSASEN);
+      }
+    }
+  } else if (dwc2->guid < 0x5000) {
+    // the later version uses VBDEN with battery charging detection
+    if (vbus_sensing) {
+      gccfg |= STM32_GCCFG_VBDEN;
+    } else {
+      gccfg &= ~STM32_GCCFG_VBDEN;
+    }
+  } else {
+    // from 0x5000 ST seems to use femtoPHY for UTMI+ HS PHY. Which use VBVALEXTOEN and VBVALOVAL for software override
+    // external VBUS sensing
+    // Note: N6 does not support hardware VBUS sensing, so the software override is always active. Therefore, VBDEN and
+    //       VBVALEXTOEN are not available
+#if CFG_TUSB_MCU == OPT_MCU_STM32N6
+    if (is_host) {
+      gccfg |= STM32_GCCFG_PULLDOWNEN;
+      gccfg &= ~(STM32_GCCFG_VBVALOVAL);
+    } else {
+      gccfg &= ~STM32_GCCFG_PULLDOWNEN;
+      gccfg |= STM32_GCCFG_VBVALOVAL;
+    }
+#else
+    if (is_host) {
+      gccfg |= STM32_GCCFG_PULLDOWNEN;
+      gccfg &= ~(STM32_GCCFG_VBDEN | STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
+    } else {
+      gccfg &= ~STM32_GCCFG_PULLDOWNEN;
+      if (vbus_sensing) {
+        gccfg |= STM32_GCCFG_VBDEN;
+        gccfg &= ~(STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL);
+      } else {
+        gccfg &= ~STM32_GCCFG_VBDEN;
+        gccfg |= STM32_GCCFG_VBVALEXTOEN | STM32_GCCFG_VBVALOVAL;
+      }
+    }
+#endif
+  }
+
+  dwc2->stm32_gccfg = gccfg;
+}
+
 //------------- DCache -------------//
 #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
 
@@ -321,8 +400,13 @@ static mem_region_t uncached_regions[] = {
   // DTCM (although USB DMA can't transfer to/from DTCM)
   {.start = 0x20000000, .end = 0x2002FFFF},
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-    // DTCM
+  // DTCM
   {.start = 0x20000000, .end = 0x2000FFFF},
+#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
+  // DTCM NS
+  {.start = 0x20000000, .end = 0x2003FFFF},
+  // DTCM S
+  {.start = 0x30000000, .end = 0x3003FFFF},
 #else
 #error "Cache maintenance is not supported yet"
 #endif
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 7693ce02a..596bd0b34 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -1650,24 +1650,38 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000
 #define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable
 
-// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
-//#define STM32_GCCFG_SDEN_Pos                   (22U)
-//#define STM32_GCCFG_SDEN_Msk                   (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
-//#define STM32_GCCFG_SDEN                       STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
+// GUID < 0x2000: VBUSASEN, VBUSBSEN, NOVBUSSENS bits
+#define STM32_GCCFG_VBUSASEN_Pos         (18U)
+#define STM32_GCCFG_VBUSASEN_Msk         (0x1UL << STM32_GCCFG_VBUSASEN_Pos)      // 0x00040000
+#define STM32_GCCFG_VBUSASEN             STM32_GCCFG_VBUSASEN_Msk                 // Enable A-device (host) VBUS sensing
 
-// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
-#define STM32_GCCFG_VBVALOVAL_Pos              (23U)
-#define STM32_GCCFG_VBVALOVAL_Msk              (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
-#define STM32_GCCFG_VBVALOVAL                  STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
+#define STM32_GCCFG_VBUSBSEN_Pos         (19U)
+#define STM32_GCCFG_VBUSBSEN_Msk         (0x1UL << STM32_GCCFG_VBUSBSEN_Pos)      // 0x00080000
+#define STM32_GCCFG_VBUSBSEN             STM32_GCCFG_VBUSBSEN_Msk                 // Enable B-device (peripheral) VBUS sensing
 
-#define STM32_GCCFG_VBVALEXTOEN_Pos            (24U)
-#define STM32_GCCFG_VBVALEXTOEN_Msk            (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
-#define STM32_GCCFG_VBVALEXTOEN                STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
+#define STM32_GCCFG_NOVBUSSENS_Pos       (21U)
+#define STM32_GCCFG_NOVBUSSENS_Msk       (0x1UL << STM32_GCCFG_NOVBUSSENS_Pos)     // 0x00200000
+#define STM32_GCCFG_NOVBUSSENS           STM32_GCCFG_NOVBUSSENS_Msk                // VBUS sensing disable option
+// GUID < 0x2000: end
 
-#define STM32_GCCFG_PULLDOWNEN_Pos             (25U)
-#define STM32_GCCFG_PULLDOWNEN_Msk             (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
-#define STM32_GCCFG_PULLDOWNEN                 STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+// TODO: stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
+// #define STM32_GCCFG_SDEN_Pos             (22U)
+// #define STM32_GCCFG_SDEN_Msk             (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
+// #define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
 
+// GUID >= 0x5000 use femtoPHY: VBVALOVA, VBVALEXTOEN, PULLDOWNEN
+#define STM32_GCCFG_VBVALOVAL_Pos        (23U)
+#define STM32_GCCFG_VBVALOVAL_Msk        (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
+#define STM32_GCCFG_VBVALOVAL            STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
+
+#define STM32_GCCFG_VBVALEXTOEN_Pos      (24U)
+#define STM32_GCCFG_VBVALEXTOEN_Msk      (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
+#define STM32_GCCFG_VBVALEXTOEN          STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
+
+#define STM32_GCCFG_PULLDOWNEN_Pos       (25U)
+#define STM32_GCCFG_PULLDOWNEN_Msk       (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
+#define STM32_GCCFG_PULLDOWNEN           STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+// GUID >= 0x5000: end
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h
index 63419abf7..aca3873df 100644
--- a/src/portable/synopsys/dwc2/dwc2_xmc.h
+++ b/src/portable/synopsys/dwc2/dwc2_xmc.h
@@ -71,6 +71,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
   //USB->ROUTE = USB_ROUTE_PHYPEN;
 }
 
+// MCU specific PHY deinit, disable PHY power
+static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) {
+  (void) dwc2;
+  (void) hs_phy_type;
+  // nothing to do
+}
+
 // MCU specific PHY update, it is called AFTER init() and core reset
 static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index c40703b09..e12e44a41 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -111,7 +111,8 @@ typedef struct {
   hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX];
 } hcd_data_t;
 
-hcd_data_t _hcd_data;
+static hcd_data_t _hcd_data;
+static tuh_configure_dwc2_t _tuh_cfg = {.use_hs_phy = TUH_OPT_HIGH_SPEED};
 
 //--------------------------------------------------------------------
 //
@@ -350,7 +351,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t pa
  * TX periodic (PTX)
  * - At least largest-EPsize*MulCount/4 (MulCount up to 3 for high-bandwidth ISO/interrupt)
 */
-static void dfifo_host_init(uint8_t rhport) {
+static void dfifo_host_init(uint8_t rhport, bool is_hs_phy) {
   const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
@@ -363,10 +364,9 @@ static void dfifo_host_init(uint8_t rhport) {
   }
 
   // fixed allocation for now, improve later:
-    // - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
-  bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
-  uint32_t nptx_largest = is_highspeed ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4;
-  uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4;
+  // - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total
+  uint32_t nptx_largest = is_hs_phy ? TUSB_EPSIZE_BULK_HS / 4 : TUSB_EPSIZE_BULK_FS / 4;
+  uint32_t ptx_largest  = is_hs_phy ? TUSB_EPSIZE_ISO_HS_MAX / 4 : 256 / 4;
 
   uint16_t nptxfsiz = 2 * nptx_largest;
   uint16_t rxfsiz = 2 * (ptx_largest + 2) + ghwcfg2.num_host_ch;
@@ -392,29 +392,23 @@ static void dfifo_host_init(uint8_t rhport) {
 // optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
-
+  TU_VERIFY(cfg_id == TUH_CFGID_DWC2 && cfg_param != NULL);
+  tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
+  _tuh_cfg = cfg->dwc2;
   return true;
 }
 
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
-  (void) rh_init;
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
   // Core Initialization
-  const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST);
+  const bool is_hs_phy = dwc2_core_is_highspeed_phy(dwc2, _tuh_cfg.use_hs_phy);
   const bool is_dma = dma_host_enabled(dwc2);
-  TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+  TU_ASSERT(dwc2_core_init(rhport, is_hs_phy, is_dma));
 
   //------------- 3.1 Host Initialization -------------//
-
-  // work at max supported speed
-  dwc2->hcfg &= ~HCFG_FSLS_ONLY;
-
   // Enable HFIR reload
   if (dwc2->gsnpsid >= DWC2_CORE_REV_2_92a) {
     dwc2->hfir |= HFIR_RELOAD_CTRL;
@@ -422,20 +416,26 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
 
   // force host mode and wait for mode switch
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
-#if CFG_TUSB_MCU == OPT_MCU_STM32N6
-  // No hardware detection of Vbus B-session is available on the STM32N6
-  dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL;
-#endif
   while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
 
-  // configure fixed-allocated fifo scheme
-  dfifo_host_init(rhport);
+  #ifdef TUP_USBIP_DWC2_STM32
+  dwc2_stm32_gccfg_cfg(dwc2, false, true);
+  #endif
+
+  if (is_hs_phy && (rh_init->speed == TUSB_SPEED_HIGH || rh_init->speed == TUSB_SPEED_AUTO)) {
+    dwc2->hcfg &= ~HCFG_FSLS_ONLY; // max speed
+  } else {
+    dwc2->hcfg |= HCFG_FSLS_ONLY;  // disable high speed mode
+  }
+
+  // configure a fixed-allocated fifo scheme
+  dfifo_host_init(rhport, is_hs_phy);
 
   dwc2->hprt = HPRT_W1_MASK; // clear all write-1-clear bits
   dwc2->hprt = HPRT_POWER; // turn on VBUS
 
   // Enable required interrupts
-  dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT;
+  dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT;
 
   // NPTX can hold at least 2 packet, change interrupt level to half-empty
   uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL;
@@ -445,6 +445,17 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   return true;
 }
 
+bool hcd_deinit(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // Turn off VBUS
+  dwc2->hprt = HPRT_W1_MASK; // clear w1c bits without side effects
+  // HPRT_POWER is not set -> VBUS off
+
+  dwc2_core_deinit(rhport);
+  return true;
+}
+
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
   dwc2_int_set(rhport, TUSB_ROLE_HOST, true);
@@ -869,7 +880,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
       break;
 
     case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR:
-      TU_ASSERT(0, ); // maybe try to change DToggle
+      // handle in channel interrupt
       break;
 
     case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED:
@@ -1009,8 +1020,11 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
       channel_xfer_in_retry(dwc2, ch_id, hcint);
     }
   } else if (hcint & HCINT_DATATOGGLE_ERR) {
+    channel->hcintmsk &= ~HCINT_DATATOGGLE_ERR;
     xfer->err_count = 0;
-    TU_ASSERT(false);
+    hcsplt.split_compl = 0; // restart with start-split
+    channel->hcsplt = hcsplt.value;
+    channel_disable(dwc2, channel);
   } else {
     // nothing to do
   }
@@ -1346,6 +1360,17 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) {
 }
 
 // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit)
+// Databook Table 2-2: System Clock Speeds
+// +-----------+------------------+----------+-----------+-------------------+
+// | PHY       | PHY Clock (MHz)  | Width    | HCFG.Sel  | HFIR (clk cycles) |
+// +-----------+------------------+----------+-----------+-------------------+
+// | HS UTMI+  | 30               | 16-bit   | 30_60     | HS:3749 FS:29999  |
+// | HS UTMI+  | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// | HS ULPI   | 60               |  8-bit   | 30_60     | HS:7499 FS:59999  |
+// | FS (dead.) | 48               | internal | 48        | FS:47999          |
+// | LS via FS | 48 (6 effective) | internal | 6         | LS:47999          |
+// +-----------+------------------+----------+-----------+-------------------+
+// HFIR = (interval_us * phy_clock) - 1, where interval is 125us (HS) or 1000us (FS/LS)
 static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) {
   uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL;
 
@@ -1438,16 +1463,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
   // TU_LOG1_HEX(gintsts);
 
-  if (gintsts & GINTSTS_CONIDSTSCHNG) {
-    // Connector ID status change
-    dwc2->gintsts = GINTSTS_CONIDSTSCHNG;
-
-    //if (dwc2->gotgctl)
-    // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS
-    //dwc2->gintmsk |= GINTMSK_PRTIM;
-    // TODO wait for SRP if OTG
-  }
-
   if (gintsts & GINTSTS_SOF) {
     const bool more_sof = handle_sof_irq(rhport, in_isr);
     if (!more_sof) {
diff --git a/src/tinyusb.mk b/src/tinyusb.mk
index 8f9d52de9..e7d1c0b5b 100644
--- a/src/tinyusb.mk
+++ b/src/tinyusb.mk
@@ -15,6 +15,7 @@ TINYUSB_SRC_C += \
 	src/class/mtp/mtp_device.c \
 	src/class/net/ecm_rndis_device.c \
 	src/class/net/ncm_device.c \
+	src/class/printer/printer_device.c \
 	src/class/usbtmc/usbtmc_device.c \
 	src/class/video/video_device.c \
 	src/class/vendor/vendor_device.c \
diff --git a/src/tusb.c b/src/tusb.c
index ed254a10b..4ea396715 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -39,23 +39,38 @@
 #include "host/usbh_pvt.h"
 #endif
 
+// Suppress IAR warning
+// Warning[Pe111]: statement is unreachable
+#if defined(__ICCARM__)
+#pragma diag_suppress = Pe111
+#endif
+
 tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM] = { TUSB_ROLE_INVALID };
 
 //--------------------------------------------------------------------
 // Weak/Default API, can be overwritten by Application
 //--------------------------------------------------------------------
 
-TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) {
 #if CFG_TUSB_OS != OPT_OS_NONE
+TU_ATTR_WEAK uint32_t tusb_time_millis_api(void) {
+  return osal_time_millis();
+}
+
+TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) {
   osal_task_delay(ms);
+}
+
 #else
-  // delay using millis() (if implemented) and/or frame number if possible
+// tusb_time_millis_api() must be implemented by user application.
+
+TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) {
+  // delay using millis()
   const uint32_t time_ms = tusb_time_millis_api();
   while ((tusb_time_millis_api() - time_ms) < ms) {}
-#endif
 }
+#endif
 
-TU_ATTR_WEAK void* tusb_app_virt_to_phys(void *virt_addr) {
+TU_ATTR_WEAK void *tusb_app_virt_to_phys(void *virt_addr) {
   return virt_addr;
 }
 
@@ -245,6 +260,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
 bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) {
   const uint16_t max_packet_size = tu_edpt_packet_size(desc_ep);
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
+  TU_ASSERT(max_packet_size > 0);
 
   switch (desc_ep->bmAttributes.xfer) {
     case TUSB_XFER_ISOCHRONOUS: {
@@ -264,7 +280,7 @@ bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) {
       break;
 
     case TUSB_XFER_INTERRUPT: {
-      uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
+      const uint16_t spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
       TU_ASSERT(max_packet_size <= spec_size);
       break;
     }
@@ -309,11 +325,9 @@ bool tu_edpt_stream_init(tu_edpt_stream_t *s, bool is_host, bool is_tx, bool ove
                          uint16_t ff_bufsize, uint8_t *ep_buf, uint16_t ep_bufsize) {
   (void) is_tx;
 
-  #if CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED == 0 // FIFO is required
   if (ff_buf == NULL || ff_bufsize == 0) {
     return false;
   }
-  #endif
 
   s->is_host = is_host;
   tu_fifo_config(&s->ff, ff_buf, ff_bufsize, overwritable);
@@ -394,7 +408,7 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t *s) {
   // Pull data from FIFO -> EP buf
   uint16_t count;
   if (s->ep_buf == NULL) {
-    count = ff_count;
+    count = tu_fifo_count(&s->ff); // re-get count since fifo can be changed
   } else {
     count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
   }
@@ -411,90 +425,45 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t *s) {
 }
 
 uint32_t tu_edpt_stream_write(tu_edpt_stream_t *s, const void *buffer, uint32_t bufsize) {
-  #if CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
-  if (0 == tu_fifo_depth(&s->ff)) {
-    // non-fifo mode: TX need ep buffer
-    TU_VERIFY(s->ep_buf != NULL, 0);
-    TU_VERIFY(stream_claim(s), 0);
-    uint32_t xact_len = tu_min32(bufsize, s->ep_bufsize);
-    memcpy(s->ep_buf, buffer, xact_len);
-    TU_ASSERT(stream_xfer(s, (uint16_t) xact_len), 0);
-    return xact_len;
-  } else
-  #endif
-  {
-    TU_VERIFY(bufsize > 0);
-    const uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
+  TU_VERIFY(bufsize > 0);
+  const uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
 
-    // flush if fifo has more than packet size or
-    // in rare case: fifo depth is configured too small (which never reach packet size)
-    if ((tu_fifo_count(&s->ff) >= s->mps) || (tu_fifo_depth(&s->ff) < s->mps)) {
-      tu_edpt_stream_write_xfer(s);
-    }
-    return ret;
+  // flush if fifo has more than packet size or
+  // in rare case: fifo depth is configured too small (which never reach packet size)
+  if ((tu_fifo_count(&s->ff) >= s->mps) || (tu_fifo_depth(&s->ff) < s->mps)) {
+    tu_edpt_stream_write_xfer(s);
   }
+  return ret;
 }
 
 uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t *s) {
-  #if CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
-  if (0 == tu_fifo_depth(&s->ff)) {
-    // non-fifo mode
-    TU_VERIFY(s->ep_addr > 0); // must be opened
-    bool is_busy = true;
-    if (s->is_host) {
-      #if CFG_TUH_ENABLED
-      is_busy = usbh_edpt_busy(s->hwid, s->ep_addr);
-    #endif
-    } else {
-      #if CFG_TUD_ENABLED
-      is_busy = usbd_edpt_busy(s->hwid, s->ep_addr);
-    #endif
-    }
-    return is_busy ? 0 : s->ep_bufsize;
-  } else
-  #endif
-  {
-    return (uint32_t)tu_fifo_remaining(&s->ff);
-  }
+  return (uint32_t)tu_fifo_remaining(&s->ff);
 }
 
 //--------------------------------------------------------------------+
 // Stream Read
 //--------------------------------------------------------------------+
 uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t *s) {
-  #if CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
-  if (0 == tu_fifo_depth(&s->ff)) {
-    // non-fifo mode: RX need ep buffer
-    TU_VERIFY(s->ep_buf != NULL, 0);
-    TU_VERIFY(stream_claim(s), 0);
-    TU_ASSERT(stream_xfer(s, s->ep_bufsize), 0);
-    return s->ep_bufsize;
-  } else
-  #endif
-  {
-    uint16_t available = tu_fifo_remaining(&s->ff);
+  uint16_t available = tu_fifo_remaining(&s->ff);
 
-    // Prepare for incoming data but only allow what we can store in the ring buffer.
-    // TODO Actually we can still carry out the transfer, keeping count of received bytes
-    // and slowly move it to the FIFO when read().
-    // This pre-check reduces endpoint claiming
-    TU_VERIFY(available >= s->mps);
-    TU_VERIFY(stream_claim(s), 0);
-    available = tu_fifo_remaining(&s->ff); // re-get available since fifo can be changed
+  // Prepare for incoming data but only allow what we can store in the ring buffer.
+  // TODO Actually we can still carry out the transfer, keeping count of received bytes
+  // and slowly move it to the FIFO when read().
+  // This pre-check reduces endpoint claiming
+  TU_VERIFY(available >= s->mps);
+  TU_VERIFY(stream_claim(s), 0);
+  available = tu_fifo_remaining(&s->ff); // re-get available since fifo can be changed
 
-    if (available >= s->mps) {
-      // multiple of packet size limit by ep bufsize
-      uint16_t count = (uint16_t) (available & ~(s->mps - 1));
-      if (s->ep_buf != NULL) {
-        count = tu_min16(count, s->ep_bufsize);
-      }
-      TU_ASSERT(stream_xfer(s, count), 0);
-      return count;
-    } else {
-      // Release endpoint since we don't make any transfer
-      stream_release(s);
-      return 0;
-    }
+  if (available >= s->mps) {
+    // multiple of packet size limit by ep bufsize
+    uint16_t count = (uint16_t) (available & ~(s->mps - 1));
+    count = tu_min16(count, s->ep_bufsize);
+    TU_ASSERT(stream_xfer(s, count), 0);
+    return count;
+  } else {
+    // Release endpoint since we don't make any transfer
+    stream_release(s);
+    return 0;
   }
 }
 
diff --git a/src/tusb.h b/src/tusb.h
index 62b3b9783..c80c8433c 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -88,6 +88,10 @@
     #include "class/msc/msc_device.h"
   #endif
 
+  #if CFG_TUD_PRINTER
+    #include "class/printer/printer_device.h"
+  #endif
+
   #if CFG_TUD_MTP
     #include "class/mtp/mtp_device.h"
   #endif
@@ -135,7 +139,7 @@
 
 
 //--------------------------------------------------------------------+
-// User API
+// Application API
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED || CFG_TUD_ENABLED
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 08a0ba2ef..f5879e1df 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -216,6 +216,7 @@
 #define OPT_MCU_AT32F402_405     2504  ///< ArteryTek AT32F402_405
 #define OPT_MCU_AT32F425         2505  ///< ArteryTek AT32F425
 #define OPT_MCU_AT32F413         2506  ///< ArteryTek AT32F413
+#define OPT_MCU_AT32F45X         2507  ///< ArteryTek AT32F45x
 
 // HPMicro
 #define OPT_MCU_HPM              2600  ///< HPMicro
@@ -237,6 +238,7 @@
 #define OPT_OS_RTTHREAD   6  ///< RT-Thread
 #define OPT_OS_RTX4       7  ///< Keil RTX 4
 #define OPT_OS_ZEPHYR     8  ///< Zephyr
+#define OPT_OS_THREADX    9  ///< ThreadX
 
 //--------------------------------------------------------------------+
 // Mode and Speed
@@ -271,6 +273,25 @@
 // USBIP
 //--------------------------------------------------------------------+
 
+//------------- ChipIdea -------------//
+// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is
+// insufficient).
+#ifndef CFG_TUD_CI_HS_VBUS_CHARGE
+  #ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
+    #define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0
+  #endif
+  #define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
+#endif
+
+// CI_HS support FIFO transfer if endpoint buffer is 4k aligned and size is multiple of 4k, also DCACHE is disabled
+#ifndef CFG_TUD_CI_HS_EPBUF_4K_ALIGNED
+  #define CFG_TUD_CI_HS_EPBUF_4K_ALIGNED 0
+#endif
+
+#if CFG_TUD_CI_HS_EPBUF_4K_ALIGNED && !CFG_TUD_MEM_DCACHE_ENABLE
+  #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
+#endif
+
 //------------- DWC2 -------------//
 // DMA mode for device
 #ifndef CFG_TUD_DWC2_DMA_ENABLE
@@ -316,57 +337,28 @@
   #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 0 // fixed hwfifo address
 #endif
 
-//------------- ChipIdea -------------//
-// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is
-// insufficient).
-#ifndef CFG_TUD_CI_HS_VBUS_CHARGE
-  #ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
-    #define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0
-  #endif
-  #define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
-#endif
-
-// CI_HS support FIFO transfer if endpoint buffer is 4k aligned and size is multiple of 4k, also DCACHE is disabled
-#ifndef CFG_TUD_CI_HS_EPBUF_4K_ALIGNED
-  #define CFG_TUD_CI_HS_EPBUF_4K_ALIGNED 0
-#endif
-
-#if CFG_TUD_CI_HS_EPBUF_4K_ALIGNED && !CFG_TUD_MEM_DCACHE_ENABLE
-  #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
-#endif
-
-//------------- pio-usb -------------//
-// Enable PIO-USB software host controller
-#ifndef CFG_TUH_RPI_PIO_USB
-  #define CFG_TUH_RPI_PIO_USB 0
-#endif
-
-#ifndef CFG_TUD_RPI_PIO_USB
-  #define CFG_TUD_RPI_PIO_USB 0
-#endif
-
-//------------ MAX3421 -------------//
-// Enable MAX3421 USB host controller
-#ifndef CFG_TUH_MAX3421
-  #define CFG_TUH_MAX3421  0
-#endif
-
 //------------ FSDEV --------------//
 #if defined(TUP_USBIP_FSDEV)
   #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
 
-  #if CFG_TUSB_FSDEV_PMA_SIZE == 512
-    #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 2 // 16-bit data
+  #if CFG_TUSB_FSDEV_PMA_SIZE == 2048 || TU_CHECK_MCU(OPT_MCU_STM32U0)
+    #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4 // 32-bit data
     #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4 // 32-bit address increase
   #elif CFG_TUSB_FSDEV_PMA_SIZE == 1024
     #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 2 // 16-bit data
     #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 2 // 16-bit address increase
-  #elif CFG_TUSB_FSDEV_PMA_SIZE == 2048
-    #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4 // 32-bit data
+  #elif CFG_TUSB_FSDEV_PMA_SIZE == 512
+    #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 2 // 16-bit data
     #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4 // 32-bit address increase
   #endif
 #endif
 
+//------------ MAX3421 -------------//
+// Enable MAX3421 USB host controller
+#ifndef CFG_TUH_MAX3421
+  #define CFG_TUH_MAX3421 0
+#endif
+
 //------------ MUSB --------------//
 #if defined(TUP_USBIP_MUSB)
   #define CFG_TUD_EDPT_DEDICATED_HWFIFO              1
@@ -374,18 +366,53 @@
   #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS   // allow odd 16bit access
   #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS    // allow odd 8bit access
   #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE           0 // fixed hwfifo
+#endif
+
+//------------- Raspberry Pi -------------//
+// Enable PIO-USB software host controller
+#ifndef CFG_TUH_RPI_PIO_USB
+  #define CFG_TUH_RPI_PIO_USB 0
+#endif
+
+#ifndef CFG_TUD_RPI_PIO_USB
+  #define CFG_TUD_RPI_PIO_USB 0
+#endif
 
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB
+  #define CFG_TUD_EDPT_DEDICATED_HWFIFO    1
+  #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 1
+  #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 1
+  #define CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE
+  #define CFG_TUSB_FIFO_HWFIFO_CUSTOM_READ
 #endif
 
 //------------ RUSB2 --------------//
 #if defined(TUP_USBIP_RUSB2)
   #define CFG_TUD_EDPT_DEDICATED_HWFIFO     1
-  #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE  (2 | (TUD_OPT_HIGH_SPEED ? 4 : 0)) // 16 bit and 32 bit data if highspeed
+  #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE  (2 | (TUD_OPT_HIGH_SPEED ? 4 : 0)) // 16 bit and 32 bit if highspeed
   #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE  0
   #define CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE // custom write since rusb2 can change access width 32 -> 16 and can write
                                             // odd byte with byte access
 #endif
 
+//------- Microchip SAMX7X -------//
+// DMA mode for device
+#ifndef CFG_TUD_SAMX7X_DMA_ENABLE
+  #ifndef CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT
+  #define CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT 0
+  #endif
+
+  #define CFG_TUD_SAMX7X_DMA_ENABLE CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT
+#endif
+
+#if (CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+  #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4
+  #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4
+  #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
+  #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
+  #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1
+#endif
+
 //--------------------------------------------------------------------
 // RootHub Mode detection
 //--------------------------------------------------------------------
@@ -461,7 +488,6 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
-
 //--------------------------------------------------------------------+
 // Common Options (Default)
 //--------------------------------------------------------------------+
@@ -506,6 +532,10 @@
   #define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
+#ifndef CFG_TUSB_OS_HAS_SCHEDULER
+  #define CFG_TUSB_OS_HAS_SCHEDULER (CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO)
+#endif
+
 #ifndef CFG_TUSB_OS_INC_PATH
   #ifndef CFG_TUSB_OS_INC_PATH_DEFAULT
   #define CFG_TUSB_OS_INC_PATH_DEFAULT
@@ -552,6 +582,11 @@
   #define CFG_TUD_INTERFACE_MAX   16
 #endif
 
+// max events processed in one tud_task_ext() call, 0 for unlimited
+#ifndef CFG_TUD_TASK_EVENTS_PER_RUN
+  #define CFG_TUD_TASK_EVENTS_PER_RUN  16
+#endif
+
 // default to max hardware endpoint, but can be smaller to save RAM
 #ifndef CFG_TUD_ENDPPOINT_MAX
   #define CFG_TUD_ENDPPOINT_MAX   TUP_DCD_ENDPOINT_MAX
@@ -566,9 +601,18 @@
   #define CFG_TUD_TEST_MODE       0
 #endif
 
+#ifndef CFG_TUD_VBUS_DETECT_HW_DEFAULT
+  #define CFG_TUD_VBUS_DETECT_HW_DEFAULT 0
+#endif
+
+// Enable VBUS Detect hardware, usually via functional GPIO
+#ifndef CFG_TUD_VBUS_DETECT_HW
+  #define CFG_TUD_VBUS_DETECT_HW CFG_TUD_VBUS_DETECT_HW_DEFAULT
+#endif
+
 //------------- Device Class Driver -------------//
 #ifndef CFG_TUD_BTH
-  #define CFG_TUD_BTH             0
+  #define CFG_TUD_BTH 0
 #endif
 
 #if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT)
@@ -632,6 +676,10 @@
   #define CFG_TUD_NCM         0
 #endif
 
+#ifndef CFG_TUD_PRINTER
+  #define CFG_TUD_PRINTER         0
+#endif
+
 #ifndef CFG_TUD_EDPT_DEDICATED_HWFIFO
   #define CFG_TUD_EDPT_DEDICATED_HWFIFO 0
 #endif
@@ -671,6 +719,11 @@
   #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
 #endif
 
+// max events processed in one tuh_task_ext() call, 0 for unlimited
+#ifndef CFG_TUH_TASK_EVENTS_PER_RUN
+  #define CFG_TUH_TASK_EVENTS_PER_RUN  16
+#endif
+
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
@@ -742,7 +795,7 @@
   #define CFG_TUH_CDC_PL2303 0
 #endif
 
-#ifndef CFG_TUH_CDC_PL2303_VID_PID_QUIRKS_LIST
+#ifndef CFG_TUH_CDC_PL2303_VID_PID_LIST
   // List of product IDs that can use the PL2303 CDC driver
   #define CFG_TUH_CDC_PL2303_VID_PID_LIST \
   { 0x067b, 0x2303 }, /* initial 2303 */ \
diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk
index b32f8d695..329dcce11 100644
--- a/test/fuzz/rules.mk
+++ b/test/fuzz/rules.mk
@@ -32,6 +32,7 @@ SRC_C += \
 	src/class/midi/midi_device.c \
 	src/class/msc/msc_device.c \
 	src/class/mtp/mtp_device.c \
+	src/class/printer/printer_device.c \
 	src/class/net/ecm_rndis_device.c \
 	src/class/net/ncm_device.c \
 	src/class/usbtmc/usbtmc_device.c \
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
index b2e883119..7cffd2da8 100755
--- a/test/hil/hil_test.py
+++ b/test/hil/hil_test.py
@@ -151,21 +151,49 @@ def read_disk_file(uid, lun, fname):
 def open_mtp_dev(uid):
     mtp = MTP()
     # MTP seems to take a while to enumerate
-    timeout = 2*ENUM_TIMEOUT
+    timeout = 2 * ENUM_TIMEOUT
     while timeout > 0:
-        # run_cmd(f"gio mount -u mtp://TinyUsb_TinyUsb_Device_{uid}/")
+        # unmount gio/gvfs MTP mount which blocks libmtp from accessing the device
+        subprocess.run(f"gio mount -u mtp://TinyUsb_TinyUsb_Device_{uid}/",
+                       shell=True, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
         for raw in mtp.detect_devices():
             mtp.device = mtp.mtp.LIBMTP_Open_Raw_Device(ctypes.byref(raw))
             if mtp.device:
                 sn = mtp.get_serialnumber().decode('utf-8')
-                #print(f'mtp serial = {sn}')
                 if sn == uid:
                     return mtp
+                mtp.disconnect()
         time.sleep(1)
         timeout -= 1
     return None
 
 
+def get_printer_dev(id, vendor_str, product_str, ifnum):
+    """Find /dev/usb/lpX by matching USB serial, vendor, product, and interface number via sysfs"""
+    vendor_str = vendor_str.replace(' ', '_') if vendor_str else ''
+    product_str = product_str.replace(' ', '_') if product_str else ''
+    for lp in glob.glob('/sys/class/usbmisc/lp*'):
+        try:
+            sn = open(f'{lp}/device/../serial').read().strip()
+            if sn == id:
+                return f'/dev/usb/{os.path.basename(lp)}'
+        except (FileNotFoundError, PermissionError, ValueError):
+            pass
+    return None
+
+
+def open_printer_dev(id, vendor_str, product_str, ifnum):
+    """Wait for printer device to enumerate and return its path"""
+    timeout = ENUM_TIMEOUT
+    while timeout > 0:
+        lp_dev = get_printer_dev(id, vendor_str, product_str, ifnum)
+        if lp_dev and os.path.exists(lp_dev):
+            return lp_dev
+        time.sleep(1)
+        timeout -= 1
+    assert False, f'Printer device not found for {id} if{ifnum:02d}'
+
+
 # -------------------------------------------------------------
 # Flashing firmware
 # -------------------------------------------------------------
@@ -302,7 +330,7 @@ def flash_esptool(board, firmware):
         idf_target = json.load(f)['IDF_TARGET']
     with open(f'{fw_dir}/flash_args') as f:
         flash_args = f.read().strip().replace('\n', ' ')
-    command = (f'esptool.py --chip {idf_target} -p {port} {flasher["args"]} '
+    command = (f'esptool --chip {idf_target} -p {port} {flasher["args"]} '
                f'--before=default_reset --after=hard_reset write_flash {flash_args}')
     ret = run_cmd(command, cwd=fw_dir)
     return ret
@@ -410,22 +438,22 @@ def test_device_cdc_dual_ports(board):
     sizes = [32, 64, 128, 256, 512, random.randint(2000, 5000)]
 
     def write_and_check(writer, payload):
-        size = len(payload)
+        payload_len = len(payload)
         for s in ser:
             s.reset_input_buffer()
         rd0 = b''
         rd1 = b''
         offset = 0
         # Write in chunks of random 1-64 bytes (device has 64-byte buffer)
-        while offset < size:
-            chunk_size = min(random.randint(1, 64), size - offset)
+        while offset < payload_len:
+            chunk_size = min(random.randint(1, 64), payload_len - offset)
             ser[writer].write(payload[offset:offset + chunk_size])
             ser[writer].flush()
             rd0 += ser[0].read(chunk_size)
             rd1 += ser[1].read(chunk_size)
             offset += chunk_size
-        assert rd0 == payload.lower(), f'Port0 wrong data ({size}): expected {payload.lower()[:16]}... was {rd0[:16]}'
-        assert rd1 == payload.upper(), f'Port1 wrong data ({size}): expected {payload.upper()[:16]}... was {rd1[:16]}'
+        assert rd0 == payload.lower(), f'Port0 wrong data ({payload_len}): expected {payload.lower()}... was {rd0}'
+        assert rd1 == payload.upper(), f'Port1 wrong data ({payload_len}): expected {payload.upper()}... was {rd1}'
 
     for size in sizes:
         payload0 = rand_ascii(size)
@@ -552,6 +580,109 @@ def test_device_hid_composite_freertos(id):
     pass
 
 
+def test_device_printer_to_cdc(board):
+    import threading
+
+    uid = board['uid']
+
+    # Wait for CDC port and printer device
+    cdc_port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
+    ser = open_serial_dev(cdc_port)
+    lp_dev = open_printer_dev(uid, 'TinyUSB', 'TinyUSB_Device', 2)
+
+    # Test 0: Verify IEEE 1284 Device ID from sysfs
+    expected_id = 'MFG:TinyUSB;MDL:Printer to CDC;CMD:PS;CLS:PRINTER;'
+    lp_name = os.path.basename(lp_dev)
+    sysfs_id_path = f'/sys/class/usbmisc/{lp_name}/device/ieee1284_id'
+    if os.path.exists(sysfs_id_path):
+        with open(sysfs_id_path) as f:
+            ieee1284_id = f.read().strip()
+        if ieee1284_id:
+            assert ieee1284_id == expected_id, (f'IEEE 1284 ID mismatch:\n'
+                                                f'  expected: {expected_id}\n  got: {ieee1284_id}')
+
+    def rand_ascii(length):
+        return "".join(random.choices(string.ascii_letters + string.digits, k=length)).encode("ascii")
+
+    sizes = [32, 64, 128, 256, 512, random.randint(2000, 5000)]
+
+    # flush any stale data
+    ser.reset_input_buffer()
+
+    # Test 1: Printer -> CDC with multiple sizes, write in random 1-64 byte chunks
+    for size in sizes:
+        test_data = rand_ascii(size)
+        ser.reset_input_buffer()
+        rd = b''
+        offset = 0
+        with open(lp_dev, 'wb') as lp:
+            while offset < size:
+                chunk_size = min(random.randint(1, 64), size - offset)
+                lp.write(test_data[offset:offset + chunk_size])
+                lp.flush()
+                rd += ser.read(chunk_size)
+                offset += chunk_size
+        # read any remaining bytes (fullspeed devices may need extra time)
+        while len(rd) < size:
+            remaining = ser.read(size - len(rd))
+            if not remaining:
+                break
+            rd += remaining
+        assert rd == test_data, (f'Printer->CDC wrong data ({size} bytes):\n'
+                                 f'  expected: {test_data[:64]}\n  received: {rd[:64]}')
+
+    # Test 2: CDC -> Printer with multiple sizes, write in random 1-64 byte chunks
+    # Use a thread to read from printer since /dev/usb/lp read blocks
+    ser.reset_input_buffer()
+    time.sleep(0.5)
+    for size in sizes:
+        test_data = rand_ascii(size)
+        rd_result = [b'', None]  # [data, error]
+        reader_ready = threading.Event()
+
+        def lp_reader():
+            try:
+                rd = b''
+                fd = os.open(lp_dev, os.O_RDONLY)
+                reader_ready.set()
+                try:
+                    while len(rd) < size:
+                        chunk = os.read(fd, min(64, size - len(rd)))
+                        if not chunk:
+                            break
+                        rd += chunk
+                finally:
+                    os.close(fd)
+                rd_result[0] = rd
+            except Exception as e:
+                rd_result[1] = e
+                reader_ready.set()
+
+        reader = threading.Thread(target=lp_reader, daemon=True)
+        reader.start()
+        # wait for reader to open lp device before writing
+        reader_ready.wait(timeout=5)
+        time.sleep(0.1)
+
+        # Write to CDC in small chunks with flush to avoid overflowing device FIFO
+        offset = 0
+        while offset < size:
+            chunk_size = min(random.randint(1, 64), size - offset)
+            ser.write(test_data[offset:offset + chunk_size])
+            ser.flush()
+            time.sleep(0.01)
+            offset += chunk_size
+
+        reader.join(timeout=10)
+        assert not reader.is_alive(), f'CDC->Printer timeout ({size} bytes)'
+        assert rd_result[1] is None, f'CDC->Printer read error: {rd_result[1]}'
+        assert rd_result[0] == test_data, (f'CDC->Printer wrong data ({size} bytes):\n'
+                                           f'  expected: {test_data[:64]}\n  received: {rd_result[0][:64]}')
+        time.sleep(0.2)
+
+    ser.close()
+
+
 def test_device_mtp(board):
     uid = board['uid']
 
@@ -623,7 +754,8 @@ device_tests = [
     'device/dfu_runtime',
     'device/cdc_msc_freertos',
     'device/hid_boot_interface',
-    # 'device/mtp'
+    'device/printer_to_cdc',
+    'device/mtp'
 ]
 
 dual_tests = [
diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json
index 047d0879c..029e5ffcd 100644
--- a/test/hil/tinyusb.json
+++ b/test/hil/tinyusb.json
@@ -13,7 +13,8 @@
             "flasher": {
                 "name": "esptool",
                 "uid": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54",
-                "args": "-b 1500000"
+                "args": "-b 1500000",
+                "comment": "use --force for ESP32-P4 v0.1"
             },
             "comment": "Use TS3USB30 mux to test both device and host"
         },
@@ -107,7 +108,6 @@
                 "host": false,
                 "dual": false
             },
-            "comment": "MSC is slow to enumerated #2602",
             "flasher": {
                 "name": "jlink",
                 "uid": "000831174392",
diff --git a/tools/build.py b/tools/build.py
index 87064b7a0..3c5c3c077 100755
--- a/tools/build.py
+++ b/tools/build.py
@@ -24,7 +24,6 @@ build_separator = '-' * 95
 build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED]
 
 verbose = False
-clean_build = False
 parallel_jobs = os.cpu_count()
 
 # CI board control lists (used when running under CI)
@@ -40,7 +39,9 @@ ci_skip_boards = {
 }
 
 ci_preferred_boards = {
-    'stm32h7': ['stm32h743eval'],
+    'samd2x_l2x': ['metro_m0_express'],
+    'samd5x_e5x': ['metro_m4_express'],
+    'stm32h7': ['stm32h743eval']
 }
 
 
@@ -96,15 +97,15 @@ def get_examples(family):
     return all_examples
 
 
-def print_build_result(board, example, status, duration):
+def print_build_result(board, build_target, status, duration):
     if isinstance(duration, (int, float)):
         duration = "{:.2f}s".format(duration)
-    print(build_format.format(board, example, build_status[status], duration))
+    print(build_format.format(board, build_target, build_status[status], duration))
 
 # -----------------------------
 # CMake
 # -----------------------------
-def cmake_board(board, build_args, build_flags_on):
+def cmake_board(board, build_args, build_flags_on, build_targets):
     ret = [0, 0, 0]
     start_time = time.monotonic()
 
@@ -133,39 +134,36 @@ def cmake_board(board, build_args, build_flags_on):
                         f'-DBOARD={board}', '-DCMAKE_BUILD_TYPE=MinSizeRel', '-DLINKERMAP_OPTION=-q -f tinyusb/src',
                         *build_args, *build_flags])
         if rcmd.returncode == 0:
-            if clean_build:
-                run_cmd(["cmake", "--build", build_dir, '--target', 'clean'])
             cmd = ["cmake", "--build", build_dir, '--parallel', str(parallel_jobs)]
-            rcmd = run_cmd(cmd)
-        if rcmd.returncode == 0:
-            ret[0] += 1
-            run_cmd(["cmake", "--build", build_dir, '--target', 'tinyusb_metrics'])
-            # print(rcmd.stdout.decode("utf-8"))
-        else:
-            ret[1] += 1
+            for target in build_targets:
+                rcmd = run_cmd(cmd + ['--target', target])
+                if rcmd.returncode != 0:
+                    break
+        ret[0 if rcmd.returncode == 0 else 1] += 1
 
-    example = 'all'
-    print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+    print_build_result(board, ','.join(build_targets), 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
     return ret
 
 
 # -----------------------------
 # Make
 # -----------------------------
-def make_one_example(example, board, make_option):
+def make_one_example(example, board, make_option, build_targets):
     # Check if board is skipped
     if build_utils.skip_example(example, board):
         print_build_result(board, example, 2, '-')
         r = 2
     else:
         start_time = time.monotonic()
-        make_args = ["make", "-C", f"examples/{example}", f"BOARD={board}", '-j', str(parallel_jobs)]
+        make_cmd = ["make", "-C", f"examples/{example}", f"BOARD={board}", '-j', str(parallel_jobs)]
         if make_option:
-            make_args += shlex.split(make_option)
-        if clean_build:
-            run_cmd(make_args + ["clean"])
-        build_result = run_cmd(make_args + ['all'])
-        r = 0 if build_result.returncode == 0 else 1
+            make_cmd += shlex.split(make_option)
+        r = 0
+        for target in build_targets:
+            build_result = run_cmd(make_cmd + [target])
+            if build_result.returncode != 0:
+                r = 1
+                break
         print_build_result(board, example, r, time.monotonic() - start_time)
 
     ret = [0, 0, 0]
@@ -173,7 +171,7 @@ def make_one_example(example, board, make_option):
     return ret
 
 
-def make_board(board, build_args):
+def make_board(board, build_args, build_targets):
     print(build_separator)
     family = find_family(board);
     all_examples = get_examples(family)
@@ -184,7 +182,7 @@ def make_board(board, build_args):
         final_status = 2
     else:
         with Pool(processes=os.cpu_count()) as pool:
-            pool_args = list((map(lambda e, b=board, o=f"{build_args}": [e, b, o], all_examples)))
+            pool_args = list((map(lambda e, b=board, o=f"{build_args}", t=build_targets: [e, b, o, t], all_examples)))
             r = pool.starmap(make_one_example, pool_args)
             # sum all element of same index (column sum)
             ret = list(map(sum, list(zip(*r))))
@@ -196,16 +194,16 @@ def make_board(board, build_args):
 # -----------------------------
 # Build Family
 # -----------------------------
-def build_boards_list(boards, build_defines, build_system, build_flags_on):
+def build_boards_list(boards, build_defines, build_system, build_flags_on, build_targets):
     ret = [0, 0, 0]
     for b in boards:
         r = [0, 0, 0]
         if build_system == 'cmake':
             build_args = [f'-D{d}' for d in build_defines]
-            r = cmake_board(b, build_args, build_flags_on)
+            r = cmake_board(b, build_args, build_flags_on, build_targets)
         elif build_system == 'make':
             build_args = ' '.join(f'{d}' for d in build_defines)
-            r = make_board(b, build_args)
+            r = make_board(b, build_args, build_targets)
         ret[0] += r[0]
         ret[1] += r[1]
         ret[2] += r[2]
@@ -255,13 +253,11 @@ def get_family_boards(family, one_random, one_first):
 # -----------------------------
 def main():
     global verbose
-    global clean_build
     global parallel_jobs
 
     parser = argparse.ArgumentParser()
     parser.add_argument('families', nargs='*', default=[], help='Families to build')
     parser.add_argument('-b', '--board', action='append', default=[], help='Boards to build')
-    parser.add_argument('-c', '--clean', action='store_true', default=False, help='Clean before build')
     parser.add_argument('-t', '--toolchain', default='gcc', help='Toolchain to use, default is gcc')
     parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake')
     parser.add_argument('-D', '--define-symbol', action='append', default=[], help='Define to pass to build system')
@@ -271,6 +267,8 @@ def main():
     parser.add_argument('--one-first', action='store_true', default=False,
                         help='Build only the first board (alphabetical) of each specified family')
     parser.add_argument('-j', '--jobs', type=int, default=os.cpu_count(), help='Number of jobs to run in parallel')
+    parser.add_argument('-T', '--target', action='append', default=[],
+                        help='Build target to use, may be specified multiple times (default: all)')
     parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
     args = parser.parse_args()
 
@@ -282,8 +280,8 @@ def main():
     build_flags_on = args.build_flags_on
     one_random = args.one_random
     one_first = args.one_first
+    build_targets = args.target if args.target else ['all']
     verbose = args.verbose
-    clean_build = args.clean
     parallel_jobs = args.jobs
 
     build_defines.append(f'TOOLCHAIN={toolchain}')
@@ -293,7 +291,7 @@ def main():
         return 1
 
     print(build_separator)
-    print(build_format.format('Board', 'Example', '\033[39mResult\033[0m', 'Time'))
+    print(build_format.format('Board', 'Target', '\033[39mResult\033[0m', 'Time'))
     total_time = time.monotonic()
 
     # get all families
@@ -312,7 +310,7 @@ def main():
         all_boards.extend(get_family_boards(f, one_random, one_first))
 
     # build all boards
-    result = build_boards_list(all_boards, build_defines, build_system, build_flags_on)
+    result = build_boards_list(all_boards, build_defines, build_system, build_flags_on, build_targets)
 
     total_time = time.monotonic() - total_time
     print(build_separator)
diff --git a/tools/codespell/ignore-words.txt b/tools/codespell/ignore-words.txt
index 957cbd86b..7ce778fab 100644
--- a/tools/codespell/ignore-words.txt
+++ b/tools/codespell/ignore-words.txt
@@ -1,14 +1,16 @@
-synopsys
-sie
-tre
-thre
-hsi
-fro
-dout
-mot
-te
 attch
+busses
+dout
 endianess
+fro
+hsi
+inout
+mot
 pris
-busses
+ptd
 ser
+sie
+synopsys
+te
+thre
+tre
diff --git a/tools/get_deps.py b/tools/get_deps.py
index deacbb23b..bf91428f4 100755
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -14,6 +14,9 @@ deps_mandatory = {
     'lib/lwip': ['https://github.com/lwip-tcpip/lwip.git',
                  '159e31b689577dbf69cf0683bbaffbd71fa5ee10',
                  'all'],
+    'lib/threadx': ['https://github.com/eclipse-threadx/threadx.git',
+                    '4b6e8100d932a3a67b34c6eb17f84f3bffb9e2ae',
+                    'all'],
     'tools/linkermap': ['https://github.com/hathach/linkermap.git',
                         '8e1f440fa15c567aceb5aa0d14f6d18c329cc67f',
                         'all'],
@@ -45,7 +48,7 @@ deps_optional = {
                                         'xmc4000'],
     'hw/mcu/microchip': ['https://github.com/hathach/microchip_driver.git',
                          '9e8b37e307d8404033bb881623a113931e1edf27',
-                         'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg'],
+                         'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x samd2x_l2x samg'],
     'hw/mcu/mindmotion/mm32sdk': ['https://github.com/hathach/mm32sdk.git',
                                   'b93e856211060ae825216c6a1d6aa347ec758843',
                                   'mm32'],
@@ -58,9 +61,18 @@ deps_optional = {
     'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
                            'b41cf930e65c734d8ec6de04f1d57d46787c76ae',
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
+    'hw/mcu/nxp/mcuxsdk-core': ['https://github.com/nxp-mcuxpresso/mcuxsdk-core',
+                            '0c5c6b16deb211110e06bde896cdff59ab213e16',
+                            'lpc51 lpc55 mcx'],
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk',
                             'a1bdae309a14ec95a4f64a96d3315a4f89c397c6',
-                            'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x imxrt'],
+                            'kinetis_k kinetis_k32l2 kinetis_kl lpc54 rw61x imxrt'],
+    'hw/mcu/nxp/mcux-devices-lpc': ['https://github.com/nxp-mcuxpresso/mcux-devices-lpc',
+                            '8096b783ec09d0d1c8629025a5f9d8e7df26e520',
+                            'lpc51 lpc55'],
+    'hw/mcu/nxp/mcux-devices-mcx': ['https://github.com/nxp-mcuxpresso/mcux-devices-mcx',
+                            'ada1c97c761123ec0c179bb9bb9f744bf9a11475',
+                            'mcx'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
                                          '675543bcc9baa8170f868ab7ba316d418dbcf41f',
                                          'rp2040'],
@@ -209,7 +221,7 @@ deps_optional = {
                                        '9442fbb71f855ff2e64fbf662b7726beba511a24',
                                        'stm32wba'],
     'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git',
-                  '143ed6cc20a7615d042b03b21e070197d473e6e5',
+                  '083944907e7d08fcb1f614b47598ce45935b8da1',
                   'msp430 msp432e4 tm4c'],
     'hw/mcu/wch/ch32v103': ['https://github.com/openwch/ch32v103.git',
                             '7578cae0b21f86dd053a1f781b2fc6ab99d0ec17',
@@ -244,20 +256,23 @@ deps_optional = {
     'hw/mcu/artery/at32f413': ['https://github.com/ArteryTek/AT32F413_Firmware_Library.git',
                                'f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450',
                                'at32f413'],
+    'hw/mcu/artery/at32f45x': ['https://github.com/ArteryTek/AT32F45x_Firmware_Library.git',
+                               '3d4a1b38be8ebac292e2350ca53bc4bfa4430233',
+                               'at32f45x'],
     'hw/mcu/hpmicro/hpm_sdk': ['https://github.com/hpmicro/hpm_sdk',
                                '8d2af741ecc4aaa82d7ee395dc1ce25d7070c3ff',
                                'hpmicro'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
-                    'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf saml2x '
+                    'imxrt kinetis_k kinetis_k32l2 kinetis_kl lpc54 rw61x mm32 msp432e4 nrf samd2x_l2x '
                     'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
                     'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
                     'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u0 stm32u5 stm32wb stm32wba '
-                    'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg '
+                    'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x samd2x_l2x samg '
                     'tm4c '],
     'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git',
                     '6f0a58d01aa9bd2feba212097f9afe7acd991d52',
-                    'ra stm32n6'],
+                    'ra stm32n6 lpc51 lpc55 mcx'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',
                          'lpc55'],
@@ -327,18 +342,16 @@ def main():
     parser.add_argument('-b', '--board', action='append', default=[], help='Boards to fetch')
     parser.add_argument('-D', '--define', action='append', default=[], help='Have no effect')
     parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Have no effect')
-    parser.add_argument('--print', action='store_true', help='Print commit hash only')
     args = parser.parse_args()
 
     families = args.families
     boards = args.board
-    print_only = args.print
 
     status = 0
-    deps = list(deps_mandatory.keys())
+    deps = []
 
     if 'all' in families:
-        deps += deps_optional.keys()
+        deps.extend(deps_optional.keys())
     else:
         families = list(families)
         if boards is not None:
@@ -346,24 +359,16 @@ def main():
                 f = find_family(b)
                 if f is not None:
                     families.append(f)
-
         for f in families:
             for d in deps_optional:
                 if d not in deps and f in deps_optional[d][2].split():
                     deps.append(d)
+        if len(deps) == 0:
+            print('WARN: no additional dependencies found for given boards or families')
 
-    if print_only:
-        pvalue = {}
-        # print only without arguments, always add CMSIS_5
-        if len(families) == 0 and len(boards) == 0:
-            deps.append('lib/CMSIS_5')
-        for d in deps:
-            commit = deps_all[d][1]
-            pvalue[d] = commit
-        print(pvalue)
-    else:
-        with Pool() as pool:
-            status = sum(pool.map(get_a_dep, deps))
+    deps.extend(deps_mandatory.keys())
+    with Pool() as pool:
+        status = sum(pool.map(get_a_dep, deps))
     return status
 
 
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index caddda826..035e40b94 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -69,6 +69,11 @@
             <path>$TUSB_DIR$/src/class/net/ncm.h</path>
             <path>$TUSB_DIR$/src/class/net/net_device.h</path>
         </group>
+        <group name="src/class/printer">
+            <path>$TUSB_DIR$/src/class/printer/printer_device.c</path>
+            <path>$TUSB_DIR$/src/class/printer/printer.h</path>
+            <path>$TUSB_DIR$/src/class/printer/printer_device.h</path>
+        </group>
         <group name="src/class/usbtmc">
             <path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
             <path>$TUSB_DIR$/src/class/usbtmc/usbtmc.h</path>
author	hathach <[email protected]>	2026-03-11 13:34:59 +0700
committer	hathach <[email protected]>	2026-03-11 13:34:59 +0700
commit	336e89792f9b572c5087b1df479d4e89542f6360 (patch)
tree	866a0acbf5dbc952b183768f2b916ff9fe36a591
parent	60154a128795bcd6ca36042cac1b8bebf1a2764e (diff)
parent	7249c65b2a5b995ff7c2b45c1171f218b9d71112 (diff)