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authorWilliam D. Jones <[email protected]>2019-09-19 01:21:29 -0400
committerWilliam D. Jones <[email protected]>2019-09-19 01:21:29 -0400
commit49f2507b3824260bcb5df3a8c740dd935ac21149 (patch)
tree67d12811b285eea322493623bd933563855157b2
parent772b0c17bf59df89bfc011b6c97cb63612afa8b8 (diff)
msp_exp430f5529lp: Implement enough functionality for board_test.
-rw-r--r--hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c65
1 files changed, 62 insertions, 3 deletions
diff --git a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c
index fe904b12b..5fa69465d 100644
--- a/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c
+++ b/hw/bsp/msp_exp430f5529lp/msp_exp430f5529lp.c
@@ -36,15 +36,66 @@
#define BUTTON_PIN BIT1
#define BUTTON_STATE_ACTIVE 1
-
static void SystemClock_Config(void)
{
+ WDTCTL = WDTPW + WDTHOLD; // Disable watchdog.
+
+ // Increase VCore to level 2- required for 16 MHz operation on this MCU.
+ PMMCTL0 = PMMPW + PMMCOREV_2;
+
+ UCSCTL3 = SELREF__XT2CLK; // FLL is fed by XT2.
+
+ // XT1 used for ACLK (default- not used in this demo)
+ P5SEL |= BIT4; // Required to enable XT1
+ // Loop until XT1 fault flag is cleared.
+ do
+ {
+ UCSCTL7 &= ~XT1LFOFFG;
+ }while(UCSCTL7 & XT1LFOFFG);
+
+ // XT2 is 4 MHz an external oscillator, use PLL to boost to 16 MHz.
+ P5SEL |= BIT2; // Required to enable XT2.
+ // Loop until XT2 fault flag is cleared
+ do
+ {
+ UCSCTL7 &= ~XT2OFFG;
+ }while(UCSCTL7 & XT2OFFG);
+ // Kickstart the DCO into the correct frequency range, otherwise a
+ // fault will occur.
+ // FIXME: DCORSEL_6 should work according to datasheet params, but generates
+ // a fault. I am not sure why it faults.
+ UCSCTL1 = DCORSEL_7;
+ UCSCTL2 = FLLD_2 + 3; // DCO freq = D * (N + 1) * (FLLREFCLK / n)
+ // DCOCLKDIV freq = (N + 1) * (FLLREFCLK / n)
+ // N = 3, D = 2, thus DCO freq = 32 MHz.
+
+ // MCLK configured for 16 MHz using XT2.
+ // SMCLK configured for 8 MHz using XT2.
+ UCSCTL4 |= SELM__DCOCLKDIV + SELS__DCOCLKDIV;
+ UCSCTL5 |= DIVM__16 + DIVS__2;
+
+ // Now wait till everything's stabilized.
+ do
+ {
+ UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
+ SFRIFG1 &= ~OFIFG;
+ }while(SFRIFG1 & OFIFG);
+
+ // Configure Timer A to use SMCLK as a source. Count 1000 ticks at 1 MHz.
+ TA0CCTL0 |= CCIE;
+ TA0CCR0 = 999; // 1000 ticks.
+ TA0CTL |= TASSEL_2 + ID_3 + MC__UP; // Use SMCLK, divide by 8, start timer.
}
void board_init(void)
{
SystemClock_Config();
+ __bis_SR_register(GIE); // Enable interrupts.
+
+ P1DIR |= LED_PIN; // LED output.
+ P1REN |= BUTTON_PIN; // Internal resistor enable.
+ P1OUT |= BUTTON_PIN; // Pullup.
}
//--------------------------------------------------------------------+
@@ -53,12 +104,19 @@ void board_init(void)
void board_led_write(bool state)
{
-
+ if(state)
+ {
+ LED_PORT |= LED_PIN;
+ }
+ else
+ {
+ LED_PORT &= ~LED_PIN;
+ }
}
uint32_t board_button_read(void)
{
- return 0;
+ return (P1IN & BIT1);
}
#if CFG_TUSB_OS == OPT_OS_NONE
@@ -66,6 +124,7 @@ volatile uint32_t system_ticks = 0;
void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void)
{
system_ticks++;
+ // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked.
}
uint32_t board_millis(void)