lpc55 correct bus_reset with highspeed on support controller

correct hsphy init for family

3 files changed, 84 insertions, 37 deletions

diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index c11c74e4d..ba16a93ab 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -164,43 +164,71 @@ void board_init(void)
   /* PORT0 PIN22 configured as USB0_VBUS */
   IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
 
-  // USB Controller
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB0 Phy */
-  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*< Turn on USB1 Phy */
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  // Port0 is Full Speed
+
+  /* Turn on USB0 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
 
   /* reset the IP to make sure it's in reset state. */
   RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
 
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-  CLOCK_EnableClock(kCLOCK_Usbh1);
-  /* Put PHY powerdown under software control */
-  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
-  /* According to reference mannual, device mode setting has to be set by access usb host register */
-  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
-  /* enable usb1 host clock */
-  CLOCK_DisableClock(kCLOCK_Usbh1);
-#endif
-
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
   // Enable USB Clock Adjustments to trim the FRO for the full speed controller
   ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
   CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
   CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-  /* enable usb0 host clock */
-  CLOCK_EnableClock(kCLOCK_Usbhsl0);
+
   /*According to reference mannual, device mode setting has to be set by access usb host register */
+  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
   USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-  /* disable usb0 host clock */
-  CLOCK_DisableClock(kCLOCK_Usbhsl0);
-  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB Device clock */
+  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+
+  /* enable USB Device clock */
+  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
 #endif
 
+#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+  // Port1 is High Speed
+
+  /* Turn on USB1 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
+
+  /* reset the IP to make sure it's in reset state. */
+  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
+
+  /* According to reference mannual, device mode setting has to be set by access usb host register */
+  CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+
+  USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
+  USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+
+  CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+
+  /* enable USB Device clock */
+  CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
+  CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
+  //USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, NULL);
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  USBPHY->PWD = 0;
+
+  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
+  USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
+
+  // TX Timing
+//  uint32_t phytx = USBPHY->TX;
+//  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+//  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+//  USBPHY->TX = phytx;
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index f22387984..090d9e602 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -61,11 +61,6 @@
 // 2000 0000 to 203F FFFF
 #define SRAM_REGION   0x20000000
 
-// Absolute max of endpoints pairs for all port
-// - 11 13 15 51 54 has 5x2 endpoints
-// - 55 usb0 (FS) has 5x2 endpoints, usb1 (HS) has 6x2 endpoints
-#define MAX_EP_PAIRS  6
-
 //--------------------------------------------------------------------+
 // IP3511 Registers
 //--------------------------------------------------------------------+
@@ -107,14 +102,19 @@ enum {
   CMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
   CMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
   CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), ///< reflect the soft-connect only, does not reflect the actual attached state
+  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
   CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
+                                            // 23-22 is link speed (only available for HighSpeed port)
   CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
   CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
   CMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
   CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
 };
 
+enum {
+  CMDSTAT_SPEED_SHIFT = 22
+};
+
 //--------------------------------------------------------------------+
 // Endpoint Command/Status List
 //--------------------------------------------------------------------+
@@ -143,6 +143,11 @@ typedef struct
   uint16_t nbytes;
 }xfer_dma_t;
 
+// Absolute max of endpoints pairs for all port
+// - 11 13 15 51 54 has 5x2 endpoints
+// - 55 usb0 (FS) has 5x2 endpoints, usb1 (HS) has 6x2 endpoints
+#define MAX_EP_PAIRS  6
+
 // NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
 // current_td is used to keep track of number of remaining & xferred bytes of the current request.
 typedef struct
@@ -150,8 +155,8 @@ typedef struct
   // 256 byte aligned, 2 for double buffer (not used)
   // Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
   ep_cmd_sts_t ep[2*MAX_EP_PAIRS][2];
-
   xfer_dma_t dma[2*MAX_EP_PAIRS];
+
   TU_ATTR_ALIGNED(64) uint8_t setup_packet[8];
 }dcd_data_t;
 
@@ -164,24 +169,25 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
 typedef struct
 {
-  dcd_registers_t* regs;  // registers
-  const IRQn_Type irqnum; // IRQ number
-  const uint8_t ep_pairs; // Max bi-directional Endpoints
+  dcd_registers_t* regs;        // registers
+  const tusb_speed_t max_speed; // max link speed
+  const IRQn_Type irqnum;       // IRQ number
+  const uint8_t ep_pairs;       // Max bi-directional Endpoints
 }dcd_controller_t;
 
 #ifdef INCLUDE_FSL_DEVICE_REGISTERS
   static const dcd_controller_t _dcd_controller[] =
   {
-      { .regs = (dcd_registers_t*) USB0_BASE  , .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
+      { .regs = (dcd_registers_t*) USB0_BASE  , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
     #if FSL_FEATURE_SOC_USBHSD_COUNT
-      { .regs = (dcd_registers_t*) USBHSD_BASE, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
+      { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
     #endif
   };
 
 #else
   static const dcd_controller_t _dcd_controller[] =
   {
-    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_pairs = 5 },
+    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
   };
 
 #endif
@@ -405,7 +411,19 @@ void dcd_int_handler(uint8_t rhport)
     if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
     {
       bus_reset(rhport);
-      dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+
+      tusb_speed_t speed = TUSB_SPEED_FULL;
+
+      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
+      {
+        // 0 : reserved, 1 : full, 2 : high, 3: super
+        if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
+        {
+          speed= TUSB_SPEED_HIGH;
+        }
+      }
+
+      dcd_event_bus_reset(rhport, speed, true);
     }
 
     if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index afc7184a0..eeab3f487 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -34,6 +34,7 @@
 //--------------------------------------------------------------------+
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #include "fsl_device_registers.h"
+  #define INCLUDE_FSL_DEVICE_REGISTERS
 #else
   // LPCOpen for 18xx & 43xx
   #include "chip.h"