diff options
| author | hathach <[email protected]> | 2014-03-12 18:39:17 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2014-03-12 18:39:17 +0700 |
| commit | 97f95c61f6f0c3a8e0a6f32889605be1a1e09cdd (patch) | |
| tree | 46c740660c8fec8461693c11c025432d8b7e9e5d | |
| parent | 439d4d96523a1ff8ad9c4c1468bb13e7fb41af62 (diff) | |
update CMSIS core for lpc176x
| -rw-r--r-- | demos/host/host_os_none/.cproject | 171 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/history.txt | 14 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h | 8 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cm3.h | 917 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h | 249 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h | 230 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h | 8 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/core_cm3.c | 339 | ||||
| -rw-r--r-- | mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c | 18 |
9 files changed, 1030 insertions, 924 deletions
diff --git a/demos/host/host_os_none/.cproject b/demos/host/host_os_none/.cproject index fa2d7a188..a6fe035f7 100644 --- a/demos/host/host_os_none/.cproject +++ b/demos/host/host_os_none/.cproject @@ -30,7 +30,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1178085975" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.1677456292" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.597047349" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.2146151354" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.2146151354" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.1396414714" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.161831329" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -55,7 +55,7 @@ <inputType id="com.crt.advproject.compiler.input.217124913" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.1376287865" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.1664735680" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.1664735680" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.572061543" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.884423800" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<option id="com.crt.advproject.gas.fpu.1152943186" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
@@ -64,7 +64,7 @@ </tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.893594288" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.1137849179" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.1187341700" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.1187341700" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.981715979" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.2116791390" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_NGX4330.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.1536072802" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -1590,7 +1590,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1432862600" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.964171687" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.502985594" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.625803892" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.625803892" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.1149795974" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.510918973" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -1615,7 +1615,7 @@ <inputType id="com.crt.advproject.compiler.input.772057054" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.973267950" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.733211533" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.733211533" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.154920324" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.220166654" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<option id="com.crt.advproject.gas.fpu.464699791" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
@@ -1624,7 +1624,7 @@ </tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.1510590263" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.1770663329" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.1264750550" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.1264750550" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.1129500777" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.1484718299" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_EA4357.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.887685321" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -3151,7 +3151,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1444344547" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.656829956" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.1095637333" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.1911872066" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.1911872066" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.48684905" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1721043515" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -3176,7 +3176,7 @@ <inputType id="com.crt.advproject.compiler.input.130411912" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.760022328" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.241619580" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.241619580" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.1962077087" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.2091558138" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<option id="com.crt.advproject.gas.fpu.1836381477" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
@@ -3185,7 +3185,7 @@ </tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.715527269" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.1597810635" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.91564752" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.91564752" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.536182609" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.592341149" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_MCB4300.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.1327431085" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -4711,7 +4711,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1516348025" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.699856147" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.2004768424" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.14610984" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.14610984" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.1843997599" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1076286246" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -4736,7 +4736,7 @@ <inputType id="com.crt.advproject.compiler.input.665307127" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.1153718858" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.1294161771" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.1294161771" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.601862595" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.1873433762" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<option id="com.crt.advproject.gas.fpu.508514296" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
@@ -4745,7 +4745,7 @@ </tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.1263316338" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.1516575641" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.513380275" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.513380275" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.1951335248" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.1050076157" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_Hitex4350.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.19303590" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -6271,7 +6271,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.461931673" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.1477382307" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.1697270528" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.114241566" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.114241566" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.1955499807" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1199696484" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -6295,7 +6295,7 @@ <inputType id="com.crt.advproject.compiler.input.1484600680" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.114684693" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.1766999311" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.1766999311" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.1230003385" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.364080237" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<inputType id="com.crt.advproject.assembler.input.53005881" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
@@ -6303,7 +6303,7 @@ </tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.754491315" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.906566981" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.967278694" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.967278694" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.1538519930" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.852885755" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_LPC4357USB.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.1045150248" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -7828,7 +7828,7 @@ <builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.335566651" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.1207646747" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.1892359128" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
- <option id="com.crt.advproject.gcc.arch.1922208309" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.arch.1922208309" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.2045365493" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1650588201" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -7841,7 +7841,7 @@ </option>
<option id="gnu.c.compiler.option.misc.other.1566376313" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections" valueType="string"/>
<option id="gnu.c.compiler.option.include.paths.643947484" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/mcu/lpc175x_6x/CMSISv2p00_LPC17xx/inc}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc}""/>
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/mcu/lpc175x_6x/LPC17xx_DriverLib/include}""/>
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/fatfs}""/>
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/boards}""/>
@@ -7849,20 +7849,20 @@ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
</option>
<option id="com.crt.advproject.c.misc.dialect.455591496" name="C Dialect" superClass="com.crt.advproject.c.misc.dialect" value="com.crt.advproject.misc.dialect.gnu99" valueType="enumerated"/>
- <option id="com.crt.advproject.gcc.fpu.2023059993" name="Floating point" superClass="com.crt.advproject.gcc.fpu" value="com.crt.advproject.gcc.fpu.fpv4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gcc.fpu.2023059993" name="Floating point" superClass="com.crt.advproject.gcc.fpu" value="com.crt.advproject.gcc.fpu.none" valueType="enumerated"/>
<inputType id="com.crt.advproject.compiler.input.2013630692" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.888595290" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
- <option id="com.crt.advproject.gas.arch.1325678596" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.arch.1325678596" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.635946568" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.194674049" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
- <option id="com.crt.advproject.gas.fpu.280334081" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
+ <option id="com.crt.advproject.gas.fpu.280334081" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.none" valueType="enumerated"/>
<inputType id="com.crt.advproject.assembler.input.556629189" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1329754856" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.2052352042" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.89021864" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
- <option id="com.crt.advproject.link.arch.1924063030" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.arch.1924063030" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.62526492" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.448095773" name="Linker script" superClass="com.crt.advproject.link.script" value=""host_os_none_Board_LPCXpresso1769.ld"" valueType="string"/>
<option id="com.crt.advproject.link.manage.431533256" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -7874,7 +7874,7 @@ <option id="gnu.c.link.option.libs.1868402007" name="Libraries (-l)" superClass="gnu.c.link.option.libs"/>
<option id="gnu.c.link.option.paths.943091458" name="Library search path (-L)" superClass="gnu.c.link.option.paths"/>
<option id="com.crt.advproject.link.gcc.hdrlib.961930336" name="Use C library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.codered.semihost" valueType="enumerated"/>
- <option id="com.crt.advproject.link.fpu.837495348" name="Floating point" superClass="com.crt.advproject.link.fpu" value="com.crt.advproject.link.fpu.fpv4" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.fpu.837495348" name="Floating point" superClass="com.crt.advproject.link.fpu" value="com.crt.advproject.link.fpu.none" valueType="enumerated"/>
<option id="com.crt.advproject.link.gcc.multicore.slave.92784419" name="Multicore slave" superClass="com.crt.advproject.link.gcc.multicore.slave"/>
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1609667925" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
@@ -9369,86 +9369,73 @@ <storageModule moduleId="com.crt.config">
<projectStorage><?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/>
-<infoList vendor="NXP"><info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4357</name>
-<family>LPC43xx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name>
+<family>LPC17xx</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/>
-<memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
-<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
-<prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
-<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
-<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
-<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
-<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/>
-<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/>
-<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/>
-<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/>
-<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/>
-<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/>
-<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/>
-<peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/>
-<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/>
-<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/>
-<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/>
-<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/>
-<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/>
-<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/>
-<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/>
-<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/>
-<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/>
-<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/>
-<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/>
-<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/>
-<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/>
-<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/>
-<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/>
-<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/>
-<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/>
-<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/>
-<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/>
-<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/>
-<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/>
-<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/>
-<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/>
-<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/>
-<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/>
-<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/>
-<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/>
-<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/>
-<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/>
-<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/>
-<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/>
-<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/>
-<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/>
-<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/>
-<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/>
-<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/>
-<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/>
-<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/>
-<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/>
-<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/>
-<peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/>
-<peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/>
+<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/>
+<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&amp;0x1" id="RIT" location="0x400B0000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/>
+<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/>
+<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/>
+<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
+<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/>
+<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/>
+<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/>
+<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/>
+<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/>
+<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/>
+<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/>
+<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
+<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/>
+<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/>
+<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/>
+<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/>
+<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/>
+<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
+<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
+<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/>
+<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
+<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/>
+<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
+<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
+<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
+<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
+<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/>
+<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/>
+<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/>
+<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/>
+<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/>
+<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
</chip>
-<processor><name gcc_name="cortex-m4">Cortex-M4</name>
+<processor><name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig></projectStorage>
diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/history.txt b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/history.txt index 6683262d5..fe1ebd85f 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/history.txt +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/history.txt @@ -1,3 +1,16 @@ +History of updates to CMSIS_CORE_LPC17xx +=========================================== + +18 July 2013 +------------ +CMSIS library project using ARM Cortex-M0 CMSIS files as +supplied in ARM's CMSIS 3.20 March 2013 release, together +with NXP's device specific files taken from old +CMSISv2p00_LPC17xx project. + +Note files are built -Os for both Debug and Release + + History of updates to CMSISv2p00_LPC17xx ======================================== @@ -9,4 +22,3 @@ December 2010 release, together with device/board specific files from NXP (as previously supplied in CMSISv1p30_LPC17xx library project, dated 24 Aug 2010). -Note files are built -Os for both Debug and Release
\ No newline at end of file diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h index 7df6d5ffb..377fdf240 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h @@ -1,6 +1,6 @@ /**************************************************************************//** * @file LPC17xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for * NXP LPC17xx Device Series * @version: V1.09 * @date: 17. March 2010 @@ -10,9 +10,9 @@ * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cm3.h b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cm3.h index 4847a18d2..122c9aa4a 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cm3.h +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cm3.h @@ -1,25 +1,40 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.01 - * @date 06. December 2010 + * @version V3.20 + * @date 25. February 2013 * * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif @@ -31,95 +46,148 @@ #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: -/** \mainpage CMSIS Cortex-M3 + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration - List of Lint messages which will be suppressed and not shown: - - not yet checked - . - Note: To re-enable a Message, insert a space before 'lint' * + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number +/** \ingroup Cortex_M3 @{ */ /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x03) /*!< Cortex core */ +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ -#if defined ( __CC_ARM ) +#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) +#elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) +#elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline #endif -#include <stdint.h> /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 -#endif /* __CORE_CM3_H_GENERIC */ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + /* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ #ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ + #define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< defines 'read only' permissions */ + #define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ -/*@} end of group CMSIS_core_definitions */ +/*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register Core Register contain: - Core Register - Core NVIC Register @@ -127,11 +195,14 @@ - Core SysTick Register - Core Debug Register - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. @{ */ @@ -214,9 +285,9 @@ typedef union /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers @{ */ @@ -239,12 +310,16 @@ typedef struct __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers @{ */ @@ -252,25 +327,27 @@ typedef struct */ typedef struct { - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -280,6 +357,9 @@ typedef struct #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ @@ -317,12 +397,17 @@ typedef struct #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ -/* SCB Interrupt Control State Register Definitions */ +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ @@ -458,8 +543,45 @@ typedef struct /** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. @{ */ @@ -508,8 +630,8 @@ typedef struct /** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ @@ -524,31 +646,31 @@ typedef struct __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ @@ -559,8 +681,11 @@ typedef struct #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ @@ -606,45 +731,307 @@ typedef struct /** \ingroup CMSIS_core_register - \defgroup CMSIS_InterruptType CMSIS Interrupt Type - Type definitions for the Cortex-M Interrupt Type Register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Interrupt Type Register. +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; -/* Interrupt Controller Type Register Definitions */ -#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -/* Auxiliary Control Register Definitions */ -#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -/*@}*/ /* end of group CMSIS_InterruptType */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) @{ */ @@ -700,23 +1087,26 @@ typedef struct #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ @@ -724,16 +1114,16 @@ typedef struct #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers @{ */ @@ -834,28 +1224,34 @@ typedef struct /*@} end of group CMSIS_CoreDebug */ -/** \ingroup CMSIS_core_register +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ @@ -864,42 +1260,43 @@ typedef struct /******************************************************************************* * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ */ /** \brief Set Priority Grouping - This function sets the priority grouping field using the required unlock sequence. + The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field + \param [in] PriorityGroup Priority grouping field. */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -907,12 +1304,11 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** \brief Get Priority Grouping - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + The function reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } @@ -920,12 +1316,11 @@ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) /** \brief Enable External Interrupt - This function enables a device specific interupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. + The function enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Number of the external interrupt to enable + \param [in] IRQn External interrupt number. Value cannot be negative. */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ } @@ -933,12 +1328,11 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) /** \brief Disable External Interrupt - This function disables a device specific interupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. + The function disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Number of the external interrupt to disable + \param [in] IRQn External interrupt number. Value cannot be negative. */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } @@ -946,14 +1340,15 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) /** \brief Get Pending Interrupt - This function reads the pending register in the NVIC and returns the pending bit + The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } @@ -961,12 +1356,11 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) /** \brief Set Pending Interrupt - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. + The function sets the pending bit of an external interrupt. - \param [in] IRQn Number of the interrupt for set pending + \param [in] IRQn Interrupt number. Value cannot be negative. */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } @@ -974,12 +1368,11 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) /** \brief Clear Pending Interrupt - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. + The function clears the pending bit of an external interrupt. - \param [in] IRQn Number of the interrupt for clear pending + \param [in] IRQn External interrupt number. Value cannot be negative. */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } @@ -987,12 +1380,14 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** \brief Get Active Interrupt - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } @@ -1000,16 +1395,14 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) /** \brief Set Interrupt Priority - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. + The function sets the priority of an interrupt. - Note: The priority cannot be set for every core interrupt. + \note The priority cannot be set for every core interrupt. - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ @@ -1020,17 +1413,16 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) /** \brief Get Interrupt Priority - This function reads the priority for the specified interrupt. The interrupt + The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { @@ -1042,19 +1434,17 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) /** \brief Encode Priority - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; @@ -1072,19 +1462,17 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P /** \brief Decode Priority - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; @@ -1100,9 +1488,9 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr /** \brief System Reset - This function initiate a system reset request to reset the MCU. + The function initiates a system reset request to reset the MCU. */ -static __INLINE void NVIC_SystemReset(void) +__STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -1119,7 +1507,8 @@ static __INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. @{ */ @@ -1127,19 +1516,25 @@ static __INLINE void NVIC_SystemReset(void) /** \brief System Tick Configuration - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | @@ -1155,27 +1550,28 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks) /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit - \return Character to transmit + \param [in] ch Character to transmit. + + \returns Character to transmit. */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); @@ -1187,14 +1583,12 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch) /** \brief ITM Receive Character - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. + The function inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character - \return -1 No character received + \return Received character. + \return -1 No character pending. */ -static __INLINE int32_t ITM_ReceiveChar (void) { +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { @@ -1208,13 +1602,12 @@ static __INLINE int32_t ITM_ReceiveChar (void) { /** \brief ITM Check Character - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available - \return 1 Character available + \return 0 No character available. + \return 1 Character available. */ -static __INLINE int32_t ITM_CheckChar (void) { +__STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ @@ -1232,5 +1625,3 @@ static __INLINE int32_t ITM_CheckChar (void) { #ifdef __cplusplus } #endif - -/*lint -restore */ diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h index 33baa1923..0a18fafc3 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmFunc.h @@ -1,28 +1,43 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.01 - * @date 06. December 2010 + * @version V3.20 + * @date 25. February 2013 * * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H -#ifndef __CORE_CMFUNC_H__ -#define __CORE_CMFUNC_H__ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -30,9 +45,13 @@ @{ */ -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ @@ -42,15 +61,11 @@ \return Control Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_CONTROL(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_CONTROL(void) +__STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } -#endif /* __ARMCC_VERSION */ /** \brief Set Control Register @@ -59,32 +74,24 @@ static __INLINE uint32_t __get_CONTROL(void) \param [in] control Control Register value to set */ -#if (__ARMCC_VERSION < 400000) -extern void __set_CONTROL(uint32_t control); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_CONTROL(uint32_t control) +__STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } -#endif /* __ARMCC_VERSION */ -/** \brief Get ISPR Register +/** \brief Get IPSR Register - This function returns the content of the ISPR Register. + This function returns the content of the IPSR Register. - \return ISPR Register value + \return IPSR Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_IPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_IPSR(void) +__STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } -#endif /* __ARMCC_VERSION */ /** \brief Get APSR Register @@ -93,15 +100,11 @@ static __INLINE uint32_t __get_IPSR(void) \return APSR Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_APSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_APSR(void) +__STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } -#endif /* __ARMCC_VERSION */ /** \brief Get xPSR Register @@ -110,15 +113,11 @@ static __INLINE uint32_t __get_APSR(void) \return xPSR Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_xPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_xPSR(void) +__STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } -#endif /* __ARMCC_VERSION */ /** \brief Get Process Stack Pointer @@ -127,15 +126,11 @@ static __INLINE uint32_t __get_xPSR(void) \return PSP Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PSP(void) +__STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } -#endif /* __ARMCC_VERSION */ /** \brief Set Process Stack Pointer @@ -144,15 +139,11 @@ static __INLINE uint32_t __get_PSP(void) \param [in] topOfProcStack Process Stack Pointer value to set */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PSP(uint32_t topOfProcStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } -#endif /* __ARMCC_VERSION */ /** \brief Get Main Stack Pointer @@ -161,15 +152,11 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack) \return MSP Register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_MSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_MSP(void) +__STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } -#endif /* __ARMCC_VERSION */ /** \brief Set Main Stack Pointer @@ -178,15 +165,11 @@ static __INLINE uint32_t __get_MSP(void) \param [in] topOfMainStack Main Stack Pointer value to set */ -#if (__ARMCC_VERSION < 400000) -extern void __set_MSP(uint32_t topOfMainStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } -#endif /* __ARMCC_VERSION */ /** \brief Get Priority Mask @@ -195,15 +178,11 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack) \return Priority Mask value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PRIMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PRIMASK(void) +__STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } -#endif /* __ARMCC_VERSION */ /** \brief Set Priority Mask @@ -212,15 +191,11 @@ static __INLINE uint32_t __get_PRIMASK(void) \param [in] priMask Priority Mask */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PRIMASK(uint32_t priMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } -#endif /* __ARMCC_VERSION */ #if (__CORTEX_M >= 0x03) @@ -247,15 +222,11 @@ static __INLINE void __set_PRIMASK(uint32_t priMask) \return Base Priority register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_BASEPRI(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_BASEPRI(void) +__STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } -#endif /* __ARMCC_VERSION */ /** \brief Set Base Priority @@ -264,15 +235,11 @@ static __INLINE uint32_t __get_BASEPRI(void) \param [in] basePri Base Priority value to set */ -#if (__ARMCC_VERSION < 400000) -extern void __set_BASEPRI(uint32_t basePri); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } -#endif /* __ARMCC_VERSION */ /** \brief Get Fault Mask @@ -281,15 +248,11 @@ static __INLINE void __set_BASEPRI(uint32_t basePri) \return Fault Mask register value */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_FAULTMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_FAULTMASK(void) +__STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } -#endif /* __ARMCC_VERSION */ /** \brief Set Fault Mask @@ -298,15 +261,11 @@ static __INLINE uint32_t __get_FAULTMASK(void) \param [in] faultMask Fault Mask value to set */ -#if (__ARMCC_VERSION < 400000) -extern void __set_FAULTMASK(uint32_t faultMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); + __regFaultMask = (faultMask & (uint32_t)1); } -#endif /* __ARMCC_VERSION */ #endif /* (__CORTEX_M >= 0x03) */ @@ -319,9 +278,9 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask) \return Floating Point Status/Control register value */ -static __INLINE uint32_t __get_FPSCR(void) +__STATIC_INLINE uint32_t __get_FPSCR(void) { -#if (__FPU_PRESENT == 1) +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else @@ -336,9 +295,9 @@ static __INLINE uint32_t __get_FPSCR(void) \param [in] fpscr Floating Point Status/Control value to set */ -static __INLINE void __set_FPSCR(uint32_t fpscr) +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { -#if (__FPU_PRESENT == 1) +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #endif @@ -347,7 +306,7 @@ static __INLINE void __set_FPSCR(uint32_t fpscr) #endif /* (__CORTEX_M == 0x04) */ - #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> @@ -367,9 +326,9 @@ static __INLINE void __set_FPSCR(uint32_t fpscr) This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) { - __ASM volatile ("cpsie i"); + __ASM volatile ("cpsie i" : : : "memory"); } @@ -378,9 +337,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) { - __ASM volatile ("cpsid i"); + __ASM volatile ("cpsid i" : : : "memory"); } @@ -390,7 +349,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) \return Control Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; @@ -405,19 +364,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) \param [in] control Control Register value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) ); + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } -/** \brief Get ISPR Register +/** \brief Get IPSR Register - This function returns the content of the ISPR Register. + This function returns the content of the IPSR Register. - \return ISPR Register value + \return IPSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; @@ -432,7 +391,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) \return APSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; @@ -447,7 +406,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) \return xPSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; @@ -462,7 +421,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) \return PSP Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; @@ -477,9 +436,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); } @@ -489,7 +448,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf \return MSP Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; @@ -504,9 +463,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); } @@ -516,7 +475,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf \return Priority Mask value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; @@ -531,9 +490,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) \param [in] priMask Priority Mask */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } @@ -544,9 +503,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) { - __ASM volatile ("cpsie f"); + __ASM volatile ("cpsie f" : : : "memory"); } @@ -555,9 +514,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) { - __ASM volatile ("cpsid f"); + __ASM volatile ("cpsid f" : : : "memory"); } @@ -567,7 +526,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void \return Base Priority register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; @@ -582,9 +541,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) \param [in] basePri Base Priority value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); } @@ -594,7 +553,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v \return Fault Mask register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; @@ -609,9 +568,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void \param [in] faultMask Fault Mask value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ @@ -625,12 +584,15 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t \return Floating Point Status/Control register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) { -#if (__FPU_PRESENT == 1) +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) uint32_t result; - __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); return(result); #else return(0); @@ -644,17 +606,20 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) \param [in] fpscr Floating Point Status/Control value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { -#if (__FPU_PRESENT == 1) - __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); #endif } #endif /* (__CORTEX_M == 0x04) */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* @@ -668,4 +633,4 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fps /*@} end of CMSIS_Core_RegAccFunctions */ -#endif /* __CORE_CMFUNC_H__ */ +#endif /* __CORE_CMFUNC_H */ diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h index 7e5463335..d213f0eed 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/core_cmInstr.h @@ -1,28 +1,42 @@ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.01 - * @date 06. December 2010 + * @version V3.20 + * @date 05. March 2013 * * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ -#ifndef __CORE_CMINSTR_H__ -#define __CORE_CMINSTR_H__ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H /* ########################## Core Instruction Access ######################### */ @@ -31,9 +45,14 @@ @{ */ -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. @@ -106,16 +125,13 @@ \param [in] value Value to reverse \return Reversed value */ -#if (__ARMCC_VERSION < 400677) -extern uint32_t __REV16(uint32_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } -#endif /* __ARMCC_VERSION */ - +#endif /** \brief Reverse byte order in signed short value @@ -124,15 +140,35 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value) \param [in] value Value to reverse \return Reversed value */ -#if (__ARMCC_VERSION < 400677) -extern int32_t __REVSH(int32_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM int32_t __REVSH(int32_t value) +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } -#endif /* __ARMCC_VERSION */ +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) #if (__CORTEX_M >= 0x03) @@ -218,11 +254,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value) This function removes the exclusive lock which is created by LDREX. */ -#if (__ARMCC_VERSION < 400000) -extern void __CLREX(void); -#else /* (__ARMCC_VERSION >= 400000) */ #define __CLREX __clrex -#endif /* __ARMCC_VERSION */ /** \brief Signed Saturate @@ -260,7 +292,7 @@ extern void __CLREX(void); -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> @@ -272,14 +304,25 @@ extern void __CLREX(void); #include <cmsis_ccs.h> -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } @@ -290,7 +333,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } @@ -301,7 +344,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } @@ -311,7 +354,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } @@ -323,7 +366,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) { __ASM volatile ("isb"); } @@ -334,7 +377,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) { __ASM volatile ("dsb"); } @@ -345,7 +388,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) { __ASM volatile ("dmb"); } @@ -358,12 +401,16 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) { +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else uint32_t result; - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); +#endif } @@ -374,11 +421,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } @@ -390,15 +437,44 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) { +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else uint32_t result; - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); } +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + #if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value @@ -408,7 +484,7 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; @@ -424,11 +500,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { - uint8_t result; + uint32_t result; - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif return(result); } @@ -440,11 +523,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { - uint16_t result; + uint32_t result; - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif return(result); } @@ -456,11 +546,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } @@ -474,11 +564,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } @@ -492,11 +582,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } @@ -510,11 +600,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } @@ -524,9 +614,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va This function removes the exclusive lock which is created by LDREX. */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) { - __ASM volatile ("clrex"); + __ASM volatile ("clrex" ::: "memory"); } @@ -569,9 +659,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) { - uint8_t result; + uint32_t result; __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); return(result); @@ -582,12 +672,12 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, + * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ @@ -595,4 +685,4 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ -#endif /* __CORE_CMINSTR_H__ */ +#endif /* __CORE_CMINSTR_H */ diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h index 4399e0480..d72cb509e 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h @@ -9,9 +9,9 @@ * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -52,7 +52,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/core_cm3.c b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/core_cm3.c deleted file mode 100644 index eb472aca3..000000000 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/core_cm3.c +++ /dev/null @@ -1,339 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V2.00 - * @date 13. September 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include <stdint.h> - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask Register. - - \return Fault Mask value - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - - -/** \brief Set the Fault Mask - - This function assigns the given value to the Fault Mask Register. - - \param [in] faultMask Fault Mask value value to set - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif diff --git a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c index d1e9bc40e..b5359089c 100644 --- a/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c +++ b/mcu/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c @@ -9,9 +9,9 @@ * Copyright (C) 2009 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -376,7 +376,7 @@ /*---------------------------------------------------------------------------- DEFINES *----------------------------------------------------------------------------*/ - + /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ @@ -389,7 +389,7 @@ /* F_cco0 = (2 * M * F_in) / N */ #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) -#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) +#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) /* Determine core clock frequency according to settings */ @@ -398,7 +398,7 @@ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) #elif ((CLKSRCSEL_Val & 0x03) == 2) #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) - #else + #else #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) #endif #else @@ -428,19 +428,19 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ switch (LPC_SC->CLKSRCSEL & 0x03) { case 0: /* Int. RC oscillator => PLL0 */ case 3: /* Reserved, default to Int. RC */ - SystemCoreClock = (IRC_OSC * + SystemCoreClock = (IRC_OSC * ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / ((LPC_SC->CCLKCFG & 0xFF)+ 1)); break; case 1: /* Main oscillator => PLL0 */ - SystemCoreClock = (OSC_CLK * + SystemCoreClock = (OSC_CLK * ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / ((LPC_SC->CCLKCFG & 0xFF)+ 1)); break; case 2: /* RTC oscillator => PLL0 */ - SystemCoreClock = (RTC_CLK * + SystemCoreClock = (RTC_CLK * ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / ((LPC_SC->CCLKCFG & 0xFF)+ 1)); |