summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorhathach <[email protected]>2026-01-14 13:06:49 +0700
committerhathach <[email protected]>2026-01-14 13:06:49 +0700
commit9a731e03e89e5e9ba530354fdfe4829b4cc0a8cf (patch)
treea3e2b865f3e2a40fc31e742763a1787d94d66075
parent86ca8fe717f379879298f6a723cafa897bae04de (diff)
correct dual port hil assert
-rw-r--r--.github/workflows/build.yml2
-rwxr-xr-xtest/hil/hil_test.py10
2 files changed, 6 insertions, 6 deletions
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 781d3b002..bb8c6d65d 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -315,7 +315,7 @@ jobs:
run: python3 tools/get_deps.py $BUILD_ARGS
- name: Build
- run: python3 tools/build.py -j 4 --toolchain iar $BUILD_ARGS
+ run: python3 tools/build.py --toolchain iar $BUILD_ARGS
- name: Test on actual hardware (hardware in the loop)
run: python3 test/hil/hil_test.py hfp.json
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
index f742bbca2..b84740867 100755
--- a/test/hil/hil_test.py
+++ b/test/hil/hil_test.py
@@ -410,22 +410,22 @@ def test_device_cdc_dual_ports(board):
sizes = [32, 64, 128, 256, 512, random.randint(2000, 5000)]
def write_and_check(writer, payload):
- size = len(payload)
+ payload_len = len(payload)
for s in ser:
s.reset_input_buffer()
rd0 = b''
rd1 = b''
offset = 0
# Write in chunks of random 1-64 bytes (device has 64-byte buffer)
- while offset < size:
- chunk_size = min(random.randint(1, 64), size - offset)
+ while offset < payload_len:
+ chunk_size = min(random.randint(1, 64), payload_len - offset)
ser[writer].write(payload[offset:offset + chunk_size])
ser[writer].flush()
rd0 += ser[0].read(chunk_size)
rd1 += ser[1].read(chunk_size)
offset += chunk_size
- assert rd0 == payload.lower(), f'Port0 wrong data ({size}): expected {payload.lower()[:16]}... was {rd0[:16]}'
- assert rd1 == payload.upper(), f'Port1 wrong data ({size}): expected {payload.upper()[:16]}... was {rd1[:16]}'
+ assert rd0 == payload.lower(), f'Port0 wrong data ({payload_len}): expected {payload.lower()}... was {rd0}'
+ assert rd1 == payload.upper(), f'Port1 wrong data ({payload_len}): expected {payload.upper()}... was {rd1}'
for size in sizes:
payload0 = rand_ascii(size)