diff options
| author | HiFiPhile <[email protected]> | 2024-06-27 20:44:40 +0200 |
|---|---|---|
| committer | HiFiPhile <[email protected]> | 2024-06-27 20:44:40 +0200 |
| commit | b82e0a9f1ed28979e04cb5e16cb9651905dd991e (patch) | |
| tree | bb87cafa73800cfb97e17ba10a390e9af2e9d06b | |
| parent | 13dedddd1963e67251f75b3e3ebd654d74d8aa56 (diff) | |
update lpc55 bsp for rtos use.
| -rw-r--r-- | hw/bsp/lpc55/family.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index cfd5b7032..f1ac86178 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -120,12 +120,17 @@ void board_init(void) { // Init 96 MHz clock BootClockFROHF96M(); +#if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); -#if CFG_TUSB_OS == OPT_OS_FREERTOS +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif // Init all GPIO ports @@ -239,6 +244,10 @@ void board_init(void) { // phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); // phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); // USBPHY->TX = phytx; + + ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer) + ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0)); + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); #endif } |