Merge branch 'master' into develop

2 files changed, 56 insertions, 29 deletions

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 4e0a583e7..25d723d96 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -148,30 +148,15 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
   ep->MXPLD = bytes_now;
 }
 
-/* centralized location for USBD interrupt enable bit mask */
-static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
-
-/*
-  NUC121/NUC125/NUC126 TinyUSB API driver implementation
-*/
-
-void dcd_init(uint8_t rhport)
+/* called by dcd_init() as well as by the ISR during a USB bus reset */
+static void bus_reset(void)
 {
-  (void) rhport;
-
-#ifdef SUPPORT_LPM
-  USBD->ATTR = 0x7D0 | USBD_LPMACK;
-#else
-  USBD->ATTR = 0x7D0;
-#endif
-
-  usb_detach();
-
   USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
 
   for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
   {
-    USBD->EP[ep_index].CFGP &= ~USBD_CFG_STATE_Msk;
+    USBD->EP[ep_index].CFG = 0;
+    USBD->EP[ep_index].CFGP = 0;
   }
 
   /* allocate the default EP0 endpoints */
@@ -187,6 +172,34 @@ void dcd_init(uint8_t rhport)
   /* USB RAM beyond what we've allocated above is available to the user */
   bufseg_addr = PERIPH_EP2_BUF_BASE;
 
+  /* Reset USB device address */
+  USBD->FADDR = 0;
+
+  /* reset EP0_IN flag */
+  active_ep0_xfer = false;
+}
+
+/* centralized location for USBD interrupt enable bit mask */
+static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
+
+/*
+  NUC121/NUC125/NUC126 TinyUSB API driver implementation
+*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+#ifdef SUPPORT_LPM
+  USBD->ATTR = 0x7D0 | USBD_LPMACK;
+#else
+  USBD->ATTR = 0x7D0;
+#endif
+
+  usb_detach();
+
+  bus_reset();
+
   usb_attach();
 
   USBD->INTSTS = enabled_irqs;
@@ -329,15 +342,7 @@ void USBD_IRQHandler(void)
       /* USB bus reset */
       USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
 
-      /* Reset all endpoints to DATA0 */
-      for(enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
-        USBD->EP[ep_index].CFG &= ~USBD_CFG_DSQSYNC_Msk;
-
-      /* Reset USB device address */
-      USBD->FADDR = 0;
-
-      /* reset EP0_IN flag */
-      active_ep0_xfer = false;
+      bus_reset();
 
       dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
     }
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 2ec7ae51c..77e355edf 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -313,6 +313,10 @@ void dcd_init(uint8_t rhport)
   // TODO Force fullspeed on non-highspeed port
   // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
 
+  #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  #endif
+
   dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
   dcd_reg->USBSTS  = dcd_reg->USBSTS;
   dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
@@ -419,6 +423,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
+  #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  #endif
+
   // Enable EP Control
   DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
 
@@ -441,10 +449,19 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
   dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
 
+  // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
+  // address to 32-byte boundaries.
+  #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  SCB_CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
+  #endif
+
   //------------- Prepare qtd -------------//
   qtd_init(p_qtd, buffer, total_bytes);
   p_qtd->int_on_complete = true;
   p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+  #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  #endif
 
   // start transfer
   DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
@@ -484,6 +501,11 @@ void dcd_isr(uint8_t rhport)
     }
   }
 
+  // Make sure we read the latest version of _dcd_data.
+  #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  #endif
+
   // TODO disconnection does not generate interrupt !!!!!!
 //	if (int_status & INTR_PORT_CHANGE)
 //	{