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authorGabriel Chouinard <[email protected]>2023-09-05 21:28:13 -0400
committerGabriel Chouinard <[email protected]>2023-09-05 21:39:28 -0400
commitc4566c4d2ba5219e6c2ea821912b888d0270ff07 (patch)
tree11fb7d5c7f5753628266db439900147b0d898a90
parent4fb15f6bb7afb105635db8370917af977d8a918a (diff)
Enable instruction cache for stm32u5 boards
-rw-r--r--hw/bsp/stm32u5/boards/stm32u575nucleo/board.h2
-rw-r--r--hw/bsp/stm32u5/family.c3
-rw-r--r--hw/bsp/stm32u5/family.mk1
3 files changed, 5 insertions, 1 deletions
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
index 75e8a0d6a..54a6d4cd7 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -61,7 +61,7 @@ static inline void board_clock_init(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
- /* Enable Power Clock*/
+ /* Enable Power Clock */
__HAL_RCC_PWR_CLK_ENABLE();
/** Configure the main internal regulator output voltage
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index a30d886aa..c1fe3f412 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -60,6 +60,9 @@ void board_init(void)
UART_CLK_EN();
+ /* Enable Instruction cache */
+ HAL_ICACHE_Enable();
+
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 9174fe96a..dace63a51 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -20,6 +20,7 @@ SRC_C += \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \