diff options
| author | hathach <[email protected]> | 2013-11-21 15:24:02 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2013-11-21 15:24:02 +0700 |
| commit | d1ef89a1543581d1703ea43b0056b5112fd64019 (patch) | |
| tree | 25b9f34fd8d42c1a178c3acfd4a92f2d25a2a2b3 | |
| parent | c303154b7a2af8e934308d9115e7b6da23c66419 (diff) | |
fixed lpc11u/13u VBUS (P0_3) with pulldown resistor for USB_VBUS_DEBOUNCED is correct
added disconnect callback for lpc11u/13u
| -rw-r--r-- | demos/device/device_os_none/.cproject | 99 | ||||
| -rw-r--r-- | demos/device/device_os_none/tusb_config.h | 6 | ||||
| -rw-r--r-- | tinyusb/device/dcd_lpc175x_6x.c | 2 | ||||
| -rw-r--r-- | tinyusb/device/dcd_lpc_11uxx_13uxx.c | 80 | ||||
| -rw-r--r-- | tinyusb/hal/hal_lpc11uxx.c | 4 | ||||
| -rw-r--r-- | tinyusb/hal/hal_lpc13uxx.c | 2 |
6 files changed, 71 insertions, 122 deletions
diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject index d70d48c79..d294f3ee4 100644 --- a/demos/device/device_os_none/.cproject +++ b/demos/device/device_os_none/.cproject @@ -1,7 +1,5 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.crt.advproject.config.exe.debug.856400198">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.856400198" moduleId="org.eclipse.cdt.core.settings" name="Board LPCXpresso1347">
@@ -74,6 +72,7 @@ <option id="gnu.c.link.option.paths.1465143173" name="Library search path (-L)" superClass="gnu.c.link.option.paths"/>
<option id="gnu.c.link.option.libs.447978281" name="Libraries (-l)" superClass="gnu.c.link.option.libs"/>
<option id="com.crt.advproject.link.gcc.hdrlib.1111642583" name="Use C library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.codered.nohost" valueType="enumerated"/>
+ <option id="com.crt.advproject.link.gcc.multicore.slave.1875369133" superClass="com.crt.advproject.link.gcc.multicore.slave"/>
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1234316494" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -367,77 +366,53 @@ <storageModule moduleId="com.crt.config">
<projectStorage><?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_2="LPC175x_6x_512.cfx" property_3="NXP" property_4="LPC1769" property_count="5" version="60000"/>
+<Properties property_0="" property_2="LPC11_12_13_64K_8K.cfx" property_3="NXP" property_4="LPC1347" property_count="5" version="60000"/>
<infoList vendor="NXP">
-<info chip="LPC1769" flash_driver="LPC175x_6x_512.cfx" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml" stub="crt_emu_cm3_nxp">
+<info chip="LPC1347" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp">
<chip>
-<name>LPC1769</name>
-<family>LPC17xx</family>
+<name>LPC1347</name>
+<family>LPC13xx (12bit ADC)</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
-<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
+<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/>
-<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
-<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/>
-<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/>
-<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/>
-<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/>
-<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/>
-<peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;0x1" id="RIT" location="0x400B0000"/>
-<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/>
-<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/>
-<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/>
-<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/>
-<peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/>
-<peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/>
-<peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/>
-<peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/>
-<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/>
-<peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/>
-<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/>
-<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/>
-<peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/>
-<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/>
-<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/>
-<peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/>
-<peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/>
-<peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/>
-<peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/>
-<peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/>
-<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/>
-<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/>
-<peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/>
-<peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/>
-<peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/>
-<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/>
-<peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/>
-<peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/>
-<peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/>
-<peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
-<peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/>
-<peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/>
-<peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/>
-<peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/>
-<peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/>
-<peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/>
-<peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/>
-<peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/>
-<peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/>
-<peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/>
-<peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/>
-<peripheralInstance derived_from="LPC17_FMC" determined="infoFile" id="FMC" location="0x40084000"/>
+<memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/>
+<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/>
+<memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/>
+<memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/>
+<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/>
+<peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/>
+<peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/>
+<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/>
+<peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/>
+<peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/>
+<peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/>
+<peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/>
+<peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/>
+<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/>
+<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/>
+<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/>
+<peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/>
+<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/>
+<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/>
+<peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/>
+<peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/>
+<peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/>
+<peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/>
+<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/>
</chip>
<processor>
<name gcc_name="cortex-m3">Cortex-M3</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig></projectStorage>
diff --git a/demos/device/device_os_none/tusb_config.h b/demos/device/device_os_none/tusb_config.h index c2f17a4a9..ed36468d2 100644 --- a/demos/device/device_os_none/tusb_config.h +++ b/demos/device/device_os_none/tusb_config.h @@ -81,10 +81,10 @@ #define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor, remove
//------------- CLASS -------------//
-#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
-#define TUSB_CFG_DEVICE_HID_MOUSE 1
+#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
+#define TUSB_CFG_DEVICE_HID_MOUSE 0
#define TUSB_CFG_DEVICE_HID_GENERIC 0
-#define TUSB_CFG_DEVICE_MSC 1
+#define TUSB_CFG_DEVICE_MSC 0
#define TUSB_CFG_DEVICE_CDC 1
diff --git a/tinyusb/device/dcd_lpc175x_6x.c b/tinyusb/device/dcd_lpc175x_6x.c index cebe31ea3..d755b94ee 100644 --- a/tinyusb/device/dcd_lpc175x_6x.c +++ b/tinyusb/device/dcd_lpc175x_6x.c @@ -218,7 +218,7 @@ void dcd_isr(uint8_t coreid) } if ( (dev_status_reg & SIE_DEV_STATUS_CONNECT_CHANGE_MASK) && !(dev_status_reg & SIE_DEV_STATUS_CONNECT_STATUS_MASK)) - { // device is disconnected, require using VBUS (P1_30) + { // TODO device is disconnected, require using VBUS (P1_30), cannot use CONNECT_STATUS as connection status usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_UNPLUGGED); } diff --git a/tinyusb/device/dcd_lpc_11uxx_13uxx.c b/tinyusb/device/dcd_lpc_11uxx_13uxx.c index 8a92183b7..bb7409d21 100644 --- a/tinyusb/device/dcd_lpc_11uxx_13uxx.c +++ b/tinyusb/device/dcd_lpc_11uxx_13uxx.c @@ -64,46 +64,16 @@ enum { };
enum {
- CMDSTAT_MASK_DEVICE_ENABLE = BIT_(7 ),
- CMDSTAT_MASK_SETUP_RECEIVED = BIT_(8 ),
- CMDSTAT_MASK_CMD_CONNECT = BIT_(16),
- CMDSTAT_MASK_CMD_SUSPEND = BIT_(17),
- CMDSTAT_MASK_CONNECT_CHANGE = BIT_(24),
- CMDSTAT_MASK_SUSPEND_CHANGE = BIT_(25),
- CMDSTAT_MASK_RESET_CHANGE = BIT_(26),
+ CMDSTAT_DEVICE_ENABLE_MASK = BIT_(7 ),
+ CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
+ CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16),
+ CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
+ CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
+ CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
+ CMDSTAT_RESET_CHANGE_MASK = BIT_(26),
+ CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
};
-#if 0
-typedef struct {
- union {
- struct {
- uint32_t dev_addr : 7;
- uint32_t dev_enable : 1;
- uint32_t setup_received : 1;
- uint32_t pll_on : 1;
- uint32_t : 1;
- uint32_t lpm_support : 1;
- uint32_t : 4; // not use interrupt on NAK
- uint32_t dev_connect : 1;
- uint32_t dev_suspend : 1;
- uint32_t : 1;
- uint32_t lpm_suspend : 1;
- uint32_t lpm_remote_wakeup : 1;
- uint32_t : 3;
- uint32_t dev_connect_change : 1;
- uint32_t dev_suspend_change : 1;
- uint32_t dev_reset_change : 1;
- uint32_t : 1;
- uint32_t vbus_debounced : 1;
- uint32_t : 3;
- }bits;
- uint32_t value;
- };
-} reg_dev_cmd_stat_t;
-
-STATIC_ASSERT( sizeof(reg_dev_cmd_stat_t) == 4, "size is not correct" );
-#endif
-
// buffer input must be 64 byte alignment
typedef struct {
volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
@@ -149,7 +119,7 @@ static inline uint16_t addr_offset(void const * p_buffer) void dcd_controller_connect(uint8_t coreid)
{
(void) coreid;
- LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_CMD_CONNECT;
+ LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
}
void dcd_controller_set_configuration(uint8_t coreid)
@@ -172,7 +142,7 @@ tusb_error_t dcd_init(void) LPC_USB->INTSTAT = LPC_USB->INTSTAT; // clear all pending interrupt
LPC_USB->INTEN = INT_MASK_DEVICE_STATUS;
- LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_DEVICE_ENABLE | CMDSTAT_MASK_CMD_CONNECT;
+ LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK;
return TUSB_ERROR_NONE;
}
@@ -192,7 +162,7 @@ static void bus_reset(void) LPC_USB->EPSKIP = 0xFFFFFFFF;
LPC_USB->INTSTAT = LPC_USB->INTSTAT; // clear all pending interrupt
- LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_SETUP_RECEIVED; // clear setup received interrupt
+ LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
LPC_USB->INTEN = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
}
@@ -207,31 +177,33 @@ void dcd_isr(uint8_t coreid) if (int_status == 0) return;
- uint32_t dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+ uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
//------------- Device Status -------------//
if ( int_status & INT_MASK_DEVICE_STATUS )
{
- if ( dev_cmd_stat & CMDSTAT_MASK_RESET_CHANGE)
- { // bus reset
+ LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK /* CMDSTAT_SUSPEND_CHANGE_MASK */;
+ if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+ {
bus_reset();
- usbd_bus_reset(0);
+ usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESET);
}
- // TODO not support suspend yet
- if ( dev_cmd_stat & CMDSTAT_MASK_SUSPEND_CHANGE) { }
-
- if ( dev_cmd_stat & CMDSTAT_MASK_CONNECT_CHANGE)
- { // device disconnect ?
+// if ( (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK) && (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) )
+// { // find a way to distinct bus suspend vs unplug/plug
+// usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_SUSPENDED);
+// }
+ if ( (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK) && !(dev_cmd_stat & CMDSTAT_VBUS_DEBOUNCED_MASK) )
+ { // device disconnect
+ usbd_dcd_bus_event_isr(0, 0);
}
- LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_RESET_CHANGE | CMDSTAT_MASK_CONNECT_CHANGE
- /* CMDSTAT_MASK_SUSPEND_CHANGE | */;
+
}
//------------- Control Endpoint -------------//
- if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_MASK_SETUP_RECEIVED) )
+ if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{ // received control request from host
// copy setup request & acknowledge so that the next setup can be received by hw
usbd_setup_received_isr(coreid, &dcd_data.setup_request);
@@ -239,7 +211,7 @@ void dcd_isr(uint8_t coreid) // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
- LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_SETUP_RECEIVED;
+ LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
}
else if ( int_status & 0x03 )
diff --git a/tinyusb/hal/hal_lpc11uxx.c b/tinyusb/hal/hal_lpc11uxx.c index 9cb188e9c..c1e504731 100644 --- a/tinyusb/hal/hal_lpc11uxx.c +++ b/tinyusb/hal/hal_lpc11uxx.c @@ -49,9 +49,11 @@ tusb_error_t hal_init(void) /* Pull-down is needed, or internally, VBUS will be floating. This is to address the wrong status in VBUSDebouncing bit in CmdStatus register. */ + // set PIO0_3 as USB_VBUS LPC_IOCON->PIO0_3 &= ~0x1F; - LPC_IOCON->PIO0_3 |= (0x01<<0); /* Secondary function VBUS */ + LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */ + // set PIO0_6 as usb connect LPC_IOCON->PIO0_6 &= ~0x07; LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */ diff --git a/tinyusb/hal/hal_lpc13uxx.c b/tinyusb/hal/hal_lpc13uxx.c index d4e3fa984..a5697afc3 100644 --- a/tinyusb/hal/hal_lpc13uxx.c +++ b/tinyusb/hal/hal_lpc13uxx.c @@ -51,7 +51,7 @@ tusb_error_t hal_init(void) address the wrong status in VBUSDebouncing bit in CmdStatus register. */ // set PIO0_3 as USB_VBUS LPC_IOCON->PIO0_3 &= ~0x1F; - LPC_IOCON->PIO0_3 |= (0x01<<0); /* Secondary function VBUS */ + LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */ // set PIO0_6 as usb connect LPC_IOCON->PIO0_6 &= ~0x07; |