Merge branch 'master' into fork/HiFiPhile/h7rs

133 files changed, 6372 insertions, 2641 deletions

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index d00ee78bd..35576a439 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -24,8 +24,15 @@ body:
 
   - type: input
     attributes:
+      label: Commit SHA
+      placeholder: e.g 3a042b37da28d0ba1e5593eb1068ca5645d77b56 or version bundled by esp-idf or pico-sdk
+    validations:
+      required: true
+
+  - type: input
+    attributes:
       label: Board
-      placeholder: e.g Feather nRF52840 Express
+      placeholder: e.g Adafruit Feather nRF52840 Express
     validations:
       required: true
 
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 28447cc80..fe2ed61c9 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -266,7 +266,7 @@ jobs:
         run: python3 tools/get_deps.py $BUILD_ARGS
 
       - name: Build
-        run: python3 tools/build.py --toolchain iar $BUILD_ARGS
+        run: python3 tools/build.py -j 4 --toolchain iar $BUILD_ARGS
 
       - name: Test on actual hardware (hardware in the loop)
         run: python3 test/hil/hil_test.py hfp.json
diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py
index fa73dc1b6..bccb07e3e 100755
--- a/.github/workflows/ci_set_matrix.py
+++ b/.github/workflows/ci_set_matrix.py
@@ -24,7 +24,7 @@ family_list = {
     "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"],
     "lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"],
     "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"],
-    "max32650 max32666 max32690 max78002": ["arm-gcc"],
+    "maxim": ["arm-gcc"],
     "mcx": ["arm-gcc"],
     "mm32": ["arm-gcc"],
     "msp430": ["msp430-gcc"],
diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
index a22c65c79..dfcca6315 100644
--- a/.github/workflows/codeql.yml
+++ b/.github/workflows/codeql.yml
@@ -124,7 +124,7 @@ jobs:
         output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif
 
     - name: Upload SARIF
-      uses: github/codeql-action/upload-sarif@v2
+      uses: github/codeql-action/upload-sarif@v3
       with:
         sarif_file: ${{ steps.step1.outputs.sarif-output }}
         category: "/language:${{matrix.language}}"
diff --git a/README.rst b/README.rst
index efbfa354b..0d6b147d9 100644
--- a/README.rst
+++ b/README.rst
@@ -167,7 +167,9 @@ Supported CPUs
 |              |         +-------------------+--------+------+-----------+------------------------+-------------------+
 |              |         | 54, 55            | ✔      |      | ✔         | lpc_ip3511             |                   |
 |              +---------+-------------------+--------+------+-----------+------------------------+-------------------+
-|              | MCX     | N9, A15           | ✔      |      | ✔         | ci_fs, ci_hs           |                   |
+|              | MCX     | N9                | ✔      |      | ✔         | ci_fs, ci_hs           |                   |
+|              |         +-------------------+--------+------+-----------+------------------------+-------------------+
+|              |         | A15               | ✔      |      |           | ci_fs                  |                   |
 +--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
 | Raspberry Pi | RP2040, RP2350              | ✔      | ✔    | ✖         | rp2040, pio_usb        |                   |
 +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 2ee40cf7e..1d3d5d717 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -165,6 +165,7 @@ lpcxpresso55s28     LPCXpresso55s28                            lpc55          ht
 lpcxpresso55s69     LPCXpresso55s69                            lpc55          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK
 mcu_link            MCU Link                                   lpc55          https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK
 frdm_mcxa153        Freedom MCXA153                            mcx            https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
+frdm_mcxa156        Freedom MCXA156                            mcx            https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156
 frdm_mcxn947        Freedom MCXN947                            mcx            https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947
 mcxn947brk          MCXN947 Breakout                           mcx            n/a
 ==================  =========================================  =============  =========================================================================================================================================================================  ======
diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
index 3101b66b9..dbc73903e 100644
--- a/examples/build_system/make/make.mk
+++ b/examples/build_system/make/make.mk
@@ -2,6 +2,9 @@
 # Common make definition for all examples
 # ---------------------------------------
 
+# upper helper function
+to_upper = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(1))))))))))))))))))))))))))))
+
 #-------------------------------------------------------------
 # Toolchain
 # Can be changed via TOOLCHAIN=gcc|iar or CC=arm-none-eabi-gcc|iccarm|clang
@@ -109,7 +112,7 @@ INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
 
-BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
+BOARD_UPPER = $(call to_upper,$(BOARD))
 CFLAGS += -DBOARD_$(BOARD_UPPER)
 
 ifdef CFLAGS_CLI
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index 41e8f0d67..04949cef9 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -58,6 +58,7 @@
 #define LWIP_HTTPD_SSI_INCLUDE_TAG      0
 
 #define LWIP_SINGLE_NETIF               1
+#define LWIP_NETIF_LINK_CALLBACK        1
 
 #define PBUF_POOL_SIZE                  4
 
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 36f402332..4bdddf6c5 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -31,6 +31,12 @@ this appears as either a RNDIS or CDC-ECM USB virtual network adapter; the OS pi
 RNDIS should be valid on Linux and Windows hosts, and CDC-ECM should be valid on Linux and macOS hosts
 
 The MCU appears to the host as IP address 192.168.7.1, and provides a DHCP server, DNS server, and web server.
+
+Link State Control:
+- Press the user button to toggle the network link state (UP/DOWN)
+- This simulates "ethernet cable unplugged/plugged" events
+- The host OS will see the network interface as disconnected/connected accordingly
+- Use this to test network error handling and recovery in host applications
 */
 /*
 Some smartphones *may* work with this implementation as well, but likely have limited (broken) drivers,
@@ -63,9 +69,6 @@ try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00
 /* lwip context */
 static struct netif netif_data;
 
-/* shared between tud_network_recv_cb() and service_traffic() */
-static struct pbuf *received_frame;
-
 /* this is used by this code, ./class/net/net_driver.c, and usb_descriptors.c */
 /* ideally speaking, this should be generated from the hardware's unique ID (if available) */
 /* it is suggested that the first byte is 0x02 to indicate a link-local address */
@@ -137,6 +140,12 @@ static err_t netif_init_cb(struct netif *netif) {
   return ERR_OK;
 }
 
+/* notifies the USB host about the link state change. */
+static void usbnet_netif_link_callback(struct netif *netif) {
+    bool link_up = netif_is_link_up(netif);
+    tud_network_link_state(BOARD_TUD_RHPORT, link_up);
+}
+
 static void init_lwip(void) {
   struct netif *netif = &netif_data;
 
@@ -147,11 +156,19 @@ static void init_lwip(void) {
   memcpy(netif->hwaddr, tud_network_mac_address, sizeof(tud_network_mac_address));
   netif->hwaddr[5] ^= 0x01;
 
-  netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ip_input);
+  netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ethernet_input);
 #if LWIP_IPV6
   netif_create_ip6_linklocal_address(netif, 1);
 #endif
   netif_set_default(netif);
+
+#if LWIP_NETIF_LINK_CALLBACK
+  // Set the link callback to notify USB host about link state changes
+  netif_set_link_callback(netif, usbnet_netif_link_callback);
+  netif_set_link_up(netif);
+#else
+  tud_network_link_state(BOARD_TUD_RHPORT, true);
+#endif
 }
 
 /* handle any DNS requests from dns-server */
@@ -164,20 +181,29 @@ bool dns_query_proc(const char *name, ip4_addr_t *addr) {
 }
 
 bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
-  /* this shouldn't happen, but if we get another packet before
-  parsing the previous, we must signal our inability to accept it */
-  if (received_frame) return false;
+  struct netif *netif = &netif_data;
 
   if (size) {
     struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL);
 
-    if (p) {
-      /* pbuf_alloc() has already initialized struct; all we need to do is copy the data */
-      memcpy(p->payload, src, size);
+    if (p == NULL) {
+      printf("ERROR: Failed to allocate pbuf of size %d\n", size);
+      return false;
+    }
+
+    /* Copy buf to pbuf */
+    pbuf_take(p, src, size);
 
-      /* store away the pointer for service_traffic() to later handle */
-      received_frame = p;
+    // Surrender ownership of our pbuf unless there was an error
+    // Only call pbuf_free if not Ok else it will panic with "pbuf_free: p->ref > 0"
+    // or steal it from whatever took ownership of it with undefined consequences.
+    // See: https://savannah.nongnu.org/patch/index.php?10121
+    if (netif->input(p, netif) != ERR_OK) {
+      printf("ERROR: netif input failed\n");
+      pbuf_free(p);
     }
+    // Signal tinyusb that the current frame has been processed.
+    tud_network_recv_renew();
   }
 
   return true;
@@ -191,29 +217,26 @@ uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
   return pbuf_copy_partial(p, dst, p->tot_len, 0);
 }
 
-static void service_traffic(void) {
-  /* handle any packet received by tud_network_recv_cb() */
-  if (received_frame) {
-    // Surrender ownership of our pbuf unless there was an error
-    // Only call pbuf_free if not Ok else it will panic with "pbuf_free: p->ref > 0"
-    // or steal it from whatever took ownership of it with undefined consequences.
-    // See: https://savannah.nongnu.org/patch/index.php?10121
-    if (ethernet_input(received_frame, &netif_data)!=ERR_OK) {
-        pbuf_free(received_frame);
+static void handle_link_state_switch(void) {
+  /* Check for button press to toggle link state */
+  static bool last_link_state = true;
+  static bool last_button_state = false;
+  bool current_button_state = board_button_read();
+
+  if (current_button_state && !last_button_state) {
+    /* Button pressed - toggle link state */
+    last_link_state = !last_link_state;
+    if (last_link_state) {
+      printf("Link state: UP\n");
+      netif_set_link_up(&netif_data);
+    } else {
+      printf("Link state: DOWN\n");
+      netif_set_link_down(&netif_data);
     }
-    received_frame = NULL;
-    tud_network_recv_renew();
+    /* LWIP callback will notify USB host about the change */
   }
+  last_button_state = current_button_state;
 
-  sys_check_timeouts();
-}
-
-void tud_network_init_cb(void) {
-  /* if the network is re-initializing and we have a leftover packet, we must do a cleanup */
-  if (received_frame) {
-    pbuf_free(received_frame);
-    received_frame = NULL;
-  }
 }
 
 int main(void) {
@@ -243,15 +266,23 @@ int main(void) {
   lwiperf_start_tcp_server_default(NULL, NULL);
 #endif
 
+#if CFG_TUD_NCM
+  printf("USB NCM network interface initialized\n");
+#elif CFG_TUD_ECM_RNDIS
+  printf("USB RNDIS/ECM network interface initialized\n");
+#endif
+
   while (1) {
     tud_task();
-    service_traffic();
+    sys_check_timeouts(); // service lwip
+    handle_link_state_switch();
   }
 
   return 0;
 }
 
 /* lwip has provision for using a mutex, when applicable */
+/* This implementation is for single-threaded use only */
 sys_prot_t sys_arch_protect(void) {
   return 0;
 }
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index 22082fc81..c774f59ff 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -85,6 +85,7 @@ extern "C" {
 #endif
 
 // Use different configurations to test all net devices (also due to resource limitations)
+#ifndef USE_ECM
 #if TU_CHECK_MCU(OPT_MCU_LPC15XX, OPT_MCU_LPC40XX, OPT_MCU_LPC51UXX, OPT_MCU_LPC54)
   #define USE_ECM 1
 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAML21, OPT_MCU_SAML22)
@@ -97,6 +98,7 @@ extern "C" {
   #define USE_ECM 0
   #define INCLUDE_IPERF
 #endif
+#endif
 
 //--------------------------------------------------------------------
 // NCM CLASS CONFIGURATION, SEE "ncm.h" FOR PERFORMANCE TUNING
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake
new file mode 100644
index 000000000..9adaefb17
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c6")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h
new file mode 100644
index 000000000..18b51410d
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Adafruit Feather EPS32-C6
+   url: https://www.adafruit.com/product/5933
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          15
+
+#define BUTTON_PIN            9
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN  21
+#define MAX3421_MOSI_PIN 22
+#define MAX3421_MISO_PIN 23
+#define MAX3421_CS_PIN   8
+#define MAX3421_INTR_PIN 7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index cf11e2441..8f6c4bee2 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -49,7 +49,9 @@ static led_strip_handle_t led_strip;
 static void max3421_init(void);
 #endif
 
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
 static bool usb_init(void);
+#endif
 
 //--------------------------------------------------------------------+
 // Implementation
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index b544689d9..2aad7d185 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -32,8 +32,6 @@ endif ()
 
 # Add example src and bsp directories
 set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
-
-# set SDKCONFIG for each IDF Target
 set(SDKCONFIG ${CMAKE_BINARY_DIR}/sdkconfig)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index faffdcbc4..0509fdc28 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -38,6 +38,11 @@ if (NOT DEFINED TOOLCHAIN)
   set(TOOLCHAIN gcc)
 endif ()
 
+# Optimization
+if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "")
+  set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE)
+endif ()
+
 #-------------------------------------------------------------
 # FAMILY and BOARD
 #-------------------------------------------------------------
@@ -483,7 +488,7 @@ function(family_flash_openocd TARGET)
   # note skip verify since it has issue with rp2040
   add_custom_target(${TARGET}-openocd
     DEPENDS ${TARGET}
-    COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
+    COMMAND ${OPENOCD} -c "tcl_port disabled; gdb_port disabled" ${OPTION_LIST} -c "init; halt; program $<TARGET_FILE:${TARGET}>" -c reset ${OPTION_LIST2} -c exit
     VERBATIM
     )
 endfunction()
@@ -503,10 +508,16 @@ endfunction()
 # Add flash openocd adi (Analog Devices) target
 # included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd
 function(family_flash_openocd_adi TARGET)
-  if (DEFINED $ENV{MAXIM_PATH})
-    # use openocd from msdk
-    set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd)
-    set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts")
+  if (DEFINED MAXIM_PATH)
+    # use openocd from msdk with MAXIM_PATH cmake variable first if the user specified it
+    set(OPENOCD ${MAXIM_PATH}/Tools/OpenOCD/openocd)
+    set(OPENOCD_OPTION2 "-s ${MAXIM_PATH}/Tools/OpenOCD/scripts")
+  elseif (DEFINED ENV{MAXIM_PATH})
+    # use openocd from msdk with MAXIM_PATH environment variable. Normalize
+    # since msdk can be Windows (MinGW) or Linux
+    file(TO_CMAKE_PATH "$ENV{MAXIM_PATH}" MAXIM_PATH_NORM)
+    set(OPENOCD ${MAXIM_PATH_NORM}/Tools/OpenOCD/openocd)
+    set(OPENOCD_OPTION2 "-s ${MAXIM_PATH_NORM}/Tools/OpenOCD/scripts")
   else()
     # compiled from source
     if (NOT DEFINED OPENOCD_ADI_PATH)
diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake
index 2146c29f7..09d97d256 100644
--- a/hw/bsp/lpc51/family.cmake
+++ b/hw/bsp/lpc51/family.cmake
@@ -36,7 +36,7 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index b41b5438e..91d1261cb 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -28,15 +28,16 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c
 
 INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+    $(TOP)/$(BOARD_PATH) \
+    $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index 90497b9fb..66320870a 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,6 +56,7 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/common
     ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/flexcomm/usart
     ${SDK_DIR}/drivers/lpc_iocon
     ${SDK_DIR}/drivers/lpc_gpio
     ${SDK_DIR}/drivers/lpuart
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index ea4c9c39c..8dc70f621 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -36,7 +36,7 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c
 
 INC += \
@@ -46,6 +46,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index cd1eb5f78..a89548635 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
     ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,9 +56,9 @@ function(add_board_target BOARD_TARGET)
     # driver
     ${SDK_DIR}/drivers/common
     ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/flexcomm/usart
     ${SDK_DIR}/drivers/lpc_iocon
     ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/lpuart
     ${SDK_DIR}/drivers/sctimer
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index d82e85904..b83942c87 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -45,7 +45,7 @@ SRC_C += \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
 	lib/sct_neopixel/sct_neopixel.c
 
 INC += \
@@ -55,11 +55,10 @@ INC += \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/ \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
 	$(TOP)/$(SDK_DIR)/drivers/sctimer
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md
deleted file mode 100644
index ca66a1ac4..000000000
--- a/hw/bsp/max32650/README.md
+++ /dev/null
@@ -1,46 +0,0 @@
-# Analog Devices MAX32650/1/2
-
-This BSP is for working with the Analog Devices
-[MAX32650](https://www.analog.com/en/products/max32650.html),
-[MAX32651](https://www.analog.com/en/products/max32651.html) and
-[MAX32652](https://www.analog.com/en/products/max32652.html)
-microcontrollers.  The following boards are supported:
- * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html)
- * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html)
- * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader)
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-### MAX32650 and MAX32652
-
-The default flashing behavior in this BSP for the MAX32650 and MAX32652 is to
-utilize JLink.  This can be done by running the `flash` or `flash-jlink` rule
-for Makefiles, or the `<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
-
-### MAX32651
-
-The MAX32651 features an integrated secure bootloader which requires the
-application image be signed prior to flashing.  Both the Makefile and CMake
-scripts account for this signing automatically when building for the
-MAX32651EVKIT.
-
-To flash the signed image, the MSDK's OpenOCD variant must be used.  To flash
-the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk`
-and `<target>-msdk` rule and target.
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake
deleted file mode 100644
index fffdcc9fb..000000000
--- a/hw/bsp/max32650/boards/max32650evkit/board.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Use the standard, non-secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
-
-function(update_board_extras TARGET)
-  #No extra arguments
-endfunction()
-
-function(prepare_image TARGET_IN)
-  #No signing required
-endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk
deleted file mode 100644
index 0bc210e11..000000000
--- a/hw/bsp/max32650/boards/max32650evkit/board.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Use the standard, non-secure linker file
-LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake
deleted file mode 100644
index fffdcc9fb..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/board.cmake
+++ /dev/null
@@ -1,10 +0,0 @@
-# Use the standard, non-secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
-
-function(update_board_extras TARGET)
-  #No extra arguments
-endfunction()
-
-function(prepare_image TARGET_IN)
-  #No signing required
-endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk
deleted file mode 100644
index 0bc210e11..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/board.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Use the standard, non-secure linker file
-LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
deleted file mode 100644
index 0e56a91ec..000000000
--- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld
+++ /dev/null
@@ -1,119 +0,0 @@
-MEMORY {
-    ROM (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
-    FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
-    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
-}
-
-SECTIONS {
-    .text :
-    {
-        _text = .;
-        KEEP(*(.isr_vector))
-        *(.text*)    /* program code */
-        *(.rodata*)  /* read-only data: "const" */
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-         /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* C++ Exception handling */
-        KEEP(*(.eh_frame*))
-        _etext = .;
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    /* it's used for C++ exception handling      */
-    /* we need to keep this to avoid overlapping */
-    .ARM.exidx :
-    {
-        __exidx_start = .;
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        __exidx_end = .;
-    } > FLASH
-
-    .data :
-    {
-        _data = ALIGN(., 4);
-        *(vtable)
-        *(.data*)           /*read-write initialized data: initialized global variable*/
-        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
-        *(.flashprog*)      /* Flash program */
-
-
-        /* These array sections are used by __libc_init_array to call static C++ constructors */
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        _edata = ALIGN(., 4);
-    } > SRAM AT>FLASH
-    __load_data = LOADADDR(.data);
-    .bss :
-    {
-        . = ALIGN(4);
-        _bss = .;
-        *(.bss*)     /*read-write zero initialized data: uninitialized global variable*/
-        *(COMMON)
-        _ebss = ALIGN(., 4);
-    } > SRAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > SRAM
-
-    .heap (COPY):
-    {
-        . = ALIGN(4);
-        PROVIDE ( end = . );
-        PROVIDE ( _end = . );
-        *(.heap*)
-        __HeapLimit = ABSOLUTE(__StackLimit);
-    } > SRAM
-
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
-}
diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c
deleted file mode 100644
index 8f0e56734..000000000
--- a/hw/bsp/max32650/family.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE);
-
-  //USB
-  // Startup the HIRC96M clock if it's not on already
-  if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
-      MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
-      MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
-  }
-
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[13];//USN Buffer
-  MXC_SYS_GetUSN(hw_id, 13);
-
-  size_t act_len = TU_MIN(max_len, 13);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake
deleted file mode 100644
index b1d5dded7..000000000
--- a/hw/bsp/max32650/family.cmake
+++ /dev/null
@@ -1,169 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific information and functions
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32650)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg")
-
-set(FAMILY_MCUS MAX32650 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32650
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32650
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32650
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-
-    # Run any board specific updates
-    update_board_extras(${TARGET})
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me10.c
-    ${PERIPH_SRC}/SYS/sys_me10.c
-    ${PERIPH_SRC}/TPU/tpu_me10.c
-    ${PERIPH_SRC}/TPU/tpu_reva.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me10.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me10.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me10.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/ICC/icc_common.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me10.c
-    ${PERIPH_SRC}/UART/uart_reva.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include
-    ${MAX32_PERIPH}/Include/MAX32650
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/TPU
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      -u sb_header #Needed when linking libraries to not lose the Signing header
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32650)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-
-  # Add the optional MSDK OpenOCD flashing
-  family_flash_msdk(${TARGET})
-endfunction()
-
-function(family_flash_msdk TARGET)
-  # Prepare the image (signed) if the board requires it
-  prepare_image(${TARGET})
-
-  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
-  add_custom_target(${TARGET}-msdk
-    DEPENDS ${TARGET}
-    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
-            -f interface/cmsis-dap.cfg -f target/max32650.cfg
-            -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
-    VERBATIM
-  )
-endfunction()
diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk
deleted file mode 100644
index d2fc293e4..000000000
--- a/hw/bsp/max32650/family.mk
+++ /dev/null
@@ -1,140 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32650/1/2 SDK
-CFLAGS +=   -DTARGET=MAX32650 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32650 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=cast-align \
-			-Wno-error=cast-qual \
-			-Wno-error=sign-compare
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# Configure the flash rule. By default, use JLink.
-SIGNED_BUILD ?= 0
-DEFAULT_FLASH = flash-jlink
-
-# If the applications needs to be signed (for the MAX32651), sign it first and
-# then need to use MSDK's OpenOCD to flash it
-# Also need to include the __SLA_FWK__ define to enable the signed header into
-# memory
-ifeq ($(SIGNED_BUILD), 1)
-# Extra definitions to build for the secure part
-CFLAGS += -D__SLA_FWK__
-DEFAULT_FLASH := sign-build flash-msdk
-endif
-
-# For flash-jlink target
-JLINK_DEVICE = max32650
-
-# Configure the flash rule
-flash: $(DEFAULT_FLASH)
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me10.c \
-	$(PERIPH_SRC)/SYS/sys_me10.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me10.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me10.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me10.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/ICC/icc_common.c \
-	$(PERIPH_SRC)/TPU/tpu_me10.c \
-	$(PERIPH_SRC)/TPU/tpu_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me10.c \
-	$(PERIPH_SRC)/UART/uart_reva.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TPU \
-	$(PERIPH_SRC)/UART
-
-
-# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
-# MAX32651 has a secure bootloader which requires the image to be signed before
-# loading into flash. All MAX32651EVKIT's have the same key for evaluation
-# purposes, so create a special flash rule to sign the binary and flash using
-# the MSDK.
-MCU_PATH = $(TOP)/hw/mcu/analog/max32/
-# Assume no extension for sign utility
-SIGN_EXE = sign_app
-ifeq ($(OS), Windows_NT)
-# Must use .exe extension on Windows, since the binaries
-# for Linux may live in the same place.
-SIGN_EXE := sign_app.exe
-else
-UNAME = $(shell uname -s)
-ifneq ($(findstring MSYS_NT,$(UNAME)),)
-# Must also use .exe extension for MSYS2
-SIGN_EXE := sign_app.exe
-endif
-endif
-
-# Rule to sign the build.  This will in-place modify the existing .elf file
-# an populate the .sig section with the signature value
-sign-build: $(BUILD)/$(PROJECT).elf
-	$(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
-	$(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
-		key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
-		ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
-	$(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32650.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index e5a76af85..000000000
--- a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "mxc_device.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/max32666/README.md b/hw/bsp/max32666/README.md
deleted file mode 100644
index 902d82e25..000000000
--- a/hw/bsp/max32666/README.md
+++ /dev/null
@@ -1,32 +0,0 @@
-# Analog Devices MAX32665/6
-
-This BSP is for working with the Analog Devices
-[MAX32665](https://www.analog.com/en/products/max32665.html) and
-[MAX32666](https://www.analog.com/en/products/max32666.html) microcontrollers.
-The following boards are supported:
- * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html)
- * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html)
-
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontrollers utilize the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32666/boards/max32666evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32666/boards/max32666evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32666/boards/max32666fthr/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32666/boards/max32666fthr/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake
deleted file mode 100644
index 49798729a..000000000
--- a/hw/bsp/max32666/family.cmake
+++ /dev/null
@@ -1,147 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32666)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg")
-
-set(FAMILY_MCUS MAX32666 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32665
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32665
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32666
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me14.c
-    ${PERIPH_SRC}/SYS/sys_me14.c
-    ${PERIPH_SRC}/TPU/tpu_me14.c
-    ${PERIPH_SRC}/TPU/tpu_reva.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me14.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me14.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me14.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me14.c
-    ${PERIPH_SRC}/UART/uart_reva.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include
-    ${MAX32_PERIPH}/Include/MAX32665
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/TPU
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-  -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32666)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-endfunction()
diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk
deleted file mode 100644
index b4f7d1e57..000000000
--- a/hw/bsp/max32666/family.mk
+++ /dev/null
@@ -1,93 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
-LD_FILE = $(FAMILY_PATH)/max32666.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32665/6 SDK
-CFLAGS +=   -DTARGET=MAX32665 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32665 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=cast-align \
-			-Wno-error=cast-qual
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max32666
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32665.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me14.c \
-	$(PERIPH_SRC)/SYS/sys_me14.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me14.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me14.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me14.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/TPU/tpu_me14.c \
-    $(PERIPH_SRC)/TPU/tpu_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me14.c \
-	$(PERIPH_SRC)/UART/uart_reva.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TPU \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index e5a76af85..000000000
--- a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "mxc_device.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/max32690/README.md b/hw/bsp/max32690/README.md
deleted file mode 100644
index 081ae0ad4..000000000
--- a/hw/bsp/max32690/README.md
+++ /dev/null
@@ -1,31 +0,0 @@
-# Analog Devices MAX32690
-
-This BSP is for working with the Analog Devices
-[MAX32690](https://www.analog.com/en/products/max32690.html) microcontroller.
-The following boards are supported:
- * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html)
- * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html)
-
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP
-compatible debug probe. However, at the time of writing, the necessary flashing
-algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
-branch.  To utilize the provided debug probes, please install the bundled MSDK
-package which includes the appropriate OpenOCD modifications.   To leverage this
-OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-msdk` CMake
-target.
diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32690/boards/apard32690/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32690/boards/apard32690/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max32690/boards/max32690evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max32690/boards/max32690evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c
deleted file mode 100644
index 7ba5fbef3..000000000
--- a/hw/bsp/max32690/family.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mcr_regs.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
-
-  //USB
-  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
-  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
-
-  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake
deleted file mode 100644
index 0d544d9e6..000000000
--- a/hw/bsp/max32690/family.cmake
+++ /dev/null
@@ -1,152 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max32690)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg")
-
-set(FAMILY_MCUS MAX32690 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX32690
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX32690
-    FLASH_ORIGIN=0x10000000
-    FLASH_SIZE=0x340000
-    SRAM_ORIGIN=0x20000000
-    SRAM_SIZE=0x100000
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX32690
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_me18.c
-    ${PERIPH_SRC}/SYS/sys_me18.c
-    ${PERIPH_SRC}/CTB/ctb_me18.c
-    ${PERIPH_SRC}/CTB/ctb_reva.c
-    ${PERIPH_SRC}/CTB/ctb_common.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_me18.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_me18.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_me18.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_me18.c
-    ${PERIPH_SRC}/UART/uart_revb.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include
-    ${MAX32_PERIPH}/Include/MAX32690
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/CTB
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX32690)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-    target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_openocd_adi(${TARGET})
-endfunction()
diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk
deleted file mode 100644
index d4df8ef2f..000000000
--- a/hw/bsp/max32690/family.mk
+++ /dev/null
@@ -1,101 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S
-LD_FILE = $(FAMILY_PATH)/max32690.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX32690 SDK
-CFLAGS +=   -DTARGET=MAX32690 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX32690 \
-			-DFLASH_ORIGIN=0x10000000 \
-			-DFLASH_SIZE=0x340000 \
-			-DSRAM_ORIGIN=0x20000000 \
-			-DSRAM_SIZE=0x100000 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=unused-parameter \
-			-Wno-error=strict-prototypes \
-			-Wno-error=old-style-declaration \
-			-Wno-error=sign-compare \
-			-Wno-error=cast-qual \
-			-Wno-lto-type-mismatch
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max32690
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max32690.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_me18.c \
-	$(PERIPH_SRC)/SYS/sys_me18.c \
-	$(PERIPH_SRC)/CTB/ctb_me18.c \
-	$(PERIPH_SRC)/CTB/ctb_reva.c \
-	$(PERIPH_SRC)/CTB/ctb_common.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_me18.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_me18.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_me18.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_me18.c \
-	$(PERIPH_SRC)/UART/uart_revb.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/CTB \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index e5a76af85..000000000
--- a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "mxc_device.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       __NVIC_PRIO_BITS
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/max78002/README.md b/hw/bsp/max78002/README.md
deleted file mode 100644
index 4fb1bede4..000000000
--- a/hw/bsp/max78002/README.md
+++ /dev/null
@@ -1,28 +0,0 @@
-# Analog Devices MAX78002
-
-This BSP is for working with the Analog Devices
-[MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller.
-The following boards are supported:
- * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html)
-
-This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
-interfaces and hardware abstraction layers. This source code package is fetched
-as part of the get-deps script.
-
-The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
-is not already available on your build machine, it can be installed by using the
-bundled MSDK installation.  Details on downloading and installing can be found
-in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
-
-## Flashing
-
-The default flashing behavior in this BSP is to utilize JLink.  This can be done
-by running the `flash` or `flash-jlink` rule for Makefiles, or the
-`<target>-jlink` target for CMake.
-
-The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However,
-at the time of writing, the necessary flashing algorithms for OpenOCD have not
-yet been incorporated into the OpenOCD master branch.  To utilize the provided
-debug probes, please install the bundled MSDK package which includes the
-appropriate OpenOCD modifications.   To leverage this OpenOCD instance, run the
-`flash-msdk` Makefile rule, or `<target>-msdk` CMake target.
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake
deleted file mode 100644
index 9dc6962eb..000000000
--- a/hw/bsp/max78002/boards/max78002evkit/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-# Nothing to be done at the board level
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk
deleted file mode 100644
index a813a5327..000000000
--- a/hw/bsp/max78002/boards/max78002evkit/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-# No specific build requirements for the board.
diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c
deleted file mode 100644
index 5c23f40f9..000000000
--- a/hw/bsp/max78002/family.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: Analog Devices
-*/
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
-#endif
-
-#include "gpio.h"
-#include "mxc_sys.h"
-#include "mcr_regs.h"
-#include "mxc_device.h"
-#include "uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "board.h"
-#include "bsp/board_api.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void) {
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
-
-void board_init(void) {
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-  mxc_gpio_cfg_t gpioConfig;
-
-  // LED
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_OUT;
-  gpioConfig.mask = LED_PIN;
-  gpioConfig.pad = MXC_GPIO_PAD_NONE;
-  gpioConfig.port = LED_PORT;
-  gpioConfig.vssel = LED_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-  board_led_write(false);
-
-  // Button
-  gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
-  gpioConfig.func = MXC_GPIO_FUNC_IN;
-  gpioConfig.mask = BUTTON_PIN;
-  gpioConfig.pad = BUTTON_PULL;
-  gpioConfig.port = BUTTON_PORT;
-  gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
-  MXC_GPIO_Config(&gpioConfig);
-
-  // UART
-  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
-  UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V
-
-  //USB
-  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
-  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-#if LED_STATE_ON
-  state = !state;
-#endif
-  if (state) {
-    MXC_GPIO_OutClr(LED_PORT, LED_PIN);
-  } else {
-    MXC_GPIO_OutSet(LED_PORT, LED_PIN);
-  }
-}
-
-uint32_t board_button_read(void) {
-  uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
-  return BUTTON_STATE_ACTIVE == state;
-}
-
-size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
-
-  size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
-  memcpy(id, hw_id, act_len);
-  return act_len;
-}
-
-int board_uart_read(uint8_t *buf, int len) {
-  int uart_val;
-  int act_len = 0;
-
-  while (act_len < len) {
-    if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
-      break;
-    } else {
-      *buf++ = (uint8_t) uart_val;
-      act_len++;
-    }
-  }
-  return act_len;
-}
-
-int board_uart_write(void const *buf, int len) {
-  int act_len = 0;
-  const uint8_t *ch_ptr = (const uint8_t *) buf;
-  while (act_len < len) {
-    MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
-    act_len++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void) {
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler(void) {
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void) {
-}
diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake
deleted file mode 100644
index ce0fcfa08..000000000
--- a/hw/bsp/max78002/family.cmake
+++ /dev/null
@@ -1,166 +0,0 @@
-include_guard()
-
-set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
-set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# Get the linker file from current location (family)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld)
-set(LD_FILE_Clang ${LD_FILE_GNU})
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(JLINK_DEVICE max78000)
-
-set(FAMILY_MCUS MAX78002 CACHE INTERNAL "")
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    TARGET=MAX78002
-    TARGET_REV=0x4131
-    MXC_ASSERT_ENABLE
-    MAX78002
-    IAR_PRAGMAS=0
-    CFG_TUSB_MCU=OPT_MCU_MAX78002
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-    )
-endfunction()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif ()
-
-  # Startup & Linker script
-  set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S)
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  set(PERIPH_SRC ${MAX32_PERIPH}/Source)
-  add_library(${BOARD_TARGET} STATIC
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c
-    ${PERIPH_SRC}/SYS/mxc_assert.c
-    ${PERIPH_SRC}/SYS/mxc_delay.c
-    ${PERIPH_SRC}/SYS/mxc_lock.c
-    ${PERIPH_SRC}/SYS/nvic_table.c
-    ${PERIPH_SRC}/SYS/pins_ai87.c
-    ${PERIPH_SRC}/SYS/sys_ai87.c
-    ${PERIPH_SRC}/AES/aes_ai87.c
-    ${PERIPH_SRC}/AES/aes_revb.c
-    ${PERIPH_SRC}/FLC/flc_common.c
-    ${PERIPH_SRC}/FLC/flc_ai87.c
-    ${PERIPH_SRC}/FLC/flc_reva.c
-    ${PERIPH_SRC}/GPIO/gpio_common.c
-    ${PERIPH_SRC}/GPIO/gpio_ai87.c
-    ${PERIPH_SRC}/GPIO/gpio_reva.c
-    ${PERIPH_SRC}/ICC/icc_ai87.c
-    ${PERIPH_SRC}/ICC/icc_reva.c
-    ${PERIPH_SRC}/TRNG/trng_ai87.c
-    ${PERIPH_SRC}/TRNG/trng_revb.c
-    ${PERIPH_SRC}/UART/uart_common.c
-    ${PERIPH_SRC}/UART/uart_ai87.c
-    ${PERIPH_SRC}/UART/uart_revb.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${MAX32_CMSIS}/Include
-    ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include
-    ${MAX32_PERIPH}/Include/MAX78002
-    ${PERIPH_SRC}/SYS
-    ${PERIPH_SRC}/GPIO
-    ${PERIPH_SRC}/AES
-    ${PERIPH_SRC}/TRNG
-    ${PERIPH_SRC}/ICC
-    ${PERIPH_SRC}/FLC
-    ${PERIPH_SRC}/UART
-    )
-
-  target_compile_options(${BOARD_TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-  )
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_Clang}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-    )
-
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MAX78002)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/mentor/musb/dcd_musb.c
-    )
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-  target_compile_options(${TARGET} PRIVATE
-    -Wno-error=strict-prototypes
-    -Wno-error=redundant-decls
-  )
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_jlink(${TARGET})
-  family_flash_msdk(${TARGET})
-endfunction()
-
-# Add flash msdk target
-function(family_flash_msdk TARGET)
-  set(MAXIM_PATH "$ENV{MAXIM_PATH}")
-
-  add_custom_target(${TARGET}-msdk
-    DEPENDS ${TARGET}
-    COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
-		        -f interface/cmsis-dap.cfg -f target/max78002.cfg
-		        -c "program $<TARGET_FILE:${TARGET}> verify; init; reset; exit"
-    VERBATIM
-    )
-endfunction()
diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk
deleted file mode 100644
index 997816261..000000000
--- a/hw/bsp/max78002/family.mk
+++ /dev/null
@@ -1,99 +0,0 @@
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
-
-# Important locations in the hw support for MCU
-MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
-MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
-
-# Add any board specific make rules
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CPU_CORE ?= cortex-m4
-PORT ?= 0
-
-# GCC
-SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S
-LD_FILE = $(FAMILY_PATH)/max78002.ld
-
-# --------------
-# Compiler Flags
-# --------------
-# Flags for the MAX78002 SDK
-CFLAGS +=   -DTARGET=MAX78002 \
-			-DTARGET_REV=0x4131 \
-			-DMXC_ASSERT_ENABLE \
-			-DMAX78002 \
-			-DIAR_PRAGMAS=0
-
-# Flags for TUSB features
-CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \
-  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
-# mcu driver cause following warnings
-CFLAGS += 	-Wno-error=redundant-decls \
-			-Wno-error=strict-prototypes \
-			-Wno-error=unused-parameter \
-			-Wno-error=enum-conversion \
-			-Wno-error=sign-compare \
-			-Wno-error=cast-qual
-
-LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
-
-# For flash-jlink target
-JLINK_DEVICE = max78000
-
-# flash target using Jlink by default
-flash: flash-jlink
-
-# Optional flash option when running within an installed MSDK to use OpenOCD
-# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
-# If the MSDK is installed, flash-msdk can be run to utilize the the modified
-# openocd with the algorithms
-MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
-flash-msdk: $(BUILD)/$(PROJECT).elf
-	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
-		-f interface/cmsis-dap.cfg -f target/max78002.cfg \
-		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
-
-# -----------------
-# Sources & Include
-# -----------------
-PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
-SRC_C += \
-	src/portable/mentor/musb/dcd_musb.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \
-	$(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \
-	$(PERIPH_SRC)/SYS/mxc_assert.c \
-	$(PERIPH_SRC)/SYS/mxc_delay.c \
-	$(PERIPH_SRC)/SYS/mxc_lock.c \
-	$(PERIPH_SRC)/SYS/nvic_table.c \
-	$(PERIPH_SRC)/SYS/pins_ai87.c \
-	$(PERIPH_SRC)/SYS/sys_ai87.c \
-	$(PERIPH_SRC)/AES/aes_ai87.c \
-	$(PERIPH_SRC)/AES/aes_revb.c \
-	$(PERIPH_SRC)/FLC/flc_common.c \
-	$(PERIPH_SRC)/FLC/flc_ai87.c \
-	$(PERIPH_SRC)/FLC/flc_reva.c \
-	$(PERIPH_SRC)/GPIO/gpio_common.c \
-	$(PERIPH_SRC)/GPIO/gpio_ai87.c \
-	$(PERIPH_SRC)/GPIO/gpio_reva.c \
-	$(PERIPH_SRC)/ICC/icc_ai87.c \
-	$(PERIPH_SRC)/ICC/icc_reva.c \
-	$(PERIPH_SRC)/TRNG/trng_ai87.c \
-	$(PERIPH_SRC)/TRNG/trng_revb.c \
-	$(PERIPH_SRC)/UART/uart_common.c \
-	$(PERIPH_SRC)/UART/uart_ai87.c \
-	$(PERIPH_SRC)/UART/uart_revb.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MAX32_CMSIS)/Include \
-	$(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \
-	$(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \
-	$(PERIPH_SRC)/SYS \
-	$(PERIPH_SRC)/GPIO \
-	$(PERIPH_SRC)/AES \
-	$(PERIPH_SRC)/ICC \
-	$(PERIPH_SRC)/FLC \
-	$(PERIPH_SRC)/TRNG \
-	$(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h
index e5a76af85..e5a76af85 100644
--- a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h
diff --git a/hw/bsp/maxim/README.md b/hw/bsp/maxim/README.md
new file mode 100644
index 000000000..e2983e899
--- /dev/null
+++ b/hw/bsp/maxim/README.md
@@ -0,0 +1,43 @@
+# Analog Devices MAXIM
+
+This BSP is for working with the Analog microcontrollers
+ - [MAX32650](https://www.analog.com/en/products/max32650.html),
+ - [MAX32651](https://www.analog.com/en/products/max32651.html)
+ - [MAX32652](https://www.analog.com/en/products/max32652.html)
+ - [MAX32665](https://www.analog.com/en/products/max32665.html)
+ - [MAX32666](https://www.analog.com/en/products/max32666.html)
+ - [MAX32690](https://www.analog.com/en/products/max32690.html)
+ - [MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller.
+
+The following boards are supported:
+ * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html)
+ * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html)
+ * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader)
+ * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html)
+ * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html)
+ * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html)
+ * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html)
+ * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html)
+
+This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device
+interfaces and hardware abstraction layers. This source code package is fetched
+as part of the get-deps script.
+
+The microcontroller utilizes the standard GNU ARM toolchain.  If this toolchain
+is not already available on your build machine, it can be installed by using the
+bundled MSDK installation.  Details on downloading and installing can be found
+in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/).
+
+## Flashing
+
+The default flashing behavior in this BSP is to utilize JLink.  This can be done
+by running the `flash` or `flash-jlink` rule for Makefiles, or the
+`<target>-jlink` target for CMake.
+
+Most the Evaluation Kit and boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch.  To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications.   To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `<target>-openocd` CMake
+target.
diff --git a/hw/bsp/maxim/boards/apard32690/board.cmake b/hw/bsp/maxim/boards/apard32690/board.cmake
new file mode 100644
index 000000000..a03d05f8d
--- /dev/null
+++ b/hw/bsp/maxim/boards/apard32690/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32690)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/maxim/boards/apard32690/board.h
index 87b9c4e88..19f74bf56 100644
--- a/hw/bsp/max32690/boards/apard32690/board.h
+++ b/hw/bsp/maxim/boards/apard32690/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32690.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/apard32690/board.mk b/hw/bsp/maxim/boards/apard32690/board.mk
new file mode 100644
index 000000000..d8a0c9cae
--- /dev/null
+++ b/hw/bsp/maxim/boards/apard32690/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32690
diff --git a/hw/bsp/maxim/boards/max32650evkit/board.cmake b/hw/bsp/maxim/boards/max32650evkit/board.cmake
new file mode 100644
index 000000000..59721e756
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650evkit/board.cmake
@@ -0,0 +1,8 @@
+set(MAX_DEVICE max32650)
+
+function(update_board TARGET)
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/maxim/boards/max32650evkit/board.h
index 65ed2659e..9c1f55f8e 100644
--- a/hw/bsp/max32650/boards/max32650evkit/board.h
+++ b/hw/bsp/maxim/boards/max32650evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32650evkit/board.mk b/hw/bsp/maxim/boards/max32650evkit/board.mk
new file mode 100644
index 000000000..3a4108005
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32650
diff --git a/hw/bsp/maxim/boards/max32650fthr/board.cmake b/hw/bsp/maxim/boards/max32650fthr/board.cmake
new file mode 100644
index 000000000..59721e756
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650fthr/board.cmake
@@ -0,0 +1,8 @@
+set(MAX_DEVICE max32650)
+
+function(update_board TARGET)
+endfunction()
+
+function(prepare_image TARGET_IN)
+  #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/maxim/boards/max32650fthr/board.h
index 755fa15b5..af0fa1c39 100644
--- a/hw/bsp/max32650/boards/max32650fthr/board.h
+++ b/hw/bsp/maxim/boards/max32650fthr/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32650fthr/board.mk b/hw/bsp/maxim/boards/max32650fthr/board.mk
new file mode 100644
index 000000000..3a4108005
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32650fthr/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32650
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/maxim/boards/max32651evkit/board.cmake
index bd8077a42..773989126 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.cmake
+++ b/hw/bsp/maxim/boards/max32651evkit/board.cmake
@@ -1,22 +1,23 @@
+set(MAX_DEVICE max32650)
+
 # Use the secure linker file
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/max32651.ld)
 
-function(update_board_extras TARGET)
+function(update_board TARGET)
   # for the signed target, need to add the __SLA_FWK__ define
   target_compile_definitions(${TARGET} PUBLIC
     __SLA_FWK__
     )
 endfunction()
 
-function(prepare_image TARGET_IN)
-  #For the signed target, set up a POST_BUILD command to sign the elf file once
-  #created
+function(sign_image TARGET_IN)
+  #For the signed target, set up a POST_BUILD command to sign the elf file once created
   if((WIN32) OR (MINGW) OR (MSYS))
     set(SIGN_EXE "sign_app.exe")
   else()
     set(SIGN_EXE "sign_app")
   endif()
-  set(MCU_PATH "${TOP}/hw/mcu/analog/max32/")
+  set(MCU_PATH "${TOP}/hw/mcu/analog/msdk/")
 
   # Custom POST_BUILD command
   add_custom_command(
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/maxim/boards/max32651evkit/board.h
index 0b49ff309..dbf2a4b7c 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.h
+++ b/hw/bsp/maxim/boards/max32651evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32650.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/maxim/boards/max32651evkit/board.mk
index b609598c1..5d4971148 100644
--- a/hw/bsp/max32650/boards/max32651evkit/board.mk
+++ b/hw/bsp/maxim/boards/max32651evkit/board.mk
@@ -1,5 +1,7 @@
+MAX_DEVICE = max32650
+
 # Use the secure linker file
-LD_FILE = $(BOARD_PATH)/max32651.ld
+LD_FILE = $(FAMILY_PATH)/linker/max32651.ld
 
 # Let the family script know the build needs to be signed
 SIGNED_BUILD := 1
diff --git a/hw/bsp/maxim/boards/max32666evkit/board.cmake b/hw/bsp/maxim/boards/max32666evkit/board.cmake
new file mode 100644
index 000000000..e7116b603
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32665)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/maxim/boards/max32666evkit/board.h
index 54589444d..42965d3c5 100644
--- a/hw/bsp/max32666/boards/max32666evkit/board.h
+++ b/hw/bsp/maxim/boards/max32666evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32665.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32666evkit/board.mk b/hw/bsp/maxim/boards/max32666evkit/board.mk
new file mode 100644
index 000000000..a1cf3045d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32665
diff --git a/hw/bsp/maxim/boards/max32666fthr/board.cmake b/hw/bsp/maxim/boards/max32666fthr/board.cmake
new file mode 100644
index 000000000..e7116b603
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666fthr/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32665)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/maxim/boards/max32666fthr/board.h
index 0caea5934..fbb217949 100644
--- a/hw/bsp/max32666/boards/max32666fthr/board.h
+++ b/hw/bsp/maxim/boards/max32666fthr/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max32665.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max32666fthr/board.mk b/hw/bsp/maxim/boards/max32666fthr/board.mk
new file mode 100644
index 000000000..a1cf3045d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32666fthr/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32665
diff --git a/hw/bsp/maxim/boards/max32690evkit/board.cmake b/hw/bsp/maxim/boards/max32690evkit/board.cmake
new file mode 100644
index 000000000..a03d05f8d
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32690evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max32690)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/maxim/boards/max32690evkit/board.h
index aa8dbb1de..41c73621f 100644
--- a/hw/bsp/max32690/boards/max32690evkit/board.h
+++ b/hw/bsp/maxim/boards/max32690evkit/board.h
@@ -32,13 +32,12 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "max32690.h"
+
 // LED
 #define LED_PORT        MXC_GPIO0
 #define LED_PIN         MXC_GPIO_PIN_14
diff --git a/hw/bsp/maxim/boards/max32690evkit/board.mk b/hw/bsp/maxim/boards/max32690evkit/board.mk
new file mode 100644
index 000000000..d8a0c9cae
--- /dev/null
+++ b/hw/bsp/maxim/boards/max32690evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max32690
diff --git a/hw/bsp/maxim/boards/max78002evkit/board.cmake b/hw/bsp/maxim/boards/max78002evkit/board.cmake
new file mode 100644
index 000000000..dd4c3c215
--- /dev/null
+++ b/hw/bsp/maxim/boards/max78002evkit/board.cmake
@@ -0,0 +1,4 @@
+set(MAX_DEVICE max78002)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/maxim/boards/max78002evkit/board.h
index 85d55d7de..8c1fc13d4 100644
--- a/hw/bsp/max78002/boards/max78002evkit/board.h
+++ b/hw/bsp/maxim/boards/max78002evkit/board.h
@@ -32,8 +32,7 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#include "gpio.h"
-#include "mxc_sys.h"
+#include "max78002.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hw/bsp/maxim/boards/max78002evkit/board.mk b/hw/bsp/maxim/boards/max78002evkit/board.mk
new file mode 100644
index 000000000..b19e95187
--- /dev/null
+++ b/hw/bsp/maxim/boards/max78002evkit/board.mk
@@ -0,0 +1 @@
+MAX_DEVICE = max78002
diff --git a/hw/bsp/max32666/family.c b/hw/bsp/maxim/family.c
index 05306c6c9..0ef6b8c4d 100644
--- a/hw/bsp/max32666/family.c
+++ b/hw/bsp/maxim/family.c
@@ -35,7 +35,9 @@
 
 #include "gpio.h"
 #include "mxc_sys.h"
+#if __has_include("mcr_regs.h")
 #include "mcr_regs.h"
+#endif
 #include "mxc_device.h"
 #include "uart.h"
 
@@ -88,16 +90,45 @@ void board_init(void) {
   MXC_GPIO_Config(&gpioConfig);
 
   // UART
+#if MAX_PERIPH_ID == 14
   MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP);
+#elif MAX_PERIPH_ID == 18 || MAX_PERIPH_ID == 87
+  MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+  #if MAX_PERIPH_ID == 87
+  UART_PORT->vssel |= UART_VDDIO_BITS; // Set necessary bits to 3.3V
+  #endif
+#endif
 
   //USB
+#if defined(MAX32650)
   // Startup the HIRC96M clock if it's not on already
-  if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
-      MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+  if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
+    MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
+    MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
   }
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
 
+#elif defined(MAX32665) || defined(MAX32666)
+  // Startup the HIRC96M clock if it's not on already
+  if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
+    MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+  }
   MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
   MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+
+#elif defined(MAX32690)
+  MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+
+#  elif  defined(MAX78002)
+  MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+#else
+  #error "Unsupported MAXIM MCU for board_dfu_init"
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -121,13 +152,18 @@ uint32_t board_button_read(void) {
 }
 
 size_t board_get_unique_id(uint8_t id[], size_t max_len) {
-  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
-                                          /* All other 2nd parameter is optional checksum buffer */
-  MXC_SYS_GetUSN(hw_id, NULL);
+#if defined(MAX32650)
+  // USN is 13 bytes on this device
+  MXC_SYS_GetUSN(id, 13);
+  return 13;
+#else
+  uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer
+  MXC_SYS_GetUSN(hw_id, NULL); // 2nd parameter is optional checksum buffer
 
   size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
   memcpy(id, hw_id, act_len);
   return act_len;
+#endif
 }
 
 int board_uart_read(uint8_t *buf, int len) {
diff --git a/hw/bsp/maxim/family.cmake b/hw/bsp/maxim/family.cmake
new file mode 100644
index 000000000..75daec753
--- /dev/null
+++ b/hw/bsp/maxim/family.cmake
@@ -0,0 +1,196 @@
+include_guard()
+
+# stub: overridden by board.cmake if needed
+function(sign_image TARGET_IN)
+endfunction()
+
+set(MSDK_LIB ${TOP}/hw/mcu/analog/msdk/Libraries)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+string(TOUPPER ${MAX_DEVICE} MAX_DEVICE_UPPER)
+cmake_print_variables(MAX_DEVICE MAX_DEVICE_UPPER)
+
+set(JLINK_DEVICE ${MAX_DEVICE})
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${MAX_DEVICE}.cfg")
+
+set(FAMILY_MCUS ${MAX_DEVICE_UPPER} CACHE INTERNAL "")
+
+if (${MAX_DEVICE} STREQUAL "max32650")
+  set(PERIPH_ID 10)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666")
+  set(PERIPH_ID 14)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max32690")
+  set(PERIPH_ID 18)
+  set(PERIPH_SUFFIX "me")
+elseif (${MAX_DEVICE} STREQUAL "max78002")
+  set(PERIPH_ID 87)
+  set(PERIPH_SUFFIX "ai")
+else()
+  message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}")
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S)
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MAX_DEVICE}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  # Common
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c
+    ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c
+    ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${MSDK_LIB}/CMSIS/5.9.0/Core/Include
+    ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include
+    ${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER}
+    ${MSDK_LIB}/PeriphDrivers/Source/SYS
+    ${MSDK_LIB}/PeriphDrivers/Source/GPIO
+    ${MSDK_LIB}/PeriphDrivers/Source/ICC
+    ${MSDK_LIB}/PeriphDrivers/Source/FLC
+    ${MSDK_LIB}/PeriphDrivers/Source/UART
+    )
+
+  # device specific
+  if (${MAX_DEVICE} STREQUAL "max32650" OR
+    ${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/TPU
+      )
+  elseif (${MAX_DEVICE} STREQUAL "max32690")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/CTB
+      )
+  elseif (${MAX_DEVICE} STREQUAL "max78002")
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c
+      ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${MSDK_LIB}/PeriphDrivers/Source/AES
+      ${MSDK_LIB}/PeriphDrivers/Source/TRNG
+      )
+  else()
+    message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}")
+  endif()
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    TARGET=${MAX_DEVICE_UPPER}
+    TARGET_REV=0x4131
+    MXC_ASSERT_ENABLE
+    ${MAX_DEVICE_UPPER}
+    IAR_PRAGMAS=0
+    MAX_PERIPH_ID=${PERIPH_ID}
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+  target_compile_options(${BOARD_TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+  )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_${MAX_DEVICE_UPPER})
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/mentor/musb/dcd_musb.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=strict-prototypes
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+
+  sign_image(${TARGET}) # for secured device such as max32651
+  family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/maxim/family.mk b/hw/bsp/maxim/family.mk
new file mode 100644
index 000000000..3ddf8cf39
--- /dev/null
+++ b/hw/bsp/maxim/family.mk
@@ -0,0 +1,190 @@
+MSDK_LIB = hw/mcu/analog/msdk/Libraries
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+JLINK_DEVICE = ${MAX_DEVICE}
+MAX_DEVICE_UPPER = $(call to_upper,${MAX_DEVICE})
+
+ifeq ($(MAX_DEVICE),max32650)
+  PERIPH_ID = 10
+  PERIPH_SUFFIX = me
+endif
+
+ifneq ($(filter $(MAX_DEVICE),max32665 max32666),)
+  PERIPH_ID = 14
+  PERIPH_SUFFIX = me
+endif
+
+ifeq ($(MAX_DEVICE),max32690)
+  PERIPH_ID = 18
+  PERIPH_SUFFIX = me
+endif
+
+ifeq ($(MAX_DEVICE),max78002)
+  PERIPH_ID = 87
+  PERIPH_SUFFIX = ai
+endif
+
+ifndef PERIPH_ID
+  $(error Unsupported MAX device: ${MAX_DEVICE})
+endif
+
+# Configure the flash rule. By default, use JLink.
+SIGNED_BUILD ?= 0
+DEFAULT_FLASH = flash-jlink
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DTARGET=${MAX_DEVICE_UPPER}\
+  -DTARGET_REV=0x4131 \
+	-DMXC_ASSERT_ENABLE \
+	-D${MAX_DEVICE_UPPER} \
+	-DIAR_PRAGMAS=0 \
+	-DMAX_PERIPH_ID=${PERIPH_ID} \
+  -DCFG_TUSB_MCU=OPT_MCU_${MAX_DEVICE_UPPER} \
+  -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += \
+	-Wno-error=old-style-declaration \
+	-Wno-error=redundant-decls \
+  -Wno-error=strict-prototypes \
+	-Wno-error=unused-parameter \
+	-Wno-error=cast-align \
+	-Wno-error=cast-qual \
+	-Wno-error=sign-compare \
+	-Wno-error=enum-conversion \
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+LD_FILE_GCC ?= $(FAMILY_PATH)/linker/${MAX_DEVICE}.ld
+
+# If the applications needs to be signed (for the MAX32651), sign it first and
+# then need to use MSDK's OpenOCD to flash it
+# Also need to include the __SLA_FWK__ define to enable the signed header into
+# memory
+ifeq ($(SIGNED_BUILD), 1)
+# Extra definitions to build for the secure part
+CFLAGS += -D__SLA_FWK__
+DEFAULT_FLASH := sign-build flash-msdk
+endif
+
+# -----------------
+# Sources & Include
+# -----------------
+
+# common
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c \
+	${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+	${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c \
+	${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c \
+	${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+
+SRC_S_GCC += ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/${MSDK_LIB}/CMSIS/5.9.0/Core/Include \
+	$(TOP)/${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER} \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/SYS \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/GPIO \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/ICC \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/FLC \
+	$(TOP)/${MSDK_LIB}/PeriphDrivers/Source/UART \
+
+# device specific
+ifneq ($(filter $(MAX_DEVICE),max32650 max32665 max32666),)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c \
+
+  INC += $(TOP)/${MSDK_LIB}/PeriphDrivers/Source/TPU
+endif
+
+ifeq (${MAX_DEVICE},max32690)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c \
+		${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \
+
+  INC += ${TOP}/${MSDK_LIB}/PeriphDrivers/Source/CTB
+endif
+
+ifeq (${MAX_DEVICE},max78002)
+  SRC_C += \
+		${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c \
+		${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c \
+		${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c \
+
+  INC += \
+		${TOP}/${MSDK_LIB}/PeriphDrivers/Source/AES \
+		${TOP}/${MSDK_LIB}/PeriphDrivers/Source/TRNG
+endif
+
+
+# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
+# MAX32651 has a secure bootloader which requires the image to be signed before
+# loading into flash. All MAX32651EVKIT's have the same key for evaluation
+# purposes, so create a special flash rule to sign the binary and flash using
+# the MSDK.
+MCU_PATH = $(TOP)/hw/mcu/analog/msdk/
+# Assume no extension for sign utility
+SIGN_EXE = sign_app
+ifeq ($(OS), Windows_NT)
+# Must use .exe extension on Windows, since the binaries
+# for Linux may live in the same place.
+SIGN_EXE := sign_app.exe
+else
+UNAME = $(shell uname -s)
+ifneq ($(findstring MSYS_NT,$(UNAME)),)
+# Must also use .exe extension for MSYS2
+SIGN_EXE := sign_app.exe
+endif
+endif
+
+# Rule to sign the build.  This will in-place modify the existing .elf file
+# an populate the .sig section with the signature value
+sign-build: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
+	$(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
+		key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
+		ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
+	$(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+	$(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+		-f interface/cmsis-dap.cfg -f target/max32650.cfg \
+		-c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# Configure the flash rule
+flash: $(DEFAULT_FLASH)
diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/maxim/linker/max32650.ld
index 0e56a91ec..0e56a91ec 100644
--- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld
+++ b/hw/bsp/maxim/linker/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/maxim/linker/max32651.ld
index 3921d10f2..3921d10f2 100644
--- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld
+++ b/hw/bsp/maxim/linker/max32651.ld
diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/maxim/linker/max32665.ld
index 06c124247..06c124247 100644
--- a/hw/bsp/max32666/max32666.ld
+++ b/hw/bsp/maxim/linker/max32665.ld
diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/maxim/linker/max32690.ld
index 64b906a54..64b906a54 100644
--- a/hw/bsp/max32690/max32690.ld
+++ b/hw/bsp/maxim/linker/max32690.ld
diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/maxim/linker/max78002.ld
index e5c4866ee..e5c4866ee 100644
--- a/hw/bsp/max78002/max78002.ld
+++ b/hw/bsp/maxim/linker/max78002.ld
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
index fb1290088..86f987de9 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
@@ -39,10 +39,10 @@ extern "C" {
 // LED
 #define LED_GPIO              GPIO3
 #define LED_CLK               kCLOCK_GateGPIO3
-#define LED_PIN               12 // red
+#define LED_PIN               12 //red
 #define LED_STATE_ON          0
 
-// ISP button (Dummy, use unused pin
+// ISP button
 #define BUTTON_GPIO           GPIO3
 #define BUTTON_CLK            kCLOCK_GateGPIO3
 #define BUTTON_PIN            29 //sw2
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
index f16bc51f6..5a132dc67 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
@@ -45,14 +45,13 @@ processor_version: 0.13.0
  * Variables
  ******************************************************************************/
 /* System clock frequency. */
-//uint32_t SystemCoreClock;
+//extern uint32_t SystemCoreClock;
 
 /*******************************************************************************
  ************************ BOARD_InitBootClocks function ************************
  ******************************************************************************/
 void BOARD_InitBootClocks(void)
 {
-    BOARD_BootClockFRO96M();
 }
 
 /*******************************************************************************
@@ -386,7 +385,6 @@ void BOARD_BootClockFRO64M(void)
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!Configuration
 name: BOARD_BootClockFRO96M
-called_from_default_init: true
 outputs:
 - {id: CLK_1M_clock.outFreq, value: 1 MHz}
 - {id: CLK_48M_clock.outFreq, value: 48 MHz}
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
index cc8f56e63..47709951b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
@@ -4,7 +4,6 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-
 /***********************************************************************************************************************
  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@@ -18,16 +17,13 @@ product: Pins v14.0
 processor: MCXA153
 package_id: MCXA153VLH
 mcu_data: ksdk2_0
-processor_version: 0.14.3
-pin_labels:
-- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
+processor_version: 0.14.4
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  */
 /* clang-format on */
 
 #include "fsl_common.h"
 #include "fsl_port.h"
-#include "fsl_gpio.h"
 #include "pin_mux.h"
 
 /* FUNCTION ************************************************************************************************************
@@ -47,8 +43,10 @@ void BOARD_InitBootPins(void)
 BOARD_InitPins:
 - options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
 - pin_list:
-  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  */
 /* clang-format on */
@@ -61,15 +59,6 @@ BOARD_InitPins:
  * END ****************************************************************************************************************/
 void BOARD_InitPins(void)
 {
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
-    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
-
-    /* write to PORT0: Peripheral clock is enabled */
-    CLOCK_EnableClock(kCLOCK_GatePORT0);
-
-    /* Write to GPIO3: Peripheral clock is enabled */
     CLOCK_EnableClock(kCLOCK_GateGPIO3);
     /* Write to PORT3: Peripheral clock is enabled */
     CLOCK_EnableClock(kCLOCK_GatePORT3);
@@ -78,30 +67,13 @@ void BOARD_InitPins(void)
     /* PORT3 peripheral is released from reset */
     RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
 
-    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
-                                       kPORT_PullDisable,
-                                       /* Low internal pull resistor value is selected. */
-                                       kPORT_LowPullResistor,
-                                       /* Fast slew rate is configured */
-                                       kPORT_FastSlewRate,
-                                       /* Passive input filter is disabled */
-                                       kPORT_PassiveFilterDisable,
-                                       /* Open drain output is disabled */
-                                       kPORT_OpenDrainDisable,
-                                       /* Low drive strength is configured */
-                                       kPORT_LowDriveStrength,
-                                       /* Normal drive strength is configured */
-                                       kPORT_NormalDriveStrength,
-                                       /* Pin is configured as P3_12 */
-                                       kPORT_MuxAlt0,
-                                       /* Digital input enabled */
-                                       kPORT_InputBufferEnable,
-                                       /* Digital input is not inverted */
-                                       kPORT_InputNormal,
-                                       /* Pin Control Register fields [15:0] are not locked */
-                                       kPORT_UnlockRegister};
-    /* PORT3_12 (pin 38) is configured as P3_12 */
-      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
+
+    /* Write to PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+    /* LPUART0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    /* PORT0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
 
     const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
                                                     kPORT_PullUp,
@@ -152,7 +124,6 @@ void BOARD_InitPins(void)
                                                     kPORT_UnlockRegister};
     /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
     PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
-
 }
 /***********************************************************************************************************************
  * EOF
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
index 06b6fdee9..2c0e617a5 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
@@ -1,9 +1,13 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
 
 #ifndef _PIN_MUX_H_
 #define _PIN_MUX_H_
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
new file mode 100644
index 000000000..a6aa6c2e4
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MCXA156)
+set(MCU_CORE MCXA156)
+
+set(JLINK_DEVICE MCXA156_M33)
+set(PYOCD_TARGET MCXA156)
+set(NXPLINK_DEVICE MCXA156:MCXA156)
+
+set(PORT 0)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXA156VLH
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.h b/hw/bsp/mcx/boards/frdm_mcxa156/board.h
new file mode 100644
index 000000000..6c19797c6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.h
@@ -0,0 +1,69 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: Freedom MCXA156
+   url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_GateGPIO3
+#define LED_PIN               12 // red
+#define LED_STATE_ON          0
+
+// ISP button
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_GateGPIO0
+#define BUTTON_PIN            6 //SW3
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART0
+
+static inline void board_uart_init_clock(void) {
+  /* attach 12 MHz clock to LPUART0 (debug console) */
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+}
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
new file mode 100644
index 000000000..d4a59b32a
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXA156
+MCU_CORE = MCXA156
+PORT = 0
+
+CPU_CORE = cortex-m33-nodsp-nofp
+CFLAGS += \
+	-DCPU_MCXA156VLH \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
+
+JLINK_DEVICE = MCXA156
+PYOCD_TARGET = MCXA156
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c
new file mode 100644
index 000000000..f549af243
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v13.0
+processor: MCXA156
+package_id: MCXA156VLL
+mcu_data: ksdk2_0
+processor_version: 0.15.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockFRO96M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CPU_clock.outFreq, value: 12 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO24M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 6 MHz}
+- {id: System_clock.outFreq, value: 24 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO24M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO48M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO48M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO64M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 64 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
+- {id: FRO_HF_clock.outFreq, value: 64 MHz}
+- {id: MAIN_clock.outFreq, value: 64 MHz}
+- {id: Slow_clock.outFreq, value: 16 MHz}
+- {id: System_clock.outFreq, value: 64 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 64 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO64M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO96M
+called_from_default_init: true
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 96 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
+- {id: FRO_HF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+- {id: UTICK_clock.outFreq, value: 1 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: CLKOUTDIV_HALT, value: Enable}
+- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO96M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h
new file mode 100644
index 000000000..3f5dfefda
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO24M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO64M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c
new file mode 100644
index 000000000..de35103a6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v15.0
+processor: MCXA156
+package_id: MCXA156VLL
+mcu_data: ksdk2_0
+processor_version: 0.15.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+  - {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable,
+    drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+
+      RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+  /* GPIO3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GateGPIO3);
+  /* PORT3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GatePORT3);
+  /* GPIO3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+  /* PORT3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+
+  /* GPIO3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GateGPIO0);
+  /* PORT3: Peripheral clock is enabled */
+  CLOCK_EnableClock(kCLOCK_GatePORT0);
+  /* GPIO3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+  /* PORT3 peripheral is released from reset */
+  RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+
+    /* PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+    /* LPUART0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    /* PORT0 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+
+    const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_RXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_2 (pin 78) is configured as LPUART0_RXD */
+    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config);
+
+    const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_TXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_3 (pin 79) is configured as LPUART0_TXD */
+    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h
new file mode 100644
index 000000000..fb7d1fc04
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
index a35b6818a..bb15620ef 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h
@@ -49,17 +49,22 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_DEV              LPUART4
+#define UART_DEV                   LPUART4
+#define LP_FLEXCOMM_INST           4
+
+#include "fsl_lpflexcomm.h"
 
 static inline void board_uart_init_clock(void) {
+
   /* attach FRO 12M to FLEXCOMM4 */
+
+  LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART);
+
   CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
   CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
   RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
 
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+}
 
 // XTAL
 #define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.c b/hw/bsp/mcx/drivers/spc/fsl_spc.c
new file mode 100644
index 000000000..b16ca5fc5
--- /dev/null
+++ b/hw/bsp/mcx/drivers/spc/fsl_spc.c
@@ -0,0 +1,1680 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_spc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mcx_spc"
+#endif
+
+/*
+ * $Coverage Justification Reference$
+ *
+ * $Justification spc_c_ref_1$
+ * The SPC busy status flag is too short to get coverage data.
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Gets selected power domain's requested low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t.
+ *
+ * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t.
+ */
+spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+
+    uint32_t val;
+
+    val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT);
+    return (spc_power_domain_low_power_mode_t)val;
+}
+
+/*!
+ * brief Gets Isolation status for each power domains.
+ *
+ * This function gets the status which indicates whether certain
+ * peripheral and the IO pads are in a latched state as a result
+ * of having been in POWERDOWN mode.
+ *
+ * param base SPC peripheral base address.
+ * return Current isolation status for each power domains.
+ */
+uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->SC;
+    return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT);
+}
+
+/*!
+ * brief Configs Low power request output pin.
+ *
+ * This function configs the low power request output pin
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer the spc_LowPower_Request_config_t structure.
+ */
+void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg;
+
+    reg = base->LPREQ_CFG;
+    reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK);
+
+    if (config->enable)
+    {
+        reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) |
+               SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override));
+    }
+    else
+    {
+        reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK;
+    }
+
+    base->LPREQ_CFG = reg;
+}
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t.
+ */
+void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg;
+
+    reg = (base->VDD_CORE_GLITCH_DETECT_SC) &
+          ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK |
+            SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK);
+
+    reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) |
+           SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt);
+
+    base->VDD_CORE_GLITCH_DETECT_SC = reg;
+}
+#endif
+
+/*!
+ * brief Set SRAM operate voltage.
+ *
+ * param base SPC peripheral base address.
+ * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage.
+ */
+void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    reg |= SPC_SRAMCTL_VSM(config->operateVoltage);
+
+    base->SRAMCTL = reg;
+
+    if (config->requestVoltageUpdate)
+    {
+        base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK;
+        while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL)
+        {
+            /* Wait until acknowledged */
+            ;
+        }
+        base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK;
+    }
+}
+
+/*!
+ * brief Configs Bandgap mode in Active mode.
+ *
+ * @note To disable bandgap in Active mode:
+ *          1. Disable all LVD's and HVD's in active mode;
+ *          2. Disable Glitch detect;
+ *          3. Configure LDO's and DCDC to low drive strength in active mode;
+ *          4. Invoke this function to disable bandgap in active mode;
+ *      otherwise the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * param base SPC peripheral base address.
+ * param mode The Bandgap mode be selected.
+ *
+ * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode.
+ * retval kStatus_Success Config Bandgap mode in Active power mode successful.
+ */
+status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode)
+{
+    uint32_t reg;
+    uint32_t state;
+
+    reg = base->ACTIVE_CFG;
+
+    if (mode == kSPC_BandgapDisabled)
+    {
+        state = SPC_GetActiveModeVoltageDetectStatus(base);
+
+        /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */
+        if (state != 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+        /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) ==
+            SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+        /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+        if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) ==
+            SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+    }
+
+    reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK;
+    reg |= SPC_ACTIVE_CFG_BGMODE(mode);
+
+    base->ACTIVE_CFG = reg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs Bandgap mode in Low Power mode.
+ *
+ * @note To disable Bandgap in Low-power mode:
+ *          1. Disable all LVD's ad HVD's in low power mode;
+ *          2. Disable Glitch detect in low power mode;
+ *          3. Configure LDO's and DCDC to low drive strength in low power mode;
+ *          4. Disable bandgap in low power mode;
+ *      Otherwise, the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * param base SPC peripheral base address.
+ * param mode The Bandgap mode be selected.
+ *
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ * retval kStatus_Success Config Bandgap mode in Low Power power mode successful.
+ */
+status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode)
+{
+    uint32_t reg;
+    uint32_t state;
+
+    reg = base->LP_CFG;
+
+    if (mode == kSPC_BandgapDisabled)
+    {
+        state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base);
+
+        /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */
+        if (state != 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+        if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+        if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+        if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) ==
+            SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength))
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+        /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */
+        if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+#endif
+    }
+
+    reg &= ~SPC_LP_CFG_BGMODE_MASK;
+    reg |= SPC_LP_CFG_BGMODE(mode);
+    base->LP_CFG = reg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs CORE voltage detect options.
+ *
+ * This function configs CORE voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_core_voltage_detect_config_t structure.
+ */
+void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U);
+
+    base->VD_CORE_CFG = reg;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+/*!
+ * brief Enables the Core High Voltage Detector in Active mode.
+ *
+ * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in active mode.
+ *          false   -   Disable Core High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable Core High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the Core High Voltage Detector in Low Power mode.
+ *
+ * note If the CORE_LDO high voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each regulator
+ * must not set to low in low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in low power mode.
+ *          false   -   Disable Core High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+
+/*!
+ * brief Enables the Core VDD Low Voltage Detector in Active mode.
+ *
+ * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core LVD.
+ *          true    -   Enable Core Low voltage detector in active mode.
+ *          false   -   Disable Core Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable Core Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the Core Low Voltage Detector in Low Power mode.
+ *
+ * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core Low voltage detector in low power mode.
+ *          false   -   Disable Core Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set system VDD Low-voltage level selection.
+ *
+ * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level
+ * must be done after disabling the System VDD low voltage reset and interrupt.
+ *
+ * @deprecated In latest RM, reserved for all devices, will removed in next release.
+ *
+ * param base SPC peripheral base address.
+ * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details.
+ */
+void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)
+{
+    (void)level;
+    (void)base;
+
+    /*
+    uint32_t reg;
+
+    reg = base->VD_SYS_CFG;
+
+    base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK);
+    reg |= SPC_VD_SYS_CFG_LVSEL(level);
+
+    base->VD_SYS_CFG = reg; */
+}
+
+/*!
+ * brief Configs SYS VDD voltage detect options.
+ *
+ * This function config SYS voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_system_voltage_detect_config_t structure.
+ */
+void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U);
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U);
+
+    base->VD_SYS_CFG = reg;
+
+    (void)(config->level);
+    /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */
+}
+
+/*!
+ * brief Enables the System VDD High Voltage Detector in Active mode.
+ *
+ * note If the System_LDO high voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of
+ * each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in active mode.
+ *          false   -   Disable System High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable System High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD Low Voltage Detector in Active mode.
+ *
+ * note If the System_LDO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System LVD.
+ *          true    -   Enable System Low voltage detector in active mode.
+ *          false   -   Disable System Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable the System Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD High Voltage Detector in Low Power mode.
+ *
+ * note If the System_LDO high voltage detect is enabled in low power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in low power mode.
+ *          false   -   Disable System High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the System VDD Low Voltage Detector in Low Power mode.
+ *
+ * note If the System_LDO low voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable System HVD.
+ *          true    -   Enable System Low voltage detector in low power mode.
+ *          false   -   Disable System Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK;
+    }
+
+    return status;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * brief Set IO VDD Low-Voltage level selection.
+ *
+ * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level
+ * must be done after disabling the IO VDD low voltage reset and interrupt.
+ *
+ * param base SPC peripheral base address.
+ * param level IO VDD Low-voltage level selection.
+ */
+void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)
+{
+    uint32_t reg;
+
+    reg = base->VD_IO_CFG;
+
+    base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK);
+    reg |= SPC_VD_IO_CFG_LVSEL(level);
+
+    base->VD_IO_CFG = reg;
+}
+
+/*!
+ * brief Configs IO VDD voltage detect options.
+ *
+ * This function config IO voltage detect options.
+ * Note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * param base       SPC peripheral base address.
+ * param config     Pointer to spc_IO_voltage_detect_config_t structure.
+ */
+void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t reg = 0UL;
+
+    /* Set trip voltage level. */
+    SPC_SetIOVDDLowVoltageLevel(base, config->level);
+
+    reg = base->VD_IO_CFG;
+    reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK);
+
+    reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U);
+    reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U);
+    reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U);
+    reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U);
+
+    base->VD_IO_CFG = reg;
+}
+
+/*!
+ * brief Enables the IO VDD High Voltage Detector in Active mode.
+ *
+ * note If the IO high voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength
+ * of each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in active mode.
+ *          false   -   Disable IO High voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable IO High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD Low Voltage Detector in Active mode.
+ *
+ * note If the IO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength
+ * of each regulator must not set to low in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in active mode.
+ *          false   -   Disable IO Low voltage detector in active mode.
+ *
+ * retval kStatus_Success Enable IO Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD High Voltage Detector in Low Power mode.
+ *
+ * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in low power mode.
+ *          false   -   Disable IO High voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Enables the IO VDD Low Voltage Detector in Low Power mode.
+ *
+ * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO Low voltage detector in low power mode.
+ *          false   -   Disable IO Low voltage detector in low power mode.
+ *
+ * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable)
+{
+    status_t status = kStatus_Success;
+
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * brief Configs external voltage domains
+ *
+ * This function configs external voltage domains isolation.
+ *
+ * param base SPC peripheral base address.
+ * param lowPowerIsoMask The mask of external domains isolate enable during low power mode.
+ * param IsoMask The mask of external domains isolate.
+ */
+void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask)
+{
+    uint32_t reg = 0UL;
+
+    reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask);
+    base->EVD_CFG = reg;
+}
+
+/*!
+ * brief Configs Core LDO Regulator in Active mode.
+ *
+ * @note The bandgap must be enabled before invoking this function.
+ * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_Core_LDO_option_t structure.
+ *
+ * retval kStatus_Success Config Core LDO regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function.
+ * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength,
+ *                                                  all LVDs/HVDs must be disabled before invoking this function.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option)
+{
+    assert(option != NULL);
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameters. */
+    /*  1. Bandgap must not be disabled. */
+    if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /*  2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */
+    if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) &&
+        (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+
+    if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage))
+    {
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+        (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength);
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+        (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage);
+    }
+
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+    (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength);
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Voltage level in Active mode.
+ *
+ * @note In active mode, the Core LDO voltage level should only be changed when the
+ *  Core LDO is in normal drive strength.
+ *
+ * @note Update Core LDO voltage level will set Busy flag,
+ *      this function return only when busy flag is cleared by hardware
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * retval kStatus_SPC_CORELDOVoltageSetFail  Core LDO voltage level should only be
+ *                                          changed when the CORE_LDO is in normal drive strength.
+ * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)
+{
+    if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))
+    {
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+        if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength)
+        {
+            return kStatus_SPC_CORELDOVoltageSetFail;
+        }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+        base->ACTIVE_CFG =
+            ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel));
+
+        /*
+         * $Branch Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+        {
+        }
+    }
+    return kStatus_Success;
+}
+
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+/*!
+ * brief Set Core LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_drive_strength_t.
+ *
+ * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful.
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled,
+            core_ldo's drive strength can not set to low.
+ * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_CoreLDO_LowDriveStrength)
+    {
+        /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low.
+         */
+        if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+        }
+    }
+
+    if (driveStrength == kSPC_CoreLDO_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength));
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+/*!
+ * brief Configs CORE LDO Regulator in low power mode
+ *
+ * This function configs CORE LDO Regulator in Low Power mode.
+ * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage
+ * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap
+ * must be programmed to select bandgap enabled.
+ * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE
+ * LDO Drive Strength is set as Normal.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure.
+ * retval kStatus_Success Config Core LDO regulator in power mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option)
+{
+    status_t status = kStatus_Success;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength);
+    if (status == kStatus_Success)
+    {
+        (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage);
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Voltage level in Low power mode.
+ *
+ * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the
+ * same value in active and low power mode. Application should take care of this limitation.
+ *
+ * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should
+ * take care of this limitation.
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation.
+ * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)
+{
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+            * $Line Coverage Justification$
+            * $ref spc_c_ref_1$.
+            */
+        return kStatus_SPC_Busy;
+    }
+
+    base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel));
+
+    /*
+        * $Branch Coverage Justification$
+        * $ref spc_c_ref_1$.
+        */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Core LDO VDD Regulator Drive Strength in Low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify drive strength of CORE LDO in low power mode.
+ *
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set
+ *           as low.
+ * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_CoreLDO_LowDriveStrength)
+    {
+        /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to
+         * low.
+         */
+        if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+        }
+    }
+    else
+    {
+        /* To specify normal drive strength, the bandgap must be enabled in low power mode. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength));
+
+    return kStatus_Success;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * brief Configs System LDO VDD Regulator in Active mode.
+ *
+ * This function configs System LDO VDD Regulator in Active mode.
+ * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed
+ * to a value that enable the bandgap.
+ * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will
+ * be ignored.
+ * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD
+ * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal.
+ * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled.
+ * Otherwise it will be fail to regulator to Over Drive Voltage.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure.
+ * retval kStatus_Success Config System LDO regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be
+ * ignored.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option)
+{
+    assert(option != NULL);
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameters before setting registers. */
+    /*  1. To set to low DS, all LVDs/HVDs must be disabled previously. */
+    if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) &&
+        (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+    /* 2. If specify normal drive strength, bandgap must not be disabled. */
+    if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) &&
+        (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /* 3. Must disable system LDO high voltage detector before specifying overdrive voltage. */
+    if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) &&
+        ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL))
+    {
+        return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+    }
+
+    (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength);
+    (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set System LDO Regulator voltage level in Active mode.
+ *
+ * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the
+ * life of chip.
+ *
+ * param base SPC peripheral base address.
+ * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully.
+ * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying
+ * overdrive voltage.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel)
+{
+    if (voltageLevel == kSPC_SysLDO_OverDriveVoltage)
+    {
+        /* Must disable system LDO high voltage detector before specifying overdrive voltage. */
+        if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set System LDO Regulator Drive Strength in Active mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength  of System LDO Regulator in Active mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in active mode.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_SysLDO_LowDriveStrength)
+    {
+        /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */
+        if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+        }
+    }
+
+    if (driveStrength == kSPC_SysLDO_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs System LDO regulator in low power modes.
+ *
+ * This function configs System LDO regulator in low power modes.
+ * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power
+ * mode must be programmed to a value that enables the Bandgap.
+ * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration
+ * to set System LDO Regulator drive strength as Low will be ignored.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure.
+ *
+ * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option)
+{
+    status_t status;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength);
+
+    return status;
+}
+
+/*!
+ * brief Set System LDO Regulator drive strength in Low Power Mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode.
+ *
+ * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in low power mode.
+ * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_SysLDO_LowDriveStrength)
+    {
+        /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */
+        if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL)
+        {
+            return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+        }
+    }
+    else
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * brief Configs DCDC VDD Regulator in Active mode.
+ *
+ * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_active_mode_DCDC_option_t structure.
+ *
+ * retval kStatus_Success Config DCDC regulator in Active power mode successful.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option)
+{
+    assert(option != NULL);
+    status_t status = kStatus_Success;
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength);
+
+    if (status == kStatus_Success)
+    {
+        SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage);
+    }
+
+    /*
+     * $Branch Coverage Justification$
+     * $ref spc_c_ref_1$.
+     */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return status;
+}
+
+/*!
+ * brief Set DCDC VDD Regulator drive strength in Active mode.
+ *
+ * note To set DCDC drive strength as Normal, the bandgap must be enabled.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully.
+ * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_DCDC_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs DCDC VDD Regulator in Low power modes.
+ *
+ * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed
+ * to a value that enables the Bandgap.
+ * In Deep Power Down mode, DCDC regulator is always turned off.
+ *
+ * param base SPC peripheral base address.
+ * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure.
+ *
+ * retval kStatus_Success Config DCDC regulator in low power mode successfully.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option)
+{
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        /*
+         * $Line Coverage Justification$
+         * $ref spc_c_ref_1$.
+         */
+        return kStatus_SPC_Busy;
+    }
+
+    /* Check input parameter before setting registers. */
+    if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) &&
+        (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+    /*
+        1. Configure to desired voltage level.
+        2. Change to low drive strength.
+        3. Configure same voltage level in active mode.
+    */
+    SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage);
+
+    /* Change to desired drive strength. */
+    if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength)
+    {
+        (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength);
+    }
+
+    /*
+     * $Branch Coverage Justification$
+     * $ref spc_c_ref_1$.
+     */
+    while ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set DCDC VDD Regulator drive strength in Low power mode.
+ *
+ * param base SPC peripheral base address.
+ * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully.
+ * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)
+{
+    if (driveStrength == kSPC_DCDC_NormalDriveStrength)
+    {
+        /* If specify normal drive strength, bandgap must not be disabled. */
+        if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)
+        {
+            return kStatus_SPC_BandgapModeWrong;
+        }
+    }
+
+    base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Config DCDC Burst options
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_DCDC_burst_config_t structure.
+ */
+void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config)
+{
+    assert(config != NULL);
+    uint32_t reg;
+    reg = base->DCDC_CFG;
+    reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK);
+    reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq);
+    reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U);
+    base->DCDC_CFG = reg;
+
+    /* Blocking until previous DCDC burst completed. */
+    while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL)
+    {
+    }
+
+    if ((config->sofwareBurstRequest) || (config->externalBurstRequest))
+    {
+        /* Clear DCDC burst acknowledge flag. */
+        base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK;
+    }
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest);
+
+    if (config->sofwareBurstRequest)
+    {
+        base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK;
+    }
+}
+
+/*!
+ * brief Set the count value of the reference clock.
+ *
+ * This function set the count value of the reference clock to control the frequency
+ * of dcdc refresh when dcdc is configured in Pulse Refresh mode.
+ *
+ * param base SPC peripheral base address.
+ * param count The count value, 16 bit width.
+ */
+void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count)
+{
+    uint32_t reg;
+
+    reg = base->DCDC_BURST_CFG;
+    reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK;
+    reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count);
+
+    base->DCDC_BURST_CFG = reg;
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * brief Configs all settings of regulators in Active mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in active mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other low-level functions.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_active_mode_regulators_config_t structure.
+ * retval kStatus_Success Config regulators in Active power mode successful.
+ * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong.
+ * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed.
+ * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage.
+ * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored.
+ * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored.
+ */
+status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base);
+
+    /* Check input parameters */
+    /*  1. Bandgap should not be disabled if any of regulator in normal drive strength or
+            if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */
+    if ((config->bandgapMode == kSPC_BandgapDisabled) &&
+        ((activeModeVDValue != 0UL)
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+         || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+         || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+         || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+         || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+             ))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /*  2. Must disable system LDO high voltage detector before specifying SysLDO to overdrive voltage  */
+    if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) &&
+        (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage))
+    {
+        return kStatus_SPC_SYSLDOOverDriveVoltageFail;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+    /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    /* 5. Core LDO and DCDC should have same voltage level. */
+    if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage)
+    {
+        return kStatus_SPC_CORELDOVoltageWrong;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    if ((base->SC & SPC_SC_BUSY_MASK) != 0UL)
+    {
+        return kStatus_SPC_Busy;
+    }
+
+    base->ACTIVE_CFG =
+        ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode);
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configs regulators in Low Power mode.
+ *
+ * This function provides the method to config all on-chip regulators in Low Power mode.
+ *
+ * param base SPC peripheral base address.
+ * param config Pointer to spc_lowpower_mode_regulators_config_t structure.
+ * retval #kStatus_Success Config regulators in Low power mode successful.
+ * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings.
+ * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config)
+{
+    assert(config != NULL);
+    uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base);
+
+    /* Check input parameters */
+    /*  1. Bandgap should not be disabled if any of regulator in normal drive strength or
+            if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */
+    if ((config->bandgapMode == kSPC_BandgapDisabled) &&
+        ((lpModeVDValue != 0UL)
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+         || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+         || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+         || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+         || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength)
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+             ))
+    {
+        return kStatus_SPC_BandgapModeWrong;
+    }
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_SYSLDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+    /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */
+    if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength))
+    {
+        return kStatus_SPC_CORELDOLowDriveStrengthIgnore;
+    }
+#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    /* 5. Core LDO and DCDC should have same voltage level. */
+    if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage)
+    {
+        return kStatus_SPC_CORELDOVoltageWrong;
+    }
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+    base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode);
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+    SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+    SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+    (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption);
+
+    return kStatus_Success;
+}
diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.h b/hw/bsp/mcx/drivers/spc/fsl_spc.h
new file mode 100644
index 000000000..69a001098
--- /dev/null
+++ b/hw/bsp/mcx/drivers/spc/fsl_spc.h
@@ -0,0 +1,2433 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_SPC_H_
+#define FSL_SPC_H_
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mcx_spc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief SPC driver version 2.4.2. */
+#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
+/*! @} */
+
+#define SPC_EVD_CFG_REG_EVDISO_SHIFT   0UL
+#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL
+#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT  16UL
+
+#define SPC_EVD_CFG_REG_EVDISO(x)   ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT)
+#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT)
+#define SPC_EVD_CFG_REG_EVDSTAT(x)  ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT)
+
+#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK))
+#define VDD_CORE_GLITCH_DETECT_SC                             GLITCH_DETECT_SC
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG      SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK               SPC_GLITCH_DETECT_SC_LOCK_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK         SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT              SPC_GLITCH_DETECT_SC_CNT_SELECT
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK                 SPC_GLITCH_DETECT_SC_RE_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE                      SPC_GLITCH_DETECT_SC_RE
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK            SPC_GLITCH_DETECT_SC_TIMEOUT_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT                 SPC_GLITCH_DETECT_SC_TIMEOUT
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK                 SPC_GLITCH_DETECT_SC_IE_MASK
+#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE                      SPC_GLITCH_DETECT_SC_IE
+#endif
+
+/*!
+ * @brief SPC status enumeration.
+ *
+ * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual
+ * to check.
+ */
+enum
+{
+    kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any
+                                                                type of power mode transition. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be
+                                                                                    ignored for LVD/HVD enabled. */
+    kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive
+                                                                    strength setting be ignored for LVD/HVD enabled. */
+#endif                                                                          /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive
+                                                                    voltage failed for SYS LDO HVD must be disabled. */
+    kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U),  /*!< SYS LDO Low driver strength
+                                                                        setting be ignored for LDO LVD/HVD enabled. */
+#endif                                                                             /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+    kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength
+                                                                        setting be ignored for LDO LVD/HVD enabled. */
+    kStatus_SPC_CORELDOVoltageWrong   = MAKE_STATUS(kStatusGroup_SPC, 7U),         /*!< Core LDO voltage is wrong. */
+    kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U),         /*!< Core LDO voltage set fail. */
+    kStatus_SPC_BandgapModeWrong      = MAKE_STATUS(kStatusGroup_SPC, 6U),         /*!< Selected Bandgap Mode wrong. */
+};
+
+/*!
+ * @brief Voltage Detect Status Flags.
+ */
+enum _spc_voltage_detect_flags
+{
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+    kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK,      /*!< IO VDD High-Voltage detect flag. */
+    kSPC_IOVDDLowVoltageDetectFlag  = SPC_VD_STAT_IOVDD_LVDF_MASK,      /*!< IO VDD Low-Voltage detect flag. */
+#endif                                                                  /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+    kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */
+    kSPC_SystemVDDLowVoltageDetectFlag  = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+    kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK,  /*!< Core VDD High-Voltage detect flag. */
+#endif                                                                  /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+    kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK,   /*!< Core VDD Low-Voltage detect flag. */
+};
+
+/*!
+ * @brief SPC power domain isolation status.
+ * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to
+ * check.
+ */
+enum _spc_power_domains
+{
+    kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */
+    kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */
+};
+
+/*!
+ * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes.
+ * @anchor spc_analog_module_control
+ */
+enum _spc_analog_module_control
+{
+    kSPC_controlVref       = 1UL << 0UL,  /*!< Enable/disable VREF in active or low-power modes. */
+    kSPC_controlUsb3vDet   = 1UL << 1UL,  /*!< Enable/disable USB3V_Det in active or low-power modes. */
+    kSPC_controlDac0       = 1UL << 4UL,  /*!< Enable/disable DAC0 in active or low-power modes. */
+    kSPC_controlDac1       = 1UL << 5UL,  /*!< Enable/disable DAC1 in active or low-power modes.  */
+    kSPC_controlDac2       = 1UL << 6UL,  /*!< Enable/disable DAC2 in active or low-power modes. */
+    kSPC_controlOpamp0     = 1UL << 8UL,  /*!< Enable/disable OPAMP0 in active or low-power modes. */
+    kSPC_controlOpamp1     = 1UL << 9UL,  /*!< Enable/disable OPAMP1 in active or low-power modes. */
+    kSPC_controlOpamp2     = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */
+    kSPC_controlCmp0       = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */
+    kSPC_controlCmp1       = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */
+    kSPC_controlCmp2       = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */
+    kSPC_controlCmp0Dac    = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */
+    kSPC_controlCmp1Dac    = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */
+    kSPC_controlCmp2Dac    = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */
+    kSPC_controlAllModules = 0x770773UL,  /*!< Enable/disable all modules in active or low-power modes. */
+};
+
+/*!
+ * @brief The enumeration of spc power domain, the connected power domain is chip specific, please refer to chip's RM
+ * for details.
+ */
+typedef enum _spc_power_domain_id
+{
+    kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */
+    kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */
+} spc_power_domain_id_t;
+
+/*!
+ * @brief The enumeration of Power domain's low power mode.
+ */
+typedef enum _spc_power_domain_low_power_mode
+{
+    kSPC_SleepWithSYSClockRunning     = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */
+    kSPC_DeepSleepWithSysClockOff     = 1U, /*!< Power domain request deep sleep mode with system clock off. */
+    kSPC_PowerDownWithSysClockOff     = 2U, /*!< Power domain request power down mode with system clock off. */
+    kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */
+} spc_power_domain_low_power_mode_t;
+
+/*!
+ * @brief SPC low power request output pin polarity.
+ */
+typedef enum _spc_lowPower_request_pin_polarity
+{
+    kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Request Pin. */
+    kSPC_LowTruePolarity  = 0x1U, /*!< Control the Low Polarity of the Low Power Request Pin. */
+} spc_lowpower_request_pin_polarity_t;
+
+/*!
+ * @brief SPC low power request output override.
+ */
+typedef enum _spc_lowPower_request_output_override
+{
+    kSPC_LowPowerRequestNotForced  = 0x0U, /*!< Not Forced. */
+    kSPC_LowPowerRequestReserved   = 0x1U, /*!< Reserved. */
+    kSPC_LowPowerRequestForcedLow  = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */
+    kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */
+} spc_lowpower_request_output_override_t;
+
+/*!
+ * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_bandgap_mode
+{
+    kSPC_BandgapDisabled              = 0x0U, /*!< Bandgap disabled. */
+    kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */
+    kSPC_BandgapEnabledBufferEnabled  = 0x2U, /*!< Bandgap enabled with Buffer enabled. */
+    kSPC_BandgapReserved              = 0x3U, /*!< Reserved. */
+} spc_bandgap_mode_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode.
+ *
+ * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes.
+ */
+typedef enum _spc_dcdc_voltage_level
+{
+    kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention
+                                           Voltage(Only supportedin low power modes) */
+    kSPC_DCDC_MidVoltage       = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */
+    kSPC_DCDC_NormalVoltage    = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */
+    kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */
+} spc_dcdc_voltage_level_t;
+
+/*!
+ * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode.
+ *
+ * @note Different drive strength differ in these DCDC characteristics:
+ *              Maximum load current
+ *              Quiescent current
+ *              Transient response.
+ */
+typedef enum _spc_dcdc_drive_strength
+{
+    kSPC_DCDC_PulseRefreshMode = 0x0U,    /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode,
+                                           * This enum member is only useful for Low Power Mode config, please
+                                           * note that pulse refresh mode is invalid in SLEEP mode.
+                                           */
+    kSPC_DCDC_LowDriveStrength    = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */
+    kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */
+} spc_dcdc_drive_strength_t;
+#endif                                    /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief SYS LDO regulator voltage level enumeration in Active mode.
+ */
+typedef enum _spc_sys_ldo_voltage_level
+{
+    kSPC_SysLDO_NormalVoltage    = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */
+    kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */
+} spc_sys_ldo_voltage_level_t;
+
+/*!
+ * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_sys_ldo_drive_strength
+{
+    kSPC_SysLDO_LowDriveStrength    = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */
+    kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */
+} spc_sys_ldo_drive_strength_t;
+#endif                                      /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+/*!
+ * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode.
+ */
+typedef enum _spc_core_ldo_voltage_level
+{
+    kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use
+                                            #kSPC_Core_LDO_RetentionVoltage as instead. */
+    kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that
+                                           only useful in low power modes and not all devices support this options
+                                           please refer to devices' RM for details. */
+    kSPC_CoreLDO_MidDriveVoltage  = 0x1U,  /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */
+    kSPC_CoreLDO_NormalVoltage    = 0x2U,  /*!< Core LDO VDD regulator regulate to Normal Voltage. */
+    kSPC_CoreLDO_OverDriveVoltage = 0x3U,  /*!< Core LDO VDD regulator regulate to overdrive Voltage. */
+} spc_core_ldo_voltage_level_t;
+
+/*!
+ * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode.
+ */
+typedef enum _spc_core_ldo_drive_strength
+{
+    kSPC_CoreLDO_LowDriveStrength    = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */
+    kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */
+} spc_core_ldo_drive_strength_t;
+
+/*!
+ * @brief IO VDD Low-Voltage Level Select.
+ */
+typedef enum _spc_low_voltage_level_select
+{
+    kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */
+    kSPC_LowVoltageSafeLevel   = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */
+
+    kSPC_LowVoltageHighRange = 0x0U,   /*!< High range LVD threshold. */
+    kSPC_LowVoltageLowRange  = 0x1U,  /*!< Low range LVD threshold. */
+} spc_low_voltage_level_select_t;
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core.
+ */
+typedef enum _spc_vdd_core_glitch_ripple_counter_select
+{
+    kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+    kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter
+                                                    to detect glitch on VDD Core. */
+} spc_vdd_core_glitch_ripple_counter_select_t;
+#endif
+
+/*!
+ * @brief The list of the operating voltage for the SRAM's read/write timing margin.
+ */
+typedef enum _spc_sram_operate_voltage
+{
+    kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */
+    kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */
+    kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */
+} spc_sram_operate_voltage_t;
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief The configuration of VDD Core glitch detector.
+ */
+typedef struct _spc_vdd_core_glitch_detector_config
+{
+    spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */
+    uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial
+                              glitch is detected. */
+    bool enableReset;          /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */
+    bool enableInterrupt;      /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */
+} spc_vdd_core_glitch_detector_config_t;
+#endif
+
+typedef struct _spc_sram_voltage_config
+{
+    spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's
+                                                     read/write timing margin.  */
+    bool requestVoltageUpdate;                 /*!< Used to control whether request an SRAM trim value change. */
+} spc_sram_voltage_config_t;
+
+/*!
+ * @brief Low Power Request output pin configuration.
+ */
+typedef struct _spc_lowpower_request_config
+{
+    bool enable;                                     /*!< Low Power Request Output enable. */
+    spc_lowpower_request_pin_polarity_t polarity;    /*!< Low Power Request Output pin polarity select. */
+    spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */
+} spc_lowpower_request_config_t;
+
+/*!
+ * @brief Core LDO regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_core_ldo_option
+{
+    spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */
+#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
+    spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength
+                                                            selection in Active mode */
+#endif                                                  /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+} spc_active_mode_core_ldo_option_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief System LDO regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_sys_ldo_option
+{
+    spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */
+    spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength
+                                                            selection in Active mode. */
+} spc_active_mode_sys_ldo_option_t;
+#endif                                                /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator options in Active mode.
+ */
+typedef struct _spc_active_mode_dcdc_option
+{
+    spc_dcdc_voltage_level_t DCDCVoltage;        /*!< DCDC Regulator Voltage Level selection in Active mode. */
+    spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */
+} spc_active_mode_dcdc_option_t;
+#endif                                           /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * @brief Core LDO regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_core_ldo_option
+{
+    spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */
+    spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength
+                                                            selection in Low Power mode */
+} spc_lowpower_mode_core_ldo_option_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @brief System LDO regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_sys_ldo_option
+{
+    spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength
+                                                            selection in Low Power mode. */
+} spc_lowpower_mode_sys_ldo_option_t;
+#endif                                                /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @brief DCDC regulator options in Low Power mode.
+ */
+typedef struct _spc_lowpower_mode_dcdc_option
+{
+    spc_dcdc_voltage_level_t DCDCVoltage;        /*!< DCDC Regulator Voltage Level selection in Low Power mode. */
+    spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */
+} spc_lowpower_mode_dcdc_option_t;
+
+/*!
+ * @brief DCDC Burst configuration.
+ * @deprecated Do not recommend to use this structure.
+ */
+typedef struct _spc_dcdc_burst_config
+{
+    bool sofwareBurstRequest;  /*!< Enable/Disable DCDC Software Burst Request. */
+    bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */
+    bool stabilizeBurstFreq;   /*!< Enable/Disable DCDC frequency stabilization. */
+    uint8_t freq;              /*!< The frequency of the current burst.  */
+} spc_dcdc_burst_config_t;
+#endif                         /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+/*!
+ * @brief CORE/SYS/IO VDD Voltage Detect options.
+ */
+typedef struct _spc_voltage_detect_option
+{
+    bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */
+    bool HVDResetEnable;     /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */
+    bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */
+    bool LVDResetEnable;     /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */
+} spc_voltage_detect_option_t;
+
+/*!
+ * @brief Core Voltage Detect configuration.
+ */
+typedef struct _spc_core_voltage_detect_config
+{
+    spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */
+} spc_core_voltage_detect_config_t;
+
+/*!
+ * @brief System Voltage Detect Configuration.
+ */
+typedef struct _spc_system_voltage_detect_config
+{
+    spc_voltage_detect_option_t option;   /*!< System VDD Voltage Detect option. */
+    spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */
+} spc_system_voltage_detect_config_t;
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * @brief IO Voltage Detect Configuration.
+ */
+typedef struct _spc_io_voltage_detect_config
+{
+    spc_voltage_detect_option_t option;   /*!< IO VDD Voltage Detect option. */
+    spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */
+} spc_io_voltage_detect_config_t;
+#endif                                    /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * @brief Active mode configuration.
+ */
+typedef struct _spc_active_mode_regulators_config
+{
+    spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */
+#endif           /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */
+#endif                                        /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    spc_active_mode_sys_ldo_option_t SysLDOOption;   /*!< Specify System LDO configurations in active mode. */
+#endif                                               /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+    spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */
+} spc_active_mode_regulators_config_t;
+
+/*!
+ * @brief Low Power Mode configuration.
+ */
+typedef struct _spc_lowpower_mode_regulators_config
+{
+    bool lpIREF;                    /*!< Enable/disable low power IREF in low power modes. */
+    spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+    bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */
+#endif           /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+    bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */
+#endif            /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+    spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */
+#endif                                          /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+    spc_lowpower_mode_sys_ldo_option_t SysLDOOption;   /*!< Specify system LDO configurations in low power modes. */
+#endif                                                 /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+    spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */
+} spc_lowpower_mode_regulators_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name SPC Status
+ * @{
+ */
+/*!
+ * @brief Gets Isolation status for each power domains.
+ *
+ * This function gets the status which indicates whether certain
+ * peripheral and the IO pads are in a latched state as a result
+ * of having been in POWERDOWN mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Current isolation status for each power domains. See @ref _spc_power_domains for details.
+ */
+uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base);
+
+/*!
+ * @brief Clears peripherals and I/O pads isolation flags for each power domains.
+ *
+ * This function clears peripherals and I/O pads isolation flags for each power domains.
+ * After recovering from the POWERDOWN mode, user must invoke this function to release the
+ * I/O pads and certain peripherals to their normal run mode state. Before invoking this
+ * function, user must restore chip configuration in particular pin configuration for enabled
+ * WUU wakeup pins.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base)
+{
+    base->SC |= SPC_SC_ISO_CLR_MASK;
+}
+
+/*!
+ * @brief Gets SPC busy status flag.
+ *
+ * This function gets SPC busy status flag. When SPC executing any type of power mode
+ * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set
+ * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level
+ * in ACTIVE mode, the SPC busy status flag is set and this function return true.
+ *
+ * @param base SPC peripheral base address.
+ * @return Ack busy flag.
+ *          true    -   SPC is busy.
+ *          false   -   SPC is not busy.
+ */
+static inline bool SPC_GetBusyStatusFlag(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_BUSY_MASK) != 0UL);
+}
+
+/*!
+ * @brief Checks system low power request.
+ *
+ * @note Only when all power domains request low power mode entry, the result of this function is true. That means when
+ * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register.
+ *
+ * @param base SPC peripheral base address.
+ * @return The system low power request check result.
+ *       - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode
+ *                 configuration are based on the LP_CFG configuration register.
+ *       - \b false SPC in active mode and ACTIVE_CFG register control system power supply.
+ */
+static inline bool SPC_CheckLowPowerReqest(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK);
+}
+
+/*!
+ * @brief Clears system low power request, set SPC in active mode.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_ClearLowPowerRequest(SPC_Type *base)
+{
+    base->SC |= SPC_SC_SPC_LP_REQ_MASK;
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT)
+/*!
+ * @brief Checks whether the power switch is on.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval true The power switch is on.
+ * @retval false The power switch is off.
+ */
+static inline bool SPC_CheckSwitchState(SPC_Type *base)
+{
+    return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL);
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */
+
+/*!
+ * @brief Gets selected power domain's requested low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ *
+ * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t.
+ */
+spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId);
+
+/*!
+ * @brief Checks power domain's low power request.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ * @return The result of power domain's low power request.
+ *            - \b true The selected power domain requests low power mode entry.
+ *            - \b false The selected power domain does not request low power mode entry.
+ */
+static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+    return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) ==
+            SPC_PD_STATUS_PWR_REQ_STATUS_MASK);
+}
+
+/*!
+ * @brief Clears selected power domain's low power request flag.
+ *
+ * @param base SPC peripheral base address.
+ * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t.
+ */
+static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId)
+{
+    assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT);
+    base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK;
+}
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG)
+/*!
+ * @name SRAM Retention LDO Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V.
+ *
+ * @param base SPC peripheral base address.
+ * @param trimValue Reference voltage trim value.
+ */
+static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue)
+{
+    base->SRAMRETLDO_REFTRIM =
+        ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue));
+}
+
+/*!
+ * @brief Enables/disables SRAM retention LDO.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable SRAM LDO :
+ *          - \b true Enable SRAM LDO;
+ *          - \b false Disable SRAM LDO.
+ */
+static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK;
+    }
+    else
+    {
+        base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK;
+    }
+}
+
+/*!
+ * @brief
+ *
+ * @todo Need to check.
+ *
+ * @param base SPC peripheral base address.
+ * @param mask The OR'ed value of SRAM Array.
+ */
+static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask)
+{
+    base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask);
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */
+
+/*!
+ * @name Low Power Request configuration
+ * @{
+ */
+/*!
+ * @brief Configs Low power request output pin.
+ *
+ * This function config the low power request output pin
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer the @ref spc_lowpower_request_config_t structure.
+ */
+void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config);
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG)
+/*!
+ * @name Integrated Power Switch Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the integrated power switch manually.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable the integrated power switch:
+ *             - \b true Enable the integrated power switch;
+ *             - \b false Disable the integrated power switch.
+ */
+static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK);
+    }
+    else
+    {
+        base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK);
+    }
+}
+
+/*!
+ * @brief Enables/disables the integrated power switch automatically.
+ *
+ * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low
+ * power modes:
+ * @code
+ *   SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true);
+ * @endcode
+ *
+ * @param base SPC peripheral base address.
+ * @param sleepGate Enable the integrated power switch when chip enter low power modes:
+ *          - \b true SPC asserts an output pin at low-power entry to power-gate the switch;
+ *          - \b false SPC does not assert an output pin at low-power entry to power-gate the switch.
+ * @param wakeupUngate Enables the switch after wake-up from low power modes:
+ *          - \b true SPC asserts an output pin at low-power exit to power-ungate the switch;
+ *          - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch.
+ */
+static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate)
+{
+    uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK));
+
+    tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate);
+
+    base->CFG = tmp32;
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @name VDD Core Glitch Detector Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t.
+ */
+void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config);
+
+/*!
+ * @brief Checks selected 4-bit glitch ripple counter's output.
+ *
+ * @param base SPC peripheral base address.
+ * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t.
+ *
+ * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings.
+ * @retval false The selected ripple counter output is 0.
+ */
+
+static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base,
+                                                      spc_vdd_core_glitch_ripple_counter_select_t rippleCounter)
+{
+    return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) ==
+            SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)));
+}
+
+/*!
+ * @brief Clears output of selected glitch ripple counter.
+ *
+ * @param base SPC peripheral base address.
+ * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t.
+ */
+static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base,
+                                                      spc_vdd_core_glitch_ripple_counter_select_t rippleCounter)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC |=
+        SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter));
+}
+
+/*!
+ * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK;
+}
+
+/*!
+ * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base)
+{
+    base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK;
+}
+
+/*!
+ * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable.
+ * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable.
+ */
+static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base)
+{
+    return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL);
+}
+
+/*! @} */
+#endif
+
+/*!
+ * @name SRAM Control APIs
+ * @{
+ */
+
+/*!
+ * @brief Set SRAM operate voltage.
+ *
+ * @param base SPC peripheral base address.
+ * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage.
+ */
+void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config);
+
+/*! @} */
+
+/*!
+ * @name Active Mode configuration
+ * @{
+ */
+
+/*!
+ * @brief Gets the Bandgap mode in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration.
+ */
+static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base)
+{
+    return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >>
+                                          SPC_ACTIVE_CFG_BGMODE_SHIFT);
+}
+
+/*!
+ * @brief Gets all voltage detectors status in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return All voltage detectors status in Active mode.
+ */
+static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base)
+{
+    uint32_t state;
+    state = base->ACTIVE_CFG &
+            (
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+                SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK |
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+                SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+                | SPC_ACTIVE_CFG_CORE_HVDE_MASK
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+            );
+    return state;
+}
+
+/*!
+ * @brief Configs Bandgap mode in Active mode.
+ *
+ * @note To disable bandgap in Active mode:
+ *          1. Disable all LVD's and HVD's in active mode;
+ *          2. Disable Glitch detect;
+ *          3. Configure LDO's and DCDC to low drive strength in active mode;
+ *          4. Invoke this function to disable bandgap in active mode;
+ *      otherwise the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * @param base SPC peripheral base address.
+ * @param mode The Bandgap mode be selected.
+ *
+ * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode.
+ * @retval #kStatus_Success Config Bandgap mode in Active power mode successful.
+ */
+status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+/*!
+ * @brief Enables/Disable the CMP Bandgap Buffer in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference voltage to CMP.
+ */
+static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+/*!
+ * @brief Sets the delay when the regulators change voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param delay The number of SPC timer clock cycles.
+ */
+static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay)
+{
+    base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay);
+}
+
+/*!
+ * @brief Configs all settings of regulators in Active mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in active mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_active_mode_regulators_config_t structure.
+ *
+ * @retval #kStatus_Success Config regulators in Active power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to
+ *                                                  System VDD HVD is not disabled.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function.
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config);
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Disables/Enables VDD Core Glitch Detect in Active mode.
+ *
+ * @note State of glitch detect disable feature will be ignored if bandgap is disabled and
+ * glitch detect hardware will be forced to OFF state.
+ *
+ * @param base SPC peripheral base address.
+ * @param disable Used to disable/enable VDD Core Glitch detect feature.
+ *         - \b true Disable VDD Core Low Voltage detect;
+ *         - \b false Enable VDD Core Low Voltage detect.
+ */
+static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable)
+{
+    if (disable)
+    {
+        base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+    else
+    {
+        base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+}
+
+/*!
+ * @brief Check if Glitch detect hardware is enabled in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Indicate if Glitch detector is enabled.
+ */
+static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base)
+{
+    if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */
+
+/*!
+ * @brief Enables analog modules in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value
+ * of @ref spc_analog_module_control.
+ */
+static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Disables analog modules in active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value
+ * of @ref spc_analog_module_control.
+ */
+static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Gets enabled analog modules that enabled in active mode.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @return The mask of enabled analog modules that enabled in active mode.
+ */
+static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base)
+{
+    return base->ACTIVE_CFG1;
+}
+
+/*! @} */
+
+/*!
+ * @name Low Power mode configuration
+ * @{
+ */
+
+/*!
+ * @brief Gets the Bandgap mode in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration.
+ */
+static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base)
+{
+    return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT);
+}
+
+/*!
+ * @brief Gets the status of all voltage detectors in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return The status of all voltage detectors in low power mode.
+ */
+static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base)
+{
+    uint32_t state;
+    state = base->LP_CFG & (
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+                               SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK |
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+                               SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+                               | SPC_LP_CFG_CORE_HVDE_MASK
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+                           );
+    return state;
+}
+
+/*!
+ * @brief Enables/Disables Low Power IREF in low power modes.
+ *
+ * This function enables/disables Low Power IREF. Low Power IREF can only get
+ * disabled in Deep power down mode. In other low power modes, the Low Power IREF
+ * is always enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Low Power IREF.
+ *          true    -   Enable Low Power IREF for Low Power modes.
+ *          false   -   Disable Low Power IREF for Deep Power Down mode.
+ */
+static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK;
+    }
+}
+
+/*!
+ * @brief Configs Bandgap mode in Low Power mode.
+ *
+ * @note To disable Bandgap in Low-power mode:
+ *          1. Disable all LVD's ad HVD's in low power mode;
+ *          2. Disable Glitch detect in low power mode;
+ *          3. Configure LDO's and DCDC to low drive strength in low power mode;
+ *          4. Disable bandgap in low power mode;
+ *      Otherwise, the error status will be reported.
+ *
+ * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please
+ * take care of other system resources.
+ *
+ * @param base SPC peripheral base address.
+ * @param mode The Bandgap mode be selected.
+ *
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful.
+ */
+status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT)
+/*!
+ * @brief Enables/disables SRAM_LDO deep power low power IREF.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable low power IREF :
+ *        - \b true: Low Power IREF is enabled ;
+ *        - \b false: Low Power IREF is disabled for power saving.
+ */
+static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT)
+/*!
+ * @brief Enables/Disables CMP Bandgap Buffer.
+ *
+ * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off
+ * in Deep Power Down mode.
+ *
+ * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference Voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference Voltage to CMP.
+ */
+static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/Disables CMP Bandgap Buffer.
+ *
+ * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off
+ * in Deep Power Down mode.
+ *
+ * @deprecated No longer used.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CMP Bandgap buffer.
+ *          true    -   Enable Buffer Stored Reference Voltage to CMP.
+ *          false   -   Disable Buffer Stored Reference Voltage to CMP.
+ */
+static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT)
+/*!
+ * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes.
+ *
+ * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the
+ * external input CORE VDD to a lower voltage level to reduce internal leakage.
+ * IVS is invalid in Sleep or Deep power down mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IVS.
+ *          true    -   enable CORE VDD IVS in Power Down mode.
+ *          false   -   disable CORE VDD IVS in Power Down mode.
+ */
+static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */
+
+/*!
+ * @brief Sets the delay when exit the low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes.
+ */
+static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay)
+{
+    base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay);
+}
+
+/*!
+ * @brief Configs all settings of regulators in Low power mode at a time.
+ *
+ * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators'
+ * drive strength and voltage level) in low power mode at a time.
+ *
+ * @note Enable/disable LVDs/HVDs before invoking this function.
+ *
+ * @note This function will check input parameters based on hardware restrictions before setting registers, if input
+ * parameters do not satisfy hardware restrictions the specific error will be reported.
+ *
+ * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware
+ * restrictions otherwise some unknown issue may occur:
+ *        1. If Core LDO's drive strength are set to same value in both Active mode and low power mode,
+ *          the voltage level should also set to same value.
+ *        2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set
+ *          to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are
+ *          enabled, an unexpected LVD can occur.
+ *
+ * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_lowpower_mode_regulators_config_t structure.
+ * @retval #kStatus_Success Config regulators in Low power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level.
+ */
+status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config);
+
+#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT)
+/*!
+ * @brief Disable/Enable VDD Core Glitch Detect in low power mode.
+ *
+ * @note State of glitch detect disable feature will be ignored if bandgap is disabled and
+ * glitch detect hardware will be forced to OFF state.
+ *
+ * @param base SPC peripheral base address.
+ * @param disable Used to disable/enable VDD Core Glitch detect feature.
+ *         - \b true Disable VDD Core Low Voltage detect;
+ *         - \b false Enable VDD Core Low Voltage detect.
+ */
+static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable)
+{
+    if (disable)
+    {
+        base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+    else
+    {
+        base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK;
+    }
+}
+
+/*!
+ * @brief Check if Glitch detect hardware is enabled in low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Indicate if Glitch detector is enabled.
+ */
+static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base)
+{
+    if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif
+
+/*!
+ * @brief Enables analog modules in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value
+                    of @ref spc_analog_module_control.
+ */
+static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Disables analog modules in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value
+                    of @ref spc_analog_module_control.
+ */
+static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)
+{
+    base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue);
+}
+
+/*!
+ * @brief Gets enabled analog modules that enabled in low power modes.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @return The mask of enabled analog modules that enabled in low power modes.
+ */
+static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base)
+{
+    return base->LP_CFG1;
+}
+
+/*! @} */
+
+/*!
+ * @name Voltage Detect Status
+ * @{
+ */
+/*!
+ * @brief Get Voltage Detect Status Flags.
+ *
+ * @param base SPC peripheral base address.
+ * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details.
+ */
+static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base)
+{
+    return (uint8_t)(base->VD_STAT);
+}
+
+/*!
+ * @brief Clear Voltage Detect Status Flags.
+ *
+ * @param base SPC peripheral base address.
+ * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details.
+ */
+static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask)
+{
+    base->VD_STAT |= mask;
+}
+
+/*! @} */
+
+/*!
+ * @name Voltage Detect configuration for Core voltage domain.
+ * @{
+ */
+
+/*!
+ * @brief Configs CORE voltage detect options.
+ *
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_core_voltage_detect_config_t structure.
+ */
+void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config);
+
+/*!
+ * @brief Locks Core voltage detect reset setting.
+ *
+ * This function locks core voltage detect reset setting. After invoking this function
+ * any configuration of Core voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlocks Core voltage detect reset setting.
+ *
+ * This function unlocks core voltage detect reset setting. If locks the Core
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the Core Low Voltage Detector in Active mode.
+ *
+ * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core LVD.
+ *          true    -   Enable Core Low voltage detector in active mode.
+ *          false   -   Disable Core Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode.
+ *
+ * This function enables/disables the Core Low Voltage Detector.
+ * If enabled the Core Low Voltage detector. The Bandgap mode in
+ * low power mode must be programmed so that Bandgap is enabled.
+ *
+ * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core Low voltage detector in low power mode.
+ *          false   -   Disable Core Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD)
+/*!
+ * @brief Enables/Disables the Core High Voltage Detector in Active mode.
+ *
+ * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in active mode.
+ *          false   -   Disable Core High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the Core High Voltage Detector in Low Power mode.
+ *
+ * This function enables/disables the Core High Voltage Detector.
+ * If enabled the Core High Voltage detector. The Bandgap mode in
+ * low power mode must be programmed so that Bandgap is enabled.
+ *
+ * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable Core HVD.
+ *          true    -   Enable Core High voltage detector in low power mode.
+ *          false   -   Disable Core High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable);
+#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */
+
+/*! @} */
+
+/*!
+ * @name Voltage detect configuration for System Voltage domain
+ * @{
+ */
+/*!
+ * @brief Set system VDD Low-voltage level selection.
+ *
+ * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level
+ * must be done after disabling the System VDD low voltage reset and interrupt.
+ *
+ * @deprecated In latest RM, reserved for all devices, will removed in next release.
+ *
+ * @param base SPC peripheral base address.
+ * @param level System VDD Low-Voltage level selection.
+ */
+void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level);
+
+/*!
+ * @brief Configs SYS voltage detect options.
+ *
+ * This function config SYS voltage detect options.
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_system_voltage_detect_config_t structure.
+ */
+void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config);
+
+/*!
+ * @brief Lock System voltage detect reset setting.
+ *
+ * This function locks system voltage detect reset setting. After invoking this function
+ * any configuration of System Voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlock System voltage detect reset setting.
+ *
+ * This function unlocks system voltage detect reset setting. If locks the System
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the System High Voltage Detector in Active mode.
+ *
+ * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in active mode.
+ *          false   -   Disable System High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disable the System Low Voltage Detector in Active mode.
+ *
+ * @note If the System_LDO low voltage detect is enabled in Active mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System LVD.
+ *          true    -   Enable System Low voltage detector in active mode.
+ *          false   -   Disable System Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the System High Voltage Detector in Low Power mode.
+ *
+ * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note
+ * that the bandgap must be enabled and the drive strength of each regulator must
+ * not set to low in Low Power  mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System High voltage detector in low power mode.
+ *          false   -   Disable System High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the System Low Voltage Detector in Low Power mode.
+ *
+ * @note If the System_LDO low voltage detect is enabled in Low Power mode,
+ * please note that the bandgap must be enabled and the drive strength of each
+ * regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System HVD.
+ *          true    -   Enable System Low voltage detector in low power mode.
+ *          false   -   Disable System Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*! @} */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD)
+/*!
+ * @name Voltage detect configuration for IO voltage domain
+ * @{
+ */
+/*!
+ * @brief Set IO VDD Low-Voltage level selection.
+ *
+ * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level
+ * must be done after disabling the IO VDD low voltage reset and interrupt.
+ *
+ * @param base SPC peripheral base address.
+ * @param level IO VDD Low-voltage level selection.
+ */
+void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level);
+
+/*!
+ * @brief Configs IO voltage detect options.
+ *
+ * This function config IO voltage detect options.
+ * @note: Setting both the voltage detect interrupt and reset
+ *       enable will cause interrupt to be generated on exit from reset.
+ *       If those conditioned is not desired, interrupt/reset so only one is enabled.
+ *
+ * @param base       SPC peripheral base address.
+ * @param config     Pointer to spc_voltage_detect_config_t structure.
+ */
+void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config);
+
+/*!
+ * @brief Lock IO Voltage detect reset setting.
+ *
+ * This function locks IO voltage detect reset setting. After invoking this function
+ * any configuration of system voltage detect reset will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Unlock IO voltage detect reset setting.
+ *
+ * This function unlocks IO voltage detect reset setting. If locks the IO
+ * voltage detect reset setting, invoking this function to unlock.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base)
+{
+    base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK;
+}
+
+/*!
+ * @brief Enables/Disables the IO High Voltage Detector in Active mode.
+ *
+ * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in active mode.
+ *          false   -   Disable IO High voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO Low Voltage Detector in Active mode.
+ *
+ * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in active mode.
+ *          false   -   Disable IO Low voltage detector in active mode.
+ *
+ * @retval #kStatus_Success Enable IO Low Voltage Detect successfully.
+ */
+status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO High Voltage Detector in Low Power mode.
+ *
+ * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO HVD.
+ *          true    -   Enable IO High voltage detector in low power mode.
+ *          false   -   Disable IO High voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable);
+
+/*!
+ * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode.
+ *
+ * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled
+ * and the drive strength of each regulator must not set to low in Low Power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable IO LVD.
+ *          true    -   Enable IO Low voltage detector in low power mode.
+ *          false   -   Disable IO Low voltage detector in low power mode.
+ *
+ * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully.
+ */
+status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable);
+
+/*! @} */
+
+#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */
+
+/*!
+ * @name External Voltage domains configuration
+ * @{
+ */
+/*!
+ * @brief Configs external voltage domains
+ *
+ * This function configs external voltage domains isolation.
+ *
+ * @param base SPC peripheral base address.
+ * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference
+ * Manual for the Bitmap.
+ * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap.
+ */
+void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask);
+
+/*!
+ * @brief Gets External Domains status.
+ *
+ * @param base SPC peripheral base address.
+ * @return The status of each external domain.
+ */
+static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base)
+{
+    return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT);
+}
+
+/*! @} */
+
+/*!
+ * @name Low Level APIs To Set CORE LDO Regulator
+ * @{
+ */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG)
+/*!
+ * @brief Enable/Disable Core LDO regulator.
+ *
+ * @note The CORE LDO enable bit is write-once.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable CORE LDO Regulator.
+ *          true   -   Enable CORE LDO Regulator.
+ *          false  -   Disable CORE LDO Regulator.
+ */
+static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If CORE_LDO is disabled, all RAMs data will powered off.
+         */
+        base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \
+     FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT)
+/*!
+ * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down.
+ *
+ * @note This function only useful when enabled the CORE LDO Regulator.
+ *
+ * @param base SPC peripheral base address.
+ * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode.
+ *          true    -   CORE LDO Regulator will discharge in Deep Power Down mode.
+ *          false   -   CORE LDO Regulator will not discharge in Deep Power Down mode.
+ */
+static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown)
+{
+    if (pulldown)
+    {
+        base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK;
+    }
+    else
+    {
+        base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */
+
+/*!
+ * @brief Configs Core LDO Regulator in Active mode.
+ *
+ * @note The bandgap must be enabled before invoking this function.
+ * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_core_ldo_option_t structure.
+ *
+ * @retval kStatus_Success Config Core LDO regulator in Active power mode successful.
+ * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function.
+ * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength,
+ *                                                  all LVDs/HVDs must be disabled before invoking this function.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option);
+
+/*!
+ * @brief Set Core LDO Regulator Voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * @note In active mode, the Core LDO voltage level should only be changed when the
+ *  Core LDO is in normal drive strength.
+ *
+ * @note Update Core LDO voltage level will set Busy flag,
+ *      this function return only when busy flag is cleared by hardware
+ *
+ * @retval kStatus_SPC_CORELDOVoltageSetFail  The drive strength of Core LDO is not normal.
+ * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Gets CORE LDO Regulator Voltage level.
+ *
+ * This function returns the voltage level of CORE LDO Regulator in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration.
+ */
+static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base)
+{
+    return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >>
+                                                    SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS)
+/*!
+ * @brief Set Core LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please
+        refer to @ref spc_core_ldo_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled,
+            core_ldo's drive strength can not set to low.
+ * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed.
+ */
+status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t.
+ */
+static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base)
+{
+    return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >>
+                                                     SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT);
+}
+#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
+
+/*!
+ * @brief Configs CORE LDO Regulator in low power mode
+ *
+ * This function configs CORE LDO Regulator in Low Power mode.
+ * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage
+ * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap
+ * must be programmed to select bandgap enabled.
+ * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE
+ * LDO Drive Strength set as Normal.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config Core LDO regulator in power mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option);
+
+/*!
+ * @brief Set Core LDO VDD Regulator Voltage level in Low power mode.
+ *
+ * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power
+ *  mode must be same.
+ * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as
+ * Normal.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please
+        refer to @ref spc_core_ldo_voltage_level_t.
+ *
+ * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same.
+ * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful.
+ * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @return The CORE LDO VDD Regulator's voltage level.
+ */
+static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base)
+{
+    return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >>
+                                                     SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT));
+}
+
+/*!
+ * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify drive strength of CORE LDO in low power mode.
+ *
+ * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set
+ *           as low.
+ * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength.
+ */
+status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Gets CORE LDO VDD Drive Strength for Low Power modes.
+ *
+ * @param base SPC peripheral base address.
+ * @return The CORE LDO's VDD Drive Strength.
+ */
+static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base)
+{
+    return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >>
+                                                     SPC_LP_CFG_CORELDO_VDD_DS_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO)
+/*!
+ * @name Low Level APIs To Set System LDO Regulator
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable System LDO regulator.
+ *
+ * @note The SYSTEM LDO enable bit is write-once.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable System LDO Regulator.
+ *          true     -   Enable System LDO Regulator.
+ *          false    -    Disable System LDO Regulator.
+ */
+static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If SYSTEM_LDO is disabled, may cause some unexpected issues.
+         */
+        base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Enable/Disable current sink feature of System LDO Regulator.
+ *
+ * @param base SPC peripheral base address.
+ * @param sink Enable/Disable current sink feature.
+ *          true    -   Enable current sink feature of System LDO Regulator.
+ *          false   -   Disable current sink feature of System LDO Regulator.
+ */
+static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink)
+{
+    if (sink)
+    {
+        base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK;
+    }
+    else
+    {
+        base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK;
+    }
+}
+
+/*!
+ * @brief Configs System LDO VDD Regulator in Active mode.
+ *
+ * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed
+ * to a value that enables the bandgap.
+ * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will
+ * be ignored.
+ * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD
+ * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal.
+ * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be
+ * disabled. Otherwise it will be fail to regulator to Over Drive Voltage.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config System LDO regulator in Active power mode successful.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive
+ * voltage.
+ * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be
+ * ignored.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option);
+
+/*!
+ * @brief Set System LDO Regulator voltage level in Active mode.
+ *
+ * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the
+ * life of chip.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully.
+ * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifying
+ * overdrive voltage.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel);
+
+/*!
+ * @brief Get System LDO Regulator voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t.
+ */
+static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >>
+                                                   SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT);
+}
+
+/*!
+ * @brief Set System LDO Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength  of System LDO Regulator in Active mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in active mode.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get System LDO Regulator Drive Strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t.
+ */
+static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >>
+                                                    SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT);
+}
+
+/*!
+ * @brief Configs System LDO regulator in low power modes.
+ *
+ * This function configs System LDO regulator in low power modes.
+ * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power
+ * mode must be programmed to a value that enables the Bandgap.
+ * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration
+ * to set System LDO Regulator drive strength as Low will be ignored.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure.
+ *
+ * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option);
+
+/*!
+ * @brief Set System LDO Regulator drive strength in Low Power Mode.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode.
+ *
+ * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully.
+ * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any
+            voltage detect feature is enabled in low power mode.
+ * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables
+            the bandgap if attempt to specify normal drive strength.
+ */
+status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get System LDO Regulator drive strength in Low Power Mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t.
+ */
+static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >>
+                                                    SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT);
+}
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC)
+/*!
+ * @name Low Level APIs To Set DCDC Regulator
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable DCDC Regulator.
+ *
+ * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Enable/Disable DCDC Regulator.
+ *          true    -   Enable DCDC Regulator.
+ *          false   -   Disable DCDC Regulator.
+ */
+static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK;
+    }
+    else
+    {
+        /*
+         * $Branch Coverage Justification$
+         * If DCDC is disabled, all RAMs data will powered off.
+         */
+        base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Config DCDC Burst options
+ *
+ * @param base SPC peripheral base address.
+ * @param config Pointer to spc_dcdc_burst_config_t structure.
+ */
+void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config);
+
+/*!
+ * @brief Trigger a software burst request to DCDC.
+ *
+ * @param base SPC peripheral base address.
+ */
+static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base)
+{
+    /* Blocking until previous DCDC burst completed. */
+    while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL)
+    {
+    }
+
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK;
+}
+
+/*!
+ * @brief Check if burst acknowledge flag is asserted.
+ *
+ * @param base SPC peripheral base address.
+ *
+ * @retval false DCDC burst not complete.
+ * @retval true DCDC burst complete.
+ */
+static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base)
+{
+    return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL);
+}
+
+/*!
+ * @brief Clear DCDC busrt acknowledge flag.
+ *
+ * @param base SPC periphral base address.
+ */
+static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base)
+{
+    base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK;
+}
+
+/*!
+ * @brief Set the count value of the reference clock to configure the period of DCDC not active.
+ *
+ * @note This function is only useful when DCDC's drive strength is set as pulse refresh.
+ * @note The pulse duration(time between on and off) is: reference clock period * (count + 2).
+ *
+ * @param base SPC peripheral base address.
+ * @param count The count value, 16 bit width.
+ */
+void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count);
+
+#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN)
+/*!
+ * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param enable Used to enable/disable bleed resistor.
+ */
+static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK;
+    }
+    else
+    {
+        base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */
+
+/*!
+ * @brief Configs DCDC_CORE Regulator in Active mode.
+ *
+ * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_active_mode_dcdc_option_t structure.
+ *
+ * @retval #kStatus_Success Config DCDC regulator in Active power mode successful.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option);
+
+/*!
+ * @brief Set DCDC_CORE Regulator voltage level in Active mode.
+ *
+ * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)
+{
+    base->ACTIVE_CFG =
+        (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel);
+}
+
+/*!
+ * @brief Get DCDC_CORE Regulator voltage level in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >>
+                                                 SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT));
+}
+
+/*!
+ * @brief Set DCDC_CORE Regulator drive strength in Active mode.
+ *
+ * @note To set DCDC drive strength as Normal, the bandgap must be enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get DCDC_CORE Regulator drive strength in Active mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ */
+static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >>
+                                                  SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT));
+}
+
+/*!
+ * @brief Configs DCDC_CORE Regulator in Low power modes.
+ *
+ * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed
+ * to a value that enables the Bandgap.
+ * @note In Deep Power Down mode, DCDC regulator is always turned off.
+ *
+ * @param base SPC peripheral base address.
+ * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure.
+ *
+ * @retval #kStatus_Success Config DCDC regulator in low power mode successfully.
+ * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition.
+ * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option);
+
+/*!
+ * @brief Set DCDC_CORE Regulator drive strength in Low power mode.
+ *
+ * @note To set drive strength as normal, the bandgap must be enabled.
+ *
+ * @param base SPC peripheral base address.
+ * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ *
+ * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully.
+ * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.
+ */
+status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength);
+
+/*!
+ * @brief Get DCDC_CORE Regulator drive strength in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t.
+ */
+static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base)
+{
+    return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >>
+                                                  SPC_LP_CFG_DCDC_VDD_DS_SHIFT));
+}
+
+/*!
+ * @brief Set DCDC_CORE Regulator voltage level in Low power mode.
+ *
+ * @note To change DCDC level in Low-Power mode:
+ *          1. Configure LP_CFG[DCDC_VDD_LVL] to desired level;
+ *          2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength;
+ *  	    3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1.
+ *
+ * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed,
+ * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level.
+ *
+ * @param base SPC peripheral base address.
+ * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)
+{
+    base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel);
+    (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength);
+    SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel);
+}
+
+/*!
+ * @brief Get DCDC_CORE Regulator voltage level in Low power mode.
+ *
+ * @param base SPC peripheral base address.
+ * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t.
+ */
+static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base)
+{
+    return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >>
+                                                 SPC_LP_CFG_DCDC_VDD_LVL_SHIFT));
+}
+
+/*! @} */
+#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* FSL_SPC_H_ */
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 2b9c60beb..2dfefeb92 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -60,9 +60,14 @@ void USB0_IRQHandler(void) {
 
 
 void board_init(void) {
+
   BOARD_InitPins();
+
   BOARD_InitBootClocks();
+
+  #ifdef XTAL0_CLK_HZ
   CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+  #endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -84,15 +89,7 @@ void board_init(void) {
   board_led_write(0);
 
 #ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
+  // No neo pixel support yet
 #endif
 
   // Button
@@ -103,9 +100,6 @@ void board_init(void) {
 #endif
 
 #ifdef UART_DEV
-  // UART
-//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
 
   // Enable UART when debug log is on
   board_uart_init_clock();
@@ -115,6 +109,7 @@ void board_init(void) {
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
   uart_config.enableTx = true;
   uart_config.enableRx = true;
+
   LPUART_Init(UART_DEV, &uart_config, 12000000u);
 #endif
 
@@ -196,17 +191,6 @@ void board_init(void) {
 
 void board_led_write(bool state) {
   GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
 }
 
 uint32_t board_button_read(void) {
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 413c1b372..f857ed31a 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -10,6 +10,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 if (MCU_VARIANT STREQUAL "MCXA153")
   set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
   set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+elseif (MCU_VARIANT STREQUAL "MCXA156")
+    set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
+    set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
 elseif (MCU_VARIANT STREQUAL "MCXN947")
   set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
   set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
@@ -38,12 +41,14 @@ function(add_board_target BOARD_TARGET)
   endif()
   set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
+
   add_library(${BOARD_TARGET} STATIC
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     # driver
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c
     # mcu
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
@@ -51,18 +56,27 @@ function(add_board_target BOARD_TARGET)
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/drivers/gpio/
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/port
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc
     ${SDK_DIR}/devices/${MCU_VARIANT}
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
     )
 
   if (${FAMILY_MCUS} STREQUAL "MCXN9")
+
     target_sources(${BOARD_TARGET} PRIVATE
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+            ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
+    )
+
+    target_include_directories(${BOARD_TARGET} PUBLIC
+            ${SDK_DIR}/drivers/lpflexcomm
     )
   elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
-    target_sources(${BOARD_TARGET} PRIVATE
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
-  )
+
+
   endif()
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 58149fb8d..676475cc9 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -35,18 +35,19 @@ SRC_C += \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+	${SDK_DIR}/drivers/gpio/fsl_gpio.c \
+	${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \
+	${SDK_DIR}/drivers/common/fsl_common_arm.c\
+	hw/bsp/mcx/drivers/spc/fsl_spc.c
 
 # fsl_lpflexcomm for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
-	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
+	SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
 endif
 
 # fsl_spc for MCXNA15
 ifeq ($(MCU_VARIANT), MCXA153)
-	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
+
 endif
 
 INC += \
@@ -54,5 +55,15 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
 	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/ \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
+  	$(TOP)/$(SDK_DIR)/drivers/common\
+  	$(TOP)/$(SDK_DIR)/drivers/gpio\
+  	$(TOP)/$(SDK_DIR)/drivers/port\
+   	$(TOP)/hw/bsp/mcx/drivers/spc
+
+
+
 
 SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 55c52033c..99d3059fc 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -1,9 +1,6 @@
-# TODO more docs and example on how to use this file
-# TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target
-
 cmake_minimum_required(VERSION 3.20)
 
-# Add tinyusb to a existing target
+# Add tinyusb to a existing target, DCD and HCD drivers are not included
 function(tinyusb_target_add TARGET)
   target_sources(${TARGET} PRIVATE
     # common
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index a54e6d662..299eb97c8 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -81,6 +81,7 @@ typedef struct {
 static netd_interface_t _netd_itf;
 CFG_TUD_MEM_SECTION static netd_epbuf_t _netd_epbuf;
 static bool can_xmit;
+static bool ecm_link_is_up = true;  // Store link state for ECM mode
 
 void tud_network_recv_renew(void) {
   usbd_edpt_xfer(0, _netd_itf.ep_out, _netd_epbuf.rx, NETD_PACKET_SIZE);
@@ -95,7 +96,11 @@ void netd_report(uint8_t *buf, uint16_t len) {
   const uint8_t rhport = 0;
   len = tu_min16(len, sizeof(ecm_notify_t));
 
-  TU_VERIFY(usbd_edpt_claim(rhport, _netd_itf.ep_notif), );
+  if (!usbd_edpt_claim(rhport, _netd_itf.ep_notif)) {
+    TU_LOG1("ECM: Failed to claim notification endpoint\n");
+    return;
+  }
+
   memcpy(_netd_epbuf.notify, buf, len);
   usbd_edpt_xfer(rhport, _netd_itf.ep_notif, _netd_epbuf.notify, len);
 }
@@ -181,8 +186,6 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
     // Open endpoint pair for RNDIS
     TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0);
 
-    tud_network_init_cb();
-
     // we are ready to transmit a packet
     can_xmit = true;
 
@@ -196,11 +199,11 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
 }
 
 static void ecm_report(bool nc) {
-  const ecm_notify_t ecm_notify_nc = {
+  ecm_notify_t ecm_notify_nc = {
     .header = {
       .bmRequestType = 0xA1,
       .bRequest = 0, /* NETWORK_CONNECTION aka NetworkConnection */
-      .wValue = 1,   /* Connected */
+      .wValue = ecm_link_is_up ? 1 : 0,   /* Use current link state */
       .wLength = 0,
     },
   };
@@ -259,7 +262,6 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
                 // TODO should be merge with RNDIS's after endpoint opened
                 // Also should have opposite callback for application to disable network !!
-                tud_network_init_cb();
                 can_xmit = true; // we are ready to transmit a packet
                 tud_network_recv_renew(); // prepare for incoming packets
               }
@@ -286,7 +288,10 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */
           if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) {
             tud_control_xfer(rhport, request, NULL, 0);
-            ecm_report(true);
+            // Only send connection notification if link is up
+            if (ecm_link_is_up) {
+              ecm_report(true);
+            }
           }
         } else {
           if (request->bmRequestType_bit.direction == TUSB_DIR_IN) {
@@ -363,9 +368,8 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   }
 
   if (_netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif)) {
-    if (sizeof(tusb_control_request_t) == xferred_bytes) {
-      ecm_report(false);
-    }
+    // Notification transfer complete - endpoint is now free
+    // Don't automatically send speed change notification after link state changes
   }
 
   return true;
@@ -398,4 +402,31 @@ void tud_network_xmit(void *ref, uint16_t arg) {
   do_in_xfer(_netd_epbuf.tx, len);
 }
 
+// Set the network link state (up/down) and notify the host
+void tud_network_link_state(uint8_t rhport, bool is_up) {
+  (void)rhport;
+
+  if (_netd_itf.ecm_mode) {
+    ecm_link_is_up = is_up;
+
+    // For ECM mode, send network connection notification only
+    // Don't trigger speed change notification for link state changes
+    ecm_notify_t notify = {
+      .header = {
+        .bmRequestType = 0xA1,
+        .bRequest = 0,        /* NETWORK_CONNECTION */
+        .wValue = is_up ? 1 : 0,  /* 0 = disconnected, 1 = connected */
+        .wLength = 0,
+      },
+    };
+    notify.header.wIndex = _netd_itf.itf_num;
+    netd_report((uint8_t *)&notify, sizeof(notify.header));
+  } else {
+    // For RNDIS mode, we would need to implement RNDIS status indication
+    // This is more complex and requires RNDIS_INDICATE_STATUS_MSG
+    // For now, RNDIS doesn't support dynamic link state changes
+    (void)is_up;
+  }
+}
+
 #endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index f9fda0698..02833c5f1 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -110,6 +110,7 @@ typedef struct {
     NOTIFICATION_DONE
   } notification_xmit_state;                            // state of notification transmission
   bool notification_xmit_is_running;                    // notification is currently transmitted
+  bool link_is_up;                                      // current link state
 
   // misc
   bool tud_network_recv_renew_active;                   // tud_network_recv_renew() is active (avoid recursive invocations)
@@ -218,7 +219,7 @@ static void notification_xmit(uint8_t rhport, bool force_next) {
           .direction = TUSB_DIR_IN
         },
         .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
-        .wValue = 1 /* Connected */,
+        .wValue = ncm_interface.link_is_up ? 1 : 0,  /* Dynamic link state */
         .wIndex = ncm_interface.itf_num,
         .wLength = 0,
       },
@@ -232,6 +233,7 @@ static void notification_xmit(uint8_t rhport, bool force_next) {
     ncm_interface.notification_xmit_is_running = true;
   } else {
     TU_LOG_DRV("  NOTIFICATION_FINISHED\n");
+    ncm_interface.notification_xmit_is_running = false;
   }
 } // notification_xmit
 
@@ -755,6 +757,32 @@ static void tud_network_recv_renew_r(uint8_t rhport) {
   tud_network_recv_renew();
 } // tud_network_recv_renew
 
+/**
+ * Set the link state and send notification to host
+ */
+void tud_network_link_state(uint8_t rhport, bool is_up) {
+  TU_LOG_DRV("tud_network_link_state(%d, %d)\n", rhport, is_up);
+
+  if (ncm_interface.link_is_up == is_up) {
+    // No change in link state
+    return;
+  }
+
+  ncm_interface.link_is_up = is_up;
+
+  // Only send notification if we have an active data interface
+  if (ncm_interface.itf_data_alt != 1) {
+    TU_LOG_DRV("  link state notification skipped (interface not active)\n");
+    return;
+  }
+
+  // Reset notification state to send link state update
+  ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
+
+  // Trigger notification transmission
+  notification_xmit(rhport, false);
+}
+
 //-----------------------------------------------------------------------------
 //
 // all the netd_*() stuff (interface TinyUSB -> driver)
@@ -774,6 +802,12 @@ void netd_init(void) {
   for (int i = 0; i < RECV_NTB_N; ++i) {
     ncm_interface.recv_free_ntb[i] = &ncm_epbuf.recv[i].ntb;
   }
+  // Default link state - can be configured via CFG_TUD_NCM_DEFAULT_LINK_UP
+  #ifdef CFG_TUD_NCM_DEFAULT_LINK_UP
+  ncm_interface.link_is_up = CFG_TUD_NCM_DEFAULT_LINK_UP;
+  #else
+  ncm_interface.link_is_up = true; // Default to link up if not set.
+  #endif
 } // netd_init
 
 /**
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 4c9a92f2d..fff2623b7 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -87,6 +87,11 @@ void tud_network_init_cb(void);
 // TODO removed later since it is not part of tinyusb stack
 extern uint8_t tud_network_mac_address[6];
 
+//------------- NCM -------------//
+
+// Set the network link state (up/down) and notify the host
+void tud_network_link_state(uint8_t rhport, bool is_up);
+
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 2fc0ac944..7f1fd8c41 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -196,8 +196,8 @@ void vendord_reset(uint8_t rhport) {
 
 uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) {
   TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0);
+  const uint8_t* desc_end = (const uint8_t*)desc_itf + max_len;
   const uint8_t* p_desc = tu_desc_next(desc_itf);
-  const uint8_t* desc_end = (uint8_t const*)desc_itf + max_len;
 
   // Find available interface
   vendord_interface_t* p_vendor = NULL;
@@ -210,26 +210,26 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin
   TU_VERIFY(p_vendor, 0);
 
   p_vendor->itf_num = desc_itf->bInterfaceNumber;
-  uint8_t found_ep = 0;
-  while (found_ep < desc_itf->bNumEndpoints) {
-    // skip non-endpoint descriptors
-    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) ) {
-      p_desc = tu_desc_next(p_desc);
-    }
-    if (p_desc >= desc_end) {
-      break;
-    }
-
-    const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
-    TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
-    found_ep++;
+  while (tu_desc_is_valid(p_desc, desc_end)) {
+    const uint8_t desc_type = tu_desc_type(p_desc);
+    if (desc_type == TUSB_DESC_INTERFACE || desc_type == TUSB_DESC_INTERFACE_ASSOCIATION) {
+      break; // end of this interface
+    } else if (desc_type == TUSB_DESC_ENDPOINT) {
+      const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
+      TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
 
-    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
-      tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep);
-      tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
-    } else {
-      tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep);
-      TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data
+      // open endpoint stream, skip if already opened
+      if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+        if (p_vendor->tx.stream.ep_addr == 0) {
+          tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep);
+          tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
+        }
+      } else {
+        if (p_vendor->rx.stream.ep_addr == 0) {
+          tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep);
+          TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data
+        }
+      }
     }
 
     p_desc = tu_desc_next(p_desc);
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index a0175d664..6678265b5 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -369,6 +369,10 @@
   #define TUP_DCD_ENDPOINT_MAX    7 // only 5 TX FIFO for endpoint IN
   #define CFG_TUSB_OS_INC_PATH_DEFAULT   freertos/
 
+  #if CFG_TUSB_MCU == OPT_MCU_ESP32S3
+    #define TUP_MCU_MULTIPLE_CORE 1
+  #endif
+
   // Disable slave if DMA is enabled
   #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUD_DWC2_DMA_ENABLE
   #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUH_DWC2_DMA_ENABLE
@@ -381,6 +385,8 @@
 
   #define CFG_TUSB_OS_INC_PATH_DEFAULT   freertos/
 
+  #define TUP_MCU_MULTIPLE_CORE   1
+
   // Disable slave if DMA is enabled
   #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUD_DWC2_DMA_ENABLE
   #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUH_DWC2_DMA_ENABLE
@@ -410,6 +416,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define TUP_DCD_EDPT_ISO_ALLOC
   #define TUP_DCD_ENDPOINT_MAX    16
+  #define TUP_MCU_MULTIPLE_CORE   1
 
   #define TU_ATTR_FAST_FUNC       __attribute__((section(".time_critical.tinyusb")))
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e000a4bd3..fd7f01b67 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -586,6 +586,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_subtype(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_SUBTYPE];
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_is_valid(void const* desc, uint8_t const* desc_end) {
+  const uint8_t* desc8 = (uint8_t const*) desc;
+  return (desc8 < desc_end) && (tu_desc_next(desc) <= desc_end);
+}
+
+
 // find descriptor that match byte1 (type)
 uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1);
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 9c381d5e0..6e5fcf3b6 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -340,15 +340,16 @@ TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8
 enum { RHPORT_INVALID = 0xFFu };
 tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
-// Event queue
-// usbd_int_set() is used as mutex in OS NONE config
+static OSAL_SPINLOCK_DEF(_usbd_spin, usbd_int_set);
+
+// Event queue: usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
-tu_static osal_queue_t _usbd_q;
+static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
 #if OSAL_MUTEX_REQUIRED
-  tu_static osal_mutex_def_t _ubsd_mutexdef;
-  tu_static osal_mutex_t _usbd_mutex;
+  static osal_mutex_def_t _ubsd_mutexdef;
+  static osal_mutex_t _usbd_mutex;
 #else
   #define _usbd_mutex   NULL
 #endif
@@ -466,7 +467,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   TU_ASSERT(rh_init);
 
   TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport,
-    rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
+              rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
@@ -475,6 +476,8 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   tu_varclr(&_usbd_dev);
   _usbd_queued_setup = 0;
 
+  osal_spin_init(&_usbd_spin);
+
 #if OSAL_MUTEX_REQUIRED
   // Init device mutex
   _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
@@ -1242,17 +1245,21 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr)
 // USBD API For Class Driver
 //--------------------------------------------------------------------+
 
-void usbd_int_set(bool enabled)
-{
-  if (enabled)
-  {
+void usbd_int_set(bool enabled) {
+  if (enabled) {
     dcd_int_enable(_usbd_rhport);
-  }else
-  {
+  } else {
     dcd_int_disable(_usbd_rhport);
   }
 }
 
+void usbd_spin_lock(bool in_isr) {
+  osal_spin_lock(&_usbd_spin, in_isr);
+}
+void usbd_spin_unlock(bool in_isr) {
+  osal_spin_unlock(&_usbd_spin, in_isr);
+}
+
 // Parse consecutive endpoint descriptors (IN & OUT)
 bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
 {
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 190d6fd7f..5c6f9dbee 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -68,6 +68,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR
 typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
 void usbd_int_set(bool enabled);
+void usbd_spin_lock(bool in_isr);
+void usbd_spin_unlock(bool in_isr);
 
 //--------------------------------------------------------------------+
 // USBD Endpoint API
diff --git a/src/host/usbh.c b/src/host/usbh.c
index b7d5a05f2..f2e5c1f0e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -147,6 +147,9 @@ static osal_mutex_t _usbh_mutex;
 #define _usbh_mutex   NULL
 #endif
 
+// Spinlock for interrupt handler
+static OSAL_SPINLOCK_DEF(_usbh_spin, usbh_int_set);
+
 // Event queue: usbh_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
@@ -424,6 +427,8 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
     TU_LOG_INT_USBH(sizeof(tu_fifo_t));
     TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
 
+    osal_spin_init(&_usbh_spin);
+
     // Event queue
     _usbh_q = osal_queue_create(&_usbh_qdef);
     TU_ASSERT(_usbh_q != NULL);
@@ -895,6 +900,14 @@ void usbh_int_set(bool enabled) {
   }
 }
 
+void usbh_spin_lock(bool in_isr) {
+  osal_spin_lock(&_usbh_spin, in_isr);
+}
+
+void usbh_spin_unlock(bool in_isr) {
+  osal_spin_unlock(&_usbh_spin, in_isr);
+}
+
 void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
   hcd_event_t event = { 0 };
   event.event_id = USBH_EVENT_FUNC_CALL;
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 6f34d8bb3..13eede869 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -42,7 +42,7 @@
 //--------------------------------------------------------------------+
 
 // Endpoint Bulk size depending on host mx speed
-#define TUH_EPSIZE_BULK_MPS   (TUD_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
+#define TUH_EPSIZE_BULK_MPS   (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
 
 // forward declaration
 struct tuh_xfer_s;
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 61b012493..cb092e5f3 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -71,6 +71,9 @@ void usbh_int_set(bool enabled);
 
 void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
 
+void usbh_spin_lock(bool in_isr);
+void usbh_spin_unlock(bool in_isr);
+
 //--------------------------------------------------------------------+
 // USBH Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 38d45da44..a33280425 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -75,6 +75,10 @@ typedef void (*osal_task_func_t)( void * );
 // OSAL Porting API
 // Should be implemented as static inline function in osal_port.h header
 /*
+   void osal_spin_init(osal_spinlock_t *ctx);
+   void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr)
+   void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr);
+
    osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
    bool osal_semaphore_delete(osal_semaphore_t semd_hdl);
    bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index a3a0f3a3f..bde5ec010 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -42,20 +42,20 @@ extern "C" {
 //--------------------------------------------------------------------+
 
 #if configSUPPORT_STATIC_ALLOCATION
-  typedef StaticSemaphore_t osal_semaphore_def_t;
-  typedef StaticSemaphore_t osal_mutex_def_t;
+typedef StaticSemaphore_t osal_semaphore_def_t;
+typedef StaticSemaphore_t osal_mutex_def_t;
 #else
-  // not used therefore defined to smallest possible type to save space
-  typedef uint8_t osal_semaphore_def_t;
-  typedef uint8_t osal_mutex_def_t;
+
+// not used therefore defined to the smallest possible type to save space
+typedef uint8_t osal_semaphore_def_t;
+typedef uint8_t osal_mutex_def_t;
 #endif
 
 typedef SemaphoreHandle_t osal_semaphore_t;
 typedef SemaphoreHandle_t osal_mutex_t;
 typedef QueueHandle_t osal_queue_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
@@ -83,16 +83,14 @@ typedef struct
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-
 TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) {
-  if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY;
-  if ( msec == 0 ) return 0;
+  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) { return portMAX_DELAY; }
+  if (msec == 0) { return 0; }
 
   uint32_t ticks = pdMS_TO_TICKS(msec);
 
-  // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms
-  // we still need to delay at least 1 tick
-  if ( ticks == 0 ) ticks = 1;
+  // If configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms, we still need to delay at least 1 tick
+  if (ticks == 0) { ticks = 1; }
 
   return ticks;
 }
@@ -102,9 +100,70 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
-// Semaphore API
+// Spinlock API
 //--------------------------------------------------------------------+
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+#if TUSB_MCU_VENDOR_ESPRESSIF
+// Espressif critical take spinlock as argument and does not use in_isr
+typedef portMUX_TYPE osal_spinlock_t;
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  spinlock_initialize(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  portENTER_CRITICAL(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  portEXIT_CRITICAL(ctx);
+}
+
+#else
+
+typedef UBaseType_t osal_spinlock_t;
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (in_isr) {
+    if (!TUP_MCU_MULTIPLE_CORE) {
+      (void) ctx;
+      return; // single core MCU does not need to lock in ISR
+    }
+    *ctx = taskENTER_CRITICAL_FROM_ISR();
+  } else {
+    taskENTER_CRITICAL();
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (in_isr) {
+    if (!TUP_MCU_MULTIPLE_CORE) {
+      (void) ctx;
+      return; // single core MCU does not need to lock in ISR
+    }
+    taskEXIT_CRITICAL_FROM_ISR(*ctx);
+  } else {
+    taskEXIT_CRITICAL();
+  }
+}
 
+#endif
+
+//--------------------------------------------------------------------+
+// Semaphore API
+//--------------------------------------------------------------------+
 TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateBinaryStatic(semdef);
@@ -120,19 +179,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
-  if ( !in_isr ) {
+  if (!in_isr) {
     return xSemaphoreGive(sem_hdl) != 0;
   } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
-
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
-    if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
-#else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-#endif
-
     return res != 0;
   }
 }
@@ -148,7 +200,6 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 //--------------------------------------------------------------------+
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
-
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateMutexStatic(mdef);
@@ -174,7 +225,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 //--------------------------------------------------------------------+
 // QUEUE API
 //--------------------------------------------------------------------+
-
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   osal_queue_t q;
 
@@ -201,19 +251,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
-  if ( !in_isr ) {
+  if (!in_isr) {
     return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0;
   } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
-
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5)
-    if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
-#else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-#endif
-
     return res != 0;
   }
 }
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index 16def0d2a..ee95e684f 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -41,6 +41,32 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef os_sr_t osal_spinlock_t;
+
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+ (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  OS_ENTER_CRITICAL(*ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  OS_ENTER_CRITICAL(*ctx);
+}
+
+//--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
 typedef struct os_sem  osal_semaphore_def_t;
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 40e9bb83a..a8eb1042b 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -41,6 +41,33 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
 #endif
 
 //--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef struct {
+  void (* interrupt_set)(bool);
+} osal_spinlock_t;
+
+// For SMP, spinlock must be locked by hardware, cannot just use interrupt
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name = { .interrupt_set = _int_set }
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!in_isr) {
+    ctx->interrupt_set(false);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!in_isr) {
+    ctx->interrupt_set(true);
+  }
+}
+
+//--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
 typedef struct {
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 315de0950..ace5907d7 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -44,6 +44,27 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef critical_section_t osal_spinlock_t; // pico implement critical section with spinlock
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  critical_section_init(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  (void) in_isr;
+  critical_section_enter_blocking(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  (void) in_isr;
+  critical_section_exit(ctx);
+}
+
+//--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
 typedef struct semaphore osal_semaphore_def_t, * osal_semaphore_t;
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index c27814835..a778f5425 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -43,6 +43,32 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef struct rt_spinlock osal_spinlock_t;
+
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  rt_spin_lock_init(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  rt_spin_lock(ctx);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  rt_spin_unlock(ctx);
+}
+
+//--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
 typedef struct rt_semaphore osal_semaphore_def_t;
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index 35909e4d6..35860ddd5 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -57,6 +57,25 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
+// Spinlock API, stub not implemented
+//--------------------------------------------------------------------+
+typedef uint8_t osal_spinlock_t;
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  (void) ctx; (void) in_isr;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  (void) ctx; (void) in_isr;
+}
+
+//--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
 typedef OS_SEM osal_semaphore_def_t;
diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h
index 8ecb13c6d..91f225f79 100644
--- a/src/osal/osal_zephyr.h
+++ b/src/osal/osal_zephyr.h
@@ -36,6 +36,35 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 }
 
 //--------------------------------------------------------------------+
+// Spinlock API
+//--------------------------------------------------------------------+
+typedef struct {
+  struct k_spinlock lock;
+  k_spinlock_key_t key;
+} osal_spinlock_t;
+
+#define OSAL_SPINLOCK_DEF(_name, _int_set) \
+  osal_spinlock_t _name
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
+  (void) ctx;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  ctx->key = k_spin_lock(&ctx->lock);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
+  k_spin_unlock(&ctx->lock, ctx->key);
+}
+
+//--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
 typedef struct k_sem osal_semaphore_def_t, * osal_semaphore_t;
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index bb33200f2..971dbd62e 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,9 +28,9 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-#include <stdatomic.h>
 #include "host/hcd.h"
 #include "host/usbh.h"
+#include "host/usbh_pvt.h"
 
 //--------------------------------------------------------------------+
 //
@@ -233,7 +233,7 @@ typedef struct {
     uint8_t hxfr;
   }sndfifo_owner;
 
-  atomic_flag busy; // busy transferring
+  bool busy_lock; // busy transferring
 
 #if OSAL_MUTEX_REQUIRED
   OSAL_MUTEX_DEF(spi_mutexdef);
@@ -327,7 +327,9 @@ TU_ATTR_ALWAYS_INLINE static inline void mode_write(uint8_t rhport, uint8_t data
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
-  if ( _hcd_data.peraddr == data ) return; // no need to change address
+  if (_hcd_data.peraddr == data) {
+    return; // no need to change address
+  }
 
   _hcd_data.peraddr = data;
   reg_write(rhport, PERADDR_ADDR, data, in_isr);
@@ -373,7 +375,7 @@ TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint
 
 static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
   uint8_t hirq;
-  uint8_t const reg = RCVVFIFO_ADDR;
+  const uint8_t reg = RCVVFIFO_ADDR;
 
   max3421_spi_lock(rhport, in_isr);
 
@@ -389,7 +391,7 @@ static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool
 //--------------------------------------------------------------------+
 
 static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
-  uint8_t const is_out = 1-ep_dir;
+  const uint8_t is_out = 1-ep_dir;
   for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     // control endpoint is bi-direction (skip check)
@@ -727,8 +729,8 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
-  uint8_t const ep_num = tu_edpt_number(ep_addr);
-  uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
+  const uint8_t ep_num = tu_edpt_number(ep_addr);
+  const uint8_t ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
   TU_VERIFY(ep);
 
@@ -744,8 +746,17 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xferred_len = 0;
   ep->state = EP_STATE_ATTEMPT_1;
 
+  bool has_xfer = false;
+
+  usbh_spin_lock(false);
+  if (!_hcd_data.busy_lock) {
+    _hcd_data.busy_lock = true;
+    has_xfer = true;
+  }
+  usbh_spin_unlock(false);
+
   // carry out transfer if not busy
-  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+  if (has_xfer) {
     xact_generic(rhport, ep, true, false);
   }
 
@@ -781,8 +792,17 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->xferred_len = 0;
   ep->state = EP_STATE_ATTEMPT_1;
 
+  bool has_xfer = false;
+
+  usbh_spin_lock(false);
+  if (!_hcd_data.busy_lock) {
+    _hcd_data.busy_lock = true;
+    has_xfer = true;
+  }
+  usbh_spin_unlock(false);
+
   // carry out transfer if not busy
-  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+  if (has_xfer) {
     xact_setup(rhport, ep, false);
   }
 
@@ -848,8 +868,8 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
 }
 
 static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) {
-  uint8_t const ep_dir = 1-ep->hxfr_bm.is_out;
-  uint8_t const ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir);
+  const uint8_t ep_dir = 1 - ep->hxfr_bm.is_out;
+  const uint8_t ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir);
 
   // save data toggle
   if (ep_dir) {
@@ -867,7 +887,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
     xact_generic(rhport, next_ep, true, in_isr);
   }else {
     // no more pending
-    atomic_flag_clear(&_hcd_data.busy);
+    usbh_spin_lock(in_isr);
+    _hcd_data.busy_lock = false;
+    usbh_spin_unlock(in_isr);
   }
 }
 
@@ -906,7 +928,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
         xact_generic(rhport, next_ep, true, in_isr);
       } else {
         // no more pending in this frame -> clear busy
-        atomic_flag_clear(&_hcd_data.busy);
+        usbh_spin_lock(in_isr);
+        _hcd_data.busy_lock = false;
+        usbh_spin_unlock(in_isr);
       }
       return;
 
@@ -997,8 +1021,8 @@ void print_hirq(uint8_t hirq) {
 // Interrupt handler
 void hcd_int_handler(uint8_t rhport, bool in_isr) {
   uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien;
-  if (!hirq) return;
-//  print_hirq(hirq);
+  if (!hirq) { return; }
+  //  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
@@ -1017,8 +1041,19 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     }
 
     // start usb transfer if not busy
-    if (ep_retry != NULL && !atomic_flag_test_and_set(&_hcd_data.busy)) {
-      xact_generic(rhport, ep_retry, true, in_isr);
+    if (ep_retry != NULL) {
+      bool has_xfer = false;
+
+      usbh_spin_lock(in_isr);
+      if (!_hcd_data.busy_lock) {
+        _hcd_data.busy_lock = true;
+        has_xfer = true;
+      }
+      usbh_spin_unlock(in_isr);
+
+      if (has_xfer) {
+        xact_generic(rhport, ep_retry, true, in_isr);
+      }
     }
   }
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index a716dc24c..244f5a2d4 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -239,7 +239,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   usbmode |= USBMODE_CM_DEVICE;
   dcd_reg->USBMODE = usbmode;
 
+#ifdef CFG_TUD_CI_HS_VBUS_CHARGE
+  dcd_reg->OTGSC = OTGSC_VBUS_CHARGE | OTGSC_OTG_TERMINATION;
+#else
   dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
+#endif
 
 #if !TUD_OPT_HIGH_SPEED
   dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 52d675611..865c51894 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -39,6 +39,7 @@
 #define DWC2_DEBUG    2
 
 #include "device/dcd.h"
+#include "device/usbd_pvt.h"
 #include "dwc2_common.h"
 
 //--------------------------------------------------------------------+
@@ -52,6 +53,7 @@ typedef struct {
   uint8_t interval;
 } xfer_ctl_t;
 
+// This variable is modified from ISR context, so it must be protected by critical section
 static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
 
@@ -321,6 +323,9 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
   }
 }
 
+// Since this function returns void, it is not possible to return a boolean success message
+// We must make sure that this function is not called when the EP is disabled
+// Must be called from critical section
 static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
@@ -531,6 +536,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
+  usbd_spin_lock(false);
+
   _dcd_data.allocated_epin_count = 0;
 
   // Disable non-control interrupt
@@ -548,8 +555,9 @@ void dcd_edpt_close_all(uint8_t rhport) {
 
   dfifo_flush_tx(dwc2, 0x10); // all tx fifo
   dfifo_flush_rx(dwc2);
-
   dfifo_device_init(rhport); // re-init dfifo
+
+  usbd_spin_unlock(false);
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
@@ -567,21 +575,31 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
-
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer = buffer;
-  xfer->ff = NULL;
-  xfer->total_len = total_bytes;
+  bool ret;
 
-  // EP0 can only handle one packet
-  if (epnum == 0) {
-    _dcd_data.ep0_pending[dir] = total_bytes;
+  usbd_spin_lock(false);
+
+  if (xfer->max_size == 0) {
+    ret = false;  // Endpoint is closed
+  } else {
+    xfer->buffer = buffer;
+    xfer->ff = NULL;
+    xfer->total_len = total_bytes;
+
+    // EP0 can only handle one packet
+    if (epnum == 0) {
+      _dcd_data.ep0_pending[dir] = total_bytes;
+    }
+
+    // Schedule packets to be sent within interrupt
+    edpt_schedule_packets(rhport, epnum, dir);
+    ret = true;
   }
 
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir);
+  usbd_spin_unlock(false);
 
-  return true;
+  return ret;
 }
 
 // The number of bytes has to be given explicitly to allow more flexible control of how many
@@ -594,17 +612,27 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
-
   xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer = NULL;
-  xfer->ff = ff;
-  xfer->total_len = total_bytes;
+  bool ret;
 
-  // Schedule packets to be sent within interrupt
-  // TODO xfer fifo may only available for slave mode
-  edpt_schedule_packets(rhport, epnum, dir);
+  usbd_spin_lock(false);
 
-  return true;
+  if (xfer->max_size == 0) {
+    ret = false;  // Endpoint is closed
+  } else {
+    xfer->buffer = NULL;
+    xfer->ff = ff;
+    xfer->total_len = total_bytes;
+
+    // Schedule packets to be sent within interrupt
+    // TODO xfer fifo may only available for slave mode
+    edpt_schedule_packets(rhport, epnum, dir);
+    ret = true;
+  }
+
+  usbd_spin_unlock(false);
+
+  return ret;
 }
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
@@ -631,6 +659,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
 //--------------------------------------------------------------------
 
 // 7.4.1 Initialization on USB Reset
+// Must be called from critical section
 static void handle_bus_reset(uint8_t rhport) {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
   const uint8_t ep_count =  dwc2_ep_count(dwc2);
@@ -983,14 +1012,16 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
  */
 void dcd_int_handler(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
   const uint32_t gintmask = dwc2->gintmsk;
   const uint32_t gintsts = dwc2->gintsts & gintmask;
 
   if (gintsts & GINTSTS_USBRST) {
     // USBRST is start of reset.
     dwc2->gintsts = GINTSTS_USBRST;
+
+    usbd_spin_lock(true);
     handle_bus_reset(rhport);
+    usbd_spin_unlock(true);
   }
 
   if (gintsts & GINTSTS_ENUMDNE) {
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index 3309760ff..49b8c54cb 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -55,8 +55,8 @@ static const dwc2_controller_t _dwc2_controller[] = {
 // On ESP32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] = {
-{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
-{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
+  { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
 };
 #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 98f1a91b5..104f669c9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -195,6 +195,7 @@
 
 // Analog Devices
 #define OPT_MCU_MAX32690         2400  ///< ADI MAX32690
+#define OPT_MCU_MAX32665         2401  ///< ADI MAX32666/5
 #define OPT_MCU_MAX32666         2401  ///< ADI MAX32666/5
 #define OPT_MCU_MAX32650         2402  ///< ADI MAX32650/1/2
 #define OPT_MCU_MAX78002         2403  ///< ADI MAX78002
@@ -267,6 +268,15 @@
   #define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
 #endif
 
+// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is insufficient).
+#ifndef CFG_TUD_CI_HS_VBUS_CHARGE
+  #ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
+  #define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0
+  #endif
+
+  #define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT
+#endif
+
 // Enable DWC2 Slave mode for host
 #ifndef CFG_TUH_DWC2_SLAVE_ENABLE
   #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json
index 8a835e4c0..11b118cea 100644
--- a/test/hil/tinyusb.json
+++ b/test/hil/tinyusb.json
@@ -47,18 +47,6 @@
             }
         },
         {
-            "name": "max32666fthr",
-            "uid": "0C81464124010B20FF0A08CC2C",
-            "tests": {
-                "device": true, "host": false, "dual": false
-            },
-            "flasher": {
-                "name": "openocd_adi",
-                "uid": "E6614C311B597D32",
-                "args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg"
-            }
-        },
-        {
             "name": "metro_m4_express",
             "uid": "9995AD485337433231202020FF100A34",
             "tests": {
@@ -212,6 +200,18 @@
     ],
     "boards-skip": [
         {
+            "name": "max32666fthr",
+            "uid": "0C81464124010B20FF0A08CC2C",
+            "tests": {
+                "device": true, "host": false, "dual": false
+            },
+            "flasher": {
+                "name": "openocd_adi",
+                "uid": "E6614C311B597D32",
+                "args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg"
+            }
+        },
+        {
             "name": "stm32f769disco",
             "uid": "21002F000F51363531383437",
             "build" : {
diff --git a/tools/build.py b/tools/build.py
index d28ddd929..6e73681fe 100755
--- a/tools/build.py
+++ b/tools/build.py
@@ -23,6 +23,7 @@ build_separator = '-' * 95
 build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED]
 
 verbose = False
+parallel_jobs = os.cpu_count()
 
 # -----------------------------
 # Helper
@@ -100,23 +101,27 @@ def cmake_board(board, toolchain, build_flags_on):
             if build_utils.skip_example(example, board):
                 ret[2] += 1
             else:
-                rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" '
+                rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G Ninja '
                                f'-DBOARD={board} {build_flags}')
                 if rcmd.returncode == 0:
                     rcmd = run_cmd(f'cmake --build {build_dir}/{example}')
                 ret[0 if rcmd.returncode == 0 else 1] += 1
     else:
-        rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel '
+        rcmd = run_cmd(f'cmake examples -B {build_dir} -G Ninja -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel '
                        f'-DTOOLCHAIN={toolchain} {build_flags}')
         if rcmd.returncode == 0:
             cmd = f"cmake --build {build_dir}"
-            # circleci docker return $nproc as 36 core, limit parallel according to resource class. Required for IAR, also prevent crashed/killed by docker
+            njobs = parallel_jobs
+
+            # circleci docker return $nproc as 36 core, limit parallel according to resource class.
+            # Required for IAR, also prevent crashed/killed by docker
             if os.getenv('CIRCLECI'):
                 resource_class = { 'small': 1, 'medium': 2, 'medium+': 3, 'large': 4 }
                 for rc in resource_class:
                     if rc in os.getenv('CIRCLE_JOB'):
-                        cmd += f' --parallel {resource_class[rc]}'
+                        njobs = resource_class[rc]
                         break
+            cmd += f' --parallel {njobs}'
             rcmd = run_cmd(cmd)
         ret[0 if rcmd.returncode == 0 else 1] += 1
 
@@ -211,6 +216,7 @@ def build_family(family, toolchain, build_system, build_flags_on, one_per_family
 # -----------------------------
 def main():
     global verbose
+    global parallel_jobs
 
     parser = argparse.ArgumentParser()
     parser.add_argument('families', nargs='*', default=[], help='Families to build')
@@ -219,6 +225,7 @@ def main():
     parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake')
     parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Build flag to pass to build system')
     parser.add_argument('-1', '--one-per-family', action='store_true', default=False, help='Build only one random board inside a family')
+    parser.add_argument('-j', '--jobs', type=int, default=os.cpu_count(), help='Number of jobs to run in parallel')
     parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
     args = parser.parse_args()
 
@@ -229,6 +236,7 @@ def main():
     build_flags_on = args.build_flags_on
     one_per_family = args.one_per_family
     verbose = args.verbose
+    parallel_jobs = args.jobs
 
     if len(families) == 0 and len(boards) == 0:
         print("Please specify families or board to build")
diff --git a/tools/get_deps.py b/tools/get_deps.py
index e67239438..eff221f25 100755
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -25,9 +25,9 @@ deps_optional = {
     'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git',
                          '8e5e89e8e132c0fd90e72d5422e5d3d68232b756',
                          'fc100s'],
-    'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git',
+    'hw/mcu/analog/msdk' : ['https://github.com/analogdevicesinc/msdk.git',
                              'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75',
-                             'max32650 max32666 max32690 max78002'],
+                             'maxim'],
     'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git',
                                          '91060164afe239fcb394122e8bf9eb24d3194eb1',
                                          'brtmm90x'],
@@ -55,8 +55,8 @@ deps_optional = {
     'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
                            'b41cf930e65c734d8ec6de04f1d57d46787c76ae',
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
-    'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
-                            '144f1eb7ea8c06512e12f12b27383601c0272410',
+    'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk',
+                            'a1bdae309a14ec95a4f64a96d3315a4f89c397c6',
                             'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git',
                                          '032a469e79f6a4ba40760d7868e6db26e15002d7',