diff options
| author | Zixun LI <[email protected]> | 2026-03-12 10:55:18 +0100 |
|---|---|---|
| committer | Zixun LI <[email protected]> | 2026-03-12 10:55:18 +0100 |
| commit | e2884a1b88ce89b6e724e3d3b441b8ee1f83c06c (patch) | |
| tree | c322110908d4282ca7e37fe52dc9ce42be15b073 | |
| parent | c06dc871d651ddaf756afdc59ed148c4b1af314d (diff) | |
| parent | ac61a5b176b44db503d8bcc287a622463b65e48e (diff) | |
Merge branch 'master' into ncm_restart
388 files changed, 21174 insertions, 8800 deletions
diff --git a/.circleci/config2.yml b/.circleci/config2.yml index a31b0a818..bb0ac350f 100644 --- a/.circleci/config2.yml +++ b/.circleci/config2.yml @@ -110,7 +110,7 @@ commands: no_output_timeout: 20m command: | if [ << parameters.toolchain >> == esp-idf ]; then - docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.2 python tools/build.py << parameters.build-args >> --target all << parameters.family >> + docker run --rm -v $PWD:/project -w /project espressif/idf:v5.5.3 python tools/build.py << parameters.build-args >> --target all << parameters.family >> else # Toolchain option default is gcc if [ << parameters.toolchain >> == arm-clang ]; then diff --git a/.github/actions/setup_toolchain/espressif/action.yml b/.github/actions/setup_toolchain/espressif/action.yml index e9d645ac8..90ef753c4 100644 --- a/.github/actions/setup_toolchain/espressif/action.yml +++ b/.github/actions/setup_toolchain/espressif/action.yml @@ -7,7 +7,7 @@ inputs: toolchain_version: description: 'Toolchain version' required: false - default: 'v5.3.2' + default: 'v5.5.3' runs: using: "composite" diff --git a/.github/membrowse_pr_message.j2 b/.github/membrowse_pr_message.j2 new file mode 100644 index 000000000..fbba1ee78 --- /dev/null +++ b/.github/membrowse_pr_message.j2 @@ -0,0 +1,38 @@ +{#- Top 10 targets with biggest memory changes + project dashboard link -#} +{% set section_columns = ['.text', '.rodata', '.data', '.bss'] -%} +{#- --- Compute per-target total absolute delta and collect changed targets --- -#} +{% set changed = [] -%} +{% for target in targets -%} +{% if target.has_changes -%} +{% set ns = namespace(total_delta=0, total_current=0) -%} +{% for region in target.regions -%} +{% set ns.total_delta = ns.total_delta + region.delta -%} +{% set ns.total_current = ns.total_current + region.used_size -%} +{% endfor -%} +{% set total_old = ns.total_current - ns.total_delta -%} +{% set pct = (ns.total_delta / total_old * 100) if total_old > 0 else 0 -%} +{% set abs_pct = (ns.total_delta | abs) if total_old == 0 else (pct | abs) -%} +{% set _ = changed.append({'target': target, 'total_current': ns.total_current, 'total_old': total_old, 'total_delta': ns.total_delta, 'pct': pct, 'abs_pct': abs_pct}) -%} +{% endif -%} +{% endfor -%} +{#- --- Sort by absolute percentage change descending and take top 10 --- -#} +{% set sorted_changed = changed | sort(attribute='abs_pct', reverse=true) -%} +{% set top10 = sorted_changed[:10] -%} +{#- --- Render --- -#} +{% if top10 %} +### Top {{ top10 | length }} targets by memory change (%) (out of {{ targets | length }} targets) {% if dashboard_url %} [View Project Dashboard →]({{ dashboard_url }}){% endif %} + +| target | .text | .rodata | .data | .bss | total | % diff | +|--------|-------|---------|-------|------|-------|--------| +{% for info in top10 -%} +{% set target = info.target -%} +{% set section_map = {} -%} +{% for section in target.sections -%} +{% set _ = section_map.update({section.name: section}) -%} +{% endfor -%} +| {% if target.comparison_url %}[{{ target.name }}]({{ target.comparison_url }}){% else %}{{ target.name }}{% endif %} | +{%- for col in section_columns %} {% if col in section_map %}{{ "{:,}".format(section_map[col].old.size) }} → {{ "{:,}".format(section_map[col].size) }} ({{ section_map[col].delta_str }}){% else %}—{% endif %} |{% endfor %} {{ "{:,}".format(info.total_old) }} → {{ "{:,}".format(info.total_current) }} ({% if info.total_delta >= 0 %}+{{ "{:,}".format(info.total_delta) }}{% else %}{{ "{:,}".format(info.total_delta) }}{% endif %}) | {% if info.total_old > 0 %}{% if info.pct >= 0 %}+{% endif %}{{ "%.1f" | format(info.pct) }}%{% else %}N/A{% endif %} | +{% endfor %} +{% else %} +No memory changes detected across {{ targets | length }} target{{ 's' if targets | length != 1 else '' }}.{% if dashboard_url %} [View Project Dashboard →]({{ dashboard_url }}){% endif %} +{% endif -%} diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9d8b90f5a..e0ce08141 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -182,6 +182,7 @@ jobs: name: metrics-comment path: | metrics_compare.md + metrics.json pr_number.txt - name: Post Code Metrics as PR Comment @@ -291,7 +292,14 @@ jobs: - name: Test on actual hardware run: | - python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS + python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS || \ + (if [ -f "${{ env.HIL_JSON }}.skip" ]; then + SKIP_BOARDS=$(cat "${{ env.HIL_JSON }}.skip") + echo "Re-running with SKIP_BOARDS=$SKIP_BOARDS" + python3 test/hil/hil_test.py ${{ env.HIL_JSON }} $SKIP_BOARDS + else + exit 1 + fi) # --------------------------------------- # Hardware in the loop (HIL) diff --git a/.github/workflows/claude-code-review.yml b/.github/workflows/claude-code-review.yml new file mode 100644 index 000000000..5d7efc115 --- /dev/null +++ b/.github/workflows/claude-code-review.yml @@ -0,0 +1,32 @@ +name: Claude Code Review + +on: + pull_request_target: + types: [opened, synchronize, ready_for_review, reopened] + +jobs: + claude-review: + if: false + runs-on: ubuntu-latest + permissions: + contents: read + pull-requests: write + issues: read + id-token: write + + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + fetch-depth: 1 + + - name: Run Claude Code Review + id: claude-review + uses: anthropics/claude-code-action@v1 + with: + claude_code_oauth_token: ${{ secrets.CLAUDE_CODE_OAUTH_TOKEN }} + plugin_marketplaces: 'https://github.com/anthropics/claude-code.git' + plugins: 'code-review@claude-code-plugins' + prompt: '/code-review:code-review ${{ github.repository }}/pull/${{ github.event.pull_request.number }}' + # See https://github.com/anthropics/claude-code-action/blob/main/docs/usage.md + # or https://code.claude.com/docs/en/cli-reference for available options diff --git a/.github/workflows/claude.yml b/.github/workflows/claude.yml new file mode 100644 index 000000000..9471a0591 --- /dev/null +++ b/.github/workflows/claude.yml @@ -0,0 +1,49 @@ +name: Claude Code + +on: + issue_comment: + types: [created] + pull_request_review_comment: + types: [created] + issues: + types: [opened, assigned] + pull_request_review: + types: [submitted] + +jobs: + claude: + if: | + (github.event_name == 'issue_comment' && contains(github.event.comment.body, '@claude')) || + (github.event_name == 'pull_request_review_comment' && contains(github.event.comment.body, '@claude')) || + (github.event_name == 'pull_request_review' && contains(github.event.review.body, '@claude')) || + (github.event_name == 'issues' && (contains(github.event.issue.body, '@claude') || contains(github.event.issue.title, '@claude'))) + runs-on: ubuntu-latest + permissions: + contents: read + pull-requests: read + issues: read + id-token: write + actions: read # Required for Claude to read CI results on PRs + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + fetch-depth: 1 + + - name: Run Claude Code + id: claude + uses: anthropics/claude-code-action@v1 + with: + claude_code_oauth_token: ${{ secrets.CLAUDE_CODE_OAUTH_TOKEN }} + + # This is an optional setting that allows Claude to read CI results on PRs + additional_permissions: | + actions: read + + # Optional: Give a custom prompt to Claude. If this is not specified, Claude will perform the instructions specified in the comment that tagged it. + # prompt: 'Update the pull request description to include a summary of changes.' + + # Optional: Add claude_args to customize behavior and configuration + # See https://github.com/anthropics/claude-code-action/blob/main/docs/usage.md + # or https://code.claude.com/docs/en/cli-reference for available options + # claude_args: '--allowed-tools Bash(gh pr:*)' diff --git a/.github/workflows/membrowse-comment.yml b/.github/workflows/membrowse-comment.yml index a99c9db51..952d8ba37 100644 --- a/.github/workflows/membrowse-comment.yml +++ b/.github/workflows/membrowse-comment.yml @@ -9,30 +9,25 @@ on: jobs: post-comment: runs-on: ubuntu-latest + # Run the comment job even if some of the builds fail if: > github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion != 'cancelled' permissions: + contents: read actions: read pull-requests: write steps: - name: Checkout repository uses: actions/checkout@v6 - - name: Download Artifacts - id: download - uses: actions/download-artifact@v5 - with: - run-id: ${{ github.event.workflow_run.id }} - github-token: ${{ secrets.GITHUB_TOKEN }} - name: membrowse-comment - path: reports - continue-on-error: true - - name: Post Membrowse PR comment - if: steps.download.outcome == 'success' + if: ${{ env.MEMBROWSE_API_KEY != '' }} uses: membrowse/membrowse-action/comment-action@v1 with: - json_files: 'reports/*.json' + api_key: ${{ secrets.MEMBROWSE_API_KEY }} + commit: ${{ github.event.workflow_run.head_sha }} + comment_template: .github/membrowse_pr_message.j2 env: + MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 822a70236..6f87e2a29 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -96,6 +96,7 @@ <configuration PROFILE_NAME="itsybitsy_m4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=itsybitsy_m4" /> <configuration PROFILE_NAME="same54_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same54_xplained -DLOG=1 -DLOGGER=RTT" /> <configuration PROFILE_NAME="samg55_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=samg55_xplained" /> + <configuration PROFILE_NAME="same70_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same70_xplained -DLOG=1" /> <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" /> <configuration PROFILE_NAME="nrf52840dk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nrf52840dk -DLOG=1 -DLOGGER=RTT -DTRACE_ETM=1" /> <configuration PROFILE_NAME="nrf52840dk-zephyr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=nrf52840dk -DLOG=1 -DTRACE_ETM=1 -DRTOS=zephyr" BUILD_OPTIONS="-v" /> @@ -21,6 +21,8 @@ information that does not match the info here. - For specific board families: `python3 tools/get_deps.py FAMILY_NAME` (e.g., rp2040, stm32f4), or `python3 tools/get_deps.py -b BOARD_NAME` - Dependencies are cached in `lib/` and `hw/mcu/` directories +- For **Espressif** boards, initialize the ESP-IDF environment before any build/flash/monitor command: + `. $HOME/code/esp-idf/export.sh` ## Build Examples @@ -59,6 +61,19 @@ make BOARD=raspberry_pi_pico all -- takes 2-3 seconds. NEVER CANCEL. Set timeout to 5+ minutes. +**Option 4: Espressif Example with ESP-IDF** + +Only ESP-IDF-enabled examples are supported for Espressif boards. Use FreeRTOS examples such as `examples/device/cdc_msc_freertos` +that contain `idf_component_register()` support. + +```bash +. $HOME/code/esp-idf/export.sh +cd examples/device/cdc_msc_freertos +idf.py -DBOARD=espressif_s3_devkitc build +``` + +Use `-DBOARD=...` with any supported board under `hw/bsp/espressif/boards/`. NEVER CANCEL. Set timeout to 10+ minutes. + ## Build Options @@ -90,14 +105,74 @@ make BOARD=raspberry_pi_pico all - CMake: `ninja cdc_msc-uf2` - Make: `make BOARD=raspberry_pi_pico all uf2` - **List all targets** (CMake/Ninja): `ninja -t targets` +- **Espressif flash**: + - Run `. $HOME/code/esp-idf/export.sh` + - `cd examples/device/cdc_msc_freertos` + - `idf.py -DBOARD=espressif_s3_devkitc flash` +- **Espressif serial monitor / chip log output**: + - Run `. $HOME/code/esp-idf/export.sh` + - `cd examples/device/cdc_msc_freertos` + - `idf.py -DBOARD=espressif_s3_devkitc monitor` + +## GDB Debugging + +Look up the board's `JLINK_DEVICE` and `OPENOCD_OPTION` from `hw/bsp/*/boards/*/board.cmake` (or `board.mk`). -## J-Link GDB Server + RTT Logging +### JLinkGDBServer + +**Terminal 1 – start the GDB server:** +```bash +JLinkGDBServer -device stm32h743xi -if SWD -speed 4000 \ + -port 2331 -swoport 2332 -telnetport 2333 -nogui +``` + +**Terminal 2 – connect GDB:** +```bash +arm-none-eabi-gdb /tmp/build/firmware.elf +(gdb) target remote :2331 +(gdb) monitor reset halt +(gdb) load +(gdb) continue +``` + +To break on entry instead of running immediately: +```bash +(gdb) monitor reset halt +(gdb) load +(gdb) break main +(gdb) continue +``` + +### OpenOCD + +**Terminal 1 – start the GDB server:** +```bash +openocd -f interface/stlink.cfg -f target/stm32h7x.cfg +# or with J-Link probe: +openocd -f interface/jlink.cfg -f target/stm32h7x.cfg +``` + +For boards that define `OPENOCD_OPTION` in `board.cmake`, use those options directly: +```bash +openocd $(cat hw/bsp/FAMILY/boards/BOARD/board.cmake | grep OPENOCD_OPTION | ...) +``` + +**Terminal 2 – connect GDB (OpenOCD default port is 3333):** +```bash +arm-none-eabi-gdb /tmp/build/firmware.elf +(gdb) target remote :3333 +(gdb) monitor reset halt +(gdb) load +(gdb) continue +``` + +### RTT Logging with JLinkGDBServer - Build with RTT logging enabled (example): `cd examples/device/cdc_msc && make BOARD=stm32h743eval LOG=2 LOGGER=rtt all` - Flash with J-Link: `cd examples/device/cdc_msc && make BOARD=stm32h743eval LOG=2 LOGGER=rtt flash-jlink` -- Launch GDB server (keep this running in terminal 1): +- Launch GDB server with RTT port (keep this running in terminal 1): `JLinkGDBServer -device stm32h743xi -if SWD -speed 4000 -port 2331 -swoport 2332 -telnetport 2333 -RTTTelnetPort 19021 -nogui` - Read RTT output (terminal 2): `JLinkRTTClient` @@ -105,7 +180,6 @@ make BOARD=raspberry_pi_pico all `JLinkRTTClient | tee rtt.log` - For non-interactive capture: `timeout 20s JLinkRTTClient > rtt.log` -- Use the board-specific `JLINK_DEVICE` from `hw/bsp/*/boards/*/board.mk` if you are not using `stm32h743eval`. ## Unit Testing @@ -258,6 +332,9 @@ take 2-5 minutes. NEVER CANCEL. Set timeout to 20+ minutes. - `examples/device/cdc_msc/`: Most commonly used example for testing - `test/unit-test/project.yml`: Ceedling test configuration +#### MCU Reference Manuals and Datasheets +- Look in `$HOME/Documents/Calibre Library` for all MCU reference manuals, datasheets and board schematics. + #### Debugging Build Issues - **Missing compiler**: Install `gcc-arm-none-eabi` package - **Missing dependencies**: Run `python3 tools/get_deps.py FAMILY` diff --git a/CLAUDE.md b/CLAUDE.md new file mode 120000 index 000000000..47dc3e3d8 --- /dev/null +++ b/CLAUDE.md @@ -0,0 +1 @@ +AGENTS.md
\ No newline at end of file diff --git a/README.rst b/README.rst index a3863c375..ba42a7afe 100644 --- a/README.rst +++ b/README.rst @@ -87,6 +87,7 @@ Supports multiple device configurations by dynamically changing USB descriptors, - Communication Device Class (CDC) - Device Firmware Update (DFU): DFU mode (WIP) and Runtime - Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ... +- Printer class - Mass Storage Class (MSC): with multiple LUNs - Musical Instrument Digital Interface (MIDI) - Media Transfer Protocol (MTP/PTP) @@ -205,7 +206,9 @@ Supported CPUs | | +-------------------+--------+------+-----------+------------------------+--------------------+ | | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | | | | +-------------------+--------+------+-----------+------------------------+--------------------+ -| | | 54, 55 | ✔ | | ✔ | lpc_ip3511 | | +| | | 54 | ⚠| ⚠| ✔ | lpc_ip3511, lpc_ip3516 | NRND, read errata | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | 55 | ✔ | ✔ | ✔ | lpc_ip3511, lpc_ip3516 | | | +---------+-------------------+--------+------+-----------+------------------------+--------------------+ | | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs, ehci | | | | +-------------------+--------+------+-----------+------------------------+--------------------+ diff --git a/docs/faq.rst b/docs/faq.rst index a5fe09495..97e8e72ff 100644 --- a/docs/faq.rst +++ b/docs/faq.rst @@ -15,7 +15,7 @@ Yes, TinyUSB is released under the MIT license, allowing commercial use with min **Q: Does TinyUSB require an RTOS?** -No, TinyUSB works in bare metal environments. It also supports FreeRTOS, RT-Thread, and Mynewt. +No, TinyUSB works in bare metal environments. It also supports FreeRTOS, RT-Thread, ThreadX, and Mynewt. **Q: How much memory does TinyUSB use?** diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index 660df67cb..7173f455e 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -30,6 +30,7 @@ set(EXAMPLE_LIST msc_dual_lun mtp net_lwip_webserver + printer_to_cdc uac2_headset uac2_speaker_fb usbtmc diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 5767c7453..c9c6dd46c 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -155,7 +155,7 @@ void tud_resume_cb(void) { // In a real application, this would be replaced with actual I2S receive callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) { return; // not enough time } @@ -408,7 +408,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/audio_4_channel_mic_freertos/skip.txt b/examples/device/audio_4_channel_mic_freertos/skip.txt index 4c2780096..db01347ed 100644 --- a/examples/device/audio_4_channel_mic_freertos/skip.txt +++ b/examples/device/audio_4_channel_mic_freertos/skip.txt @@ -9,7 +9,6 @@ mcu:MKL25ZXX mcu:MSP430x5xx mcu:RP2040 mcu:SAMD11 -mcu:SAMX7X mcu:VALENTYUSB_EPTRI mcu:RAXXX mcu:STM32L0 diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index 2441eefbc..876a41d06 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -138,7 +138,7 @@ void tud_resume_cb(void) { // In a real application, this would be replaced with actual I2S receive callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) { return; // not enough time } @@ -402,7 +402,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/audio_test_freertos/skip.txt b/examples/device/audio_test_freertos/skip.txt index 2da7808e7..7463aa86a 100644 --- a/examples/device/audio_test_freertos/skip.txt +++ b/examples/device/audio_test_freertos/skip.txt @@ -9,7 +9,6 @@ mcu:MKL25ZXX mcu:MSP430x5xx mcu:RP2040 mcu:SAMD11 -mcu:SAMX7X mcu:VALENTYUSB_EPTRI mcu:RAXXX family:broadcom_32bit diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index baeec870f..952176997 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -146,7 +146,7 @@ void tud_resume_cb(void) { // In a real application, this would be replaced with actual I2S receive callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) { return; // not enough time } @@ -614,7 +614,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index ee0829e5b..71e7e1da7 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -39,11 +39,35 @@ enum { #define HELLO_STR "Hello from TinyUSB\r\n" -int main(void) { - board_init(); - board_led_write(true); +// board test example does not use both device and host stack +#if CFG_TUSB_OS != OPT_OS_NONE +uint32_t tusb_time_millis_api(void) { + return osal_time_millis(); +} + +void tusb_time_delay_ms_api(uint32_t ms) { + osal_task_delay(ms); +} +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +// Task parameter type: ULONG for ThreadX, void* for FreeRTOS and noos +#if CFG_TUSB_OS == OPT_OS_THREADX + #define RTOS_PARAM ULONG +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + #define RTOS_PARAM void* + static void freertos_init(void); +#else + #define RTOS_PARAM void* +#endif +static void board_test_loop(RTOS_PARAM param) { + (void) param; uint32_t start_ms = 0; + (void) start_ms; bool led_state = false; while (1) { @@ -58,26 +82,94 @@ int main(void) { } // Blink and print every interval ms - if (!(board_millis() - start_ms < interval_ms)) { - start_ms = board_millis(); - - if (ch < 0) { - // skip if echoing - printf(HELLO_STR); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + vTaskDelay(interval_ms / portTICK_PERIOD_MS); + #elif CFG_TUSB_OS == OPT_OS_THREADX + tx_thread_sleep(_osal_ms2tick(interval_ms)); + #else + if (tusb_time_millis_api() - start_ms < interval_ms) { + continue; // not enough time + } + #endif + start_ms = tusb_time_millis_api(); - #ifndef LOGGER_UART - board_uart_write(HELLO_STR, sizeof(HELLO_STR)-1); - #endif - } + if (ch < 0) { + // skip if echoing + printf(HELLO_STR); - board_led_write(led_state); - led_state = !led_state; // toggle + #ifndef LOGGER_UART + board_uart_write(HELLO_STR, sizeof(HELLO_STR)-1); + #endif } + + board_led_write(led_state); + led_state = !led_state; // toggle } } +int main(void) { + board_init(); + board_led_write(true); + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + freertos_init(); +#elif CFG_TUSB_OS == OPT_OS_THREADX + tx_kernel_enter(); +#else + board_test_loop(NULL); +#endif + + return 0; +} + #ifdef ESP_PLATFORM void app_main(void) { main(); } #endif + +//--------------------------------------------------------------------+ +// FreeRTOS +//--------------------------------------------------------------------+ +#if CFG_TUSB_OS == OPT_OS_FREERTOS + +#ifdef ESP_PLATFORM +#define MAIN_STACK_SIZE 4096 +#else +#define MAIN_STACK_SIZE 512 +#endif + +#if configSUPPORT_STATIC_ALLOCATION +static StackType_t _main_stack[MAIN_STACK_SIZE]; +static StaticTask_t _main_taskdef; +#endif + +static void freertos_init(void) { + #if configSUPPORT_STATIC_ALLOCATION + xTaskCreateStatic(board_test_loop, "main", MAIN_STACK_SIZE, NULL, 1, _main_stack, &_main_taskdef); + #else + xTaskCreate(board_test_loop, "main", MAIN_STACK_SIZE, NULL, 1, NULL); + #endif + + #ifndef ESP_PLATFORM + vTaskStartScheduler(); + #endif +} + +//--------------------------------------------------------------------+ +// ThreadX +//--------------------------------------------------------------------+ +#elif CFG_TUSB_OS == OPT_OS_THREADX + +#define MAIN_TASK_STACK_SIZE 1024 +static TX_THREAD _main_thread; +static ULONG _main_thread_stack[MAIN_TASK_STACK_SIZE / sizeof(ULONG)]; + +void tx_application_define(void *first_unused_memory) { + (void) first_unused_memory; + static CHAR main_thread_name[] = "main"; + tx_thread_create(&_main_thread, main_thread_name, board_test_loop, 0, + _main_thread_stack, MAIN_TASK_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} +#endif diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index 5ccb06a8a..6f918218d 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -157,7 +157,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h index 710c01ee2..633a3faea 100644 --- a/examples/device/cdc_dual_ports/src/tusb_config.h +++ b/examples/device/cdc_dual_ports/src/tusb_config.h @@ -103,10 +103,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -// Leave it as default size (512 for HS, 64 for FS) unless your host application -// is able to send ZLP (Zero Length Packet) to terminate transfer ! -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #ifdef __cplusplus } diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index 06a4f732f..b00a0e3a9 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -160,7 +160,7 @@ void led_blinking_task(void) { if (blink_enable) { // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index e091c2985..017acd039 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -238,7 +238,7 @@ int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, u (void) buffer; (void) bufsize; - // currently no other commands is supported + // currently no other commands are supported // Set Sense = Invalid Command Operation (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h index 3f2f05f20..f0709d8fb 100644 --- a/examples/device/cdc_msc/src/tusb_config.h +++ b/examples/device/cdc_msc/src/tusb_config.h @@ -103,10 +103,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -// Leave it as default size (512 for HS, 64 for FS) unless your host application -// is able to send ZLP (Zero Length Packet) to terminate transfer ! -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt index d90741df7..d3a096eb0 100644 --- a/examples/device/cdc_msc_freertos/skip.txt +++ b/examples/device/cdc_msc_freertos/skip.txt @@ -9,7 +9,6 @@ mcu:MKL25ZXX mcu:MSP430x5xx mcu:RP2040 mcu:SAMD11 -mcu:SAMX7X mcu:VALENTYUSB_EPTRI mcu:RAXXX mcu:STM32L0 diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index 29ff86281..ff918205e 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -324,20 +324,17 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE // - READ10 and WRITE10 has their own callbacks int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) { - // read10 & write10 has their own callback and MUST not be handled here + (void) lun; + (void) scsi_cmd; (void) buffer; (void) bufsize; - switch (scsi_cmd[0]) { - default: - // Set Sense = Invalid Command Operation - tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + // currently no other commands are supported - // negative means error -> tinyusb could stall and/or response with failed status - return -1; - } + // Set Sense = Invalid Command Operation + (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); - return -1; + return -1; // stall/failed command request; } #endif diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index 8277b1604..a78f2ea05 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -110,10 +110,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -// Leave it as default size (512 for HS, 64 for FS) unless your host application -// is able to send ZLP (Zero Length Packet) to terminate transfer ! -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c index 22c462be7..cb7b3a142 100644 --- a/examples/device/cdc_uac2/src/main.c +++ b/examples/device/cdc_uac2/src/main.c @@ -65,8 +65,6 @@ int main(void) // printf("Hello, world!\r\n"); #endif } - - return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/cdc_uac2/src/tusb_config.h b/examples/device/cdc_uac2/src/tusb_config.h index 5eb2e8f74..358ff6747 100644 --- a/examples/device/cdc_uac2/src/tusb_config.h +++ b/examples/device/cdc_uac2/src/tusb_config.h @@ -159,10 +159,10 @@ extern "C" { #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -// Leave it as default size (512 for HS, 64 for FS) unless your host application -// is able to send ZLP (Zero Length Packet) to terminate transfer ! -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #ifdef __cplusplus } diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c index 73a262d0c..7760c402b 100644 --- a/examples/device/cdc_uac2/src/uac2_app.c +++ b/examples/device/cdc_uac2/src/uac2_app.c @@ -66,7 +66,7 @@ uint8_t current_resolution; // In a real application, this would be replaced with actual I2S send/receive callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) { return; // not enough time } @@ -303,7 +303,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; } start_ms += blink_interval_ms; diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 77632bf1a..fb3c22630 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -199,7 +199,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 5de651bcd..6f412e8de 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -132,7 +132,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index dac74bb7a..8ebb42f9a 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -170,7 +170,7 @@ void midi_task(void) { while( tud_midi_available() ) tud_midi_packet_read(packet); // send note every 1000 ms - if (board_millis() - start_ms < 286) { + if (tusb_time_millis_api() - start_ms < 286) { return; // not enough time } start_ms += 286; @@ -209,7 +209,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return;// not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index e95b2e197..b545e4652 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -215,20 +215,17 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE // - READ10 and WRITE10 has their own callbacks int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) { - // read10 & write10 has their own callback and MUST not be handled here + (void) lun; + (void) scsi_cmd; (void) buffer; (void) bufsize; - switch (scsi_cmd[0]) { - default: - // Set Sense = Invalid Command Operation - tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + // currently no other commands are supported - // negative means error -> tinyusb could stall and/or response with failed status - return -1; - } + // Set Sense = Invalid Command Operation + (void) tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); - return -1; + return -1; // stall/failed command request; } #endif diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index 44a91db67..7f2153ae9 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -67,8 +67,6 @@ int main(void) { hid_task(); } - - return 0; } //--------------------------------------------------------------------+ @@ -109,7 +107,7 @@ void hid_task(void) { const uint32_t interval_ms = 10; static uint32_t start_ms = 0; - if (board_millis() - start_ms < interval_ms) { + if (tusb_time_millis_api() - start_ms < interval_ms) { return; // not enough time } start_ms += interval_ms; @@ -238,7 +236,7 @@ void led_blinking_task(void) { } // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 9693d564d..7c9d5af8d 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -209,7 +209,7 @@ void hid_task(void) { const uint32_t interval_ms = 10; static uint32_t start_ms = 0; - if (board_millis() - start_ms < interval_ms) { + if (tusb_time_millis_api() - start_ms < interval_ms) { return; // not enough time } start_ms += interval_ms; @@ -298,7 +298,7 @@ void led_blinking_task(void) { } // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt index 01990a5b4..06920db67 100644 --- a/examples/device/hid_composite_freertos/skip.txt +++ b/examples/device/hid_composite_freertos/skip.txt @@ -9,7 +9,6 @@ mcu:MKL25ZXX mcu:MSP430x5xx mcu:RP2040 mcu:SAMD11 -mcu:SAMX7X mcu:VALENTYUSB_EPTRI mcu:RAXXX family:broadcom_32bit diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 9837a47d9..2a6b91a8a 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -168,7 +168,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index 0bccd13c1..c71a9cbad 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -120,7 +120,7 @@ void hid_task(void) const uint32_t interval_ms = 10; static uint32_t start_ms = 0; - if ( board_millis() - start_ms < interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time start_ms += interval_ms; uint32_t const btn = board_button_read(); @@ -205,7 +205,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index fd58e3021..1154c1d60 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -134,7 +134,7 @@ void midi_task(void) } // send note periodically - if (board_millis() - start_ms < 286) { + if (tusb_time_millis_api() - start_ms < 286) { return; // not enough time } start_ms += 286; @@ -174,7 +174,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/midi_test_freertos/skip.txt b/examples/device/midi_test_freertos/skip.txt index 01990a5b4..06920db67 100644 --- a/examples/device/midi_test_freertos/skip.txt +++ b/examples/device/midi_test_freertos/skip.txt @@ -9,7 +9,6 @@ mcu:MKL25ZXX mcu:MSP430x5xx mcu:RP2040 mcu:SAMD11 -mcu:SAMX7X mcu:VALENTYUSB_EPTRI mcu:RAXXX family:broadcom_32bit diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index 62b1c872a..a4ade6f9b 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -31,7 +31,7 @@ #include "tusb.h" //--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF PROTYPES +// MACRO CONSTANT TYPEDEF PROTOTYPES //--------------------------------------------------------------------+ /* Blink pattern @@ -41,71 +41,177 @@ */ enum { BLINK_NOT_MOUNTED = 250, - BLINK_MOUNTED = 1000, - BLINK_SUSPENDED = 2500, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, }; static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; -void led_blinking_task(void); +// Task parameter type: ULONG for ThreadX, void* for FreeRTOS and noos +#if CFG_TUSB_OS == OPT_OS_THREADX + #define RTOS_PARAM ULONG +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + #define RTOS_PARAM void* + static void freertos_init(void); +#else + #define RTOS_PARAM void* +#endif -/*------------- MAIN -------------*/ -int main(void) { - board_init(); +void led_blinking_task(RTOS_PARAM param); - // init device stack on configured roothub port +//--------------------------------------------------------------------+ +// USB Device Task +//--------------------------------------------------------------------+ +static void usb_device_init(void) { tusb_rhport_init_t dev_init = { - .role = TUSB_ROLE_DEVICE, + .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUD_RHPORT, &dev_init); - board_init_after_tusb(); +} + +#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO +static void usb_device_task(RTOS_PARAM param) { + (void) param; + usb_device_init(); while (1) { - tud_task(); // tinyusb device task - led_blinking_task(); + tud_task(); } } +#endif //--------------------------------------------------------------------+ -// Device callbacks +// Main //--------------------------------------------------------------------+ +int main(void) { + board_init(); -// Invoked when device is mounted +#if CFG_TUSB_OS == OPT_OS_FREERTOS + freertos_init(); + +#elif CFG_TUSB_OS == OPT_OS_THREADX + tx_kernel_enter(); + +#else + // noos + pico-sdk: init USB then run polling loop + usb_device_init(); + + while (1) { + tud_task(); + led_blinking_task(NULL); + } +#endif +} + +#ifdef ESP_PLATFORM +void app_main(void) { + main(); +} +#endif + +//--------------------------------------------------------------------+ +// Device callbacks +//--------------------------------------------------------------------+ void tud_mount_cb(void) { blink_interval_ms = BLINK_MOUNTED; } -// Invoked when device is unmounted void tud_umount_cb(void) { blink_interval_ms = BLINK_NOT_MOUNTED; } -// Invoked when usb bus is suspended -// remote_wakeup_en : if host allow us to perform remote wakeup -// Within 7ms, device must draw an average of current less than 2.5 mA from bus void tud_suspend_cb(bool remote_wakeup_en) { (void) remote_wakeup_en; blink_interval_ms = BLINK_SUSPENDED; } -// Invoked when usb bus is resumed void tud_resume_cb(void) { blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; } //--------------------------------------------------------------------+ -// BLINKING TASK +// Blinking Task //--------------------------------------------------------------------+ -void led_blinking_task(void) { +void led_blinking_task(RTOS_PARAM param) { + (void) param; static uint32_t start_ms = 0; static bool led_state = false; - // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time - start_ms += blink_interval_ms; + while (1) { +#if CFG_TUSB_OS == OPT_OS_FREERTOS + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); +#elif CFG_TUSB_OS == OPT_OS_THREADX + tx_thread_sleep(_osal_ms2tick(blink_interval_ms)); +#else + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { + return; // not enough time + } +#endif + + start_ms += blink_interval_ms; + board_led_write(led_state); + led_state = 1 - led_state; // toggle + } +} + +//--------------------------------------------------------------------+ +// FreeRTOS +//--------------------------------------------------------------------+ +#if CFG_TUSB_OS == OPT_OS_FREERTOS + +#ifdef ESP_PLATFORM +#define USBD_STACK_SIZE 4096 +#else +#define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2 * (CFG_TUSB_DEBUG ? 2 : 1)) +#endif +#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE - board_led_write(led_state); - led_state = 1 - led_state; // toggle +#if configSUPPORT_STATIC_ALLOCATION +static StackType_t _usb_device_stack[USBD_STACK_SIZE]; +static StaticTask_t _usb_device_taskdef; +static StackType_t _blinky_stack[BLINKY_STACK_SIZE]; +static StaticTask_t _blinky_taskdef; +#endif + + +static void freertos_init(void) { + #if configSUPPORT_STATIC_ALLOCATION + xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, _usb_device_stack, &_usb_device_taskdef); + xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, _blinky_stack, &_blinky_taskdef); + #else + xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); + xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); + #endif + #ifndef ESP_PLATFORM + vTaskStartScheduler(); + #endif +} + +//--------------------------------------------------------------------+ +// ThreadX +//--------------------------------------------------------------------+ +#elif CFG_TUSB_OS == OPT_OS_THREADX + +#define USBD_STACK_SIZE 4096 +#define BLINKY_STACK_SIZE 512 + +static TX_THREAD _usb_device_thread; +static ULONG _usb_device_stack[USBD_STACK_SIZE / sizeof(ULONG)]; +static TX_THREAD _blinky_thread; +static ULONG _blinky_stack[BLINKY_STACK_SIZE / sizeof(ULONG)]; + +void tx_application_define(void *first_unused_memory) { + (void) first_unused_memory; + static CHAR usbd_name[] = "usbd"; + static CHAR blinky_name[] = "blinky"; + tx_thread_create(&_usb_device_thread, usbd_name, usb_device_task, 0, + _usb_device_stack, USBD_STACK_SIZE, + 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); + tx_thread_create(&_blinky_thread, blinky_name, led_blinking_task, 0, + _blinky_stack, BLINKY_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } + +#endif diff --git a/examples/device/mtp/src/main.c b/examples/device/mtp/src/main.c index 57d1535b2..6ffa435d1 100644 --- a/examples/device/mtp/src/main.c +++ b/examples/device/mtp/src/main.c @@ -102,7 +102,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time + if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 3fb852cb3..ae8189624 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -304,8 +304,6 @@ int main(void) { handle_link_state_switch(); led_blinking_task(); } - - return 0; } // Invoked when device is mounted @@ -342,5 +340,5 @@ void sys_arch_unprotect(sys_prot_t pval) { /* lwip needs a millisecond time source, and the TinyUSB board support code has one available */ uint32_t sys_now(void) { - return board_millis(); + return tusb_time_millis_api(); } diff --git a/examples/device/printer_to_cdc/CMakeLists.txt b/examples/device/printer_to_cdc/CMakeLists.txt new file mode 100644 index 000000000..3c8ab3653 --- /dev/null +++ b/examples/device/printer_to_cdc/CMakeLists.txt @@ -0,0 +1,29 @@ +cmake_minimum_required(VERSION 3.20) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +project(printer_to_cdc C CXX ASM) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}) +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + +add_executable(${PROJECT_NAME}) + +# Example source +target_sources(${PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) + +# Example include +target_include_directories(${PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT_NAME} noos) diff --git a/examples/device/printer_to_cdc/Makefile b/examples/device/printer_to_cdc/Makefile new file mode 100644 index 000000000..1a4b428dc --- /dev/null +++ b/examples/device/printer_to_cdc/Makefile @@ -0,0 +1,11 @@ +include ../../../hw/bsp/family_support.mk + +INC += \ + src \ + + +# Example source +EXAMPLE_SOURCE += $(wildcard src/*.c) +SRC_C += $(addprefix $(EXAMPLE_PATH)/, $(EXAMPLE_SOURCE)) + +include ../../../hw/bsp/family_rules.mk diff --git a/examples/device/printer_to_cdc/README.md b/examples/device/printer_to_cdc/README.md new file mode 100644 index 000000000..ecb9a678f --- /dev/null +++ b/examples/device/printer_to_cdc/README.md @@ -0,0 +1,80 @@ +#### Printer to CDC + +This example demonstrates a USB composite device with a Printer class interface and a CDC serial interface. Data flows bidirectionally between the two: + +- Data sent to the Printer (from host) is forwarded to the CDC serial port +- Data sent to the CDC serial port (from host) is forwarded to the Printer IN endpoint + +This is useful for debugging printer class communication or as a reference for implementing printer class devices. + +#### USB Interfaces + +| Interface | Class | Description | +|-----------|-------|-------------| +| 0 | CDC ACM | Virtual serial port | +| 2 | Printer | USB Printer (bidirectional, protocol 2) | + +#### How to Test + +The device exposes two endpoints on the host: +- `/dev/ttyACM0` (CDC serial port) +- `/dev/usb/lp0` (USB printer) + +Note: the actual device numbers may vary depending on your system. + +**Prerequisites (Linux):** + +```bash +# Load the USB printer kernel module if not already loaded +sudo modprobe usblp + +# Check devices exist +ls /dev/ttyACM* /dev/usb/lp* +``` + +**Test Printer to CDC (host writes to printer, reads from CDC):** + +```bash +# Terminal 1: read from CDC +cat /dev/ttyACM0 + +# Terminal 2: write to printer +echo "hello from printer" > /dev/usb/lp0 +# "hello from printer" appears in Terminal 1 +``` + +**Test CDC to Printer (host writes to CDC, reads from printer):** + +```bash +# Terminal 1: read from printer IN endpoint +cat /dev/usb/lp0 + +# Terminal 2: write to CDC +echo "hello from cdc" > /dev/ttyACM0 +# "hello from cdc" appears in Terminal 1 +``` + +**Interactive bidirectional test:** + +```bash +# Terminal 1: open CDC serial port +minicom -D /dev/ttyACM0 + +# Terminal 2: send to printer +echo "tinyusb print example" > /dev/usb/lp0 +# Text appears in minicom. Type in minicom to send data back through printer TX. +``` + +#### IEEE 1284 Device ID + +The device responds to GET_DEVICE_ID requests with: + +``` +MFG:TinyUSB;MDL:Printer to CDC;CMD:PS;CLS:PRINTER; +``` + +Verify with: + +```bash +cat /sys/class/usbmisc/lp0/device/ieee1284_id +``` diff --git a/examples/device/printer_to_cdc/src/main.c b/examples/device/printer_to_cdc/src/main.c new file mode 100644 index 000000000..ffaf709b4 --- /dev/null +++ b/examples/device/printer_to_cdc/src/main.c @@ -0,0 +1,117 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +/* This example demonstrates a USB Printer + CDC composite device. + * Data received on the Printer interface is forwarded to the CDC serial port, + * and data received on the CDC serial port is forwarded back to the Printer interface. + * + * To test: + * 1. Flash the device + * 2. Open a serial terminal on the CDC port (e.g. /dev/ttyACM0) + * 3. Send data to the printer: echo "hello" > /dev/usb/lp0 + * 4. The data appears on the CDC serial terminal + * 5. Type in the serial terminal to send data back through the printer TX + */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> + +#include "bsp/board_api.h" +#include "tusb.h" + +#include "usb_descriptors.h" + +// -------------------------------------------------------------------+ +// Tasks +// -------------------------------------------------------------------+ + +// Forward data from Printer RX to CDC TX +static void printer_to_cdc_task(void) { + uint32_t avail = tud_printer_read_available(); + if (avail == 0 || !tud_cdc_write_available()) { + return; + } + + uint8_t buf[64]; + uint32_t count = tud_printer_read(buf, TU_MIN(sizeof(buf), tud_cdc_write_available())); + if (count > 0) { + tud_cdc_write(buf, count); + tud_cdc_write_flush(); + } +} + +// Forward data from CDC RX to Printer TX +static void cdc_to_printer_task(void) { + uint32_t avail = tud_printer_write_available(); + if (tud_cdc_available() == 0 || avail == 0) { + return; + } + + uint8_t buf[64]; + uint32_t count = tud_cdc_read(buf, TU_MIN(sizeof(buf), avail)); + if (count > 0) { + tud_printer_write(buf, count); + tud_printer_write_flush(); + } +} + +int main(void) { + board_init(); + // init device stack on configured roothub port + tusb_rhport_init_t dev_init = {.role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO}; + tusb_init(BOARD_TUD_RHPORT, &dev_init); + board_init_after_tusb(); + + while (1) { + tud_task(); // tinyusb device task + printer_to_cdc_task(); // forward printer data to CDC + cdc_to_printer_task(); // forward CDC data to printer + } +} + +//--------------------------------------------------------------------+ +// Printer callbacks +//--------------------------------------------------------------------+ + +void tud_printer_rx_cb(uint8_t itf) { + (void)itf; +} + +// IEEE 1284 Device ID: first 2 bytes are big-endian total length (including the 2 length bytes). +// The rest is the Device ID string using standard abbreviated keys. +static const char printer_device_id[] = + "\x00\x34" // total length = 52 = 0x0034 (big-endian) + "MFG:TinyUSB;" + "MDL:Printer to CDC;" + "CMD:PS;" + "CLS:PRINTER;"; + +TU_VERIFY_STATIC(sizeof(printer_device_id) - 1 == 52, "device ID length mismatch"); + +uint8_t const *tud_printer_get_device_id_cb(uint8_t itf) { + (void)itf; + return (uint8_t const *)printer_device_id; +} diff --git a/examples/device/printer_to_cdc/src/tusb_config.h b/examples/device/printer_to_cdc/src/tusb_config.h new file mode 100644 index 000000000..74b96c8f6 --- /dev/null +++ b/examples/device/printer_to_cdc/src/tusb_config.h @@ -0,0 +1,120 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT + #define BOARD_TUD_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUD_MAX_SPEED + #define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU + #error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS + #define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG + #define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION + #define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN + #define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE + #define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_HID 0 +#define CFG_TUD_CDC 1 +#define CFG_TUD_MSC 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 +#define CFG_TUD_PRINTER 1 + +// CDC FIFO size of TX and RX +#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +// Printer buffer sizes +#define CFG_TUD_PRINTER_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_PRINTER_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_PRINTER_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_PRINTER_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/device/printer_to_cdc/src/usb_descriptors.c b/examples/device/printer_to_cdc/src/usb_descriptors.c new file mode 100644 index 000000000..30d309ed4 --- /dev/null +++ b/examples/device/printer_to_cdc/src/usb_descriptors.c @@ -0,0 +1,208 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "bsp/board_api.h" +#include "tusb.h" + +#include "usb_descriptors.h" + +#define USB_VID 0xCafe +#define USB_PID 0x4005 +#define USB_BCD 0x0200 + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +static tusb_desc_device_t const desc_device = { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = USB_BCD, + + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = USB_VID, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +uint8_t const *tud_descriptor_device_cb(void) { + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +// Endpoint numbers +#if defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY) + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + #define EPNUM_PRINTER_OUT 0x04 + #define EPNUM_PRINTER_IN 0x85 +#else + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x82 + #define EPNUM_PRINTER_OUT 0x03 + #define EPNUM_PRINTER_IN 0x83 +#endif + +// full speed configuration +static uint8_t const desc_fs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + // Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 16, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), + + // Interface number, string index, EP Bulk Out address, EP Bulk In address, EP size + TUD_PRINTER_DESCRIPTOR(ITF_NUM_PRINTER, 5, EPNUM_PRINTER_OUT, EPNUM_PRINTER_IN, 64), +}; + +#if TUD_OPT_HIGH_SPEED +// high speed configuration +static uint8_t const desc_hs_configuration[] = { + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 16, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512), + + TUD_PRINTER_DESCRIPTOR(ITF_NUM_PRINTER, 5, EPNUM_PRINTER_OUT, EPNUM_PRINTER_IN, 512), +}; + +// other speed configuration +static uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN]; + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +static tusb_desc_device_qualifier_t const desc_device_qualifier = { + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = USB_BCD, + + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +uint8_t const *tud_descriptor_device_qualifier_cb(void) { + return (uint8_t const *) &desc_device_qualifier; +} + +uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) { + (void) index; + + // if link speed is high return fullspeed config, and vice versa + memcpy(desc_other_speed_config, + (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration, + CONFIG_TOTAL_LEN); + + desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG; + + return desc_other_speed_config; +} + +#endif // TUD_OPT_HIGH_SPEED + +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void) index; + +#if TUD_OPT_HIGH_SPEED + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; +#else + return desc_fs_configuration; +#endif +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, + STRID_CDC, + STRID_PRINTER, +}; + +static char const *string_desc_arr[] = { + (const char[]) { 0x09, 0x04 }, // 0: supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serial, use unique ID if possible + "TinyUSB CDC", // 4: CDC Interface + "TinyUSB Printer", // 5: Printer Interface +}; + +static uint16_t _desc_str[32 + 1]; + +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void) langid; + size_t chr_count; + + switch (index) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = board_usb_get_serial(_desc_str + 1, 32); + break; + + default: + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { return NULL; } + + const char *str = string_desc_arr[index]; + + chr_count = strlen(str); + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; + if (chr_count > max_count) { chr_count = max_count; } + + for (size_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + break; + } + + _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + return _desc_str; +} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h b/examples/device/printer_to_cdc/src/usb_descriptors.h index 8f100284a..830593b4d 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h +++ b/examples/device/printer_to_cdc/src/usb_descriptors.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2019, Ha Thach (tinyusb.org) + * Copyright (c) 2026 Ha Thach (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -20,36 +20,18 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. */ -/* metadata: - name: Adafruit Metro M7 1011 SD - url: https://www.adafruit.com/product/5600 -*/ - -#ifndef BOARD_METRO_M7_1011_SD_H_ -#define BOARD_METRO_M7_1011_SD_H_ - -// required since iMXRT MCUX-SDK include this file for board size -#define BOARD_FLASH_SIZE (8*1024*1024) - -// LED: IOMUXC_GPIO_03_GPIOMUX_IO03 -#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL -#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL -#define LED_STATE_ON 1 - -// D8 as button: GPIO8 -#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL -#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL -#define BUTTON_STATE_ACTIVE 0 +#ifndef USB_DESCRIPTORS_H_ +#define USB_DESCRIPTORS_H_ -// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD -#define UART_PORT LPUART1 -#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT +enum { + ITF_NUM_CDC, + ITF_NUM_CDC_DATA, + ITF_NUM_PRINTER, + ITF_NUM_TOTAL, +}; -static inline void BOARD_ConfigMPU(void) { -} +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_PRINTER_DESC_LEN) -#endif +#endif /* USB_DESCRIPTORS_H_ */ diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 96fa66f1e..0ea63d8f7 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -559,7 +559,7 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const *p_reques // In a real application, this would be replaced with actual I2S send/receive callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) return;// not enough time start_ms = curr_ms; // When new data arrived, copy data from speaker buffer, to microphone buffer @@ -605,7 +605,7 @@ void audio_control_task(void) { static uint32_t start_ms = 0; static uint32_t btn_prev = 0; - if (board_millis() - start_ms < interval_ms) return;// not enough time + if (tusb_time_millis_api() - start_ms < interval_ms) return;// not enough time start_ms += interval_ms; uint32_t btn = board_button_read(); @@ -644,7 +644,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; + if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c index 7b4e2d64c..c3e97bb28 100644 --- a/examples/device/uac2_speaker_fb/src/main.c +++ b/examples/device/uac2_speaker_fb/src/main.c @@ -534,8 +534,9 @@ bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex)); uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue)); - if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0) + if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0) { blink_interval_ms = BLINK_MOUNTED; + } return true; } @@ -569,7 +570,8 @@ bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t fu fifo_count = tud_audio_available(); // Same averaging method used in UAC2 class - fifo_count_avg = (uint32_t) (((uint64_t) fifo_count_avg * 63 + ((uint32_t) fifo_count << 16)) >> 6); + const uint32_t ff_count32 = (uint32_t) fifo_count << 16; + fifo_count_avg = (uint32_t) (((uint64_t) fifo_count_avg * 63 + ff_count32) >> 6); return true; } @@ -583,7 +585,7 @@ bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t fu // In a real application, this would be replaced with actual I2S transmit callback. void audio_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) return;// not enough time start_ms = curr_ms; @@ -610,7 +612,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; + if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; start_ms += blink_interval_ms; board_led_write(led_state); @@ -624,7 +626,7 @@ void led_blinking_task(void) { // Every 1ms, we will sent 1 debug information report void audio_debug_task(void) { static uint32_t start_ms = 0; - uint32_t curr_ms = board_millis(); + uint32_t curr_ms = tusb_time_millis_api(); if (start_ms == curr_ms) return;// not enough time start_ms = curr_ms; diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 5cbbb85ef..b1269b117 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -124,12 +124,12 @@ void led_blinking_task(void) { led_state = true; board_led_write(true); - start_ms = board_millis(); + start_ms = tusb_time_millis_api(); doPulse = false; } else if (led_state == true) { - if ( board_millis() - start_ms < 750) //Spec says blink must be between 500 and 1000 ms. + if ( tusb_time_millis_api() - start_ms < 750) //Spec says blink must be between 500 and 1000 ms. { return; // not enough time } @@ -140,7 +140,7 @@ void led_blinking_task(void) else { // Blink every interval ms - if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c index 4c3724ac4..35e8618f5 100644 --- a/examples/device/usbtmc/src/usbtmc_app.c +++ b/examples/device/usbtmc/src/usbtmc_app.c @@ -209,19 +209,19 @@ void usbtmc_app_task_iter(void) { case 0: break; case 1: - queryDelayStart = board_millis(); + queryDelayStart = tusb_time_millis_api(); queryState = 2; break; case 2: - if( (board_millis() - queryDelayStart) > resp_delay) { - queryDelayStart = board_millis(); + if( (tusb_time_millis_api() - queryDelayStart) > resp_delay) { + queryDelayStart = tusb_time_millis_api(); queryState=3; status |= 0x10u; // MAV status |= 0x40u; // SRQ } break; case 3: - if( (board_millis() - queryDelayStart) > resp_delay) { + if( (tusb_time_millis_api() - queryDelayStart) > resp_delay) { queryState = 4; } break; diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index ffa2a7afa..df9f77a1c 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -231,7 +231,7 @@ static void video_send_frame(void) { if (!already_sent) { already_sent = 1; tx_busy = 1; - start_ms = board_millis(); + start_ms = tusb_time_millis_api(); #if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); #elif defined (CFG_EXAMPLE_VIDEO_READONLY) @@ -247,7 +247,7 @@ static void video_send_frame(void) { #endif } - unsigned cur = board_millis(); + unsigned cur = tusb_time_millis_api(); if (cur - start_ms < interval_ms) { return; // not enough time } @@ -316,7 +316,7 @@ void led_blinking_task(void* param) { #if CFG_TUSB_OS == OPT_OS_FREERTOS vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); #else - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } #endif diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index 79b149f2b..debd336fd 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -221,13 +221,13 @@ static void video_send_frame(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { if (!(already_sent & (1u << idx))) { already_sent |= 1u << idx; tx_busy |= 1u << idx; - start_ms[idx] = board_millis(); + start_ms[idx] = tusb_time_millis_api(); fb_size = get_framebuf(ctl_idx, stm_idx, frame_num[idx], &fp); tud_video_n_frame_xfer(ctl_idx, stm_idx, fp, fb_size); } - unsigned cur = board_millis(); + unsigned cur = tusb_time_millis_api(); if (cur - start_ms[idx] < interval_ms[idx]) return; // not enough time if (tx_busy & (1u << idx)) return; start_ms[idx] += interval_ms[idx]; @@ -280,7 +280,7 @@ void led_blinking_task(void* param) { #if CFG_TUSB_OS == OPT_OS_FREERTOS vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); #else - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time + if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time #endif start_ms += blink_interval_ms; diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index 155768b76..4be5e4db4 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -257,7 +257,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } start_ms += blink_interval_ms; diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt index 4978f1fab..8727ea938 100644 --- a/examples/dual/CMakeLists.txt +++ b/examples/dual/CMakeLists.txt @@ -12,6 +12,7 @@ else () set(EXAMPLE_LIST host_hid_to_device_cdc host_info_to_device_cdc + dynamic_switch ) foreach (example ${EXAMPLE_LIST}) diff --git a/examples/dual/dynamic_switch/CMakeLists.txt b/examples/dual/dynamic_switch/CMakeLists.txt new file mode 100644 index 000000000..7cad30727 --- /dev/null +++ b/examples/dual/dynamic_switch/CMakeLists.txt @@ -0,0 +1,30 @@ +cmake_minimum_required(VERSION 3.20) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +project(dynamic_switch C CXX ASM) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}) + +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + +add_executable(${PROJECT_NAME}) + +# Example source +target_sources(${PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) + +# Example include +target_include_directories(${PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_dual_usb_example(${PROJECT_NAME} noos) diff --git a/examples/dual/dynamic_switch/CMakePresets.json b/examples/dual/dynamic_switch/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/dual/dynamic_switch/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/dual/dynamic_switch/Makefile b/examples/dual/dynamic_switch/Makefile new file mode 100644 index 000000000..44ab54ad7 --- /dev/null +++ b/examples/dual/dynamic_switch/Makefile @@ -0,0 +1,16 @@ +include ../../../hw/bsp/family_support.mk + +INC += \ + src \ + +# Example source +EXAMPLE_SOURCE += $(wildcard src/*.c) +SRC_C += $(addprefix $(EXAMPLE_PATH)/, $(EXAMPLE_SOURCE)) + +# Include device and host stack +SRC_C += \ + src/class/cdc/cdc_device.c \ + src/host/hub.c \ + src/host/usbh.c + +include ../../../hw/bsp/family_rules.mk diff --git a/examples/dual/dynamic_switch/README.md b/examples/dual/dynamic_switch/README.md new file mode 100644 index 000000000..034787f18 --- /dev/null +++ b/examples/dual/dynamic_switch/README.md @@ -0,0 +1,60 @@ +# Dynamic Switch Example + +This example demonstrates TinyUSB's dual-role capability by allowing runtime switching between USB device and host modes. + +## Features + +- **Button-triggered mode switching**: Press the board button to switch between device and host modes +- **Device Mode**: Acts as a USB CDC (Virtual Serial Port) that echoes all received data +- **Host Mode**: Enumerates connected USB devices and prints device information +- **Dynamic switching**: Deinitializes the current stack and reinitializes in the new mode + +## Usage + +1. **Build and flash** the example to your board +2. **Default behavior**: The board starts in **Device mode** +3. **Device mode**: + - Connect the board to a PC + - Open a serial terminal (e.g., `screen /dev/ttyACM0` or PuTTY) + - Type characters - they will be echoed back to you +4. **Switch to Host mode**: + - Press the board button + - Connect a USB device to the board + - The board will enumerate the device and print its descriptors to the debug console +5. **Switch back to Device mode**: Press the button again + +## LED Patterns + +The onboard LED indicates the USB connection status: + +- **Fast blink (250ms)**: Not mounted/connected +- **Slow blink (1000ms)**: Successfully mounted/connected +- **Very slow blink (2500ms)**: Suspended (device mode only) + +## Serial Output + +The example prints status messages to the debug UART: + +``` +====================================== +TinyUSB Dynamic Switch Example +Press button to switch between device and host modes +Starting in DEVICE mode... +====================================== + +[DEVICE] Mounted + +--- Switching USB mode --- +Stopping DEVICE mode... +Starting HOST mode... +Mode switch complete! + +[HOST] Device attached, address = 1 +Device 1: ID 1234:5678 SN ABC123 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 0200 + bDeviceClass 239 + ... +``` diff --git a/examples/dual/dynamic_switch/only.txt b/examples/dual/dynamic_switch/only.txt new file mode 100644 index 000000000..70be49b28 --- /dev/null +++ b/examples/dual/dynamic_switch/only.txt @@ -0,0 +1,12 @@ +family:espressif +mcu:LPC43XX +mcu:MIMXRT1XXX +mcu:STM32C0 +mcu:STM32G0 +mcu:STM32H5 +mcu:STM32F2 +mcu:STM32F4 +mcu:STM32U5 +mcu:STM32F7 +mcu:STM32H7 +mcu:STM32H7RS diff --git a/examples/dual/dynamic_switch/src/CMakeLists.txt b/examples/dual/dynamic_switch/src/CMakeLists.txt new file mode 100644 index 000000000..cef2b46ee --- /dev/null +++ b/examples/dual/dynamic_switch/src/CMakeLists.txt @@ -0,0 +1,4 @@ +# This file is for ESP-IDF only +idf_component_register(SRCS "main.c" "usb_descriptors.c" + INCLUDE_DIRS "." + REQUIRES boards tinyusb_src) diff --git a/examples/dual/dynamic_switch/src/main.c b/examples/dual/dynamic_switch/src/main.c new file mode 100644 index 000000000..c9ad2a835 --- /dev/null +++ b/examples/dual/dynamic_switch/src/main.c @@ -0,0 +1,496 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +/* This example demonstrates dynamic switching between device and host modes: + * - Press button to switch between device and host modes + * - Device mode: CDC echo (echoes input back to output) + * - Host mode: Prints connected device information + */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> + +#include "bsp/board_api.h" +#include "tusb.h" + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + #ifdef ESP_PLATFORM + #define USBD_STACK_SIZE 4096 + #define USBH_STACK_SIZE 4096 + #else + // Increase stack size when debug log is enabled + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) + #define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) + #endif + + #define CDC_STACK_SIZE (configMINIMAL_STACK_SIZE * (CFG_TUSB_DEBUG ? 2 : 1)) + #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTOTYPES +//--------------------------------------------------------------------+ + +// English +#define LANGUAGE_ID 0x0409 + +/* Blink pattern + * - 250 ms : not mounted + * - 1000 ms : mounted + * - 2500 ms : suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +#if CFG_TUSB_OS == OPT_OS_FREERTOS +// static task for FreeRTOS +#if configSUPPORT_STATIC_ALLOCATION +StackType_t blinky_stack[BLINKY_STACK_SIZE]; +StaticTask_t blinky_taskdef; + +StackType_t usb_stack[USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE]; +StaticTask_t usb_taskdef; + +StackType_t cdc_stack[CDC_STACK_SIZE]; +StaticTask_t cdc_taskdef; +#endif +#endif + +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; +static tusb_role_t current_role = TUSB_ROLE_DEVICE; + +#if CFG_TUSB_OS == OPT_OS_FREERTOS +static void usb_task(void *param); +void led_blinking_task(void *param); +void cdc_task(void *params); +#else +void led_blinking_task(void); +void cdc_task(void); +#endif +void usb_mode_switch(void); +static void print_device_info(uint8_t daddr); +static void print_utf16(uint16_t* temp_buf, size_t buf_len); + +// Declare buffer for USB transfer +CFG_TUH_MEM_SECTION struct { + TUH_EPBUF_TYPE_DEF(tusb_desc_device_t, device); + TUH_EPBUF_DEF(serial, 64*sizeof(uint16_t)); + TUH_EPBUF_DEF(buf, 128*sizeof(uint16_t)); +} desc; + +//--------------------------------------------------------------------+ +// Main +//--------------------------------------------------------------------+ + +int main(void) { + board_init(); + + printf("\r\n======================================\r\n"); + printf("TinyUSB Dynamic Switch Example\r\n"); + printf("Press button to switch between device and host modes\r\n"); + printf("Starting in DEVICE mode...\r\n"); + printf("======================================\r\n\r\n"); + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // Create FreeRTOS tasks +#if configSUPPORT_STATIC_ALLOCATION + xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef); + xTaskCreateStatic(usb_task, "usb", USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE, + NULL, configMAX_PRIORITIES-1, usb_stack, &usb_taskdef); + xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef); +#else + xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); + xTaskCreate(usb_task, "usb", USBD_STACK_SIZE > USBH_STACK_SIZE ? USBD_STACK_SIZE : USBH_STACK_SIZE, + NULL, configMAX_PRIORITIES - 1, NULL); + xTaskCreate(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL); +#endif + +#ifndef ESP_PLATFORM + // only start scheduler for non-espressif mcu + vTaskStartScheduler(); +#endif + +#else + // Initialize in device mode by default + tusb_rhport_init_t dev_init = { + .role = TUSB_ROLE_DEVICE, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_RHPORT, &dev_init); + current_role = TUSB_ROLE_DEVICE; + + board_init_after_tusb(); + + while (1) { + // Check for button press to switch modes + static bool pending_switch = false; + if (board_button_read()) { + if (!pending_switch) { + pending_switch = true; + usb_mode_switch(); + } + } else { + pending_switch = false; + } + + // Process USB tasks based on current mode + if (current_role == TUSB_ROLE_DEVICE) { + tud_task(); + cdc_task(); + } else { + tuh_task(); + } + + led_blinking_task(); + } +#endif +} + +#ifdef ESP_PLATFORM +void app_main(void) { + main(); +} +#endif + +#if CFG_TUSB_OS == OPT_OS_FREERTOS +// USB Task for FreeRTOS +// This top level thread processes all usb events and mode switching +static void usb_task(void *param) { + (void) param; + + // init device stack on configured roothub port + // This should be called after scheduler/kernel is started. + // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. + tusb_rhport_init_t dev_init = { + .role = TUSB_ROLE_DEVICE, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_RHPORT, &dev_init); + current_role = TUSB_ROLE_DEVICE; + + board_init_after_tusb(); + + // RTOS forever loop + while (1) { + // Check for button press to switch modes + static bool pending_switch = false; + if (board_button_read()) { + if (!pending_switch) { + pending_switch = true; + usb_mode_switch(); + } + } else { + pending_switch = false; + } + + // Process USB tasks based on current mode + // Use _ext version to allow return and read button state + if (current_role == TUSB_ROLE_DEVICE) { + tud_task_ext(10, false); + } else { + tuh_task_ext(10, false); + } + } +} +#endif + +//--------------------------------------------------------------------+ +// Mode Switching +//--------------------------------------------------------------------+ + +void usb_mode_switch(void) { + printf("\r\n--- Switching USB mode ---\r\n"); + + // Deinitialize current mode + if (current_role == TUSB_ROLE_DEVICE) { + printf("Stopping DEVICE mode...\r\n"); + tusb_deinit(BOARD_RHPORT); + } else { + printf("Stopping HOST mode...\r\n"); + tusb_deinit(BOARD_RHPORT); + } + +#if CFG_TUSB_OS == OPT_OS_FREERTOS + vTaskDelay(pdMS_TO_TICKS(100)); // Small delay for clean transition +#else + tusb_time_delay_ms_api(100); // Small delay for clean transition +#endif // Switch to the other mode + if (current_role == TUSB_ROLE_DEVICE) { + printf("Starting HOST mode...\r\n"); + tusb_rhport_init_t host_init = { + .role = TUSB_ROLE_HOST, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_RHPORT, &host_init); + current_role = TUSB_ROLE_HOST; + } else { + printf("Starting DEVICE mode...\r\n"); + tusb_rhport_init_t dev_init = { + .role = TUSB_ROLE_DEVICE, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_RHPORT, &dev_init); + current_role = TUSB_ROLE_DEVICE; + } + + blink_interval_ms = BLINK_NOT_MOUNTED; + printf("Mode switch complete!\r\n\r\n"); +} + +//--------------------------------------------------------------------+ +// Device Mode: CDC Task +//--------------------------------------------------------------------+ + +#if CFG_TUSB_OS == OPT_OS_FREERTOS +void cdc_task(void *params) { + (void) params; + + // RTOS forever loop + while (1) { + // Only process CDC when in device mode + if (current_role == TUSB_ROLE_DEVICE) { + // Connected and there are data available + while (tud_cdc_available()) { + uint8_t buf[64]; + + // Read data + uint32_t count = tud_cdc_read(buf, sizeof(buf)); + + // Echo back + tud_cdc_write(buf, count); + + // Add newline for carriage return + for (uint32_t i = 0; i < count; i++) { + if (buf[i] == '\r') { + tud_cdc_write_char('\n'); + break; + } + } + } + + tud_cdc_write_flush(); + } + + vTaskDelay(pdMS_TO_TICKS(10)); + } +} +#else +void cdc_task(void) { + // Connected and there are data available + if (tud_cdc_available()) { + uint8_t buf[64]; + + // Read data + uint32_t count = tud_cdc_read(buf, sizeof(buf)); + + // Echo back + for (uint32_t i = 0; i < count; i++) { + tud_cdc_write_char(buf[i]); + + if (buf[i] == '\r') { + tud_cdc_write_char('\n'); + } + } + + tud_cdc_write_flush(); + } +} +#endif + +//--------------------------------------------------------------------+ +// Device Callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted +void tud_mount_cb(void) { + printf("[DEVICE] Mounted\r\n"); + blink_interval_ms = BLINK_MOUNTED; +} + +// Invoked when device is unmounted +void tud_umount_cb(void) { + printf("[DEVICE] Unmounted\r\n"); + blink_interval_ms = BLINK_NOT_MOUNTED; +} + +// Invoked when usb bus is suspended +void tud_suspend_cb(bool remote_wakeup_en) { + (void) remote_wakeup_en; + printf("[DEVICE] Suspended\r\n"); + blink_interval_ms = BLINK_SUSPENDED; +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) { + printf("[DEVICE] Resumed\r\n"); + blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; +} + +//--------------------------------------------------------------------+ +// Host Callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted (configured) +void tuh_mount_cb(uint8_t daddr) { + printf("[HOST] Device attached, address = %d\r\n", daddr); + blink_interval_ms = BLINK_MOUNTED; + print_device_info(daddr); +} + +// Invoked when device is unmounted (unplugged) +void tuh_umount_cb(uint8_t daddr) { + printf("[HOST] Device removed, address = %d\r\n", daddr); + blink_interval_ms = BLINK_NOT_MOUNTED; +} + +//--------------------------------------------------------------------+ +// Host Device Info +//--------------------------------------------------------------------+ + +static void print_device_info(uint8_t daddr) { + // Get Device Descriptor + uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc.device, 18); + if (XFER_RESULT_SUCCESS != xfer_result) { + printf("Failed to get device descriptor\r\n"); + return; + } + + printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct); + + xfer_result = XFER_RESULT_FAILED; + if (desc.device.iSerialNumber != 0) { + xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial)); + } + if (XFER_RESULT_SUCCESS != xfer_result) { + uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial; + serial[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * 3 + 2)); + serial[1] = 'n'; + serial[2] = '/'; + serial[3] = 'a'; + serial[4] = 0; + } + print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2); + printf("\r\n"); + + printf("Device Descriptor:\r\n"); + printf(" bLength %u\r\n", desc.device.bLength); + printf(" bDescriptorType %u\r\n", desc.device.bDescriptorType); + printf(" bcdUSB %04x\r\n", desc.device.bcdUSB); + printf(" bDeviceClass %u\r\n", desc.device.bDeviceClass); + printf(" bDeviceSubClass %u\r\n", desc.device.bDeviceSubClass); + printf(" bDeviceProtocol %u\r\n", desc.device.bDeviceProtocol); + printf(" bMaxPacketSize0 %u\r\n", desc.device.bMaxPacketSize0); + printf(" idVendor 0x%04x\r\n", desc.device.idVendor); + printf(" idProduct 0x%04x\r\n", desc.device.idProduct); + printf(" bcdDevice %04x\r\n", desc.device.bcdDevice); + + // Get Manufacturer string + if (desc.device.iManufacturer) { + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf))) { + printf(" iManufacturer %u ", desc.device.iManufacturer); + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + printf("\r\n"); + } + } + + // Get Product string + if (desc.device.iProduct) { + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf))) { + printf(" iProduct %u ", desc.device.iProduct); + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + printf("\r\n"); + } + } + + // Get Serial string + if (desc.device.iSerialNumber) { + printf(" iSerialNumber %u ", desc.device.iSerialNumber); + print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2); + printf("\r\n"); + } else { + printf(" iSerialNumber 0\r\n"); + } + + printf(" bNumConfigurations %u\r\n", desc.device.bNumConfigurations); + printf("\r\n"); +} + +static void print_utf16(uint16_t* temp_buf, size_t buf_len) { + if (temp_buf[0] == 0 || (temp_buf[0] >> 8) != TUSB_DESC_STRING) { + printf("(invalid)"); + return; + } + + size_t chr_count = (temp_buf[0] & 0xff) / 2 - 1; + if (chr_count > buf_len - 1) { + chr_count = buf_len - 1; + } + + for (size_t i = 0; i < chr_count; i++) { + uint16_t ch = temp_buf[1 + i]; + if (ch <= 0x7F) { + putchar((char) ch); + } else { + // TODO support UTF16 to UTF8 conversion + putchar('?'); + } + } +} + +//--------------------------------------------------------------------+ +// Blinking Task +//--------------------------------------------------------------------+ + +#if CFG_TUSB_OS == OPT_OS_FREERTOS +void led_blinking_task(void *param) { + (void) param; + static bool led_state = false; + + // RTOS forever loop + while (1) { + board_led_write(led_state); + led_state = 1 - led_state; // toggle + vTaskDelay(pdMS_TO_TICKS(blink_interval_ms)); + } +} +#else +void led_blinking_task(void) { + static uint32_t start_ms = 0; + static bool led_state = false; + + // Blink every interval ms + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { + return; // not enough time + } + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} +#endif diff --git a/examples/dual/dynamic_switch/src/tusb_config.h b/examples/dual/dynamic_switch/src/tusb_config.h new file mode 100644 index 000000000..f3e016305 --- /dev/null +++ b/examples/dual/dynamic_switch/src/tusb_config.h @@ -0,0 +1,160 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used can be defined by board.mk, default to port 0 +#ifndef BOARD_RHPORT + #if defined(BOARD_TUD_RHPORT) + #define BOARD_RHPORT BOARD_TUD_RHPORT + #else + #define BOARD_RHPORT 0 + #define BOARD_TUD_RHPORT 0 + #endif +#endif + +#if defined(BOARD_TUH_RHPORT) + #if BOARD_TUH_RHPORT != BOARD_RHPORT + #undef BOARD_TUH_RHPORT + #define BOARD_TUH_RHPORT BOARD_RHPORT + #endif +#else + #define BOARD_TUH_RHPORT BOARD_RHPORT +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_MAX_SPEED + #if defined(BOARD_TUD_MAX_SPEED) + #define BOARD_MAX_SPEED BOARD_TUD_MAX_SPEED + #else + #define BOARD_MAX_SPEED OPT_MODE_DEFAULT_SPEED + #endif +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU +#error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device and Host stacks (dual role) +#define CFG_TUD_ENABLED 1 +#define CFG_TUH_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_MAX_SPEED +#define CFG_TUH_MAX_SPEED BOARD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUD_MEM_SECTION +#define CFG_TUD_MEM_SECTION +#endif + +#ifndef CFG_TUD_MEM_ALIGN +#define CFG_TUD_MEM_ALIGN __attribute__((aligned(4))) +#endif + +#ifndef CFG_TUH_MEM_SECTION +#define CFG_TUH_MEM_SECTION CFG_TUD_MEM_SECTION +#endif + +#ifndef CFG_TUH_MEM_ALIGN +#define CFG_TUH_MEM_ALIGN CFG_TUD_MEM_ALIGN +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 1 +#define CFG_TUD_MSC 0 +#define CFG_TUD_HID 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 + +// CDC FIFO size of TX and RX +#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +//-------------------------------------------------------------------- +// HOST CONFIGURATION +//-------------------------------------------------------------------- + +// Size of buffer to hold descriptors and other data used for enumeration +#define CFG_TUH_ENUMERATION_BUFSIZE 256 + +#define CFG_TUH_HUB 1 +// max device support (excluding hub device) +#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports + +#define CFG_TUH_CDC 0 +#define CFG_TUH_HID 0 +#define CFG_TUH_MSC 0 +#define CFG_TUH_VENDOR 0 + +// max endpoint pair supported by each device +#define CFG_TUH_ENDPOINT_MAX 16 + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/dual/dynamic_switch/src/usb_descriptors.c b/examples/dual/dynamic_switch/src/usb_descriptors.c new file mode 100644 index 000000000..54ffc2c18 --- /dev/null +++ b/examples/dual/dynamic_switch/src/usb_descriptors.c @@ -0,0 +1,199 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "bsp/board_api.h" +#include "tusb.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB] + */ +#define PID_MAP(itf, n) ((CFG_TUD_##itf) ? (1 << (n)) : 0) +#define USB_PID (0x4000 | PID_MAP(CDC, 0) | PID_MAP(MSC, 1) | PID_MAP(HID, 2) | \ + PID_MAP(MIDI, 3) | PID_MAP(VENDOR, 4)) + +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +static tusb_desc_device_t const desc_device = { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = USB_BCD, + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = USB_VID, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const *tud_descriptor_device_cb(void) { + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +enum { + ITF_NUM_CDC = 0, + ITF_NUM_CDC_DATA, + ITF_NUM_TOTAL +}; + +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x82 + +#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY) + // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + +#else + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x82 + +#endif + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) + +static uint8_t const desc_fs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), +}; + +#if TUD_OPT_HIGH_SPEED +static uint8_t const desc_hs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512), +}; +#endif + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void) index; // for multiple configurations + +#if TUD_OPT_HIGH_SPEED + // Although we are highspeed, host may be fullspeed. + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; +#else + return desc_fs_configuration; +#endif +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, +}; + +// array of pointer to string descriptors +static char const *string_desc_arr[] = { + (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials, will use unique ID if possible + "TinyUSB CDC", // 4: CDC Interface +}; + +static uint16_t _desc_str[32 + 1]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void) langid; + size_t chr_count; + + switch (index) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = board_usb_get_serial(_desc_str + 1, 32); + break; + + default: + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { return NULL; } + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if (chr_count > max_count) { chr_count = max_count; } + + // Convert ASCII string into UTF-16 + for (size_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + break; + } + + // first byte is length (including header), second byte is string type + _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + return _desc_str; +} diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 8c53588c3..c8fca48f8 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -98,8 +98,6 @@ int main(void) { tuh_task(); // tinyusb host task led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ @@ -284,7 +282,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time + if (tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h index 2843e0b83..fb2a401b5 100644 --- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h +++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h @@ -114,8 +114,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) //-------------------------------------------------------------------- // HOST CONFIGURATION diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index fffb54d58..fe2199a69 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -106,7 +106,7 @@ static void usb_device_init(void) { .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUD_RHPORT, &dev_init); - tud_cdc_configure_t cdc_cfg = TUD_CDC_CONFIGURE_DEFAULT(); + tud_cdc_configure_t cdc_cfg = CFG_TUD_CDC_CONFIGURE_DEFAULT(); cdc_cfg.tx_persistent = true; cdc_cfg.tx_overwritabe_if_not_connected = false; tud_cdc_configure(&cdc_cfg); @@ -213,13 +213,13 @@ void cdc_task(void) { static uint32_t connected_ms = 0; if (!tud_cdc_connected()) { - connected_ms = board_millis(); + connected_ms = tusb_time_millis_api(); return; } // delay a bit otherwise we can outpace host's terminal. Linux will set LineState (DTR) then Line Coding. // If we send data before Linux's terminal set Line Coding, it can be ignored --> missing data with hardware test loop - if (board_millis() - connected_ms < 100) { + if (tusb_time_millis_api() - connected_ms < 100) { return; // wait for stable connection } @@ -309,7 +309,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return;// not enough time } start_ms += blink_interval_ms; diff --git a/examples/dual/host_info_to_device_cdc/src/tusb_config.h b/examples/dual/host_info_to_device_cdc/src/tusb_config.h index 601c27dae..99e9315a4 100644 --- a/examples/dual/host_info_to_device_cdc/src/tusb_config.h +++ b/examples/dual/host_info_to_device_cdc/src/tusb_config.h @@ -114,8 +114,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 256) -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) //-------------------------------------------------------------------- // HOST CONFIGURATION diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index f07d63f9d..1ddfc2b5c 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -8,6 +8,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/bare_api/skip.txt b/examples/host/bare_api/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/bare_api/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index c693d6b00..544f38102 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -37,11 +37,13 @@ #define BUF_COUNT 4 -tusb_desc_device_t desc_device; +CFG_TUH_MEM_SECTION tusb_desc_device_t desc_device; -uint8_t buf_pool[BUF_COUNT][64]; +CFG_TUH_MEM_SECTION uint8_t buf_pool[BUF_COUNT][64]; uint8_t buf_owner[BUF_COUNT] = { 0 }; // device address that owns buffer +CFG_TUH_MEM_SECTION uint16_t temp_buf[128]; // temp buffer for string descriptor + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -74,8 +76,6 @@ int main(void) { tuh_task(); led_blinking_task(); } - - return 0; } /*------------- TinyUSB Callbacks -------------*/ @@ -120,8 +120,6 @@ void print_device_descriptor(tuh_xfer_t *xfer) { printf(" bcdDevice %04x\r\n" , desc_device.bcdDevice); // Get String descriptor using Sync API - uint16_t temp_buf[128]; - printf(" iManufacturer %u ", desc_device.iManufacturer); if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); @@ -335,7 +333,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < interval_ms) { + if (tusb_time_millis_api() - start_ms < interval_ms) { return; // not enough time } start_ms += interval_ms; @@ -386,12 +384,12 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) { return (int) total_bytes; } -static void print_utf16(uint16_t *temp_buf, size_t buf_len) { - if ((temp_buf[0] & 0xff) == 0) return;// empty - size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); - size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); - _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); - ((uint8_t *) temp_buf)[utf8_len] = '\0'; +static void print_utf16(uint16_t *buf, size_t buf_len) { + if ((buf[0] & 0xff) == 0) return;// empty + size_t utf16_len = ((buf[0] & 0xff) - 2) / sizeof(uint16_t); + size_t utf8_len = (size_t) _count_utf8_bytes(buf + 1, utf16_len); + _convert_utf16le_to_utf8(buf + 1, utf16_len, (uint8_t *) buf, sizeof(uint16_t) * buf_len); + ((uint8_t *) buf)[utf8_len] = '\0'; - printf("%s", (char *) temp_buf); + printf("%s", (char *) buf); } diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index f07d63f9d..1ddfc2b5c 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -8,6 +8,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/cdc_msc_hid/skip.txt b/examples/host/cdc_msc_hid/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/cdc_msc_hid/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index c309a7cae..c27ad93fe 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -92,7 +92,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < interval_ms) { + if (tusb_time_millis_api() - start_ms < interval_ms) { return;// not enough time } start_ms += interval_ms; diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index b0460b362..753fa7cd3 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -6,6 +6,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/cdc_msc_hid_freertos/skip.txt b/examples/host/cdc_msc_hid_freertos/skip.txt index 2ba4438fd..54e7be1ba 100644 --- a/examples/host/cdc_msc_hid_freertos/skip.txt +++ b/examples/host/cdc_msc_hid_freertos/skip.txt @@ -1 +1,2 @@ mcu:RP2040 +board:lpcxpresso54114 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index 714c1078a..742935dcf 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -9,6 +9,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/device_info/skip.txt b/examples/host/device_info/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/device_info/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index ab617e989..b0e38dd6b 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -105,7 +105,6 @@ int main(void) { tuh_task(); // tinyusb host task led_blinking_task(NULL); } - return 0; #endif } @@ -246,7 +245,7 @@ void led_blinking_task(void* param) { #if CFG_TUSB_OS == OPT_OS_FREERTOS vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); #else - if (board_millis() - start_ms < blink_interval_ms) { + if (tusb_time_millis_api() - start_ms < blink_interval_ms) { return; // not enough time } #endif diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 8ec2f5cfe..45ca6846f 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -8,6 +8,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/hid_controller/skip.txt b/examples/host/hid_controller/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/hid_controller/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index f8c3d029b..5417811f0 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -168,7 +168,7 @@ void hid_app_task(void) const uint32_t interval_ms = 200; static uint32_t start_ms = 0; - uint32_t current_time_ms = board_millis(); + uint32_t current_time_ms = tusb_time_millis_api(); if ( current_time_ms - start_ms >= interval_ms) { start_ms = current_time_ms; diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index fa70d7d1a..a9eebc90b 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -79,7 +79,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if ( board_millis() - start_ms < interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time start_ms += interval_ms; board_led_write(led_state); diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt index 9d647a340..c71aacd87 100644 --- a/examples/host/midi_rx/only.txt +++ b/examples/host/midi_rx/only.txt @@ -11,6 +11,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/midi_rx/skip.txt b/examples/host/midi_rx/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/midi_rx/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/midi_rx/src/main.c b/examples/host/midi_rx/src/main.c index 78b1a11b9..fb36906c6 100644 --- a/examples/host/midi_rx/src/main.c +++ b/examples/host/midi_rx/src/main.c @@ -58,8 +58,6 @@ int main(void) { led_blinking_task(); midi_host_rx_task(); } - - return 0; } //--------------------------------------------------------------------+ @@ -72,7 +70,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < interval_ms) return;// not enough time + if (tusb_time_millis_api() - start_ms < interval_ms) return;// not enough time start_ms += interval_ms; board_led_write(led_state); diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index f07d63f9d..1ddfc2b5c 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -8,6 +8,8 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:LPC54 +mcu:LPC55 mcu:MAX3421 mcu:MIMXRT10XX mcu:MIMXRT11XX diff --git a/examples/host/msc_file_explorer/skip.txt b/examples/host/msc_file_explorer/skip.txt new file mode 100644 index 000000000..308796869 --- /dev/null +++ b/examples/host/msc_file_explorer/skip.txt @@ -0,0 +1 @@ +board:lpcxpresso54114 diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index f9ec0ff5f..f6bf9a60a 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -92,8 +92,6 @@ int main(void) { msc_app_task(); led_blinking_task(); } - - return 0; } //--------------------------------------------------------------------+ @@ -118,7 +116,7 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < interval_ms) return; // not enough time + if (tusb_time_millis_api() - start_ms < interval_ms) return; // not enough time start_ms += interval_ms; board_led_write(led_state); diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index 40a9ef57e..6ac63e937 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -49,11 +49,14 @@ #define CLI_BINDING_COUNT 8 static EmbeddedCli *_cli; -static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)]; +static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)]; //------------- Elm Chan FatFS -------------// -static FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device -static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX]; +static CFG_TUH_MEM_SECTION FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device +static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX]; + +static CFG_TUH_MEM_SECTION FIL file1, file2; +static CFG_TUH_MEM_SECTION uint8_t rw_buf[512]; // define the buffer to be place in USB/DMA memory with correct alignment/cache line size CFG_TUH_MEM_SECTION static struct { @@ -67,34 +70,30 @@ CFG_TUH_MEM_SECTION static struct { bool cli_init(void); -bool msc_app_init(void) -{ - for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) { +bool msc_app_init(void) { + for (size_t i = 0; i < CFG_TUH_DEVICE_MAX; i++) { _disk_busy[i] = false; } - // disable stdout buffered for echoing typing command - #ifndef __ICCARM__ // TODO IAR doesn't support stream control ? +// disable stdout buffered for echoing typing command +#ifndef __ICCARM__ // TODO IAR doesn't support stream control ? setbuf(stdout, NULL); - #endif +#endif cli_init(); return true; } -void msc_app_task(void) -{ +void msc_app_task(void) { if (!_cli) { return; } int ch = board_getchar(); - if ( ch > 0 ) - { - while( ch > 0 ) - { - embeddedCliReceiveChar(_cli, (char) ch); + if (ch > 0) { + while (ch > 0) { + embeddedCliReceiveChar(_cli, (char)ch); ch = board_getchar(); } embeddedCliProcess(_cli); @@ -105,33 +104,32 @@ void msc_app_task(void) // //--------------------------------------------------------------------+ -static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { - msc_cbw_t const* cbw = cb_data->cbw; - msc_csw_t const* csw = cb_data->csw; +static bool inquiry_complete_cb(uint8_t dev_addr, const tuh_msc_complete_data_t *cb_data) { + const msc_cbw_t *cbw = cb_data->cbw; + const msc_csw_t *csw = cb_data->csw; - if (csw->status != 0) - { + if (csw->status != 0) { printf("Inquiry failed\r\n"); return false; } // Print out Vendor ID, Product ID and Rev - printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev); + printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, + scsi_resp.inquiry.product_rev); // Get capacity of device - uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun); - uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun); + const uint32_t block_count = tuh_msc_get_block_count(dev_addr, cbw->lun); + const uint32_t block_size = tuh_msc_get_block_size(dev_addr, cbw->lun); - printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size)); + printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024 * 1024) / block_size)); // printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size); // For simplicity: we only mount 1 LUN per device - uint8_t const drive_num = dev_addr-1; - char drive_path[3] = "0:"; + const uint8_t drive_num = dev_addr - 1; + char drive_path[3] = "0:"; drive_path[0] += drive_num; - if ( f_mount(&fatfs[drive_num], drive_path, 1) != FR_OK ) - { + if (f_mount(&fatfs[drive_num], drive_path, 1) != FR_OK) { puts("mount failed"); } @@ -139,151 +137,134 @@ static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const f_chdir(drive_path); // print the drive label -// char label[34]; -// if ( FR_OK == f_getlabel(drive_path, label, NULL) ) -// { -// puts(label); -// } + // char label[34]; + // if ( FR_OK == f_getlabel(drive_path, label, NULL) ) + // { + // puts(label); + // } return true; } //------------- IMPLEMENTATION -------------// -void tuh_msc_mount_cb(uint8_t dev_addr) -{ +void tuh_msc_mount_cb(uint8_t dev_addr) { printf("A MassStorage device is mounted\r\n"); - uint8_t const lun = 0; + const uint8_t lun = 0; tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0); } -void tuh_msc_umount_cb(uint8_t dev_addr) -{ +void tuh_msc_umount_cb(uint8_t dev_addr) { printf("A MassStorage device is unmounted\r\n"); - uint8_t const drive_num = dev_addr-1; - char drive_path[3] = "0:"; + const uint8_t drive_num = dev_addr - 1; + char drive_path[3] = "0:"; drive_path[0] += drive_num; f_unmount(drive_path); -// if ( phy_disk == f_get_current_drive() ) -// { // active drive is unplugged --> change to other drive -// for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++) -// { -// if ( disk_is_ready(i) ) -// { -// f_chdrive(i); -// cli_init(); // refractor, rename -// } -// } -// } + // if ( phy_disk == f_get_current_drive() ) + // { // active drive is unplugged --> change to other drive + // for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++) + // { + // if ( disk_is_ready(i) ) + // { + // f_chdrive(i); + // cli_init(); // refractor, rename + // } + // } + // } } //--------------------------------------------------------------------+ // DiskIO //--------------------------------------------------------------------+ -static void wait_for_disk_io(BYTE pdrv) -{ - while(_disk_busy[pdrv]) - { +static void wait_for_disk_io(BYTE pdrv) { + while (_disk_busy[pdrv]) { tuh_task(); } } -static bool disk_io_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ - (void) dev_addr; (void) cb_data; - _disk_busy[dev_addr-1] = false; +static bool disk_io_complete(uint8_t dev_addr, const tuh_msc_complete_data_t *cb_data) { + (void)dev_addr; + (void)cb_data; + _disk_busy[dev_addr - 1] = false; return true; } -DSTATUS disk_status ( - BYTE pdrv /* Physical drive nmuber to identify the drive */ -) -{ +DSTATUS disk_status(BYTE pdrv /* Physical drive nmuber to identify the drive */ +) { uint8_t dev_addr = pdrv + 1; return tuh_msc_mounted(dev_addr) ? 0 : STA_NODISK; } -DSTATUS disk_initialize ( - BYTE pdrv /* Physical drive nmuber to identify the drive */ -) -{ - (void) pdrv; - return 0; // nothing to do +DSTATUS disk_initialize(BYTE pdrv /* Physical drive nmuber to identify the drive */ +) { + (void)pdrv; + return 0; // nothing to do } -DRESULT disk_read ( - BYTE pdrv, /* Physical drive nmuber to identify the drive */ - BYTE *buff, /* Data buffer to store read data */ - LBA_t sector, /* Start sector in LBA */ - UINT count /* Number of sectors to read */ -) -{ - uint8_t const dev_addr = pdrv + 1; - uint8_t const lun = 0; +DRESULT disk_read(BYTE pdrv, /* Physical drive nmuber to identify the drive */ + BYTE *buff, /* Data buffer to store read data */ + LBA_t sector, /* Start sector in LBA */ + UINT count /* Number of sectors to read */ +) { + const uint8_t dev_addr = pdrv + 1; + const uint8_t lun = 0; - _disk_busy[pdrv] = true; - tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0); - wait_for_disk_io(pdrv); + _disk_busy[pdrv] = true; + tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t)count, disk_io_complete, 0); + wait_for_disk_io(pdrv); - return RES_OK; + return RES_OK; } #if FF_FS_READONLY == 0 -DRESULT disk_write ( - BYTE pdrv, /* Physical drive nmuber to identify the drive */ - const BYTE *buff, /* Data to be written */ - LBA_t sector, /* Start sector in LBA */ - UINT count /* Number of sectors to write */ -) -{ - uint8_t const dev_addr = pdrv + 1; - uint8_t const lun = 0; +DRESULT disk_write(BYTE pdrv, /* Physical drive nmuber to identify the drive */ + const BYTE *buff, /* Data to be written */ + LBA_t sector, /* Start sector in LBA */ + UINT count /* Number of sectors to write */ +) { + const uint8_t dev_addr = pdrv + 1; + const uint8_t lun = 0; - _disk_busy[pdrv] = true; - tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0); - wait_for_disk_io(pdrv); + _disk_busy[pdrv] = true; + tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t)count, disk_io_complete, 0); + wait_for_disk_io(pdrv); - return RES_OK; + return RES_OK; } #endif -DRESULT disk_ioctl ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE cmd, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - uint8_t const dev_addr = pdrv + 1; - uint8_t const lun = 0; - switch ( cmd ) - { +DRESULT disk_ioctl(BYTE pdrv, /* Physical drive nmuber (0..) */ + BYTE cmd, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) { + const uint8_t dev_addr = pdrv + 1; + const uint8_t lun = 0; + switch (cmd) { case CTRL_SYNC: // nothing to do since we do blocking return RES_OK; case GET_SECTOR_COUNT: - *((DWORD*) buff) = (WORD) tuh_msc_get_block_count(dev_addr, lun); + *((DWORD *)buff) = (WORD)tuh_msc_get_block_count(dev_addr, lun); return RES_OK; case GET_SECTOR_SIZE: - *((WORD*) buff) = (WORD) tuh_msc_get_block_size(dev_addr, lun); + *((WORD *)buff) = (WORD)tuh_msc_get_block_size(dev_addr, lun); return RES_OK; case GET_BLOCK_SIZE: - *((DWORD*) buff) = 1; // erase block size in units of sector size + *((DWORD *)buff) = 1; // erase block size in units of sector size return RES_OK; default: return RES_PARERR; } - - return RES_OK; } //--------------------------------------------------------------------+ @@ -300,12 +281,11 @@ void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context); void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context); static void cli_write_char(EmbeddedCli *cli, char c) { - (void) cli; - putchar((int) c); + (void)cli; + putchar((int)c); } -bool cli_init(void) -{ +bool cli_init(void) { EmbeddedCliConfig *config = embeddedCliDefaultConfig(); config->cliBuffer = cli_buffer; config->cliBufferSize = CLI_BUFFER_SIZE; @@ -321,230 +301,173 @@ bool cli_init(void) _cli->writeChar = cli_write_char; - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "cat", - "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..", - true, - NULL, - cli_cmd_cat - }); + embeddedCliAddBinding(_cli, + (CliCommandBinding){"cat", "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..", + true, NULL, cli_cmd_cat}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "cd", - "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.", - true, - NULL, - cli_cmd_cd - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"cd", "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.", + true, NULL, cli_cmd_cd}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "cp", - "Usage: cp SOURCE DEST\r\n\tCopy SOURCE to DEST.", - true, - NULL, - cli_cmd_cp - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"cp", "Usage: cp SOURCE DEST\r\n\tCopy SOURCE to DEST.", true, NULL, + cli_cmd_cp}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "ls", - "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).", - true, - NULL, - cli_cmd_ls - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"ls", + "Usage: ls [DIR]...\r\n\tList information about the FILEs (the " + "current directory by default).", + true, NULL, cli_cmd_ls}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "pwd", - "Usage: pwd\r\n\tPrint the name of the current working directory.", - true, - NULL, - cli_cmd_pwd - }); + embeddedCliAddBinding(_cli, + (CliCommandBinding){"pwd", "Usage: pwd\r\n\tPrint the name of the current working directory.", + true, NULL, cli_cmd_pwd}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "mkdir", - "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..", - true, - NULL, - cli_cmd_mkdir - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"mkdir", + "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not " + "already exist..", + true, NULL, cli_cmd_mkdir}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "mv", - "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST.", - true, - NULL, - cli_cmd_mv - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"mv", "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST.", true, + NULL, cli_cmd_mv}); - embeddedCliAddBinding(_cli, (CliCommandBinding) { - "rm", - "Usage: rm [FILE]...\r\n\tRemove (unlink) the FILE(s).", - true, - NULL, - cli_cmd_rm - }); + embeddedCliAddBinding(_cli, (CliCommandBinding){"rm", "Usage: rm [FILE]...\r\n\tRemove (unlink) the FILE(s).", true, + NULL, cli_cmd_rm}); return true; } -void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); // need at least 1 argument - if ( argc == 0 ) - { + if (argc == 0) { printf("invalid arguments\r\n"); return; } - for(uint16_t i=0; i<argc; i++) - { - FIL fi; - const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1 + for (uint16_t i = 0; i < argc; i++) { + FIL *fi = &file1; + const char *fpath = embeddedCliGetToken(args, i + 1); // token count from 1 - if ( FR_OK != f_open(&fi, fpath, FA_READ) ) - { + if (FR_OK != f_open(fi, fpath, FA_READ)) { printf("%s: No such file or directory\r\n", fpath); - }else - { - uint8_t buf[512]; + } else { UINT count = 0; - while ( (FR_OK == f_read(&fi, buf, sizeof(buf), &count)) && (count > 0) ) - { - for(UINT c = 0; c < count; c++) - { - const uint8_t ch = buf[c]; - if (isprint(ch) || iscntrl(ch)) - { + while ((FR_OK == f_read(fi, rw_buf, sizeof(rw_buf), &count)) && (count > 0)) { + for (UINT c = 0; c < count; c++) { + const uint8_t ch = rw_buf[c]; + if (isprint(ch) || iscntrl(ch)) { putchar(ch); - }else - { + } else { putchar('.'); } } } } - f_close(&fi); + f_close(fi); } } -void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); // only support 1 argument - if ( argc != 1 ) - { + if (argc != 1) { printf("invalid arguments\r\n"); return; } // default is current directory - const char* dpath = args; + const char *dpath = args; - if ( FR_OK != f_chdir(dpath) ) - { + if (FR_OK != f_chdir(dpath)) { printf("%s: No such file or directory\r\n", dpath); return; } } -void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); - if ( argc != 2 ) - { + if (argc != 2) { printf("invalid arguments\r\n"); return; } // default is current directory - const char* src = embeddedCliGetToken(args, 1); - const char* dst = embeddedCliGetToken(args, 2); + const char *src = embeddedCliGetToken(args, 1); + const char *dst = embeddedCliGetToken(args, 2); - FIL f_src; - FIL f_dst; + FIL *f_src = &file1; + FIL *f_dst = &file2; - if ( FR_OK != f_open(&f_src, src, FA_READ) ) - { + if (FR_OK != f_open(f_src, src, FA_READ)) { printf("cannot stat '%s': No such file or directory\r\n", src); return; } - if ( FR_OK != f_open(&f_dst, dst, FA_WRITE | FA_CREATE_ALWAYS) ) - { + if (FR_OK != f_open(f_dst, dst, FA_WRITE | FA_CREATE_ALWAYS)) { printf("cannot create '%s'\r\n", dst); return; - }else - { - uint8_t buf[512]; + } else { UINT rd_count = 0; - while ( (FR_OK == f_read(&f_src, buf, sizeof(buf), &rd_count)) && (rd_count > 0) ) - { + while ((FR_OK == f_read(f_src, rw_buf, sizeof(rw_buf), &rd_count)) && (rd_count > 0)) { UINT wr_count = 0; - if ( FR_OK != f_write(&f_dst, buf, rd_count, &wr_count) ) - { + if (FR_OK != f_write(f_dst, rw_buf, rd_count, &wr_count)) { printf("cannot write to '%s'\r\n", dst); break; } } } - f_close(&f_src); - f_close(&f_dst); + f_close(f_src); + f_close(f_dst); } -void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); // only support 1 argument - if ( argc > 1 ) - { + if (argc > 1) { printf("invalid arguments\r\n"); return; } // default is current directory - const char* dpath = "."; - if (argc) dpath = args; + const char *dpath = "."; + if (argc) { + dpath = args; + } DIR dir; - if ( FR_OK != f_opendir(&dir, dpath) ) - { + if (FR_OK != f_opendir(&dir, dpath)) { printf("cannot access '%s': No such file or directory\r\n", dpath); return; } FILINFO fno; - while( (f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0) ) - { - if ( fno.fname[0] != '.' ) // ignore . and .. entry + while ((f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0)) { + if (fno.fname[0] != '.') // ignore . and .. entry { - if ( fno.fattrib & AM_DIR ) - { + if (fno.fattrib & AM_DIR) { // directory printf("/%s\r\n", fno.fname); - }else - { + } else { printf("%-40s", fno.fname); - if (fno.fsize < 1024) - { + if (fno.fsize < 1024) { printf("%" PRIu32 " B\r\n", fno.fsize); - }else - { + } else { printf("%" PRIu32 " KB\r\n", fno.fsize / 1024); } } @@ -554,90 +477,81 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context) f_closedir(&dir); } -void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); - if (argc != 0) - { + if (argc != 0) { printf("invalid arguments\r\n"); return; } char path[256]; - if (FR_OK != f_getcwd(path, sizeof(path))) - { + if (FR_OK != f_getcwd(path, sizeof(path))) { printf("cannot get current working directory\r\n"); } puts(path); } -void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); // only support 1 argument - if ( argc != 1 ) - { + if (argc != 1) { printf("invalid arguments\r\n"); return; } // default is current directory - const char* dpath = args; + const char *dpath = args; - if ( FR_OK != f_mkdir(dpath) ) - { + if (FR_OK != f_mkdir(dpath)) { printf("%s: cannot create this directory\r\n", dpath); return; } } -void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); - if ( argc != 2 ) - { + if (argc != 2) { printf("invalid arguments\r\n"); return; } // default is current directory - const char* src = embeddedCliGetToken(args, 1); - const char* dst = embeddedCliGetToken(args, 2); + const char *src = embeddedCliGetToken(args, 1); + const char *dst = embeddedCliGetToken(args, 2); - if ( FR_OK != f_rename(src, dst) ) - { + if (FR_OK != f_rename(src, dst)) { printf("cannot mv %s to %s\r\n", src, dst); return; } } -void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context) -{ - (void) cli; (void) context; +void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context) { + (void)cli; + (void)context; uint16_t argc = embeddedCliGetTokenCount(args); // need at least 1 argument - if ( argc == 0 ) - { + if (argc == 0) { printf("invalid arguments\r\n"); return; } - for(uint16_t i=0; i<argc; i++) - { - const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1 + for (uint16_t i = 0; i < argc; i++) { + const char *fpath = embeddedCliGetToken(args, i + 1); // token count from 1 - if ( FR_OK != f_unlink(fpath) ) - { + if (FR_OK != f_unlink(fpath)) { printf("cannot remove '%s': No such file or directory\r\n", fpath); } } diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index de0db4721..f6191bfe8 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -184,7 +184,7 @@ void led_blinking_task(void) static bool led_state = false; // Blink every interval ms - if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + if ( tusb_time_millis_api() - start_ms < blink_interval_ms) return; // not enough time start_ms += blink_interval_ms; board_led_write(led_state); diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json index fabbeed93..ea6317771 100644 --- a/hw/bsp/BoardPresets.json +++ b/hw/bsp/BoardPresets.json @@ -91,6 +91,18 @@ "inherits": "default" }, { + "name": "at_start_f455", + "inherits": "default" + }, + { + "name": "at_start_f456", + "inherits": "default" + }, + { + "name": "at_start_f457", + "inherits": "default" + }, + { "name": "atsamd21_xpro", "inherits": "default" }, @@ -371,10 +383,6 @@ "inherits": "default" }, { - "name": "metro_m7_1011_sd", - "inherits": "default" - }, - { "name": "mimxrt1010_evk", "inherits": "default" }, @@ -1012,6 +1020,21 @@ "configurePreset": "at_start_f437" }, { + "name": "at_start_f455", + "description": "Build preset for the at_start_f455 board", + "configurePreset": "at_start_f455" + }, + { + "name": "at_start_f456", + "description": "Build preset for the at_start_f456 board", + "configurePreset": "at_start_f456" + }, + { + "name": "at_start_f457", + "description": "Build preset for the at_start_f457 board", + "configurePreset": "at_start_f457" + }, + { "name": "atsamd21_xpro", "description": "Build preset for the atsamd21_xpro board", "configurePreset": "atsamd21_xpro" @@ -1407,11 +1430,6 @@ "configurePreset": "metro_m7_1011" }, { - "name": "metro_m7_1011_sd", - "description": "Build preset for the metro_m7_1011_sd board", - "configurePreset": "metro_m7_1011_sd" - }, - { "name": "mimxrt1010_evk", "description": "Build preset for the mimxrt1010_evk board", "configurePreset": "mimxrt1010_evk" @@ -2288,6 +2306,45 @@ ] }, { + "name": "at_start_f455", + "steps": [ + { + "type": "configure", + "name": "at_start_f455" + }, + { + "type": "build", + "name": "at_start_f455" + } + ] + }, + { + "name": "at_start_f456", + "steps": [ + { + "type": "configure", + "name": "at_start_f456" + }, + { + "type": "build", + "name": "at_start_f456" + } + ] + }, + { + "name": "at_start_f457", + "steps": [ + { + "type": "configure", + "name": "at_start_f457" + }, + { + "type": "build", + "name": "at_start_f457" + } + ] + }, + { "name": "atsamd21_xpro", "steps": [ { @@ -3315,19 +3372,6 @@ ] }, { - "name": "metro_m7_1011_sd", - "steps": [ - { - "type": "configure", - "name": "metro_m7_1011_sd" - }, - { - "type": "build", - "name": "metro_m7_1011_sd" - } - ] - }, - { "name": "mimxrt1010_evk", "steps": [ { diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c index a6c2217fe..b7dbcbd98 100644 --- a/hw/bsp/at32f402_405/family.c +++ b/hw/bsp/at32f402_405/family.c @@ -258,7 +258,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { system_ticks++; } - uint32_t board_millis(void) + uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c index dd9b85dc5..d4a7e446d 100644 --- a/hw/bsp/at32f403a_407/family.c +++ b/hw/bsp/at32f403a_407/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c index bdaed523c..adf29e097 100644 --- a/hw/bsp/at32f413/family.c +++ b/hw/bsp/at32f413/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 2fbd4c821..b592bf6c5 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -246,7 +246,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c index f30c6a83f..71cb559dc 100644 --- a/hw/bsp/at32f423/family.c +++ b/hw/bsp/at32f423/family.c @@ -250,7 +250,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index 4ff4c8d6a..7f443509e 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -254,7 +254,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index 01dd429f8..6c6bc4d72 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -320,7 +320,7 @@ volatile uint32_t system_ticks = 0; void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } void SVC_Handler(void) { diff --git a/hw/bsp/at32f45x/family.c b/hw/bsp/at32f45x/family.c index 0593e5115..fa0c1139f 100644 --- a/hw/bsp/at32f45x/family.c +++ b/hw/bsp/at32f45x/family.c @@ -227,7 +227,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 483d9dc28..71c209950 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -161,10 +161,6 @@ void board_putchar(int c) { (void) sys_write(0, (const char*)&c, 1); } -uint32_t tusb_time_millis_api(void) { - return board_millis(); -} - //-------------------------------------------------------------------- // FreeRTOS hooks //-------------------------------------------------------------------- @@ -255,3 +251,53 @@ void vApplicationSetupTimerInterrupt(void) { #endif #endif + +//-------------------------------------------------------------------- +// ThreadX hooks for ARM Cortex-M +//-------------------------------------------------------------------- +#if CFG_TUSB_OS == OPT_OS_THREADX && defined(__ARM_ARCH) + +#include "tx_api.h" +#include "tx_initialize.h" + +// Newlib linker symbol: end of statically allocated RAM (start of heap) +extern ULONG _end; + +// CMSIS standard variable for system clock frequency +extern uint32_t SystemCoreClock; + +// Cortex-M SysTick registers (fixed addresses on all Cortex-M) +#define _TX_SYST_CSR (*((volatile uint32_t *)0xE000E010U)) +#define _TX_SYST_RVR (*((volatile uint32_t *)0xE000E014U)) +#define _TX_SYST_CVR (*((volatile uint32_t *)0xE000E018U)) +// SCB->SHP[10] = PendSV priority, [11] = SysTick priority (byte access at SCB base + 0xD22) +#define _TX_SCB_SHPR3 (*((volatile uint32_t *)0xE000ED20U)) + +VOID _tx_initialize_low_level(VOID) { + // Set the first available memory address for tx_application_define + _tx_initialize_unused_memory = (VOID *)(&_end); + + // Configure SysTick for ThreadX tick rate: enable with processor clock + interrupt + _TX_SYST_RVR = (SystemCoreClock / TX_TIMER_TICKS_PER_SECOND) - 1u; + _TX_SYST_CVR = 0u; + _TX_SYST_CSR = 0x07u; // CLKSOURCE=1, TICKINT=1, ENABLE=1 + + // SHPR3 bits[31:24] = SysTick priority, bits[23:16] = PendSV priority + // PendSV must be lowest priority (0xFF). SysTick must be higher than PendSV (0x40) + // so SysTick can preempt the PendSV scheduler idle loop (__tx_ts_wait) to tick the timer. + _TX_SCB_SHPR3 = (_TX_SCB_SHPR3 & 0x0000FFFFU) | 0x40FF0000U; +} + +// Weak callback for board-specific SysTick work (e.g. HAL_IncTick on STM32) +void osal_threadx_tick_cb(void); +TU_ATTR_WEAK void osal_threadx_tick_cb(void) { } + +// SysTick drives the ThreadX timer tick +extern void _tx_timer_interrupt(void); +void SysTick_Handler(void); +void SysTick_Handler(void) { + osal_threadx_tick_cb(); + _tx_timer_interrupt(); +} + +#endif diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index 606ac484f..4487871eb 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -98,43 +98,6 @@ int board_uart_read(uint8_t *buf, int len); // Send characters to UART. Return number of sent bytes int board_uart_write(void const *buf, int len); -#if CFG_TUSB_OS == OPT_OS_NONE -// Get current milliseconds, must be implemented when no RTOS is used -uint32_t board_millis(void); - -#elif CFG_TUSB_OS == OPT_OS_FREERTOS -static inline uint32_t board_millis(void) { - return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ ); -} - -#elif CFG_TUSB_OS == OPT_OS_MYNEWT -static inline uint32_t board_millis(void) { - return os_time_ticks_to_ms32( os_time_get() ); -} - -#elif CFG_TUSB_OS == OPT_OS_PICO -#include "pico/time.h" -static inline uint32_t board_millis(void) { - return to_ms_since_boot(get_absolute_time()); -} - -#elif CFG_TUSB_OS == OPT_OS_RTTHREAD -static inline uint32_t board_millis(void) { - return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND); -} - -#elif CFG_TUSB_OS == OPT_OS_CUSTOM -// Implement your own board_millis() in any of .c file -uint32_t board_millis(void); - -#elif CFG_TUSB_OS == OPT_OS_ZEPHYR -static inline uint32_t board_millis(void) { - return k_uptime_get_32(); -} -#else - #error "board_millis() is not implemented for this OS" -#endif - //--------------------------------------------------------------------+ // Helper functions //--------------------------------------------------------------------+ @@ -175,8 +138,8 @@ static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars // TODO remove static inline void board_delay(uint32_t ms) { - uint32_t start_ms = board_millis(); - while ( board_millis() - start_ms < ms ) { + uint32_t start_ms = tusb_time_millis_api(); + while ( tusb_time_millis_api() - start_ms < ms ) { // take chance to run usb background #if CFG_TUD_ENABLED tud_task(); diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c index f8f3b0b70..399397bb4 100644 --- a/hw/bsp/broadcom_32bit/family.c +++ b/hw/bsp/broadcom_32bit/family.c @@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) { SYSTMR->CS_b.M1 = 1; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c index f8f3b0b70..399397bb4 100644 --- a/hw/bsp/broadcom_64bit/family.c +++ b/hw/bsp/broadcom_64bit/family.c @@ -146,7 +146,7 @@ void TIMER_1_IRQHandler(void) { SYSTMR->CS_b.M1 = 1; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 15ff4b8ee..ff24cfe89 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -234,7 +234,7 @@ int board_uart_write(void const *buf, int len) } // Get current milliseconds -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { uint32_t safe_ms; diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c index 7eae62fa4..dd84b7c77 100644 --- a/hw/bsp/ch32f20x/family.c +++ b/hw/bsp/ch32f20x/family.c @@ -101,7 +101,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c index dfc041462..344dcaf0b 100644 --- a/hw/bsp/ch32v10x/family.c +++ b/hw/bsp/ch32v10x/family.c @@ -61,7 +61,7 @@ static uint32_t SysTick_Config(uint32_t ticks) { return 0; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 690acee1e..4c22450f9 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -85,7 +85,7 @@ static uint32_t SysTick_Config(uint32_t ticks) { return 0; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/ch32v30x/family.c b/hw/bsp/ch32v30x/family.c index c694f1a08..6295f7723 100644 --- a/hw/bsp/ch32v30x/family.c +++ b/hw/bsp/ch32v30x/family.c @@ -144,7 +144,7 @@ __attribute__((interrupt)) void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/cxd56/family.c b/hw/bsp/cxd56/family.c index a8e2fd52b..fd92bb9d9 100644 --- a/hw/bsp/cxd56/family.c +++ b/hw/bsp/cxd56/family.c @@ -96,7 +96,7 @@ int board_uart_write(void const *buf, int len) } // Get current milliseconds -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { struct timespec tp; diff --git a/hw/bsp/da1469x/family.c b/hw/bsp/da1469x/family.c index a64ffce67..a4f7f2e8d 100644 --- a/hw/bsp/da1469x/family.c +++ b/hw/bsp/da1469x/family.c @@ -140,7 +140,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/efm32/family.c b/hw/bsp/efm32/family.c index 39166bc4d..d318e20d6 100644 --- a/hw/bsp/efm32/family.c +++ b/hw/bsp/efm32/family.c @@ -689,7 +689,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake index fe4db4fc1..455ca90a1 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32p4") +list(APPEND SDKCONFIG_DEFAULTS "${CMAKE_CURRENT_LIST_DIR}/sdkconfig.defaults") diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults new file mode 100644 index 000000000..6b0a548f6 --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y +CONFIG_ESP32P4_REV_MIN_1=y diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index a837417f4..04d8a4001 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -50,7 +50,7 @@ static void max3421_init(void); #endif #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32H4, OPT_MCU_ESP32P4) -static bool usb_init(void); +static bool usb_init(uint8_t rhport, bool is_host); #endif //--------------------------------------------------------------------+ @@ -90,8 +90,14 @@ void board_init(void) { gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT); gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY); -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) - usb_init(); +#if CONFIG_USB_OTG_SUPPORTED + #if CFG_TUD_ENABLED + usb_init(BOARD_TUD_RHPORT, false); + #endif + + #if CFG_TUH_ENABLED + usb_init(BOARD_TUH_RHPORT, true); + #endif #endif #ifdef HIL_TS3USB30_MODE_PIN @@ -179,24 +185,30 @@ void board_reset_to_bootloader(void) { static usb_phy_handle_t phy_hdl; -bool usb_init(void) { +bool usb_init(uint8_t rhport, bool is_host) { + (void) rhport; // Configure USB PHY usb_phy_config_t phy_conf = { .controller = USB_PHY_CTRL_OTG, +#if defined(CONFIG_SOC_USB_UTMI_PHY_NUM) && CONFIG_SOC_USB_UTMI_PHY_NUM > 0 + .target = USB_PHY_TARGET_UTMI, +#else .target = USB_PHY_TARGET_INT, +#endif // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver -#if CFG_TUD_ENABLED - .otg_mode = USB_OTG_MODE_DEVICE, -#elif CFG_TUH_ENABLED - .otg_mode = USB_OTG_MODE_HOST, -#endif + .otg_mode = is_host ? USB_OTG_MODE_HOST : USB_OTG_MODE_DEVICE, // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322 // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS .otg_speed = USB_PHY_SPEED_UNDEFINED, }; - usb_new_phy(&phy_conf, &phy_hdl); + esp_err_t const err = usb_new_phy(&phy_conf, &phy_hdl); + if (err != ESP_OK) { + printf("usb_new_phy failed: %s\r\n", esp_err_to_name(err)); + phy_hdl = NULL; + return false; + } return true; } @@ -351,5 +363,4 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact)); return true; } - #endif diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c index 9e864363f..1e71333d4 100644 --- a/hw/bsp/f1c100s/family.c +++ b/hw/bsp/f1c100s/family.c @@ -79,7 +79,7 @@ int board_uart_write(void const* buf, int len) { #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 699afda92..5d21b4f79 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -105,6 +105,12 @@ set(WARN_FLAGS_GNU ) set(WARN_FLAGS_Clang ${WARN_FLAGS_GNU}) +set(WARN_FLAGS_IAR + --warnings_are_errors + --diag_suppress=Pa089 + --diag_suppress=Pe236 + ) + # Optimization if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "") set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE) @@ -238,7 +244,7 @@ function(family_add_bloaty TARGET) COMMAND ${BLOATY_EXE} ${OPTION_LIST} $<TARGET_FILE:${TARGET}> VERBATIM) - set_property(TARGET ${TARGET}-bloaty PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-bloaty PROPERTY FOLDER ${TARGET}-group) # post build # add_custom_command(TARGET ${TARGET} POST_BUILD # COMMAND ${BLOATY_EXE} --csv ${OPTION_LIST} $<TARGET_FILE:${TARGET}> > ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}_bloaty.csv @@ -259,7 +265,7 @@ function(family_add_linkermap TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-linkermap PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-linkermap PROPERTY FOLDER ${TARGET}-group) # post build add_custom_command(TARGET ${TARGET} POST_BUILD @@ -339,7 +345,7 @@ echo \"$MEMBROWSE_CMD\"") COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=0 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\"" VERBATIM ) - set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET}-group) add_custom_target(${TARGET}-membrowse-upload COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=1 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\"" @@ -351,7 +357,7 @@ echo \"$MEMBROWSE_CMD\"") endif () add_dependencies(examples-membrowse-upload ${TARGET}-membrowse-upload) - set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET}-group) endif () endfunction() @@ -380,6 +386,26 @@ function(family_add_rtos TARGET RTOS) target_link_libraries(${TARGET} PUBLIC freertos_kernel) target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS) + elseif (RTOS STREQUAL "threadx") + if (NOT TARGET threadx) + # Derive THREADX_ARCH from CMAKE_SYSTEM_CPU if not explicitly set + if (NOT DEFINED THREADX_ARCH) + string(REPLACE "-" "_" THREADX_ARCH ${CMAKE_SYSTEM_CPU}) + endif () + # Derive THREADX_TOOLCHAIN from TOOLCHAIN if not explicitly set + if (NOT DEFINED THREADX_TOOLCHAIN) + if (TOOLCHAIN STREQUAL "iar") + set(THREADX_TOOLCHAIN "iar") + elseif (TOOLCHAIN STREQUAL "clang") + set(THREADX_TOOLCHAIN "ac6") + else () + set(THREADX_TOOLCHAIN "gnu") + endif () + endif () + add_subdirectory(${TOP}/lib/threadx ${CMAKE_BINARY_DIR}/lib/threadx) + endif () + target_link_libraries(${TARGET} PUBLIC threadx) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_THREADX) elseif (RTOS STREQUAL "zephyr") target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) @@ -447,6 +473,7 @@ function(family_configure_common TARGET RTOS) target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_compile_options(${TARGET} PRIVATE $<$<OR:$<COMPILE_LANGUAGE:C>,$<COMPILE_LANGUAGE:CXX>>:${WARN_FLAGS_IAR}>) target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map") if (IAR_CSTAT) @@ -602,7 +629,7 @@ exit" VERBATIM ) - set_property(TARGET ${NAME_TARGET}-jlink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${NAME_TARGET}-jlink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -617,7 +644,7 @@ function(family_flash_stlink TARGET) COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $<TARGET_FILE:${TARGET}> --go ) - set_property(TARGET ${TARGET}-stlink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-stlink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -632,7 +659,7 @@ function(family_flash_stflash TARGET) COMMAND ${ST_FLASH} write $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin 0x8000000 ) - set_property(TARGET ${TARGET}-stflash PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-stflash PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -660,7 +687,7 @@ function(family_flash_openocd TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-openocd PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-openocd PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -723,7 +750,7 @@ function(family_flash_wlink_rs TARGET) COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-wlink-rs PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-wlink-rs PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -738,7 +765,7 @@ function(family_flash_pyocd TARGET) COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-pyocd PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-pyocd PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -748,7 +775,7 @@ function(family_flash_uf2 TARGET FAMILY_ID) DEPENDS ${TARGET} COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} --deploy $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.uf2 ) - set_property(TARGET ${TARGET}-uf2 PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-uf2 PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -764,7 +791,7 @@ function(family_flash_teensy TARGET) COMMAND ${TEENSY_CLI} --mcu=${TEENSY_MCU} -w -s $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex ) - set_property(TARGET ${TARGET}-teensy PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-teensy PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -784,7 +811,7 @@ function(family_flash_nxplink TARGET) COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}> ) - set_property(TARGET ${TARGET}-nxplink PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-nxplink PROPERTY FOLDER ${TARGET}-group) endfunction() @@ -799,7 +826,7 @@ function(family_flash_dfu_util TARGET OPTION) VERBATIM ) - set_property(TARGET ${TARGET}-dfu-util PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-dfu-util PROPERTY FOLDER ${TARGET}-group) endfunction() function(family_flash_msp430flasher TARGET) @@ -816,7 +843,7 @@ function(family_flash_msp430flasher TARGET) ${MSP430FLASHER} -w $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex -z [VCC] ) - set_property(TARGET ${TARGET}-msp430flasher PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-msp430flasher PROPERTY FOLDER ${TARGET}-group) endfunction() function(family_flash_uniflash TARGET) @@ -832,7 +859,7 @@ function(family_flash_uniflash TARGET) VERBATIM ) - set_property(TARGET ${TARGET}-uniflash PROPERTY FOLDER ${TARGET}) + set_property(TARGET ${TARGET}-uniflash PROPERTY FOLDER ${TARGET}-group) endfunction() #---------------------------------- diff --git a/hw/bsp/fomu/family.c b/hw/bsp/fomu/family.c index 9d7977bea..cf04a1f6f 100644 --- a/hw/bsp/fomu/family.c +++ b/hw/bsp/fomu/family.c @@ -117,7 +117,7 @@ int board_uart_write(void const * buf, int len) } #if CFG_TUSB_OS == OPT_OS_NONE -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index 9d15755fc..4c1099317 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -179,7 +179,7 @@ void eclic_mtip_handler(void) { system_ticks++; SysTick_Reload(TIMER_TICKS); } -uint32_t board_millis(void) { return system_ticks; } +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif #ifdef USE_FULL_ASSERT diff --git a/hw/bsp/hpmicro/family.c b/hw/bsp/hpmicro/family.c index ffec2523a..a80a8d913 100644 --- a/hw/bsp/hpmicro/family.c +++ b/hw/bsp/hpmicro/family.c @@ -108,7 +108,7 @@ int board_uart_write(void const *buf, int len) { #if CFG_TUSB_OS == OPT_OS_NONE // Get current milliseconds, must be implemented when no RTOS is used -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return (hpm_csr_get_core_cycle() / clock_get_core_clock_ticks_per_ms()); } diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake index 99681ab12..63b2a120a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1010) set(MCU_VARIANT MIMXRT1011) set(JLINK_DEVICE MIMXRT1011xxx5A) diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk index b845194c2..229b5c18c 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1010 MCU_VARIANT = MIMXRT1011 # LD file with uf2 diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug b/hw/bsp/imxrt/boards/metro_m7_1011/ozone/metro_m7_1011.jdebug index 90f9b77e5..90f9b77e5 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug +++ b/hw/bsp/imxrt/boards/metro_m7_1011/ozone/metro_m7_1011.jdebug diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake deleted file mode 100644 index 99681ab12..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake +++ /dev/null @@ -1,15 +0,0 @@ -set(MCU_VARIANT MIMXRT1011) - -set(JLINK_DEVICE MIMXRT1011xxx5A) -set(PYOCD_TARGET mimxrt1010) -set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) - -function(update_board TARGET) - target_sources(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c - ) - target_compile_definitions(${TARGET} PUBLIC - CPU_MIMXRT1011DAE5A - CFG_EXAMPLE_VIDEO_READONLY - ) -endfunction() diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk deleted file mode 100644 index b845194c2..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk +++ /dev/null @@ -1,17 +0,0 @@ -CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY -MCU_VARIANT = MIMXRT1011 - -# LD file with uf2 -LD_FILE = $(BOARD_PATH)/$(BOARD).ld - -# For flash-jlink target -JLINK_DEVICE = MIMXRT1011xxx5A - -# For flash-pyocd target -PYOCD_TARGET = mimxrt1010 - -# flash using pyocd -flash: flash-uf2 -flash-uf2: $(BUILD)/$(PROJECT).uf2 - @echo copying $< - @$(CP) $< /media/$(USER)/METROM7BOOT diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c deleted file mode 100644 index 1b28b668a..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v11.0 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 13.0.2 -board: MIMXRT1010-EVK - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USBPHY_CLK.outFreq, value: 480 MHz} -settings: -- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} -- {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5'} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} -- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} -- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} -- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = - { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Xbar1); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); - CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); -#endif - /* Disable ADC_ACLK_EN clock gate. */ - CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; - /* Set ADC_ACLK_PODF. */ - CLOCK_SetDiv(kCLOCK_AdcDiv, 11); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); -#endif - /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ - /* Set Pll3 SW clock source to use the USB1 PLL output. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Set safe value of the AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 1); - /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h deleted file mode 100644 index 119fd94bd..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c deleted file mode 100644 index aa38e02dc..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.c +++ /dev/null @@ -1,108 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v13.1 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 13.0.2 -board: MIMXRT1010-EVK -external_user_signals: {} -pin_labels: -- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11} -- {pin_num: '70', pin_signal: GPIO_SD_05} -- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED} -- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON} -- {pin_num: '79', pin_signal: GPIO_13, label: 'USB_OTG1_ID/J9[4]/Q9[2]', identifier: TRACE1} -power_domains: {NVCC_GPIO: '3.3'} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) { - BOARD_InitPins(); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} - - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} - - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT} - - {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13, speed: MHZ_200} - - {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12, speed: MHZ_200} - - {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02, speed: MHZ_200} - - {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11, speed: MHZ_200} - - {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00, speed: MHZ_200} - - {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */ - gpio_pin_config_t USER_LED_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_03 (pin 10) */ - GPIO_PinInit(GPIO1, 3U, &USER_LED_config); - - /* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */ - gpio_pin_config_t USER_BUTTON_config = { - .direction = kGPIO_DigitalInput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_08 (pin 4) */ - GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config); - - IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U); - IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & - (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) - | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) - ); - IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_11_ARM_TRACE3, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_12_ARM_TRACE2, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_13_ARM_TRACE1, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0x10E0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0x10E0U); -} - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h deleted file mode 100644 index 42c256745..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/pin_mux.h +++ /dev/null @@ -1,110 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! @brief Direction type */ -typedef enum _pin_mux_direction -{ - kPIN_MUX_DirectionInput = 0U, /* Input direction */ - kPIN_MUX_DirectionOutput = 1U, /* Output direction */ - kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ -} pin_mux_direction_t; - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */ - -/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ - -/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ - -/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ -#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_TRACE1_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_TRACE1_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_TRACE1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */ -/* Routed pin properties */ -#define BOARD_INITPINS_ADC12_2_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_ADC12_2_SIGNAL arm_trace_clk /*!< Signal name */ - -/* GPIO_11 (number 1), GPIO_11 */ -/* Routed pin properties */ -#define BOARD_INITPINS_GPIO_11_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_GPIO_11_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_GPIO_11_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_AD_00 (number 60), USB_OTG1_PWR */ -/* Routed pin properties */ -#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL ARM /*!< Peripheral name */ -#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL TRACE /*!< Signal name */ -#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */ -/* Routed pin properties */ -#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpiomux_io /*!< Signal name */ -#define BOARD_INITPINS_USER_BUTTON_CHANNEL 8U /*!< Signal channel */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c deleted file mode 100644 index 752a65629..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "evkmimxrt1010_flexspi_nor_config.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const flexspi_nor_config_t qspiflash_config = { - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 16u * 1024u * 1024u, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h deleted file mode 100644 index bb5a64448..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ - -#include <stdint.h> -#include <stdbool.h> -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related definitions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related definitions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld deleted file mode 100644 index 960fc6891..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.ld +++ /dev/null @@ -1,270 +0,0 @@ -/* -** ################################################################### -** Processors: MIMXRT1011CAE4A -** MIMXRT1011DAE5A -** -** Compiler: GNU C Compiler -** Reference manual: IMXRT1010RM Rev.0, 09/2019 -** Version: rev. 1.0, 2019-08-01 -** Build: b210709 -** -** Abstract: -** Linker file for the GNU C Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: [email protected] -** -** ################################################################### -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; -VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; - -/* Specify the memory areas */ -MEMORY -{ - m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00 - m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 - - m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400) - m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 - m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00010000 -} - -/* Define output sections */ -SECTIONS -{ - __NCACHE_REGION_START = ORIGIN(m_data2); - __NCACHE_REGION_SIZE = 0; - - .flash_config : - { - . = ALIGN(4); - __FLASH_BASE = .; - KEEP(* (.boot_hdr.conf)) /* flash config section */ - . = ALIGN(4); - } > m_flash_config - - ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); - - .ivt : AT(ivt_begin) - { - . = ALIGN(4); - KEEP(* (.boot_hdr.ivt)) /* ivt section */ - KEEP(* (.boot_hdr.boot_data)) /* boot section */ - KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ - . = ALIGN(4); - } > m_ivt - - /* The startup code goes first into internal RAM */ - .interrupts : - { - __VECTOR_TABLE = .; - __Vectors = .; - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } > m_interrupts - - /* The program code and other data goes into internal RAM */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) - . = ALIGN(4); - } > m_text - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text - - .ARM : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > m_text - - .ctors : - { - __CTOR_LIST__ = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - } > m_text - - .dtors : - { - __DTOR_LIST__ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - } > m_text - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } > m_text - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text - - __etext = .; /* define a global symbol at end of code */ - __DATA_ROM = .; /* Symbol is used by startup for data initialization */ - - .interrupts_ram : - { - . = ALIGN(4); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += VECTOR_RAM_SIZE; - . = ALIGN(4); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data - - __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); - __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - - .data : AT(__DATA_ROM) - { - . = ALIGN(4); - __DATA_RAM = .; - __data_start__ = .; /* create a global symbol at data start */ - *(m_usb_dma_init_data) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(DataQuickAccess) /* quick access data section */ - KEEP(*(.jcr*)) - . = ALIGN(4); - __data_end__ = .; /* define a global symbol at data end */ - } > m_data - - __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ - - .ram_function : AT(__ram_function_flash_start) - { - . = ALIGN(32); - __ram_function_start__ = .; - *(CodeQuickAccess) - . = ALIGN(128); - __ram_function_end__ = .; - } > m_qacode - - __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(4); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_data - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(4); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_data - - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); - text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") - - /* Uninitialized data section */ - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - . = ALIGN(4); - __START_BSS = .; - __bss_start__ = .; - *(m_usb_dma_noninit_data) - *(.bss) - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - __END_BSS = .; - } > m_data - - .heap : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += HEAP_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data - - .stack : - { - . = ALIGN(8); - . += STACK_SIZE; - } > m_data - - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - .ARM.attributes 0 : { *(.ARM.attributes) } - - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") -} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex b/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex deleted file mode 100644 index 7aab59a68..000000000 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex +++ /dev/null @@ -1,431 +0,0 @@ -<?xml version="1.0" encoding= "UTF-8" ?> -<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> - <common> - <processor>MIMXRT1011xxxxx</processor> - <package>MIMXRT1011DAE5A</package> - <board>MIMXRT1010-EVK</board> - <board_revision>A</board_revision> - <mcu_data>ksdk2_0</mcu_data> - <cores selected="core0"> - <core name="Cortex-M7F" id="core0" description="M7 core"/> - </cores> - <description></description> - </common> - <preferences> - <validate_boot_init_only>true</validate_boot_init_only> - <generate_extended_information>false</generate_extended_information> - <generate_code_modified_registers_only>false</generate_code_modified_registers_only> - <update_include_paths>true</update_include_paths> - <generate_registers_defines>false</generate_registers_defines> - </preferences> - <tools> - <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> - <generated_project_files> - <file path="board/pin_mux.c" update_enabled="true"/> - <file path="board/pin_mux.h" update_enabled="true"/> - </generated_project_files> - <pins_profile> - <processor_version>13.0.2</processor_version> - <pin_labels> - <pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/> - <pin_label pin_num="70" pin_signal="GPIO_SD_05" label=""/> - <pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/> - <pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/> - <pin_label pin_num="79" pin_signal="GPIO_13" label="USB_OTG1_ID/J9[4]/Q9[2]" identifier="TRACE1"/> - </pin_labels> - <external_user_signals> - <properties/> - </external_user_signals> - <power_domains> - <power_domain name="NVCC_GPIO" value="3.3"/> - </power_domains> - </pins_profile> - <functions_list> - <function name="BOARD_InitPins"> - <description>Configures pin routing and optionally pin electrical features.</description> - <options> - <callFromInitBoot>true</callFromInitBoot> - <coreID>core0</coreID> - <enableClock>true</enableClock> - </options> - <dependencies> - <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> - <feature name="initialized" evaluation="equal"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - </dependencies> - <pins> - <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/> - <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/> - <pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03"> - <pin_features> - <pin_feature name="identifier" value="USER_LED"/> - <pin_feature name="direction" value="OUTPUT"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"> - <pin_features> - <pin_feature name="speed" value="MHZ_200"/> - </pin_features> - </pin> - <pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08"> - <pin_features> - <pin_feature name="direction" value="INPUT"/> - <pin_feature name="pull_keeper_select" value="Pull"/> - <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> - </pin_features> - </pin> - </pins> - </function> - </functions_list> - </pins> - <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> - <generated_project_files> - <file path="board/clock_config.c" update_enabled="true"/> - <file path="board/clock_config.h" update_enabled="true"/> - </generated_project_files> - <clocks_profile> - <processor_version>13.0.2</processor_version> - </clocks_profile> - <clock_configurations> - <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> - <description></description> - <options/> - <dependencies> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>INPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>OUTPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>INPUT</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="routed" evaluation=""> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> - <feature name="direction" evaluation=""> - <data>OUTPUT</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> - <feature name="enabled" evaluation="equal" configuration="core0"> - <data>true</data> - </feature> - </dependency> - </dependencies> - <clock_sources> - <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> - </clock_sources> - <clock_outputs> - <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/> - <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> - <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> - <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> - <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> - <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> - <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> - <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> - <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> - <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> - <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> - <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> - <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> - <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> - <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> - </clock_outputs> - <clock_settings> - <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/> - <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> - <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> - <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> - <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/> - <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> - <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/> - <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> - <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> - <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> - <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/> - <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/> - <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> - <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> - <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> - <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> - <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> - </clock_settings> - <called_from_default_init>true</called_from_default_init> - </clock_configuration> - </clock_configurations> - </clocks> - <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <dcdx_profile> - <processor_version>0.0.0</processor_version> - </dcdx_profile> - <dcdx_configurations/> - </dcdx> - <periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <peripherals_profile> - <processor_version>13.0.2</processor_version> - </peripherals_profile> - <functional_groups> - <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0"> - <description></description> - <options/> - <dependencies/> - <instances> - <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="main" quick_selection="qs_interrupt"> - <setting name="clockSource" value="Lpi2cClock"/> - <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/> - </config_set> - <config_set name="interrupt_vector"/> - <config_set name="master" quick_selection="qs_master_transfer"> - <setting name="mode" value="transfer"/> - <struct name="config"> - <setting name="enableMaster" value="true"/> - <setting name="enableDoze" value="true"/> - <setting name="debugEnable" value="false"/> - <setting name="ignoreAck" value="false"/> - <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> - <setting name="baudRate_Hz" value="100000"/> - <setting name="busIdleTimeout_ns" value="0"/> - <setting name="pinLowTimeout_ns" value="0"/> - <setting name="sdaGlitchFilterWidth_ns" value="0"/> - <setting name="sclGlitchFilterWidth_ns" value="0"/> - <struct name="hostRequest"> - <setting name="enable" value="false"/> - <setting name="source" value="kLPI2C_HostRequestExternalPin"/> - <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> - </struct> - <set name="edmaRequestSources"> - <selected/> - </set> - </struct> - <struct name="transfer"> - <setting name="blocking" value="false"/> - <setting name="enable_custom_handle" value="false"/> - <struct name="callback"> - <setting name="name" value=""/> - <setting name="userData" value=""/> - </struct> - <set name="flags"> - <selected/> - </set> - <setting name="slaveAddress" value="0"/> - <setting name="direction" value="kLPI2C_Write"/> - <setting name="subaddress" value="0"/> - <setting name="subaddressSize" value="1"/> - <setting name="blocking_buffer" value="false"/> - <setting name="enable_custom_buffer" value="false"/> - <setting name="dataSize" value="1"/> - </struct> - </config_set> - </instance> - <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> - <struct name="lpuartConfig"> - <setting name="clockSource" value="LpuartClock"/> - <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> - <setting name="baudRate_Bps" value="115200"/> - <setting name="parityMode" value="kLPUART_ParityDisabled"/> - <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> - <setting name="isMsb" value="false"/> - <setting name="stopBitCount" value="kLPUART_OneStopBit"/> - <setting name="enableMatchAddress1" value="false"/> - <setting name="matchAddress1" value="0"/> - <setting name="enableMatchAddress2" value="false"/> - <setting name="matchAddress2" value="0"/> - <setting name="txFifoWatermark" value="0"/> - <setting name="rxFifoWatermark" value="1"/> - <setting name="enableRxRTS" value="false"/> - <setting name="enableTxCTS" value="false"/> - <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> - <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> - <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> - <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> - <setting name="enableTx" value="true"/> - <setting name="enableRx" value="true"/> - </struct> - </config_set> - </instance> - <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="fsl_gpio"> - <setting name="enable_irq_comb_0_15" value="false"/> - <struct name="gpio_interrupt_comb_0_15"> - <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - </config_set> - </instance> - <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> - <config_set name="fsl_gpio"> - <setting name="enable_irq_comb_0_15" value="false"/> - <struct name="gpio_interrupt_comb_0_15"> - <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - <setting name="enable_irq_comb_16_31" value="false"/> - <struct name="gpio_interrupt_comb_16_31"> - <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/> - <setting name="enable_interrrupt" value="enabled"/> - <setting name="enable_priority" value="false"/> - <setting name="priority" value="0"/> - <setting name="enable_custom_name" value="false"/> - </struct> - </config_set> - </instance> - <instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> - <config_set name="nvic"> - <array name="interrupt_table"/> - <array name="interrupts"/> - </config_set> - </instance> - </instances> - </functional_group> - </functional_groups> - <components> - <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system"> - <config_set_global name="global_system_definitions"> - <setting name="user_definitions" value=""/> - <setting name="user_includes" value=""/> - </config_set_global> - </component> - <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg"> - <config_set_global name="global_messages"/> - </component> - <component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> - <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> - </component> - <component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> - <config_set_global name="global_uart"/> - </component> - <component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> - <config_set_global name="global_can"/> - </component> - <component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> - <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> - </component> - <component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> - <config_set_global name="global_enet"/> - </component> - </components> - </periphs> - <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> - <generated_project_files/> - <tee_profile> - <processor_version>0.0.0</processor_version> - </tee_profile> - </tee> - </tools> -</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index 99681ab12..63b2a120a 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1010) set(MCU_VARIANT MIMXRT1011) set(JLINK_DEVICE MIMXRT1011xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk index 488a56fdc..c5521faf5 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1010 MCU_VARIANT = MIMXRT1011 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake index becad46d4..5661bb3e6 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1015) set(MCU_VARIANT MIMXRT1015) set(JLINK_DEVICE MIMXRT1015DAF5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk index 20c697ea1..062929902 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY +MCU_FAMILY = RT1015 MCU_VARIANT = MIMXRT1015 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake index 39c94147c..6b95dfb65 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1020) set(MCU_VARIANT MIMXRT1021) set(JLINK_DEVICE MIMXRT1021xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk index e269c8ac5..b3976b356 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A +MCU_FAMILY = RT1020 MCU_VARIANT = MIMXRT1021 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake index 45487d148..10669b32d 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1020) set(MCU_VARIANT MIMXRT1024) set(JLINK_DEVICE MIMXRT1024xxx5A) diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk index 3c325cc93..83448c399 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1024DAG5A +MCU_FAMILY = RT1020 MCU_VARIANT = MIMXRT1024 # warnings caused by mcu driver diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake index 1aee75b0d..70050dd16 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1050) set(MCU_VARIANT MIMXRT1052) set(JLINK_DEVICE MIMXRT1052xxxxB) diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk index 60aa1e28f..9331eba94 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1052DVL6B +MCU_FAMILY = RT1050 MCU_VARIANT = MIMXRT1052 JLINK_DEVICE = MIMXRT1052xxxxB diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake index f70a5f923..865695894 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk index 0317ee452..79d15880b 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake index cd75c5227..b23fee3c4 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1064) set(MCU_VARIANT MIMXRT1064) set(JLINK_DEVICE MIMXRT1064xxx6A) diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk index ddde419ae..3a65a3d89 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1064DVL6A +MCU_FAMILY = RT1064 MCU_VARIANT = MIMXRT1064 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake index d5629f8ba..dc3b8ed44 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake @@ -1,9 +1,10 @@ +set(MCU_FAMILY RT1170) set(MCU_VARIANT MIMXRT1176) if (M4 STREQUAL "1") set(MCU_CORE _cm4) set(JLINK_CORE _M4) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) + set(LD_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") else () set(MCU_CORE _cm7) diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk index 8270ae587..3f07e28fc 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk @@ -1,3 +1,4 @@ +MCU_FAMILY = RT1170 MCU_VARIANT = MIMXRT1176 ifeq ($(M4), 1) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.cmake b/hw/bsp/imxrt/boards/teensy_40/board.cmake index 41fdc78f5..55dd29897 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.cmake +++ b/hw/bsp/imxrt/boards/teensy_40/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk index 45ca0fb6e..e7f75fcae 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.mk +++ b/hw/bsp/imxrt/boards/teensy_40/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/teensy_41/board.cmake b/hw/bsp/imxrt/boards/teensy_41/board.cmake index 0fd8d528e..e8398fdbe 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.cmake +++ b/hw/bsp/imxrt/boards/teensy_41/board.cmake @@ -1,3 +1,4 @@ +set(MCU_FAMILY RT1060) set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk index 45ca0fb6e..e7f75fcae 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.mk +++ b/hw/bsp/imxrt/boards/teensy_41/board.mk @@ -1,4 +1,5 @@ CFLAGS += -DCPU_MIMXRT1062DVL6A +MCU_FAMILY = RT1060 MCU_VARIANT = MIMXRT1062 # For flash-jlink target diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index d54b41bdb..c1ee34b1a 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -239,7 +239,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index d946b591d..009b15da3 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_CORE ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(MCUX_DEVICES ${TOP}/hw/mcu/nxp/mcux-devices-rt) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -15,19 +16,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") +# XIP boot files: some devices reference RT1052's xip (see each device's xip/CMakeLists.txt) +if (MCU_FAMILY STREQUAL "RT1064") + set(XIP_DIR ${MCUX_DEVICES}/RT1064/MIMXRT1064/xip) +elseif (MCU_FAMILY STREQUAL "RT1170") + set(XIP_DIR ${MCUX_DEVICES}/RT1170/MIMXRT1176/xip) +else() + # RT1010, RT1015, RT1020, RT1050, RT1060 all use RT1052's xip + set(XIP_DIR ${MCUX_DEVICES}/RT1050/MIMXRT1052/xip) +endif() + #------------------------------------ # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) +set(LD_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED LD_FILE_IAR) -set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) +set(LD_FILE_IAR ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) endif () -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) -set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) +set(STARTUP_FILE_GNU ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) +set(STARTUP_FILE_IAR ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) #------------------------------------ @@ -37,23 +48,26 @@ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c - ${SDK_DIR}/drivers/common/fsl_common.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/igpio/fsl_gpio.c - ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c - ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c + # mcuxsdk-core drivers + ${MCUX_CORE}/drivers/common/fsl_common.c + ${MCUX_CORE}/drivers/common/fsl_common_arm.c + ${MCUX_CORE}/drivers/igpio/fsl_gpio.c + ${MCUX_CORE}/drivers/lpspi/fsl_lpspi.c + ${MCUX_CORE}/drivers/lpuart/fsl_lpuart.c + ${MCUX_CORE}/drivers/ocotp/fsl_ocotp.c + # device specific + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c ) - # Optional drivers: only available for some mcus: rt1160, rt1170 - set(OPTIONAL_DRIVER fsl_dcdc.c fsl_pmu.c fsl_anatop_ai.c) - foreach(FILE IN LISTS OPTIONAL_DRIVER) - if(EXISTS ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE}) - target_sources(${BOARD_TARGET} PRIVATE ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE}) - endif() - endforeach() + # Additional drivers in subdirectories (RT1170 power/anatop_ai) + if (MCU_FAMILY STREQUAL "RT1170") + target_sources(${BOARD_TARGET} PRIVATE + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/power/fsl_dcdc.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/power/fsl_pmu.c + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/anatop_ai/fsl_anatop_ai.c + ) + endif() if (NOT M4 STREQUAL "1") target_compile_definitions(${BOARD_TARGET} PUBLIC @@ -66,15 +80,27 @@ function(family_add_board BOARD_TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/igpio - ${SDK_DIR}/drivers/lpspi - ${SDK_DIR}/drivers/lpuart - ${SDK_DIR}/drivers/ocotp + # device specific + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT} + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers + ${MCUX_DEVICES}/${MCU_FAMILY}/periph + # mcuxsdk-core drivers + ${MCUX_CORE}/drivers/common + ${MCUX_CORE}/drivers/igpio + ${MCUX_CORE}/drivers/lpspi + ${MCUX_CORE}/drivers/lpuart + ${MCUX_CORE}/drivers/ocotp ) + # Include power/anatop_ai driver directories if they exist + foreach(SUBDIR power anatop_ai) + if(EXISTS ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/${SUBDIR}) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MCUX_DEVICES}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/${SUBDIR} + ) + endif() + endforeach() + update_board(${BOARD_TARGET}) endfunction() @@ -91,13 +117,14 @@ function(family_configure_example TARGET RTOS) ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c - ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c + ${XIP_DIR}/fsl_flexspi_nor_boot.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ${XIP_DIR} ) target_compile_definitions(${TARGET} PUBLIC __START=main # required with -nostartfiles diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index 42000671d..59735670a 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -1,11 +1,22 @@ UF2_FAMILY_ID = 0x4fb2d5bd -SDK_DIR = hw/mcu/nxp/mcux-sdk +MCUX_CORE = hw/mcu/nxp/mcuxsdk-core +MCUX_DEVICES = hw/mcu/nxp/mcux-devices-rt include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7 MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE} -MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) +MCU_DIR = $(MCUX_DEVICES)/$(MCU_FAMILY)/$(MCU_VARIANT) + +# XIP boot files: some devices reference RT1052's xip (see each device's xip/CMakeLists.txt) +ifeq ($(MCU_FAMILY),RT1064) + XIP_DIR = $(MCUX_DEVICES)/RT1064/MIMXRT1064/xip +else ifeq ($(MCU_FAMILY),RT1170) + XIP_DIR = $(MCUX_DEVICES)/RT1170/MIMXRT1176/xip +else + # RT1010, RT1015, RT1020, RT1050, RT1060 all use RT1052's xip + XIP_DIR = $(MCUX_DEVICES)/RT1050/MIMXRT1052/xip +endif CFLAGS += \ -D__START=main \ @@ -48,32 +59,36 @@ SRC_C += \ ${BOARD_PATH}/board/clock_config.c \ ${BOARD_PATH}/board/pin_mux.c \ $(MCU_DIR)/system_$(MCU_VARIANT_WITH_CORE).c \ - $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \ + $(XIP_DIR)/fsl_flexspi_nor_boot.c \ $(MCU_DIR)/drivers/fsl_clock.c \ - $(SDK_DIR)/drivers/common/fsl_common.c \ - $(SDK_DIR)/drivers/common/fsl_common_arm.c \ - $(SDK_DIR)/drivers/igpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \ - $(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \ + $(MCUX_CORE)/drivers/common/fsl_common.c \ + $(MCUX_CORE)/drivers/common/fsl_common_arm.c \ + $(MCUX_CORE)/drivers/igpio/fsl_gpio.c \ + $(MCUX_CORE)/drivers/lpuart/fsl_lpuart.c \ + $(MCUX_CORE)/drivers/ocotp/fsl_ocotp.c \ -# Optional drivers: only available for some mcus: rt1160, rt1170 -ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c)) +# Optional drivers: RT1170 power/anatop_ai subdirectories +ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/power/fsl_dcdc.c)) SRC_C += \ - ${MCU_DIR}/drivers/fsl_dcdc.c \ - ${MCU_DIR}/drivers/fsl_pmu.c \ - ${MCU_DIR}/drivers/fsl_anatop_ai.c + ${MCU_DIR}/drivers/power/fsl_dcdc.c \ + ${MCU_DIR}/drivers/power/fsl_pmu.c \ + ${MCU_DIR}/drivers/anatop_ai/fsl_anatop_ai.c +INC += \ + $(TOP)/$(MCU_DIR)/drivers/power \ + $(TOP)/$(MCU_DIR)/drivers/anatop_ai endif INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/project_template \ $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/igpio \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(SDK_DIR)/drivers/ocotp \ + $(TOP)/$(MCUX_DEVICES)/$(MCU_FAMILY)/periph \ + $(TOP)/$(MCUX_CORE)/drivers/common \ + $(TOP)/$(MCUX_CORE)/drivers/igpio \ + $(TOP)/$(MCUX_CORE)/drivers/lpuart \ + $(TOP)/$(MCUX_CORE)/drivers/ocotp \ + $(TOP)/$(XIP_DIR) \ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c index 98ef52739..1505defe0 100644 --- a/hw/bsp/kinetis_k/family.c +++ b/hw/bsp/kinetis_k/family.c @@ -143,7 +143,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/kinetis_k32l2/family.c b/hw/bsp/kinetis_k32l2/family.c index 2062b8b18..ec8dc6ecf 100644 --- a/hw/bsp/kinetis_k32l2/family.c +++ b/hw/bsp/kinetis_k32l2/family.c @@ -148,7 +148,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c index c257f4b2b..f89434d06 100644 --- a/hw/bsp/kinetis_kl/family.c +++ b/hw/bsp/kinetis_kl/family.c @@ -142,7 +142,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c index c9f18bd2f..76c2bd17c 100644 --- a/hw/bsp/lpc11/family.c +++ b/hw/bsp/lpc11/family.c @@ -130,7 +130,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc13/family.c b/hw/bsp/lpc13/family.c index e212c6a63..8513f4df4 100644 --- a/hw/bsp/lpc13/family.c +++ b/hw/bsp/lpc13/family.c @@ -83,7 +83,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c index 5f22df175..0d092d3a9 100644 --- a/hw/bsp/lpc15/family.c +++ b/hw/bsp/lpc15/family.c @@ -140,7 +140,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc17/family.c b/hw/bsp/lpc17/family.c index ba59fccca..f398f7e3c 100644 --- a/hw/bsp/lpc17/family.c +++ b/hw/bsp/lpc17/family.c @@ -145,7 +145,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 6c02c711f..2043cef99 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -143,7 +143,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c index 5ea95e9b8..237cd996b 100644 --- a/hw/bsp/lpc40/family.c +++ b/hw/bsp/lpc40/family.c @@ -156,7 +156,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index f440fb119..56834a1b0 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -185,8 +185,10 @@ void board_init(void) */ Chip_USB1_Init(); +#ifdef _BOARD_EA4357_H // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board) Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7); +#endif #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. @@ -257,7 +259,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake index 1f549bf50..6e632d266 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake @@ -7,7 +7,4 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC51U68JBD64 ) - target_link_libraries(${TARGET} PUBLIC - ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower.a - ) endfunction() diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk index 5627cb024..072037e90 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk @@ -1,4 +1,4 @@ -MCU = LPC51U68 +MCU_VARIANT = LPC51U68 CFLAGS += \ -DCPU_LPC51U68JBD64 \ diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c index bec86f87f..847972350 100644 --- a/hw/bsp/lpc51/family.c +++ b/hw/bsp/lpc51/family.c @@ -122,7 +122,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index 1823b64fc..00c6731ae 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -16,41 +17,52 @@ set(FAMILY_MCUS LPC51 CACHE INTERNAL "") # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/${MCU_VARIANT}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/iar/startup_${MCU_VARIANT}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC # driver - ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c - ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c + ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/system_${MCU_VARIANT}.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${TOP}/lib/sct_neopixel # driver - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/flexcomm - ${SDK_DIR}/drivers/lpc_iocon - ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/lpuart + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/flexcomm + ${MCUX_DIR}/drivers/flexcomm/usart + ${MCUX_DIR}/drivers/lpc_iocon + ${MCUX_DIR}/drivers/lpc_gpio # mcu - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/LPC51U68/${MCU_VARIANT} + ${SDK_DIR}/LPC51U68/${MCU_VARIANT}/drivers ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/LPC51U68/periph ) target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk index 91d1261cb..34987d183 100644 --- a/hw/bsp/lpc51/family.mk +++ b/hw/bsp/lpc51/family.mk @@ -1,8 +1,7 @@ -SDK_DIR = hw/mcu/nxp/mcux-sdk - include $(TOP)/$(BOARD_PATH)/board.mk -MCU_DIR = $(SDK_DIR)/devices/$(MCU) CPU_CORE ?= cortex-m0plus +MCUX_DIR = /hw/mcu/nxp/mcuxsdk-core +SDK_DIR = /hw/mcu/nxp/mcux-devices-lpc CFLAGS += \ -flto \ @@ -18,29 +17,28 @@ LDFLAGS_GCC += \ --specs=nosys.specs --specs=nano.specs \ # All source paths should be relative to the top level. -LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld +LD_FILE = $(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/$(MCU_VARIANT)_flash.ld SRC_C += \ src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ - $(MCU_DIR)/system_$(MCU).c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(MCU_DIR)/drivers/fsl_power.c \ - $(MCU_DIR)/drivers/fsl_reset.c \ - $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/system_$(MCU_VARIANT).c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_power.c \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \ INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ - $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ - $(TOP)/$(SDK_DIR)/drivers/lpc_gpio - -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/LPC51U68/periph \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio -LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a +SRC_S += $(TOP)$(SDK_DIR)/LPC51U68/$(MCU_VARIANT)/gcc/startup_$(MCU_VARIANT).S diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake index c0bbeecd5..b306f885a 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake @@ -6,10 +6,8 @@ set(PYOCD_TARGET LPC54114) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld) -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) -endif() +# Only Port 0 Full-Speed +set(RHPORT_DEVICE 0) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h index c43ca9d7d..1158d0675 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 0 #define LED_PIN 29 diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake index f0715fa12..aea608e60 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake @@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54608:LPCXpresso54608) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld) # Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() function(update_board TARGET) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h index e985e97e0..7a5cbea87 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 2 #define LED_PIN 2 @@ -54,6 +66,15 @@ // USB0 VBUS #define USB0_VBUS_PINMUX 0, 22, IOCON_PIO_DIG_FUNC7_EN +// Power switch +#define USBFS_POWER_PORT 4 +#define USBFS_POWER_PIN 7 +#define USBFS_POWER_STATE_ON 0 + +#define USBHS_POWER_PORT 4 +#define USBHS_POWER_PIN 9 +#define USBHS_POWER_STATE_ON 0 + // XTAL //#define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake index 1dea6f353..b0d0d404f 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake @@ -8,8 +8,11 @@ set(NXPLINK_DEVICE LPC54628:LPCXpresso54628) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld) # Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) - set(PORT 1) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() function(update_board TARGET) diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h index 837d26aef..5c858ed99 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h @@ -36,6 +36,18 @@ extern "C" { #endif +// IOCON pin mux +#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function +#define IOCON_PIO_FUNC0 0x00u +#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 +#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 +#define IOCON_PIO_INPFILT_OFF 0x0200u // Input filter disabled +#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted +#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function +#define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled +#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled + // LED #define LED_PORT 2 #define LED_PIN 2 diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 7bb73afbc..806bd53dc 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -41,18 +41,6 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -// IOCON pin mux -#define IOCON_PIO_DIGITAL_EN 0x80u // Enables digital function -#define IOCON_PIO_FUNC0 0x00u -#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 -#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 -#define IOCON_PIO_INPFILT_OFF 0x0100u // Input filter disabled -#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted -#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function -#define IOCON_PIO_MODE_PULLUP 0x10u -#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled -#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled - // Digital pin function n enabled #define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0) #define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1) @@ -149,37 +137,71 @@ void board_init(void) { USART_Init(UART_DEV, &uart_config, 12000000); #endif - // USB - IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); - #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports - #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 + #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) + /* PORT0 PIN22 configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); + // Port0 is Full Speed POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); - /*According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */ - USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */ + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) { + /*According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */ + USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK; + CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */ + + CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + } else { + #ifdef USBFS_POWER_PORT + /* Configure USB0 Power Switch Pin */ + IOCON_PinMuxSet(IOCON, USBFS_POWER_PORT, USBFS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN); - CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBFS_POWER_STATE_ON}; + GPIO_PinInit(GPIO, USBFS_POWER_PORT, USBFS_POWER_PIN, &power_pin_config); + #endif + CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); + USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK; + } #endif - #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 - // Port1 is High Speed - POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); + #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1) + // Port1 is High Speed + + /* Turn on USB1 Phy */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); - /*According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ + /* reset the IP to make sure it's in reset state. */ + RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); + + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) { + /* According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock + + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + /* enable USB Device clock */ CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U); + } else { + #ifdef USBHS_POWER_PORT + /* Configure USB1 Power Switch Pin */ + IOCON_PinMuxSet(IOCON, USBHS_POWER_PORT, USBHS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN); + + gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBHS_POWER_STATE_ON}; + GPIO_PinInit(GPIO, USBHS_POWER_PORT, USBHS_POWER_PIN, &power_pin_config); + #endif + CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 0U); + } #endif #else + IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX); // LPC5411x series only has full speed device POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */ @@ -217,7 +239,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index c6145bd41..ebc0689fd 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -12,13 +12,29 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS LPC54 CACHE INTERNAL "") -if (NOT DEFINED PORT) - set(PORT 0) -endif() +# ---------------------- +# Port & Speed Selection +# ---------------------- -# Host port will be the other port if available -set(HOST_PORT $<NOT:${PORT}>) +# default device port to USB1 highspeed, host to USB0 fullspeed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +# port 0 is fullspeed, port 1 is highspeed +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) #------------------------------------ # Startup & Linker script #------------------------------------ @@ -26,11 +42,20 @@ if (NOT DEFINED LD_FILE_GNU) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ @@ -64,24 +89,23 @@ function(family_add_board BOARD_TARGET) ) target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\) - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} __STARTUP_CLEAR_BSS ) - # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM - if (PORT EQUAL 1) + # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM + if (RHPORT_DEVICE EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED - CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=] ) - else () + endif () + if (RHPORT_HOST EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED - CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) - #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=] + CFG_TUH_USBIP_IP3516=1 ) endif () @@ -107,11 +131,23 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) + if (RHPORT_HOST EQUAL 0) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/ohci/ohci.c + ) + elseif (RHPORT_HOST EQUAL 1) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c + ) + endif () + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs -nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -120,6 +156,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/lpc54/iar/LPC54608_flash.icf b/hw/bsp/lpc54/iar/LPC54608_flash.icf new file mode 100644 index 000000000..408ab90ed --- /dev/null +++ b/hw/bsp/lpc54/iar/LPC54608_flash.icf @@ -0,0 +1,84 @@ +/* +** ################################################################### +** Processors: LPC54608J512BD208 +** LPC54608J512ET180 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b241125 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20027FFF; + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40101FFF; + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/hw/bsp/lpc54/iar/LPC54628_flash.icf b/hw/bsp/lpc54/iar/LPC54628_flash.icf new file mode 100644 index 000000000..cc6615bd6 --- /dev/null +++ b/hw/bsp/lpc54/iar/LPC54628_flash.icf @@ -0,0 +1,82 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b241125 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: [email protected] +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20027FFF; + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40101FFF; + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/hw/bsp/lpc54/iar/startup_LPC54608.s b/hw/bsp/lpc54/iar/startup_LPC54608.s new file mode 100644 index 000000000..05c4350e5 --- /dev/null +++ b/hw/bsp/lpc54/iar/startup_LPC54608.s @@ -0,0 +1,654 @@ +; ------------------------------------------------------------------------- +; @file: startup_LPC54608.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; LPC54608 +; @version: 2.0 +; @date: 2024-10-29 +; @build: b250521 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2025 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0xFFFFFFFF ;ECRP + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ;DMA controller + DCD GINT0_IRQHandler ;GPIO group 0 + DCD GINT1_IRQHandler ;GPIO group 1 + DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ;Micro-tick Timer + DCD MRT0_IRQHandler ;Multi-rate timer + DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ;SCTimer/PWM + DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ;USB device + DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD Reserved47_IRQHandler ;Reserved interrupt + DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ;Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ;SPI flash interface + DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ;SD/MMC + DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1 + DCD USB1_IRQHandler ;USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ;USB1 activity + DCD ETHERNET_IRQHandler ;Ethernet + DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt + DCD EEPROM_IRQHandler ;EEPROM interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD SHA_IRQHandler ;SHA interrupt + DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + MOVS r0,#56 + LDR r1, =0x40000220 + STR r0, [r1] ;Enable SRAM clock used by Stack + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END diff --git a/hw/bsp/lpc54/iar/startup_LPC54628.s b/hw/bsp/lpc54/iar/startup_LPC54628.s new file mode 100644 index 000000000..fec5f7fca --- /dev/null +++ b/hw/bsp/lpc54/iar/startup_LPC54628.s @@ -0,0 +1,654 @@ +; ------------------------------------------------------------------------- +; @file: startup_LPC54628.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; LPC54628 +; @version: 2.0 +; @date: 2024-10-29 +; @build: b250521 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2025 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0xFFFFFFFF ;ECRP + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD WDT_BOD_IRQHandler ;Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ;DMA controller + DCD GINT0_IRQHandler ;GPIO group 0 + DCD GINT1_IRQHandler ;GPIO group 1 + DCD PIN_INT0_IRQHandler ;Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ;Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ;Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ;Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ;Micro-tick Timer + DCD MRT0_IRQHandler ;Multi-rate timer + DCD CTIMER0_IRQHandler ;Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ;Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ;SCTimer/PWM + DCD CTIMER3_IRQHandler ;Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ;ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ;ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ;ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ;Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ;Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ;USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ;USB device + DCD RTC_IRQHandler ;RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD Reserved47_IRQHandler ;Reserved interrupt + DCD PIN_INT4_IRQHandler ;Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ;Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ;Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ;Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ;Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ;Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ;Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ;SPI flash interface + DCD FLEXCOMM8_IRQHandler ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ;SD/MMC + DCD CAN0_IRQ0_IRQHandler ;CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ;CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ;CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ;CAN1 interrupt1 + DCD USB1_IRQHandler ;USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ;USB1 activity + DCD ETHERNET_IRQHandler ;Ethernet + DCD ETHERNET_PMT_IRQHandler ;Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ;Ethernet MAC interrupt + DCD EEPROM_IRQHandler ;EEPROM interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD SHA_IRQHandler ;SHA interrupt + DCD SMARTCARD0_IRQHandler ;Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ;Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + MOVS r0,#56 + LDR r1, =0x40000220 + STR r0, [r1] ;Enable SRAM clock used by Stack + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h index dc11e47fc..fec7e9067 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.h +++ b/hw/bsp/lpc55/boards/double_m33_express/board.h @@ -37,26 +37,17 @@ #endif // LED -#define LED_PORT 0 -#define LED_PIN 1 +#define LED_PORT BOARD_INITLEDSPINS_LED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_PIN #define LED_STATE_ON 1 // WAKE button -#define BUTTON_PORT 0 -#define BUTTON_PIN 5 +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S1_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S1_PIN #define BUTTON_STATE_ACTIVE 0 -// Number of neopixels -#define NEOPIXEL_NUMBER 2 -#define NEOPIXEL_PORT 0 -#define NEOPIXEL_PIN 27 -#define NEOPIXEL_CH 6 -#define NEOPIXEL_TYPE 0 - // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0U, 29U, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0U, 30U, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.mk b/hw/bsp/lpc55/boards/double_m33_express/board.mk index d28700ca7..c0282686f 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.mk +++ b/hw/bsp/lpc55/boards/double_m33_express/board.mk @@ -1,10 +1,17 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 +RHPORT_DEVICE ?= 1 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0 LD_FILE = $(BOARD_PATH)/LPC55S69_cm33_core0_uf2.ld +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c new file mode 100644 index 000000000..16e112dfc --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.c @@ -0,0 +1,736 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +pin_labels: +- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '7', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t LED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_1 (pin 7) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config); + + IOCON->PIO[0][1] = ((IOCON->PIO[0][1] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT01 (pin 7) is configured as PIO0_1. */ + | IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h new file mode 100644 index 000000000..33f000d0a --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/board/pin_mux.h @@ -0,0 +1,383 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define PIO0_1_DIGIMODE_DIGITAL 0x01u /*!<@brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_1_FUNC_ALT0 0x00u /*!<@brief Selects pin function.: Alternative connection 0. */ + +/*! @name PIO0_1 (number 7), P18[2]/SD1_CLK + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 0U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_PIN 1U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex new file mode 100644 index 000000000..47d0909d6 --- /dev/null +++ b/hw/bsp/lpc55/boards/double_m33_express/double_m33_express.mex @@ -0,0 +1,1283 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <pin_labels> + <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED"/> + </pin_labels> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 1" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex new file mode 100644 index 000000000..cc59745f9 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/LPCXpresso55S28.mex @@ -0,0 +1,856 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S28" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="485a5299-e2fe-41ab-bc43-80d8d2a4ae02" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S28</processor> + <package>LPC55S28JBD100</package> + <board>LPCXpresso55S28</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="SYSTICK0_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.SYSTICKCLKSEL0.sel" value="SYSCON.SYSTICKCLKDIV0" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>N/A</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="DEBUG_UART" uuid="30367b6e-4b43-4345-bc10-e4052723fa66" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="ACCEL" uuid="796441cb-6cbf-48af-8003-54caaeb9a132" type="flexcomm_i2c" type_id="flexcomm_i2c_2.0.1" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + </struct> + </config_set> + </instance> + <instance name="SW" uuid="723cdb07-2d95-4daf-94b4-1dfaf0ce6c04" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="LEDS" uuid="7ec70f15-5deb-44fa-b8cf-2d12230a37ac" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="d00e8bd3-19f3-445c-9444-103d6461e0d1" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="4e239a4c-f368-4554-b66e-d1af6e8b1f5d" type_id="system_54b53072540eeeb8f8e9343e71f28176"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="7bbbd3b5-f7c2-4cb2-8b95-c037fdaf8e02" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="1560ea56-1bfb-4123-a192-daeeed8f2a1d" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="4305ffdd-d7f2-418a-b81b-8a042e7e4c75" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="fe22d2c9-7984-4e79-a7b1-8d26fad750be" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="f5a27f2d-a41b-4143-ad53-b9ee09903619" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="03fd1bc8-0fd6-4b47-a53c-1c40e2aa781e" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>N/A</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake index d935b70e6..b3d6ec722 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake @@ -1,10 +1,17 @@ set(MCU_VARIANT LPC55S28) set(MCU_CORE LPC55S28) +set(MCU_DRIVER_VARIANT LPC55S69) set(JLINK_DEVICE LPC55S28) +set(JLINK_OPTION "-USB 000727031389") + set(PYOCD_TARGET LPC55S28) set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28) +# device fullspeed, host highspeed +set(RHPORT_DEVICE 0) +set(RHPORT_HOST 1) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S28JBD100 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h index 907aee6a4..c8d3a2b8f 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h @@ -36,20 +36,18 @@ extern "C" { #endif -// LED -#define LED_PORT 1 -#define LED_PIN 6 +// LED: use red LED from generated pin_mux +#define LED_PORT BOARD_INITLEDSPINS_LED_RED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_RED_PIN #define LED_STATE_ON 0 -// WAKE button -#define BUTTON_PORT 1 -#define BUTTON_PIN 18 +// WAKE button: use S2 from generated pin_mux +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S2_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S2_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk index ec0828e41..db2e11fd7 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.mk @@ -1,9 +1,20 @@ MCU_VARIANT = LPC55S28 MCU_CORE = LPC55S28 -PORT ?= 1 +MCU_DRIVER_VARIANT = LPC55S69 + +# device fullspeed, host highspeed +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 1 CFLAGS += -DCPU_LPC55S28JBD100 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S28 PYOCD_TARGET = LPC55S28 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c new file mode 100644 index 000000000..c1e8e0575 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.c @@ -0,0 +1,335 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: PLL1_Mode, value: Normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: SYSTICK0_clock.outFreq, value: 144 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.SYSTICKCLKSEL0.sel, value: SYSCON.SYSTICKCLKDIV0} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 0U, true); /*!< Reset SYSTICKCLKDIV0 divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 1U, false); /*!< Set SYSTICKCLKDIV0 divider to value 1 */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + CLOCK_AttachClk(kSYSTICK_DIV0_to_SYSTICK0); /*!< Switch SYSTICK0 to SYSTICK_DIV0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h new file mode 100644 index 000000000..fdd472793 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/clock_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 144000000UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c new file mode 100644 index 000000000..f3b986b6c --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.c @@ -0,0 +1,157 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 +functionalGroups: +- name: BOARD_InitPeripherals + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h new file mode 100644 index 000000000..3f498f4af --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c new file mode 100644 index 000000000..924961d42 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.c @@ -0,0 +1,795 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S28 +package_id: LPC55S28JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S28 +external_user_signals: {} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_4 (pin 1) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_6 (pin 5) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_7 (pin 9) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); + + const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE); + + const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED); + + const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + gpio_pin_config_t S3_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_9 (pin 10) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config); + + gpio_pin_config_t S2_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); + + const uint32_t S2 = (/* Pin is configured as PIO1_18 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2); + + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h new file mode 100644 index 000000000..2a99795ef --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board/pin_mux.h @@ -0,0 +1,433 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_RED_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_PIN 6U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S2_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_PIN 18U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S3_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_PIN 9U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex new file mode 100644 index 000000000..9e31688b7 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/LPCXpresso55S69.mex @@ -0,0 +1,1329 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO1, 4" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 6" pin_num="5" pin_signal="PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 18" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 9" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake index f46775b27..59f7d6329 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake @@ -2,9 +2,15 @@ set(MCU_VARIANT LPC55S69) set(MCU_CORE LPC55S69_cm33_core0) set(JLINK_DEVICE LPC55S69_M33_0) +set(JLINK_OPTION "-USB 000727648789") + set(PYOCD_TARGET LPC55S69) set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) +# device highspeed, host fullspeed +set(RHPORT_DEVICE 1) +set(RHPORT_HOST 0) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CPU_LPC55S69JBD100_cm33_core0 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h index e18d5bbad..3b81411a1 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h @@ -36,20 +36,18 @@ extern "C" { #endif -// LED -#define LED_PORT 1 -#define LED_PIN 6 +// LED: use red LED from generated pin_mux +#define LED_PORT BOARD_INITLEDSPINS_LED_RED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_RED_PIN #define LED_STATE_ON 0 -// WAKE button -#define BUTTON_PORT 1 -#define BUTTON_PIN 18 +// WAKE button: use S2 from generated pin_mux +#define BUTTON_PORT BOARD_INITBUTTONSPINS_S2_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_S2_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 29, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 30, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk index 73edc88a9..e92c46f05 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.mk @@ -1,9 +1,19 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 + +# device highspeed, host fullspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 CFLAGS += -DCPU_LPC55S69JBD100_cm33_core0 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c new file mode 100644 index 000000000..979e7d065 --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.c @@ -0,0 +1,860 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO, signal: 'PIO1, 4', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '5', peripheral: GPIO, signal: 'PIO1, 6', pin_signal: PIO1_6/FC0_TXD_SCL_MISO_WS/SD0_D3/CTIMER2_MAT1/SCT_GPI3, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '9', peripheral: GPIO, signal: 'PIO1, 7', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4, direction: OUTPUT, gpio_init_state: 'true', + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_4 (pin 1) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_6 (pin 5) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO1_7 (pin 9) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); + + const uint32_t LED_BLUE = (/* Pin is configured as PIO1_4 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, LED_BLUE); + + const uint32_t LED_RED = (/* Pin is configured as PIO1_6 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN6 (coords: 5) is configured as PIO1_6 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, LED_RED); + + const uint32_t LED_GREEN = (/* Pin is configured as PIO1_7 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */ + IOCON_PinMuxSet(IOCON, BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, LED_GREEN); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t S1_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S1_GPIO, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, &S1_config); + + gpio_pin_config_t S3_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_9 (pin 10) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S3_GPIO, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, &S3_config); + + gpio_pin_config_t S2_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_S2_GPIO, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, &S2_config); + + const uint32_t S1 = (/* Pin is configured as PIO0_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN5 (coords: 88) is configured as PIO0_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S1_PORT, BOARD_INITBUTTONSPINS_S1_PIN, S1); + + const uint32_t S2 = (/* Pin is configured as PIO1_18 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S2_PORT, BOARD_INITBUTTONSPINS_S2_PIN, S2); + + if (Chip_GetVersion()==1) + { + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); + } + else + { + const uint32_t S3 = (/* Pin is configured as PIO1_9 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT1 PIN9 (coords: 10) is configured as PIO1_9 */ + IOCON_PinMuxSet(IOCON, BOARD_INITBUTTONSPINS_S3_PORT, BOARD_INITBUTTONSPINS_S3_PIN, S3); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h new file mode 100644 index 000000000..3925c937a --- /dev/null +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board/pin_mux.h @@ -0,0 +1,435 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_4 (number 1), R78/P18[5]/LEDR/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 4U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_BLUE_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN 4U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 4U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_6 (number 5), R80/P18[9]/LEDB/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 6U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_RED_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_PIN 6U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 6U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_7 (number 9), R79/P18[7]/LEDG/PWM_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_GREEN_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN 7U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S1_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S1_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S1_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S1_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S2_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S2_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S2_PIN 18U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S2_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_9 (number 10), S3/P18[1]/PIO1_9_GPIO_ARD + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_S3_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_GPIO_PIN_MASK (1U << 9U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_S3_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_S3_PIN 9U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_S3_PIN_MASK (1U << 9U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake index fd7cb6de6..bbaaf6648 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.cmake +++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake @@ -7,8 +7,6 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC - CPU_LPC55S69JBD100_cm33_core0 - # port 1 is highspeed - # BOARD_TUD_RHPORT=1 + CPU_LPC55S69JBD64_cm33_core0 ) endfunction() diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h index 1d71b3e79..d3c133f40 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.h +++ b/hw/bsp/lpc55/boards/mcu_link/board.h @@ -37,19 +37,17 @@ #endif // LED -#define LED_PORT 0 -#define LED_PIN 5 +#define LED_PORT BOARD_INITLEDSPINS_LED_PORT +#define LED_PIN BOARD_INITLEDSPINS_LED_PIN #define LED_STATE_ON 0 // WAKE button (Dummy, use unused pin -#define BUTTON_PORT 0 -#define BUTTON_PIN 30 +#define BUTTON_PORT BOARD_INITBUTTONSPINS_BUTTON_PORT +#define BUTTON_PIN BOARD_INITBUTTONSPINS_BUTTON_PIN #define BUTTON_STATE_ACTIVE 0 // UART #define UART_DEV USART0 -#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN -#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN // XTAL #define XTAL0_CLK_HZ (16 * 1000 * 1000U) diff --git a/hw/bsp/lpc55/boards/mcu_link/board.mk b/hw/bsp/lpc55/boards/mcu_link/board.mk index ceb1d0ebc..4f686a88f 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.mk +++ b/hw/bsp/lpc55/boards/mcu_link/board.mk @@ -1,9 +1,16 @@ MCU_VARIANT = LPC55S69 MCU_CORE = LPC55S69_cm33_core0 -PORT ?= 1 +RHPORT_DEVICE ?= 1 CFLAGS += -DCPU_LPC55S69JBD64_cm33_core0 +SRC_C += \ + $(TOP)/$(BOARD_PATH)/board/clock_config.c \ + $(TOP)/$(BOARD_PATH)/board/pin_mux.c \ + $(TOP)/$(BOARD_PATH)/board/peripherals.c + +INC += $(TOP)/$(BOARD_PATH)/board + JLINK_DEVICE = LPC55S69 PYOCD_TARGET = LPC55S69 diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c new file mode 100644 index 000000000..99a738f18 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.c @@ -0,0 +1,328 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FXCOM0_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 144 MHz} +- {id: USB0_clock.outFreq, value: 48 MHz} +- {id: USB1_PHY_clock.outFreq, value: 16 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_PLL_USB_OUT, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV} +- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0DIV.scale, value: '2'} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '18'} +- {id: SYSCON.PLL1_PDEC.scale, value: '2'} +- {id: SYSCON.USB0CLKDIV.scale, value: '3'} +- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.MAINCLKSELB} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; /* Enable clk_in to HS USB */ + + POWER_SetVoltageForFreq(144000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(144000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(11U) | SYSCON_PLL1CTRL_SELP(5U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(18U), + .pllRate = 144000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4) + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #else + CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false); /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */ + #endif + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 3U, false); /*!< Set USB0CLKDIV divider to value 3 */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true); /*!< Reset PLL0DIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false); /*!< Set PLL0DIV divider to value 2 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + CLOCK_AttachClk(kMAIN_CLK_to_USB0_CLK); /*!< Switch USB0_CLK to MAIN_CLK */ + CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to PLL0_DIV */ + + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} diff --git a/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h new file mode 100644 index 000000000..9112ede78 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/clock_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFRO12M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFRO12M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFRO12M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFRO12M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFRO12M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFRO12M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFRO12M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFROHF96M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFROHF96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKFROHF96M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKFROHF96M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKFROHF96M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKFROHF96M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKFROHF96M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKFROHF96M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKFROHF96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKFROHF96M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFROHF96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKFROHF96M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKFROHF96M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFROHF96M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL100M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL100M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL100M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM0_CLOCK 0UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL100M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL100M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL100M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL100M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL100M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL100M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL100M_SYSTEM_CLOCK 100000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL100M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL100M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL100M_USB1_PHY_CLOCK 0UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL100M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL100M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ + + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKPLL150M_ASYNCADC_CLOCK 0UL /* Clock consumers of ASYNCADC_clock output : ADC0 */ +#define BOARD_BOOTCLOCKPLL150M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */ +#define BOARD_BOOTCLOCKPLL150M_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM0_CLOCK 48000000UL /* Clock consumers of FXCOM0_clock output : FLEXCOMM0 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM1_CLOCK 0UL /* Clock consumers of FXCOM1_clock output : FLEXCOMM1 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM2_CLOCK 0UL /* Clock consumers of FXCOM2_clock output : FLEXCOMM2 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM3_CLOCK 0UL /* Clock consumers of FXCOM3_clock output : FLEXCOMM3 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM4_CLOCK 0UL /* Clock consumers of FXCOM4_clock output : FLEXCOMM4 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM5_CLOCK 0UL /* Clock consumers of FXCOM5_clock output : FLEXCOMM5 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM6_CLOCK 0UL /* Clock consumers of FXCOM6_clock output : FLEXCOMM6 */ +#define BOARD_BOOTCLOCKPLL150M_FXCOM7_CLOCK 0UL /* Clock consumers of FXCOM7_clock output : FLEXCOMM7 */ +#define BOARD_BOOTCLOCKPLL150M_HSLSPI_CLOCK 0UL /* Clock consumers of HSLSPI_clock output : FLEXCOMM8 */ +#define BOARD_BOOTCLOCKPLL150M_MCLK_CLOCK 0UL /* Clock consumers of MCLK_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_OSC32KHZ_CLOCK 0UL /* Clock consumers of OSC32KHZ_clock output : FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_OSTIMER32KHZ_CLOCK 0UL /* Clock consumers of OSTIMER32KHZ_clock output : OSTIMER */ +#define BOARD_BOOTCLOCKPLL150M_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU */ +#define BOARD_BOOTCLOCKPLL150M_RTC1HZ_CLOCK 0UL /* Clock consumers of RTC1HZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_RTC1KHZ_CLOCK 0UL /* Clock consumers of RTC1KHZ_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */ +#define BOARD_BOOTCLOCKPLL150M_SDIO_CLOCK 0UL /* Clock consumers of SDIO_clock output : SDIF */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : N/A */ +#define BOARD_BOOTCLOCKPLL150M_SYSTEM_CLOCK 144000000UL /* Clock consumers of System_clock output : ADC0, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DMA0, DMA1, FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, GINT0, GINT1, GPIO, INPUTMUX, IOCON, MAILBOX, MRT0, OSTIMER, PINT, PLU, PUF, SCT0, SDIF, SECGPIO, SECPINT, SWD, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT */ +#define BOARD_BOOTCLOCKPLL150M_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKPLL150M_USB0_CLOCK 48000000UL /* Clock consumers of USB0_clock output : USB0, USBFSH */ +#define BOARD_BOOTCLOCKPLL150M_USB1_PHY_CLOCK 16000000UL /* Clock consumers of USB1_PHY_clock output : USBHSD, USBHSH, USBPHY */ +#define BOARD_BOOTCLOCKPLL150M_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKPLL150M_WDT_CLOCK 0UL /* Clock consumers of WDT_clock output : WWDT */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c new file mode 100644 index 000000000..890a20fc6 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.c @@ -0,0 +1,160 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v15.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +functionalGroups: +- name: BOARD_InitPeripherals_cm33_core0 + UUID: 61d0725d-b300-49cb-9c66-b5edfbf8ffc1 + called_from_default_init: true + selectedCore: cm33_core0 +- name: BOARD_InitPeripherals_cm33_core1 + UUID: e2041cd4-ebb6-45a5-807f-e0c2dc047d48 + selectedCore: cm33_core1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system' +- global_system_definitions: + - user_definitions: '' + - user_includes: '' + - global_init: '' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'uart_cmsis_common' +- type_id: 'uart_cmsis_common' +- global_USART_CMSIS_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'gpio_adapter_common' +- type_id: 'gpio_adapter_common' +- global_gpio_adapter_common: + - quick_selection: 'default' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * BOARD_InitPeripherals_cm33_core0 functional group + **********************************************************************************************************************/ +/*********************************************************************************************************************** + * DEBUG_UART initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'DEBUG_UART' +- type: 'flexcomm_usart' +- mode: 'polling' +- custom_name_enabled: 'true' +- type_id: 'flexcomm_usart_2.2.0' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'FLEXCOMM0' +- config_sets: + - usartConfig_t: + - usartConfig: + - clockSource: 'FXCOMFunctionClock' + - clockSourceFreq: 'ClocksTool_DefaultInit' + - baudRate_Bps: '115200' + - syncMode: 'kUSART_SyncModeDisabled' + - parityMode: 'kUSART_ParityDisabled' + - stopBitCount: 'kUSART_OneStopBit' + - bitCountPerChar: 'kUSART_8BitsPerChar' + - loopback: 'false' + - txWatermark: 'kUSART_TxFifo0' + - rxWatermark: 'kUSART_RxFifo1' + - enableRx: 'true' + - enableTx: 'true' + - clockPolarity: 'kUSART_RxSampleOnFallingEdge' + - enableContinuousSCLK: 'false' + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ +const usart_config_t DEBUG_UART_config = { + .baudRate_Bps = 115200UL, + .syncMode = kUSART_SyncModeDisabled, + .parityMode = kUSART_ParityDisabled, + .stopBitCount = kUSART_OneStopBit, + .bitCountPerChar = kUSART_8BitsPerChar, + .loopback = false, + .txWatermark = kUSART_TxFifo0, + .rxWatermark = kUSART_RxFifo1, + .enableRx = true, + .enableTx = true, + .enableMode32k = false, + .clockPolarity = kUSART_RxSampleOnFallingEdge, + .enableContinuousSCLK = false +}; + +static void DEBUG_UART_init(void) { + /* Reset FLEXCOMM device */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + USART_Init(DEBUG_UART_PERIPHERAL, &DEBUG_UART_config, DEBUG_UART_CLOCK_SOURCE); +} + +/*********************************************************************************************************************** + * NVIC initialization code + **********************************************************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +instance: +- name: 'NVIC' +- type: 'nvic' +- mode: 'general' +- custom_name_enabled: 'false' +- type_id: 'nvic' +- functional_group: 'BOARD_InitPeripherals_cm33_core0' +- peripheral: 'NVIC' +- config_sets: + - nvic: + - interrupt_table: [] + - interrupts: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/* Empty initialization function (commented out) +static void NVIC_init(void) { +} */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals_cm33_core0(void) +{ + /* Initialize components */ + DEBUG_UART_init(); +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals_cm33_core0(); +} diff --git a/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h new file mode 100644 index 000000000..fc4d72c33 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/peripherals.h @@ -0,0 +1,57 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_usart.h" +#include "fsl_clock.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* Definitions for BOARD_InitPeripherals_cm33_core0 functional group */ +/* Definition of peripheral ID */ +#define DEBUG_UART_PERIPHERAL ((USART_Type *)FLEXCOMM0) +/* Definition of the clock source frequency */ +#define DEBUG_UART_CLOCK_SOURCE 48000000UL + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern const usart_config_t DEBUG_UART_config; + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ + +void BOARD_InitPeripherals_cm33_core0(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c new file mode 100644 index 000000000..a673302e5 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.c @@ -0,0 +1,839 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: LPCXpresso55S69 +expansion_headers: +- id: lpc_style_arduino + name: LPCXpresso V3 (Arduino compatible) + connectors: + - id: C1 + name: P16 + pins: + - {id: 8, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 10, name: RESET, pin_num: '32', pin_signal: RESETN} + - {id: 12, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 14, name: 5V, external_signal_types: power_supply_5V} + - {id: 16, name: GND, external_signal_types: ground} + - {id: 18, name: GND, external_signal_types: ground} + - {id: 20, name: 5V, external_signal_types: power_supply_5V} + - id: C2 + name: P17 + pins: + - {id: 1, name: D15, pin_num: '4', pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2} + - {id: 3, name: D14, pin_num: '30', pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3} + - {id: 5, name: 3.3V, external_signal_types: power_supply_3.3V} + - {id: 6, pin_num: '93', pin_signal: PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS} + - {id: 7, name: GND, external_signal_types: ground} + - {id: 8, pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5} + - {id: 9, name: D13, pin_num: '61', pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5} + - {id: 10, pin_num: '74', pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS} + - {id: 11, name: D12, pin_num: '62', pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6} + - {id: 12, pin_num: '90', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19} + - {id: 13, name: D11, pin_num: '60', pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26} + - {id: 14, pin_num: '76', pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21} + - {id: 15, name: D10, pin_num: '59', pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4} + - {id: 16, pin_num: '85', pin_signal: PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4} + - {id: 17, name: D9, pin_num: '31', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0} + - {id: 18, pin_num: '73', pin_signal: PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3} + - {id: 19, name: D8, pin_num: '24', pin_signal: PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4} + - {id: 20, pin_num: '2', pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N} + - id: C3 + name: P18 + pins: + - {id: 1, name: D7, pin_num: '10', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12} + - {id: 2, pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1} + - {id: 3, name: D6, pin_num: '40', pin_signal: PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3} + - {id: 4, pin_num: '57', pin_signal: PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D} + - {id: 5, name: D5, pin_num: '1', pin_signal: PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A} + - {id: 6, pin_num: '77', pin_signal: PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN} + - {id: 7, name: D4-LED_GREEN, pin_num: '9', pin_signal: PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4} + - {id: 8, pin_num: '42', pin_signal: PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5} + - {id: 10, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6} + - {id: 11, name: D2, pin_num: '22', pin_signal: PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2} + - {id: 12, pin_num: '82', pin_signal: PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2} + - {id: 13, name: D1, pin_num: '27', pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27} + - {id: 14, pin_num: '58', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF} + - {id: 15, name: D0, pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6} + - {id: 16, pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0} + - {id: 17, pin_num: '87', pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD} + - {id: 18, pin_num: '68', pin_signal: PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5} + - {id: 19, pin_num: '43', pin_signal: PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N} + - {id: 20, pin_num: '56', pin_signal: PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C} + - id: C4 + name: P19 + pins: + - {id: 2, name: A0, pin_num: '14', pin_signal: PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8} + - {id: 4, name: A1, pin_num: '20', pin_signal: PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0} + - {id: 6, name: A2, pin_num: '54', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A} + - {id: 7, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0} + - {id: 8, name: A3, pin_num: '91', pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0} + - {id: 9, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13} + - {id: 10, name: A4, pin_num: '71', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13} + - {id: 11, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14} + - {id: 12, name: A5, pin_num: '72', pin_signal: PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14} +pin_labels: +- {pin_num: '7', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: 'P18[2]/SD1_CLK', identifier: LED_RED} +- {pin_num: '88', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: 'S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1', + identifier: LED} +- {pin_num: '11', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, label: 'U20[2]/SD0_D3', identifier: BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitUSBPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); + BOARD_InitPins_Core0(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_UART_RX = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, DEBUG_UART_RX); + + const uint32_t DEBUG_UART_TX = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '13', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9, mode: pullDown, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '12', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, identifier: DEBUG_SWD_SWO, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t DEBUG_SWD_SWO = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN, DEBUG_SWD_SWO); + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + else + { + const uint32_t DEBUG_SWD_SWDCLK = (/* Pin is configured as SWCLK */ + IOCON_PIO_FUNC6 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN11 (coords: 13) is configured as SWCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, DEBUG_SWD_SWDCLK); + } + + if (Chip_GetVersion()==1) + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } + else + { + const uint32_t DEBUG_SWD_SWDIO = (/* Pin is configured as SWDIO */ + IOCON_PIO_FUNC6 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled), only for A0 version */ + IOCON_PIO_ASW_DIS_EN); + /* PORT0 PIN12 (coords: 12) is configured as SWDIO */ + IOCON_PinMuxSet(IOCON, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, DEBUG_SWD_SWDIO); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '97', peripheral: USBFSH, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '98', peripheral: USBFSH, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '78', peripheral: USBFSH, signal: USB_VBUS, pin_signal: PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '35', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM} + - {pin_num: '34', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP} + - {pin_num: '36', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS} + - {pin_num: '65', peripheral: USBHSH, signal: USB_OVERCURRENTN, pin_signal: PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1, mode: pullUp} + - {pin_num: '66', peripheral: USBFSH, signal: USB_OVERCURRENTN, pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, + mode: pullUp} + - {pin_num: '67', peripheral: USBFSH, signal: USB_PORTPWRN, pin_signal: PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2, mode: pullUp} + - {pin_num: '80', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitUSBPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t USB0_VBUS = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, BOARD_INITUSBPINS_USB0_VBUS_PORT, BOARD_INITUSBPINS_USB0_VBUS_PIN, USB0_VBUS); + + IOCON->PIO[0][28] = ((IOCON->PIO[0][28] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT028 (pin 66) is configured as USB0_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT7) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_28_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][12] = ((IOCON->PIO[1][12] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT112 (pin 67) is configured as USB0_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_12_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_12_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_12_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][29] = ((IOCON->PIO[1][29] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT129 (pin 80) is configured as USB1_PORTPWRN. */ + | IOCON_PIO_FUNC(PIO1_29_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_29_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_29_DIGIMODE_DIGITAL)); + + IOCON->PIO[1][30] = ((IOCON->PIO[1][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT130 (pin 65) is configured as USB1_OVERCURRENTN. */ + | IOCON_PIO_FUNC(PIO1_30_FUNC_ALT4) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_30_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_30_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT, + gpio_init_state: 'true', mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitLEDsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + gpio_pin_config_t LED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO0_5 (pin 88) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GPIO, BOARD_INITLEDSPINS_LED_PORT, BOARD_INITLEDSPINS_LED_PIN, &LED_config); + + IOCON->PIO[0][5] = ((IOCON->PIO[0][5] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT05 (pin 88) is configured as PIO0_5. */ + | IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '32', peripheral: SYSCON, signal: RESET, pin_signal: RESETN} + - {pin_num: '11', peripheral: GPIO, signal: 'PIO1, 0', pin_signal: PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11, direction: INPUT, mode: pullUp} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitBUTTONsPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t BUTTON_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_0 (pin 11) */ + GPIO_PinInit(BOARD_INITBUTTONSPINS_BUTTON_GPIO, BOARD_INITBUTTONSPINS_BUTTON_PORT, BOARD_INITBUTTONSPINS_BUTTON_PIN, &BUTTON_config); + + if (Chip_GetVersion()==1) + { + IOCON->PIO[1][0] = ((IOCON->PIO[1][0] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT10 (pin 11) is configured as PIO1_0. */ + | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL)); + } + else + { + IOCON->PIO[1][0] = ((IOCON->PIO[1][0] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function. + * : PORT10 (pin 11) is configured as PIO1_0. */ + | IOCON_PIO_FUNC(PIO1_0_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-up. + * Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO1_0_MODE_PULL_UP) + + /* Select Digital mode. + * : Enable Digital mode. + * Digital input is enabled. */ + | IOCON_PIO_DIGIMODE(PIO1_0_DIGIMODE_DIGITAL)); + } +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins_Core0: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins_Core0 + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins_Core0(void) +{ +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitI2SPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '91', peripheral: SYSCON, signal: MCLK, pin_signal: PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0, mode: inactive, slew_rate: standard, invert: disabled, + open_drain: disabled} + - {pin_num: '76', peripheral: FLEXCOMM7, signal: SCK, pin_signal: PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '74', peripheral: FLEXCOMM7, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '90', peripheral: FLEXCOMM7, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: FLEXCOMM6, signal: SCK, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, + identifier: FC6_I2S_CLK, mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled, asw: enabled} + - {pin_num: '2', peripheral: FLEXCOMM6, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N, + mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '87', peripheral: FLEXCOMM6, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitI2SPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitI2SPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t FC6_I2S_CLK = (/* Pin is configured as FC6_SCK */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is closed (enabled) */ + IOCON_PIO_ASW_EN); + /* PORT0 PIN10 (coords: 21) is configured as FC6_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_CLK_PORT, BOARD_INITI2SPINS_FC6_I2S_CLK_PIN, FC6_I2S_CLK); + + const uint32_t FC7_I2S_WS = (/* Pin is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN19 (coords: 90) is configured as FC7_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_WS_PORT, BOARD_INITI2SPINS_FC7_I2S_WS_PIN, FC7_I2S_WS); + + const uint32_t FC7_I2S_TX = (/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN20 (coords: 74) is configured as FC7_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_TX_PORT, BOARD_INITI2SPINS_FC7_I2S_TX_PIN, FC7_I2S_TX); + + const uint32_t FC7_I2S_SCK = (/* Pin is configured as FC7_SCK */ + IOCON_PIO_FUNC7 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN21 (coords: 76) is configured as FC7_SCK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC7_I2S_SCK_PORT, BOARD_INITI2SPINS_FC7_I2S_SCK_PIN, FC7_I2S_SCK); + + const uint32_t FC6_I2S_RX = (/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN13 (coords: 2) is configured as FC6_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_RX_PORT, BOARD_INITI2SPINS_FC6_I2S_RX_PIN, FC6_I2S_RX); + + const uint32_t FC6_I2S_WS = (/* Pin is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN16 (coords: 87) is configured as FC6_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC6_I2S_WS_PORT, BOARD_INITI2SPINS_FC6_I2S_WS_PIN, FC6_I2S_WS); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SCL_PORT, BOARD_INITI2SPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_FC4_I2C_SDA_PORT, BOARD_INITI2SPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); + + const uint32_t MCLK = (/* Pin is configured as MCLK */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN31 (coords: 91) is configured as MCLK */ + IOCON_PinMuxSet(IOCON, BOARD_INITI2SPINS_MCLK_PORT, BOARD_INITI2SPINS_MCLK_PIN, MCLK); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitACCELPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '30', peripheral: FLEXCOMM4, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3, mode: pullUp, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: TXD_SCL_MISO_WS, pin_signal: PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2, mode: pullUp, slew_rate: standard, + invert: disabled, open_drain: disabled} + - {pin_num: '58', peripheral: GPIO, signal: 'PIO1, 19', pin_signal: PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF, direction: INPUT, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitACCELPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitACCELPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t ACCL_INTR_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_19 (pin 58) */ + GPIO_PinInit(BOARD_INITACCELPINS_ACCL_INTR_GPIO, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, &ACCL_INTR_config); + + const uint32_t ACCL_INTR = (/* Pin is configured as PIO1_19 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT1 PIN19 (coords: 58) is configured as PIO1_19 */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_ACCL_INTR_PORT, BOARD_INITACCELPINS_ACCL_INTR_PIN, ACCL_INTR); + + const uint32_t FC4_I2C_SCL = (/* Pin is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN20 (coords: 4) is configured as FC4_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SCL_PORT, BOARD_INITACCELPINS_FC4_I2C_SCL_PIN, FC4_I2C_SCL); + + const uint32_t FC4_I2C_SDA = (/* Pin is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC5 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h new file mode 100644 index 000000000..3e14d6baf --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/board/pin_mux.h @@ -0,0 +1,393 @@ +/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_29 (number 92), P8[2]/U6[13]/FC0_USART_RXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 29U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 29U) +/* @} */ + +/*! @name PIO0_30 (number 94), P8[3]/U6[12]/FC0_USART_TXD + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 30U +/*! + * @brief PORT pin mask */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 30U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_EN 0x00u /*!<@brief Analog switch is closed (enabled), only for A0 version */ +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO0_11 (number 13), U14[4]/SWDCLK_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 11U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 11U) +/* @} */ + +/*! @name PIO0_12 (number 12), U15[4]/D7/P7[2]/IF_SWDIO + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 12U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 12U) +/* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +/*! + * @brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PORT 0U +/*! + * @brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN 10U +/*! + * @brief PORT pin mask */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWO_PIN_MASK (1U << 10U) +/* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Enables digital function */ +#define IOCON_PIO_DIGITAL_EN 0x0100u +/*! + * @brief Selects pin function 7 */ +#define IOCON_PIO_FUNC7 0x07u +/*! + * @brief Input function is not inverted */ +#define IOCON_PIO_INV_DI 0x00u +/*! + * @brief No addition pin function */ +#define IOCON_PIO_MODE_INACT 0x00u +/*! + * @brief Open drain is disabled */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u +/*! + * @brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_28_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 7. */ +#define PIO0_28_FUNC_ALT7 0x07u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_28_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_12_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_12_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_12_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_29_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_29_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_29_MODE_PULL_UP 0x02u +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_30_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 4. */ +#define PIO1_30_FUNC_ALT4 0x04u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_30_MODE_PULL_UP 0x02u + +/*! @name PIO0_22 (number 78), P10[1]/USB0_VBUS + @{ */ +#define BOARD_INITUSBPINS_USB0_VBUS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN 22U /*!<@brief PORT pin number */ +#define BOARD_INITUSBPINS_USB0_VBUS_PIN_MASK (1U << 22U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO0_5_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO0_5_FUNC_ALT0 0x00u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO0_5_MODE_PULL_UP 0x02u + +/*! @name PIO0_5 (number 88), S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */ +#define BOARD_INITLEDSPINS_LED_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_PIN 5U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */ +#define PIO1_0_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO1_0_FUNC_ALT0 0x00u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO1_0_MODE_PULL_UP 0x02u + +/*! @name PIO1_0 (number 11), U20[2]/SD0_D3 + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_BUTTON_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */ +#define BOARD_INITBUTTONSPINS_BUTTON_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_BUTTON_PIN 0U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_BUTTON_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_EN 0x0400u /*!<@brief Analog switch is closed (enabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 2 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_31 (number 91), P19[7]/P19[8]/PLU_IN0/GPIO + @{ */ +#define BOARD_INITI2SPINS_MCLK_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_MCLK_PIN 31U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_MCLK_PIN_MASK (1U << 31U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_21 (number 76), P17[14]/FC7_I2S_SCK + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_SCK_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_20 (number 74), P17[10]/FC7_I2S_TX + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_TX_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_19 (number 90), P17[12]/FC7_I2S_WS + @{ */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC7_I2S_WS_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO0_10 (number 21), U14[12]/SWO_TRGT + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PORT 0U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN 10U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_CLK_PIN_MASK (1U << 10U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_13 (number 2), P17[20]/FC6_I2S_RX + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_RX_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_16 (number 87), P18[17]/SD1_PWR_EN + @{ */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN 16U /*!<@brief PORT pin number */ +#define BOARD_INITI2SPINS_FC6_I2S_WS_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! @name PIO1_21 (number 30), P17[3]/P24[6]/FC4_I2C_SDA_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN 21U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SDA_PIN_MASK (1U << 21U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_20 (number 4), P17[1]/P24[5]/FC4_I2C_SCL_ARD + @{ */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN 20U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_FC4_I2C_SCL_PIN_MASK (1U << 20U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PIO1_19 (number 58), U7[3]/P18[14]/PLU_OUT1/GPIO + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO GPIO /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */ +#define BOARD_INITACCELPINS_ACCL_INTR_PORT 1U /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN 19U /*!<@brief PORT pin number */ +#define BOARD_INITACCELPINS_ACCL_INTR_PIN_MASK (1U << 19U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex new file mode 100644 index 000000000..c78dba808 --- /dev/null +++ b/hw/bsp/lpc55/boards/mcu_link/mcu_link.mex @@ -0,0 +1,1354 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="LPCXpresso55S69" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="acf73d26-2bf9-4855-b3be-26068672d98a" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>LPC55S69</processor> + <package>LPC55S69JBD100</package> + <board>LPCXpresso55S69</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="cm33_core0"> + <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/> + <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <custom_copyright> + <text>/* + * Copyright 2026 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +</text> + <enabled>true</enabled> + </custom_copyright> + <update_include_paths>true</update_include_paths> + <enable_parallel_routing>true</enable_parallel_routing> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="17.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>25.09.10</processor_version> + <pin_labels> + <pin_label pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="P18[2]/SD1_CLK" identifier="LED_RED"/> + <pin_label pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5" label="S1/J10[1]/U3[12]/P17[8]/P7[7]/U11[4]/P0_5-ISP1" identifier="LED"/> + <pin_label pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11" label="U20[2]/SD0_D3" identifier="BUTTON"/> + </pin_labels> + <expansion_headers> + <expansion_header id="lpc_style_arduino" name="LPCXpresso V3 (Arduino compatible)"> + <connectors> + <connector id="C1" name="P16"> + <pins> + <pin id="8" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="10" pin_num="32" pin_signal="RESETN" name="RESET"/> + <pin id="12" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="14" external_signal_types="power_supply_5V" name="5V"/> + <pin id="16" external_signal_types="ground" name="GND"/> + <pin id="18" external_signal_types="ground" name="GND"/> + <pin id="20" external_signal_types="power_supply_5V" name="5V"/> + </pins> + </connector> + <connector id="C2" name="P17"> + <pins> + <pin id="1" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2" name="D15"/> + <pin id="3" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3" name="D14"/> + <pin id="5" external_signal_types="power_supply_3.3V" name="3.3V"/> + <pin id="6" pin_num="93" pin_signal="PIO1_11/FC1_TXD_SCL_MISO_WS/CT_INP5/USB0_VBUS"/> + <pin id="7" external_signal_types="ground" name="GND"/> + <pin id="8" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"/> + <pin id="9" pin_num="61" pin_signal="PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5" name="D13"/> + <pin id="10" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"/> + <pin id="11" pin_num="62" pin_signal="PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6" name="D12"/> + <pin id="12" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"/> + <pin id="13" pin_num="60" pin_signal="PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26" name="D11"/> + <pin id="14" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"/> + <pin id="15" pin_num="59" pin_signal="PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4" name="D10"/> + <pin id="16" pin_num="85" pin_signal="PIO1_27/FC2_RTS_SCL_SSEL1/SD0_D4/CTIMER0_MAT3/CLKOUT/PLU_IN4"/> + <pin id="17" pin_num="31" pin_signal="PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0" name="D9"/> + <pin id="18" pin_num="73" pin_signal="PIO1_28/FC7_SCK/SD0_D5/CT_INP2/PLU_IN3"/> + <pin id="19" pin_num="24" pin_signal="PIO1_8/FC0_CTS_SDA_SSEL0/SD0_CLK/SCT0_OUT1/FC4_SSEL2/ADC0_4" name="D8"/> + <pin id="20" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"/> + </pins> + </connector> + <connector id="C3" name="P18"> + <pins> + <pin id="1" pin_num="10" pin_signal="PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12" name="D7"/> + <pin id="2" pin_num="7" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1"/> + <pin id="3" pin_num="40" pin_signal="PIO1_10/FC1_RXD_SDA_MOSI_DATA/CTIMER1_MAT0/SCT0_OUT3" name="D6"/> + <pin id="4" pin_num="57" pin_signal="PIO1_14/UTICK_CAP2/CTIMER1_MAT2/FC5_CTS_SDA_SSEL0/USB0_LEDN/SD1_CMD/ACMP0_D"/> + <pin id="5" pin_num="1" pin_signal="PIO1_4/FC0_SCK/SD0_D0/CTIMER2_MAT1/SCT0_OUT0/FREQME_GPIO_CLK_A" name="D5"/> + <pin id="6" pin_num="77" pin_signal="PIO1_25/FC2_TXD_SCL_MISO_WS/SCT0_OUT2/SD1_D0/UTICK_CAP0/PLU_CLKIN"/> + <pin id="7" pin_num="9" pin_signal="PIO1_7/FC0_RTS_SCL_SSEL1/SD0_D1/CTIMER2_MAT2/SCT_GPI4" name="D4-LED_GREEN"/> + <pin id="8" pin_num="42" pin_signal="PIO1_23/FC2_SCK/SCT0_OUT0/SD1_D3/FC3_SSEL2/PLU_OUT5"/> + <pin id="10" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6"/> + <pin id="11" pin_num="22" pin_signal="PIO0_15/FC6_CTS_SDA_SSEL0/UTICK_CAP2/CT_INP16/SCT0_OUT2/SD0_WR_PRT/SECURE_GPIO0_15/ADC0_2" name="D2"/> + <pin id="12" pin_num="82" pin_signal="PIO1_15/UTICK_CAP3/CT_INP7/FC5_RTS_SCL_SSEL1/FC4_RTS_SCL_SSEL1/SD1_D2"/> + <pin id="13" pin_num="27" pin_signal="PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27" name="D1"/> + <pin id="14" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"/> + <pin id="15" pin_num="3" pin_signal="PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6" name="D0"/> + <pin id="16" pin_num="64" pin_signal="PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0"/> + <pin id="17" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"/> + <pin id="18" pin_num="68" pin_signal="PIO1_26/FC2_CTS_SDA_SSEL0/SCT0_OUT3/CT_INP3/UTICK_CAP1/HS_SPI_SSEL3/PLU_IN5"/> + <pin id="19" pin_num="43" pin_signal="PIO1_17/FC6_RTS_SCL_SSEL1/SCT0_OUT4/SD1_CARD_INT_N/SD1_CARD_DET_N"/> + <pin id="20" pin_num="56" pin_signal="PIO0_18/FC4_CTS_SDA_SSEL0/SD0_WR_PRT/CTIMER1_MAT0/SCT0_OUT1/PLU_IN3/SECURE_GPIO0_18/ACMP0_C"/> + </pins> + </connector> + <connector id="C4" name="P19"> + <pins> + <pin id="2" pin_num="14" pin_signal="PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8" name="A0"/> + <pin id="4" pin_num="20" pin_signal="PIO0_23/MCLK/CTIMER1_MAT2/CTIMER3_MAT3/SCT0_OUT4/FC0_CTS_SDA_SSEL0/SD1_D1/SECURE_GPIO0_23/ADC0_0" name="A1"/> + <pin id="6" pin_num="54" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A" name="A2"/> + <pin id="7" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"/> + <pin id="8" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0" name="A3"/> + <pin id="9" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13"/> + <pin id="10" pin_num="71" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13" name="A4"/> + <pin id="11" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14"/> + <pin id="12" pin_num="72" pin_signal="PIO0_14/FC1_RTS_SCL_SSEL1/UTICK_CAP1/CT_INP1/SCT_GPI1/FC1_TXD_SCL_MISO_WS/PLU_IN1/SECURE_GPIO0_14" name="A5"/> + </pins> + </connector> + </connectors> + </expansion_header> + </expansion_headers> + </pins_profile> + <functions_list> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="92" pin_signal="PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="94" pin_signal="PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSWD_DEBUGPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SWD" signal="SWCLK" pin_num="13" pin_signal="PIO0_11/FC6_RXD_SDA_MOSI_DATA/CTIMER2_MAT2/FREQME_GPIO_CLK_A/SWCLK/SECURE_GPIO0_11/ADC0_9"> + <pin_features> + <pin_feature name="mode" value="pullDown"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWDIO" pin_num="12" pin_signal="PIO0_12/FC3_TXD_SCL_MISO_WS/SD1_BACKEND_PWR/FREQME_GPIO_CLK_B/SCT_GPI7/SD0_POW_EN/SWDIO/FC6_TXD_SCL_MISO_WS/SECURE_GPIO0_12/ADC0_10"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="SWD" signal="SWO" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="DEBUG_SWD_SWO"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitUSBPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USBFSH" description="Peripheral USBFSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSBPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSBPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USBFSH" signal="USB_DP" pin_num="97" pin_signal="USB0_DP"/> + <pin peripheral="USBFSH" signal="USB_DM" pin_num="98" pin_signal="USB0_DM"/> + <pin peripheral="USBFSH" signal="USB_VBUS" pin_num="78" pin_signal="PIO0_22/FC6_TXD_SCL_MISO_WS/UTICK_CAP1/CT_INP15/SCT0_OUT3/USB0_VBUS/SD1_D0/PLU_OUT7/SECURE_GPIO0_22"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_DM" pin_num="35" pin_signal="USB1_DM"/> + <pin peripheral="USBHSH" signal="USB_DP" pin_num="34" pin_signal="USB1_DP"/> + <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="36" pin_signal="USB1_VBUS"/> + <pin peripheral="USBHSH" signal="USB_OVERCURRENTN" pin_num="65" pin_signal="PIO1_30/FC7_TXD_SCL_MISO_WS/SD0_D7/SCT_GPI7/USB1_OVERCURRENTN/USB1_LEDN/PLU_IN1"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_OVERCURRENTN" pin_num="66" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBFSH" signal="USB_PORTPWRN" pin_num="67" pin_signal="PIO1_12/FC6_SCK/CTIMER1_MAT1/USB0_PORTPWRN/HS_SPI_SSEL2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="80" pin_signal="PIO1_29/FC7_RXD_SDA_MOSI_DATA/SD0_D6/SCT_GPI6/USB1_PORTPWRN/USB1_FRAME/PLU_IN2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitLEDsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO" signal="PIO0, 5" pin_num="88" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONsPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SYSCON" signal="RESET" pin_num="32" pin_signal="RESETN"/> + <pin peripheral="GPIO" signal="PIO1, 0" pin_num="11" pin_signal="PIO1_0/FC0_RTS_SCL_SSEL1/SD0_D3/CT_INP2/SCT_GPI4/PLU_OUT3/ADC0_11"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="pullUp"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitPins_Core0"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core0"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitPins_Core1"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>cm33_core1</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins_Core1"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitI2SPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="SYSCON" description="Peripheral SYSCON signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM7" description="Peripheral FLEXCOMM7 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM6" description="Peripheral FLEXCOMM6 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitI2SPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitI2SPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="SYSCON" signal="MCLK" pin_num="91" pin_signal="PIO1_31/MCLK/SD1_CLK/CTIMER0_MAT2/SCT0_OUT6/PLU_IN0"> + <pin_features> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="SCK" pin_num="76" pin_signal="PIO0_21/FC3_RTS_SCL_SSEL1/UTICK_CAP3/CTIMER3_MAT3/SCT_GPI3/FC7_SCK/PLU_CLKIN/SECURE_GPIO0_21"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="RXD_SDA_MOSI_DATA" pin_num="74" pin_signal="PIO0_20/FC3_CTS_SDA_SSEL0/CTIMER1_MAT1/CT_INP15/SCT_GPI2/FC7_RXD_SDA_MOSI_DATA/HS_SPI_SSEL0/PLU_IN5/SECURE_GPIO0_20/FC4_TXD_SCL_MISO_WS"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM7" signal="TXD_SCL_MISO_WS" pin_num="90" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="SCK" pin_num="21" pin_signal="PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1"> + <pin_features> + <pin_feature name="identifier" value="FC6_I2S_CLK"/> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="enabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="RXD_SDA_MOSI_DATA" pin_num="2" pin_signal="PIO1_13/FC6_RXD_SDA_MOSI_DATA/CT_INP6/USB0_OVERCURRENTN/USB0_FRAME/SD0_CARD_DET_N"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM6" signal="TXD_SCL_MISO_WS" pin_num="87" pin_signal="PIO1_16/FC6_TXD_SCL_MISO_WS/CTIMER1_MAT3/SD0_CMD"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitACCELPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>cm33_core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXCOMM4" description="Peripheral FLEXCOMM4 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitACCELPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_iocon" description="Pins initialization requires the LPC_IOCON Driver in the project." problem_level="2" source="Pins:BOARD_InitACCELPins"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXCOMM4" signal="RXD_SDA_MOSI_DATA" pin_num="30" pin_signal="PIO1_21/FC7_CTS_SDA_SSEL0/CTIMER3_MAT2/FC4_RXD_SDA_MOSI_DATA/PLU_OUT3"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="FLEXCOMM4" signal="TXD_SCL_MISO_WS" pin_num="4" pin_signal="PIO1_20/FC7_RTS_SCL_SSEL1/CT_INP14/FC4_TXD_SCL_MISO_WS/PLU_OUT2"> + <pin_features> + <pin_feature name="mode" value="pullUp"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + </pin_features> + </pin> + <pin peripheral="GPIO" signal="PIO1, 19" pin_num="58" pin_signal="PIO1_19/SCT0_OUT7/CTIMER3_MAT1/SCT_GPI7/FC4_SCK/PLU_OUT1/ACMPVREF"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="mode" value="inactive"/> + <pin_feature name="slew_rate" value="standard"/> + <pin_feature name="invert" value="disabled"/> + <pin_feature name="open_drain" value="disabled"/> + <pin_feature name="asw" value="disabled"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="18.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>25.09.10</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources/> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings/> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockFROHF96M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFROHF96M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/> + <setting id="SYSCON.MAINCLKSELA.sel" value="ANACTRL.fro_hf_clk" locked="false"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL100M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL100M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="System_clock.outFreq" value="100 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="100" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="4" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="4" locked="true"/> + </clock_settings> + <called_from_default_init>false</called_from_default_init> + </clock_configuration> + <clock_configuration name="BOARD_BootClockPLL150M" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="'XTALIN' (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="'XTALOUT' (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core1"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockPLL150M"> + <feature name="enabled" evaluation="equal" configuration="cm33_core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="System_clock.outFreq" value="144 MHz" locked="false" accuracy=""/> + <clock_output id="USB0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/> + <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="PLL0_Mode" value="Normal" locked="false"/> + <setting id="PLL1_Mode" value="Normal" locked="false"/> + <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/> + <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/> + <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/> + <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.PLL0DIV" locked="false"/> + <setting id="SYSCON.FRGCTRL0_DIV.scale" value="400" locked="false"/> + <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL1_BYPASS" locked="false"/> + <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL0DIV.scale" value="2" locked="false"/> + <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/> + <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/> + <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="true"/> + <setting id="SYSCON.PLL1CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/> + <setting id="SYSCON.PLL1M_MULT.scale" value="18" locked="false"/> + <setting id="SYSCON.PLL1_PDEC.scale" value="2" locked="false"/> + <setting id="SYSCON.USB0CLKDIV.scale" value="3" locked="false"/> + <setting id="SYSCON.USB0CLKSEL.sel" value="SYSCON.MAINCLKSELB" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="FLEXCOMM USART Driver is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.flexcomm_usart" description="An unsupported version of the FLEXCOMM USART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.2.0</data> + </feature> + </dependency> + <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>25.09.10</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals_cm33_core0" uuid="61d0725d-b300-49cb-9c66-b5edfbf8ffc1" called_from_default_init="true" id_prefix="" core="cm33_core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="FXCOM0_clock" description="FXCOM0 clock is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_rxd" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="FLEXCOMM0.usart_txd" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals_cm33_core0"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="ACCEL" uuid="b999c56a-0d01-4089-9311-9224db5272f4" type="flexcomm_i2c" type_id="flexcomm_i2c_2.3.0" mode="I2C_Polling" peripheral="FLEXCOMM4" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_i2c" quick_selection="QS_I2C_Master"> + <setting name="i2c_mode" value="kI2C_Master"/> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="i2c_master_config"> + <setting name="enableMaster" value="true"/> + <setting name="baudRate_Bps" value="100000"/> + <setting name="enableTimeout" value="false"/> + <setting name="timeout_Ms" value="35"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="9fb0504c-6159-43e2-98bb-51d75f06133a" type="flexcomm_usart" type_id="flexcomm_usart_2.2.0" mode="polling" peripheral="FLEXCOMM0" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="usartConfig_t"> + <struct name="usartConfig"> + <setting name="clockSource" value="FXCOMFunctionClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="syncMode" value="kUSART_SyncModeDisabled"/> + <setting name="parityMode" value="kUSART_ParityDisabled"/> + <setting name="stopBitCount" value="kUSART_OneStopBit"/> + <setting name="bitCountPerChar" value="kUSART_8BitsPerChar"/> + <setting name="loopback" value="false"/> + <setting name="txWatermark" value="kUSART_TxFifo0"/> + <setting name="rxWatermark" value="kUSART_RxFifo1"/> + <setting name="enableRx" value="true"/> + <setting name="enableTx" value="true"/> + <setting name="clockPolarity" value="kUSART_RxSampleOnFallingEdge"/> + <setting name="enableContinuousSCLK" value="false"/> + </struct> + </config_set> + </instance> + <instance name="LEDS" uuid="f5ad3a56-404b-44cb-8abc-7b25b5551d33" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="SW" uuid="d57ddfca-dc72-486c-a145-c7a2ab1e1a66" type="lpc_gpio" type_id="lpc_gpio_2.1.1" mode="GPIO" peripheral="GPIO" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpc_gpio"/> + </instance> + <instance name="NVIC" uuid="56761ad9-9b77-4074-917d-de0fde10cd48" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + <functional_group name="BOARD_InitPeripherals_cm33_core1" uuid="e2041cd4-ebb6-45a5-807f-e0c2dc047d48" called_from_default_init="false" id_prefix="" core="cm33_core1"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC_2" uuid="db546092-4c45-40af-938a-8cc58edd1c4f" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="905d2747-654a-47d9-91f9-81a5c6f9c407" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + <setting name="global_init" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="64cbcd7c-424d-4baf-9681-a60878969fb6" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_can" uuid="b9b018dd-ef4e-41f6-b456-f91b855cb391" type_id="generic_can"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="bafa6375-9184-4272-8102-06ea086041d7" type_id="uart_cmsis_common"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="1710dc7f-381f-4b37-8f78-0fd2f923b3ac" type_id="generic_uart"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_enet" uuid="c7fc4395-b141-4b13-a326-4145e765b2b7" type_id="generic_enet"> + <config_set_global name="global_enet"/> + </component> + <component name="gpio_adapter_common" uuid="b6ee89c2-4c58-4181-94dc-af13d8ae8ea5" type_id="gpio_adapter_common"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + </components> + </periphs> + <tee name="TEE" version="10.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + <tool_options> + <option id="_output_type_" value="c_code"/> + <option id="_legacy_source_names_" value="yes"/> + </tool_options> + </tee_profile> + <functional_group name="BOARD_InitTrustZone" called_from_default_init="true" id_prefix="" prefix_user_defined="true"> + <description></description> + <options/> + <ahb> + <relative_region start="0" size="655360" security="s_priv" memory="PROGRAM_FLASH"/> + <relative_region start="0" size="131072" security="s_priv" memory="BootROM"/> + <relative_region start="0" size="32768" security="s_priv" memory="SRAMX"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM0"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM1"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM2"/> + <relative_region start="0" size="65536" security="s_priv" memory="SRAM3"/> + <relative_region start="0" size="16384" security="s_priv" memory="SRAM4"/> + <relative_region start="0" size="16384" security="s_priv" memory="AHBperipherals_port10_ahb_secure_ctrl_area"/> + <relative_region start="0" size="16384" security="s_priv" memory="USB_RAM"/> + <masters> + <master id="HASH" security="ns_user"/> + <master id="MCM33C" security="ns_user"/> + <master id="MCM33S" security="ns_user"/> + <master id="PQ" security="ns_user"/> + <master id="SDIO" security="ns_user"/> + <master id="SDMA0" security="ns_user"/> + <master id="SDMA1" security="ns_user"/> + <master id="USBFSD" security="ns_user"/> + <master id="USBFSH" security="ns_user"/> + </masters> + <peripherals> + <peripheral id="ADC0" security="s_priv"/> + <peripheral id="AHB_SECURE_CTRL" security="s_priv"/> + <peripheral id="ANACTRL" security="s_priv"/> + <peripheral id="CASPER" security="s_priv"/> + <peripheral id="CRC_ENGINE" security="s_priv"/> + <peripheral id="CTIMER0" security="s_priv"/> + <peripheral id="CTIMER1" security="s_priv"/> + <peripheral id="CTIMER2" security="s_priv"/> + <peripheral id="CTIMER3" security="s_priv"/> + <peripheral id="CTIMER4" security="s_priv"/> + <peripheral id="DBGMAILBOX" security="s_priv"/> + <peripheral id="DMA0" security="s_priv"/> + <peripheral id="DMA1" security="s_priv"/> + <peripheral id="FLASH" security="s_priv"/> + <peripheral id="FLEXCOMM0" security="s_priv"/> + <peripheral id="FLEXCOMM1" security="s_priv"/> + <peripheral id="FLEXCOMM2" security="s_priv"/> + <peripheral id="FLEXCOMM3" security="s_priv"/> + <peripheral id="FLEXCOMM4" security="s_priv"/> + <peripheral id="FLEXCOMM5" security="s_priv"/> + <peripheral id="FLEXCOMM6" security="s_priv"/> + <peripheral id="FLEXCOMM7" security="s_priv"/> + <peripheral id="GINT0" security="s_priv"/> + <peripheral id="GINT1" security="s_priv"/> + <peripheral id="GPIO" security="s_priv"/> + <peripheral id="HASHCRYPT" security="s_priv"/> + <peripheral id="INPUTMUX" security="s_priv"/> + <peripheral id="IOCON" security="s_priv"/> + <peripheral id="MAILBOX" security="s_priv"/> + <peripheral id="MRT0" security="s_priv"/> + <peripheral id="OSTIMER" security="s_priv"/> + <peripheral id="PINT" security="s_priv"/> + <peripheral id="PLU" security="s_priv"/> + <peripheral id="PMC" security="s_priv"/> + <peripheral id="POWERQUAD" security="s_priv"/> + <peripheral id="PRINCE" security="s_priv"/> + <peripheral id="PUF" security="s_priv"/> + <peripheral id="RNG" security="s_priv"/> + <peripheral id="RTC" security="s_priv"/> + <peripheral id="SCT0" security="s_priv"/> + <peripheral id="SDIF" security="s_priv"/> + <peripheral id="SECGPIO" security="s_priv"/> + <peripheral id="SECPINT" security="s_priv"/> + <peripheral id="SPI8" security="s_priv"/> + <peripheral id="SYSCON" security="s_priv"/> + <peripheral id="SYSCTL" security="s_priv"/> + <peripheral id="USB0" security="s_priv"/> + <peripheral id="USBFSH" security="s_priv"/> + <peripheral id="USBHSD" security="s_priv"/> + <peripheral id="USBHSH" security="s_priv"/> + <peripheral id="USBPHY" security="s_priv"/> + <peripheral id="UTICK0" security="s_priv"/> + <peripheral id="WWDT" security="s_priv"/> + </peripherals> + <interrupts> + <masking> + <interrupt id="acmp_capt_irq" masked="Masked"/> + <interrupt id="adc_irq" masked="Masked"/> + <interrupt id="casper_irq" masked="Masked"/> + <interrupt id="ctimer0_irq" masked="Masked"/> + <interrupt id="ctimer1_irq" masked="Masked"/> + <interrupt id="ctimer2_irq" masked="Masked"/> + <interrupt id="ctimer3_irq" masked="Masked"/> + <interrupt id="ctimer4_irq" masked="Masked"/> + <interrupt id="flexcomm0_irq" masked="Masked"/> + <interrupt id="flexcomm1_irq" masked="Masked"/> + <interrupt id="flexcomm2_irq" masked="Masked"/> + <interrupt id="flexcomm3_irq" masked="Masked"/> + <interrupt id="flexcomm4_irq" masked="Masked"/> + <interrupt id="flexcomm5_irq" masked="Masked"/> + <interrupt id="flexcomm6_irq" masked="Masked"/> + <interrupt id="flexcomm7_irq" masked="Masked"/> + <interrupt id="global_irq0" masked="Masked"/> + <interrupt id="global_irq1" masked="Masked"/> + <interrupt id="lspi_hs_irq" masked="Masked"/> + <interrupt id="mailbox_irq" masked="Masked"/> + <interrupt id="mrt_irq" masked="Masked"/> + <interrupt id="os_event_irq" masked="Masked"/> + <interrupt id="pin_int4" masked="Masked"/> + <interrupt id="pin_int5" masked="Masked"/> + <interrupt id="pin_int6" masked="Masked"/> + <interrupt id="pin_int7" masked="Masked"/> + <interrupt id="pin_irq0" masked="Masked"/> + <interrupt id="pin_irq1" masked="Masked"/> + <interrupt id="pin_irq2" masked="Masked"/> + <interrupt id="pin_irq3" masked="Masked"/> + <interrupt id="plu_irq" masked="Masked"/> + <interrupt id="pq_irq" masked="Masked"/> + <interrupt id="qddkey_irq" masked="Masked"/> + <interrupt id="rtc_irq" masked="Masked"/> + <interrupt id="sct_irq" masked="Masked"/> + <interrupt id="sdio_irq" masked="Masked"/> + <interrupt id="sdma0_irq" masked="Masked"/> + <interrupt id="sdma1_irq" masked="Masked"/> + <interrupt id="sec_hypervisor_call_irq" masked="Masked"/> + <interrupt id="sec_int0" masked="Masked"/> + <interrupt id="sec_int1" masked="Masked"/> + <interrupt id="sec_vio_irq" masked="Masked"/> + <interrupt id="sha_irq" masked="Masked"/> + <interrupt id="sys_irq" masked="Masked"/> + <interrupt id="usb0_irq" masked="Masked"/> + <interrupt id="usb0_needclk_irq" masked="Masked"/> + <interrupt id="usb1_irq" masked="Masked"/> + <interrupt id="usb1_needclk_irq" masked="Masked"/> + <interrupt id="usb1_utmi_irq" masked="Masked"/> + <interrupt id="utick_irq" masked="Masked"/> + </masking> + <security> + <interrupt id="acmp_capt_irq" secure="Secure"/> + <interrupt id="adc_irq" secure="Secure"/> + <interrupt id="casper_irq" secure="Secure"/> + <interrupt id="ctimer0_irq" secure="Secure"/> + <interrupt id="ctimer1_irq" secure="Secure"/> + <interrupt id="ctimer2_irq" secure="Secure"/> + <interrupt id="ctimer3_irq" secure="Secure"/> + <interrupt id="ctimer4_irq" secure="Secure"/> + <interrupt id="flexcomm0_irq" secure="Secure"/> + <interrupt id="flexcomm1_irq" secure="Secure"/> + <interrupt id="flexcomm2_irq" secure="Secure"/> + <interrupt id="flexcomm3_irq" secure="Secure"/> + <interrupt id="flexcomm4_irq" secure="Secure"/> + <interrupt id="flexcomm5_irq" secure="Secure"/> + <interrupt id="flexcomm6_irq" secure="Secure"/> + <interrupt id="flexcomm7_irq" secure="Secure"/> + <interrupt id="global_irq0" secure="Secure"/> + <interrupt id="global_irq1" secure="Secure"/> + <interrupt id="lspi_hs_irq" secure="Secure"/> + <interrupt id="mailbox_irq" secure="Secure"/> + <interrupt id="mrt_irq" secure="Secure"/> + <interrupt id="os_event_irq" secure="Secure"/> + <interrupt id="pin_int4" secure="Secure"/> + <interrupt id="pin_int5" secure="Secure"/> + <interrupt id="pin_int6" secure="Secure"/> + <interrupt id="pin_int7" secure="Secure"/> + <interrupt id="pin_irq0" secure="Secure"/> + <interrupt id="pin_irq1" secure="Secure"/> + <interrupt id="pin_irq2" secure="Secure"/> + <interrupt id="pin_irq3" secure="Secure"/> + <interrupt id="plu_irq" secure="Secure"/> + <interrupt id="pq_irq" secure="Secure"/> + <interrupt id="qddkey_irq" secure="Secure"/> + <interrupt id="rtc_irq" secure="Secure"/> + <interrupt id="sct_irq" secure="Secure"/> + <interrupt id="sdio_irq" secure="Secure"/> + <interrupt id="sdma0_irq" secure="Secure"/> + <interrupt id="sdma1_irq" secure="Secure"/> + <interrupt id="sec_hypervisor_call_irq" secure="Secure"/> + <interrupt id="sec_int0" secure="Secure"/> + <interrupt id="sec_int1" secure="Secure"/> + <interrupt id="sec_vio_irq" secure="Secure"/> + <interrupt id="sha_irq" secure="Secure"/> + <interrupt id="sys_irq" secure="Secure"/> + <interrupt id="usb0_irq" secure="Secure"/> + <interrupt id="usb0_needclk_irq" secure="Secure"/> + <interrupt id="usb1_irq" secure="Secure"/> + <interrupt id="usb1_needclk_irq" secure="Secure"/> + <interrupt id="usb1_utmi_irq" secure="Secure"/> + <interrupt id="utick_irq" secure="Secure"/> + </security> + </interrupts> + <ports> + <port id="pio0"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + <port id="pio1"> + <pin_mask id="0" masked="Masked"/> + <pin_mask id="1" masked="Masked"/> + <pin_mask id="10" masked="Masked"/> + <pin_mask id="11" masked="Masked"/> + <pin_mask id="12" masked="Masked"/> + <pin_mask id="13" masked="Masked"/> + <pin_mask id="14" masked="Masked"/> + <pin_mask id="15" masked="Masked"/> + <pin_mask id="16" masked="Masked"/> + <pin_mask id="17" masked="Masked"/> + <pin_mask id="18" masked="Masked"/> + <pin_mask id="19" masked="Masked"/> + <pin_mask id="2" masked="Masked"/> + <pin_mask id="20" masked="Masked"/> + <pin_mask id="21" masked="Masked"/> + <pin_mask id="22" masked="Masked"/> + <pin_mask id="23" masked="Masked"/> + <pin_mask id="24" masked="Masked"/> + <pin_mask id="25" masked="Masked"/> + <pin_mask id="26" masked="Masked"/> + <pin_mask id="27" masked="Masked"/> + <pin_mask id="28" masked="Masked"/> + <pin_mask id="29" masked="Masked"/> + <pin_mask id="3" masked="Masked"/> + <pin_mask id="30" masked="Masked"/> + <pin_mask id="31" masked="Masked"/> + <pin_mask id="4" masked="Masked"/> + <pin_mask id="5" masked="Masked"/> + <pin_mask id="6" masked="Masked"/> + <pin_mask id="7" masked="Masked"/> + <pin_mask id="8" masked="Masked"/> + <pin_mask id="9" masked="Masked"/> + </port> + </ports> + </ahb> + <saus> + <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false"> + <region start="0" size="268435456" security="ns" enabled="true" index="0"/> + <region start="536870912" size="3221225472" security="ns" enabled="true" index="1"/> + <region start="0" size="32" security="ns" enabled="false" index="2"/> + <region start="0" size="32" security="ns" enabled="false" index="3"/> + <region start="0" size="32" security="ns" enabled="false" index="4"/> + <region start="0" size="32" security="ns" enabled="false" index="5"/> + <region start="0" size="32" security="ns" enabled="false" index="6"/> + <region start="0" size="32" security="ns" enabled="false" index="7"/> + </sau> + </saus> + <global_options> + <option id="AIRCR_PRIS" value="no"/> + <option id="AIRCR_BFHFNMINS" value="no"/> + <option id="AIRCR_SYSRESETREQS" value="no"/> + <option id="SCR_SLEEPDEEPS" value="no"/> + <option id="SHCSR_SECUREFAULTENA" value="no"/> + <option id="CPACR_CP0" value="3"/> + <option id="CPACR_CP1" value="3"/> + <option id="CPACR_CP2" value="0"/> + <option id="CPACR_CP3" value="0"/> + <option id="CPACR_CP4" value="0"/> + <option id="CPACR_CP5" value="0"/> + <option id="CPACR_CP6" value="0"/> + <option id="CPACR_CP7" value="0"/> + <option id="CPACR_CP10" value="3"/> + <option id="CPACR_CP11" value="3"/> + <option id="NSACR_CP0" value="yes"/> + <option id="NSACR_CP1" value="yes"/> + <option id="NSACR_CP2" value="no"/> + <option id="NSACR_CP3" value="no"/> + <option id="NSACR_CP4" value="no"/> + <option id="NSACR_CP5" value="no"/> + <option id="NSACR_CP6" value="no"/> + <option id="NSACR_CP7" value="no"/> + <option id="NSACR_CP10" value="yes"/> + <option id="NSACR_CP11" value="yes"/> + <option id="CPPWR_SU0" value="no"/> + <option id="CPPWR_SUS0" value="no"/> + <option id="CPPWR_SU1" value="no"/> + <option id="CPPWR_SUS1" value="no"/> + <option id="CPPWR_SU2" value="no"/> + <option id="CPPWR_SUS2" value="no"/> + <option id="CPPWR_SU3" value="no"/> + <option id="CPPWR_SUS3" value="no"/> + <option id="CPPWR_SU4" value="no"/> + <option id="CPPWR_SUS4" value="no"/> + <option id="CPPWR_SU5" value="no"/> + <option id="CPPWR_SUS5" value="no"/> + <option id="CPPWR_SU6" value="no"/> + <option id="CPPWR_SUS6" value="no"/> + <option id="CPPWR_SU7" value="no"/> + <option id="CPPWR_SUS7" value="no"/> + <option id="CPPWR_SU10" value="no"/> + <option id="CPPWR_SUS10" value="no"/> + <option id="CPPWR_SU11" value="no"/> + <option id="CPPWR_SUS11" value="no"/> + <option id="SEC_GPIO_MASK0_LOCK" value="no"/> + <option id="SEC_GPIO_MASK1_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/> + <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/> + <option id="MASTER_SEC_LEVEL_LOCK" value="no"/> + <option id="CPU0_LOCK_NS_VTOR" value="no"/> + <option id="CPU0_LOCK_NS_MPU" value="no"/> + <option id="CPU0_LOCK_S_VTAIRCR" value="no"/> + <option id="CPU0_LOCK_S_MPU" value="no"/> + <option id="CPU0_LOCK_SAU" value="no"/> + <option id="CPU0_LOCK_REG_LOCK" value="no"/> + <option id="CPU1_LOCK_NS_VTOR" value="no"/> + <option id="CPU1_LOCK_NS_MPU" value="no"/> + <option id="CPU1_LOCK_REG_LOCK" value="no"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="yes"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/> + <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/> + <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/> + </global_options> + <mpus> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false"> + <attributes> + <group index="0" id="Code" memory_type="normal" device="nGnRE"/> + <group index="1" id="RAM" memory_type="normal" device="nGnRE"/> + <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/> + <group index="3" id="3" memory_type="device" device="nGnRE"/> + <group index="4" id="4" memory_type="device" device="nGnRE"/> + <group index="5" id="5" memory_type="device" device="nGnRE"/> + <group index="6" id="6" memory_type="device" device="nGnRE"/> + <group index="7" id="7" memory_type="device" device="nGnRE"/> + </attributes> + <regions> + <region start="0" size="32" security="priv" enabled="false" index="0" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="1" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="2" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="3" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="4" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="5" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="6" executable="false" read_only="false" attributes_index="0"/> + <region start="0" size="32" security="priv" enabled="false" index="7" executable="false" read_only="false" attributes_index="0"/> + </regions> + </mpu> + </mpus> + </functional_group> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index ad0e502b5..b5d097234 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -33,9 +33,12 @@ #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" -#include "fsl_iocon.h" #include "fsl_usart.h" +#include "board/pin_mux.h" +#include "board/clock_config.h" +#include "board/peripherals.h" + #ifdef NEOPIXEL_PIN #include "fsl_sctimer.h" #include "sct_neopixel.h" @@ -45,23 +48,6 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -// IOCON pin mux -#define IOCON_PIO_DIGITAL_EN 0x0100u // Enables digital function -#define IOCON_PIO_FUNC0 0x00u // Selects pin function 0 -#define IOCON_PIO_FUNC1 0x01u // Selects pin function 1 -#define IOCON_PIO_FUNC4 0x04u // Selects pin function 4 -#define IOCON_PIO_FUNC7 0x07u // Selects pin function 7 -#define IOCON_PIO_INV_DI 0x00u // Input function is not inverted -#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function -#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled -#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled -#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ - -#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled -#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled -#define IOCON_PIO_DIG_FUNC4_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC4) // Digital pin function 2 enabled -#define IOCON_PIO_DIG_FUNC7_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC7) // Digital pin function 2 enabled - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -73,74 +59,12 @@ void USB1_IRQHandler(void) { tusb_int_handler(1, true); } -/**************************************************************** -name: BOARD_BootClockPLL100M -outputs: -- {id: System_clock.outFreq, value: 100 MHz} -settings: -- {id: PLL0_Mode, value: Normal} -- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} -- {id: ENABLE_CLKIN_ENA, value: Enabled} -- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} -- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} -- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} -- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} -- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} -- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} -sources: -- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} -- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} -******************************************************************/ -void BOARD_BootClockPLL100M(void) -{ - /*!< Set up the clock sources */ - /*!< Configure FRO192M */ - POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - - CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ - - /*!< Configure XTAL32M */ - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ - CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ - - POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ - POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); - const pll_setup_t pll0Setup = { - .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), - .pllndec = SYSCON_PLL0NDEC_NDIV(4U), - .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), - .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, - .pllRate = 100000000U, - .flags = PLL_SETUPFLAG_WAITLOCK - }; - CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ - - /*< Set SystemCoreClock variable. */ - SystemCoreClock = 100000000U; -} - void board_init(void) { - // Enable IOCON clock - CLOCK_EnableClock(kCLOCK_Iocon); + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + BOARD_InitBootPeripherals(); - // Init 100 MHz clock - BOARD_BootClockPLL100M(); + board_led_write(0); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -155,54 +79,8 @@ void board_init(void) { NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - // Init all GPIO ports - GPIO_PortInit(GPIO, 0); - GPIO_PortInit(GPIO, 1); - - // LED - IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN); - gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1}; - GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config); - - board_led_write(0); - -#ifdef NEOPIXEL_PIN - // Neopixel - static uint32_t pixelData[NEOPIXEL_NUMBER]; - IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN); - - sctpix_init(NEOPIXEL_TYPE); - sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER); - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010); - sctpix_show(); -#endif - - // Button - IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN); - gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0}; - GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config); - -#ifdef UART_DEV - // UART - IOCON_PinMuxSet(IOCON, UART_RX_PINMUX); - IOCON_PinMuxSet(IOCON, UART_TX_PINMUX); - - // Enable UART when debug log is on - CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - usart_config_t uart_config; - USART_GetDefaultConfig(&uart_config); - uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; - uart_config.enableTx = true; - uart_config.enableRx = true; - USART_Init(UART_DEV, &uart_config, 12000000); -#endif - #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) - /* PORT0 PIN22 configured as USB0_VBUS */ - IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN); // Port0 is Full Speed - NVIC_ClearPendingIRQ(USB0_IRQn); NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn); @@ -227,36 +105,6 @@ void board_init(void) { /* enable USB Device clock */ CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); } else { - const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */ - IOCON_PIO_FUNC4 | - /* Selects pull-up function */ - IOCON_PIO_MODE_PULLUP | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */ - IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config); - - const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */ - IOCON_PIO_FUNC7 | - /* Selects pull-up function */ - IOCON_PIO_MODE_PULLUP | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */ - IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config); - CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U); USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK; } @@ -274,18 +122,21 @@ void board_init(void) { RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); - /* According to reference manual, device mode setting has to be set by access usb host register */ - CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock + if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) { + /* According to reference manual, device mode setting has to be set by access usb host register */ + CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock - USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock + /* enable USB Device clock */ + CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); + } else { + CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUnused, 0U); + } - /* enable USB Device clock */ CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ); - CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); - CLOCK_EnableClock(kCLOCK_UsbRam1); // Enable PHY support for Low speed device + LS via FS Hub USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; @@ -296,11 +147,9 @@ void board_init(void) { USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; - // TX Timing -// uint32_t phytx = USBPHY->TX; -// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); -// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); -// USBPHY->TX = phytx; + // PHY Tx calibration + USBPHY->TX = ((USBPHY->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(0x05U) | USBPHY_TX_TXCAL45DP(0x0AU) | USBPHY_TX_TXCAL45DM(0x0AU))); ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer) ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0)); @@ -314,17 +163,6 @@ void board_init(void) { void board_led_write(bool state) { GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); - -#ifdef NEOPIXEL_PIN - if (state) { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010); - } else { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010); - } - sctpix_show(); -#endif } uint32_t board_button_read(void) { @@ -350,7 +188,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 1f18f9bad..2dc1c33f3 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-lpc/LPC5500) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -40,43 +41,60 @@ cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_ # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED STARTUP_FILE_GNU) - set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) + # Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69) + if (NOT DEFINED MCU_DRIVER_VARIANT) + set(MCU_DRIVER_VARIANT ${MCU_VARIANT}) + endif () + add_library(${BOARD_TARGET} STATIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/peripherals.c # driver - ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c + ${MCUX_DIR}/drivers/lpc_gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/common/fsl_common_arm.c + ${MCUX_DIR}/drivers/flexcomm/fsl_flexcomm.c + ${MCUX_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c + ${SDK_DIR}/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_power.c + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${TOP}/lib/sct_neopixel # driver - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/flexcomm - ${SDK_DIR}/drivers/flexcomm/usart - ${SDK_DIR}/drivers/lpc_iocon - ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/sctimer + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/flexcomm + ${MCUX_DIR}/drivers/flexcomm/usart + ${MCUX_DIR}/drivers/lpc_iocon + ${MCUX_DIR}/drivers/lpc_gpio + ${MCUX_DIR}/drivers/sctimer # mcu - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/${MCU_VARIANT} + ${SDK_DIR}/${MCU_DRIVER_VARIANT}/drivers + ${SDK_DIR}/periph ${CMSIS_DIR}/CMSIS/Core/Include ) target_compile_definitions(${BOARD_TARGET} PUBLIC @@ -91,11 +109,13 @@ function(family_add_board BOARD_TARGET) # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM if (RHPORT_DEVICE EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=] ) - elseif (RHPORT_HOST EQUAL 1) + endif () + if (RHPORT_HOST EQUAL 1) target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\) + [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=] + CFG_TUH_USBIP_IP3516=1 ) endif () @@ -114,9 +134,19 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c ${TOP}/lib/sct_neopixel/sct_neopixel.c ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - ${TOP}/src/portable/ohci/ohci.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) + + if (RHPORT_HOST EQUAL 0) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/ohci/ohci.c + ) + elseif (RHPORT_HOST EQUAL 1) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c + ) + endif () + target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ @@ -128,6 +158,8 @@ function(family_configure_example TARGET RTOS) "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs -nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -136,6 +168,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk index fadf852cd..2fc76ed50 100644 --- a/hw/bsp/lpc55/family.mk +++ b/hw/bsp/lpc55/family.mk @@ -1,28 +1,41 @@ UF2_FAMILY_ID = 0x2abc77ec -SDK_DIR = hw/mcu/nxp/mcux-sdk include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m33 -MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) +MCUX_DIR = hw/mcu/nxp/mcuxsdk-core +SDK_DIR = hw/mcu/nxp/mcux-devices-lpc -# Default to Highspeed PORT1 -PORT ?= 1 +# Some variants (e.g. LPC55S28) share drivers with another variant (e.g. LPC55S69) +MCU_DRIVER_VARIANT ?= $(MCU_VARIANT) + +# Default device port to USB1 highspeed, host to USB0 fullspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 CFLAGS += \ -flto \ -D__STARTUP_CLEAR_BSS \ -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \ - -DBOARD_TUD_RHPORT=$(PORT) \ + -DBOARD_TUD_RHPORT=$(RHPORT_DEVICE) \ + -DBOARD_TUH_RHPORT=$(RHPORT_HOST) \ -ifeq ($(PORT), 1) - $(info "PORT1 High Speed") +# port 0 is fullspeed, port 1 is highspeed +ifeq ($(RHPORT_DEVICE), 1) CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + # Port1 controller can only access USB_SRAM + CFLAGS += -DCFG_TUD_MEM_SECTION='__attribute__((section("m_usb_global")))' +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +endif - # LPC55 Highspeed Port1 can only write to USB_SRAM region - CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))' +ifeq ($(RHPORT_HOST), 1) + CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED + CFLAGS += -DCFG_TUH_MEM_SECTION='__attribute__((section("m_usb_global")))' + CFLAGS += -DCFG_TUH_USBIP_IP3516=1 + SRC_C += $(TOP)/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c else - $(info "PORT0 Full Speed") + CFLAGS += -DBOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED endif # mcu driver cause following warnings @@ -31,33 +44,36 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=float-equal LDFLAGS_GCC += \ -nostartfiles \ --specs=nosys.specs --specs=nano.specs \ + -Wl,--defsym=__stack_size__=0x1000 \ + -Wl,--defsym=__heap_size__=0 \ # All source paths should be relative to the top level. -LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_CORE)_flash.ld +LD_FILE ?= $(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld SRC_C += \ - src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ - $(MCU_DIR)/system_$(MCU_CORE).c \ - $(MCU_DIR)/drivers/fsl_clock.c \ - $(MCU_DIR)/drivers/fsl_power.c \ - $(MCU_DIR)/drivers/fsl_reset.c \ - $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ - $(SDK_DIR)/drivers/common/fsl_common_arm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ - lib/sct_neopixel/sct_neopixel.c + $(TOP)/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_power.c \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/fsl_flexcomm.c \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart/fsl_usart.c \ + $(TOP)/lib/sct_neopixel/sct_neopixel.c INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/sct_neopixel \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(MCU_DIR) \ - $(TOP)/$(MCU_DIR)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm/ \ - $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ - $(TOP)/$(SDK_DIR)/drivers/lpc_gpio \ - $(TOP)/$(SDK_DIR)/drivers/sctimer + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_DRIVER_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/LPC5500/periph \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(MCUX_DIR)/drivers/flexcomm/ \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_iocon \ + $(TOP)/$(MCUX_DIR)/drivers/lpc_gpio \ + $(TOP)/$(MCUX_DIR)/drivers/sctimer -SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S +SRC_S += $(TOP)/$(SDK_DIR)/LPC5500/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/maxim/family.c b/hw/bsp/maxim/family.c index 7ad7d6ff9..6ef4c12c1 100644 --- a/hw/bsp/maxim/family.c +++ b/hw/bsp/maxim/family.c @@ -202,7 +202,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake index e6619992f..f0bf9510b 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXA153) +set(MCU_FAMILY MCXA) set(MCU_CORE MCXA153) set(JLINK_DEVICE MCXA153_M33) @@ -15,10 +16,10 @@ function(update_board TARGET) CFG_EXAMPLE_VIDEO_READONLY ) target_sources(${TARGET} PRIVATE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) target_include_directories(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board + ${SDK_DIR}/${MCU_FAMILY}/periph ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk index 34558b43e..caa2e5a3b 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXA153 +MCU_FAMILY = MCXA MCU_CORE = MCXA153 PORT = 0 @@ -9,11 +10,11 @@ CFLAGS += \ -DCFG_EXAMPLE_VIDEO_READONLY SRC_C += \ - ${BOARD_PATH}/board/clock_config.c \ - ${BOARD_PATH}/board/pin_mux.c + ${BOARD_PATH}/clock_config.c \ + ${BOARD_PATH}/pin_mux.c INC += \ - $(TOP)/$(BOARD_PATH)/board + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph JLINK_DEVICE = MCXA153 PYOCD_TARGET = MCXA153 diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c index 599110d7a..599110d7a 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h index d609eb468..d609eb468 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c index 58b0f47e9..58b0f47e9 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h index 4a42f266d..4a42f266d 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake index a6aa6c2e4..0d8ec3229 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXA156) +set(MCU_FAMILY MCXA) set(MCU_CORE MCXA156) set(JLINK_DEVICE MCXA156_M33) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph1 + ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk index d4a59b32a..9d24b5fab 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXA156 +MCU_FAMILY = MCXA MCU_CORE = MCXA156 PORT = 0 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXA156VLH \ -DCFG_TUSB_MCU=OPT_MCU_MCXA15 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph1 + JLINK_DEVICE = MCXA156 PYOCD_TARGET = MCXA156 diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake index 8c3280743..3bf7851bd 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXN947) +set(MCU_FAMILY MCXN) set(MCU_CORE MCXN947_cm33_core0) set(JLINK_DEVICE MCXN947_M33_0) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph + ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk index 22fefd79b..ee1c94f94 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXN947 +MCU_FAMILY = MCXN MCU_CORE = MCXN947_cm33_core0 PORT ?= 1 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXN947VDF_cm33_core0 \ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph + JLINK_DEVICE = MCXN947_M33_0 PYOCD_TARGET = MCXN947 diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake index 8c3280743..3bf7851bd 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake +++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake @@ -1,4 +1,5 @@ set(MCU_VARIANT MCXN947) +set(MCU_FAMILY MCXN) set(MCU_CORE MCXN947_cm33_core0) set(JLINK_DEVICE MCXN947_M33_0) @@ -18,4 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c ) + target_include_directories(${TARGET} PUBLIC + ${SDK_DIR}/${MCU_FAMILY}/periph + ) endfunction() diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk index 22fefd79b..ee1c94f94 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.mk +++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk @@ -1,4 +1,5 @@ MCU_VARIANT = MCXN947 +MCU_FAMILY = MCXN MCU_CORE = MCXN947_cm33_core0 PORT ?= 1 @@ -7,6 +8,9 @@ CFLAGS += \ -DCPU_MCXN947VDF_cm33_core0 \ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \ +INC += \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph + JLINK_DEVICE = MCXN947_M33_0 PYOCD_TARGET = MCXN947 diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index 3b91678b1..a3969c217 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -219,7 +219,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index d062cec16..89e2aadf2 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -1,7 +1,8 @@ include_guard() -set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk) -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core) +set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-mcx) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -26,46 +27,55 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL # Startup & Linker script #------------------------------------ if (NOT DEFINED LD_FILE_GNU) -set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) + set(LD_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + if (NOT DEFINED STARTUP_FILE_GNU) -set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) + set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S) endif() set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) +if (NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf) +endif () + +if (NOT DEFINED STARTUP_FILE_IAR) + set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s) +endif () + #------------------------------------ # Board Target #------------------------------------ function(family_add_board BOARD_TARGET) add_library(${BOARD_TARGET} STATIC # driver - ${SDK_DIR}/drivers/gpio/fsl_gpio.c - ${SDK_DIR}/drivers/common/fsl_common_arm.c - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c + ${MCUX_DIR}/drivers/gpio/fsl_gpio.c + ${MCUX_DIR}/drivers/common/fsl_common_arm.c + ${MCUX_DIR}/drivers/lpuart/fsl_lpuart.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c # mcu - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c - ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_CORE}.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_reset.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMSIS_DIR}/CMSIS/Core/Include - ${SDK_DIR}/drivers/gpio/ - ${SDK_DIR}/drivers/lpuart - ${SDK_DIR}/drivers/common - ${SDK_DIR}/drivers/port + ${MCUX_DIR}/drivers/gpio/ + ${MCUX_DIR}/drivers/lpuart + ${MCUX_DIR}/drivers/common + ${MCUX_DIR}/drivers/port ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc - ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT} + ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers ) if (${FAMILY_MCUS} STREQUAL "MCXN9") target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + ${MCUX_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c ) target_include_directories(${BOARD_TARGET} PUBLIC - ${SDK_DIR}/drivers/lpflexcomm + ${MCUX_DIR}/drivers/lpflexcomm ) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") endif() @@ -100,7 +110,8 @@ function(family_configure_example TARGET RTOS) target_link_options(${TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs - #-nostartfiles + "LINKER:--defsym=__stack_size__=0x1000" + "LINKER:--defsym=__heap_size__=0" ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC @@ -109,6 +120,8 @@ function(family_configure_example TARGET RTOS) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${TARGET} PUBLIC "LINKER:--config=${LD_FILE_IAR}" + "LINKER:--config_def=__stack_size__=0x1000" + "LINKER:--config_def=__heap_size__=0" ) endif () diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index 4321e654a..3d63eb238 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -1,7 +1,9 @@ UF2_FAMILY_ID = 0x2abc77ec -SDK_DIR = hw/mcu/nxp/mcux-sdk include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m33 +MCUX_DIR = hw/mcu/nxp/mcuxsdk-core +SDK_DIR = hw/mcu/nxp/mcux-devices-mcx # Default to Highspeed PORT1 PORT ?= 1 @@ -13,10 +15,13 @@ CFLAGS += \ # mcu driver cause following warnings CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls -LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs +LDFLAGS_GCC += \ + --specs=nosys.specs --specs=nano.specs \ + -Wl,--defsym=__stack_size__=0x1000 \ + -Wl,--defsym=__heap_size__=0 \ # All source paths should be relative to the top level. -LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld +LD_FILE ?= $(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ifeq ($(PORT), 1) @@ -30,17 +35,17 @@ else endif SRC_C += \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ - ${SDK_DIR}/drivers/gpio/fsl_gpio.c \ - ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \ - ${SDK_DIR}/drivers/common/fsl_common_arm.c\ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/system_$(MCU_CORE).c \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_clock.c \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_reset.c \ + $(TOP)/$(MCUX_DIR)/drivers/gpio/fsl_gpio.c \ + $(TOP)/$(MCUX_DIR)/drivers/lpuart/fsl_lpuart.c \ + $(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \ hw/bsp/mcx/drivers/spc/fsl_spc.c # fsl_lpflexcomm for MCXN9 ifeq ($(MCU_VARIANT), MCXN947) - SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + SRC_C += $(MCUX_DIR)/drivers/lpflexcomm/fsl_lpflexcomm.c endif # fsl_spc for MCXNA15 @@ -50,15 +55,15 @@ endif INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ - $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ - $(TOP)/$(SDK_DIR)/drivers/ \ - $(TOP)/$(SDK_DIR)/drivers/lpuart \ - $(TOP)/$(SDK_DIR)/drivers/lpflexcomm \ - $(TOP)/$(SDK_DIR)/drivers/common\ - $(TOP)/$(SDK_DIR)/drivers/gpio\ - $(TOP)/$(SDK_DIR)/drivers/port\ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT) \ + $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers \ + $(TOP)/$(MCUX_DIR)/drivers/ \ + $(TOP)/$(MCUX_DIR)/drivers/lpuart \ + $(TOP)/$(MCUX_DIR)/drivers/lpflexcomm \ + $(TOP)/$(MCUX_DIR)/drivers/common \ + $(TOP)/$(MCUX_DIR)/drivers/gpio \ + $(TOP)/$(MCUX_DIR)/drivers/port \ $(TOP)/hw/bsp/mcx/drivers/spc -SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S +SRC_S += $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c index 663c30818..330b01f6d 100644 --- a/hw/bsp/mm32/family.c +++ b/hw/bsp/mm32/family.c @@ -175,7 +175,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c index 390a9915e..413ad7db6 100644 --- a/hw/bsp/msp430/family.c +++ b/hw/bsp/msp430/family.c @@ -102,10 +102,10 @@ static void SystemClock_Config(void) // VUSB enabled automatically. // Wait two milliseconds to stabilize, per manual recommendation. - uint32_t ms_elapsed = board_millis(); + uint32_t ms_elapsed = tusb_time_millis_api(); do { - while((board_millis() - ms_elapsed) < 2); + while((tusb_time_millis_api() - ms_elapsed) < 2); }while(!(USBPWRCTL & USBBGVBV)); // USB uses XT2 (4 MHz) directly. Enable the PLL. @@ -113,11 +113,11 @@ static void SystemClock_Config(void) USBPLLCTL |= (UPFDEN | UPLLEN); // Wait until PLL locks. Check every 2ms, per manual. - ms_elapsed = board_millis(); + ms_elapsed = tusb_time_millis_api(); do { USBPLLIR &= ~USBOOLIFG; - while((board_millis() - ms_elapsed) < 2); + while((tusb_time_millis_api() - ms_elapsed) < 2); }while(USBPLLIR & USBOOLIFG); USBKEYPID = 0; @@ -207,7 +207,7 @@ void TIMER0_A0_ISR (void) { // TAxCCR0 CCIFG resets itself as soon as interrupt is invoked. } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { uint32_t systick_mirror; diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index 0e1b0528a..90eb945f4 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -202,7 +202,7 @@ void SysTick_Handler(void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index ee3ac61e2..04bfbf320 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -296,7 +296,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/nuc100_120/family.c b/hw/bsp/nuc100_120/family.c index 752af2a56..cfe60121c 100644 --- a/hw/bsp/nuc100_120/family.c +++ b/hw/bsp/nuc100_120/family.c @@ -87,7 +87,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc121_125/family.c b/hw/bsp/nuc121_125/family.c index 089855207..dce5b4d62 100644 --- a/hw/bsp/nuc121_125/family.c +++ b/hw/bsp/nuc121_125/family.c @@ -86,7 +86,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc126/family.c b/hw/bsp/nuc126/family.c index f992fcab4..3343064e5 100644 --- a/hw/bsp/nuc126/family.c +++ b/hw/bsp/nuc126/family.c @@ -111,7 +111,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/nuc505/family.c b/hw/bsp/nuc505/family.c index 00ed92310..f1a77e4a5 100644 --- a/hw/bsp/nuc505/family.c +++ b/hw/bsp/nuc505/family.c @@ -88,7 +88,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c index da97f67a9..2bfc876e1 100644 --- a/hw/bsp/pic32mz/family.c +++ b/hw/bsp/pic32mz/family.c @@ -106,7 +106,7 @@ TU_ATTR_WEAK int board_uart_write(void const * buf, int len) } #if CFG_TUSB_OS == OPT_OS_NONE -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { // COUNTER is system clock (200MHz / 2 = 100MHz) convert to ms) return _CP0_GET_COUNT() / (100000000 / 1000); diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 1f75b47c1..f371e694b 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -169,7 +169,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index a51b3f758..adb58449d 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -370,7 +370,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx }else if (rx_buf == NULL) { ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes); }else { - ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes); + ret = spi_write_read_blocking(MAX3421_SPI, tx_buf, rx_buf, xfer_bytes); } return ret == (int) xfer_bytes; diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 82d0034a1..e31abe50b 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -98,6 +98,7 @@ target_sources(tinyusb_device_base INTERFACE ${TOP}/src/class/mtp/mtp_device.c ${TOP}/src/class/net/ecm_rndis_device.c ${TOP}/src/class/net/ncm_device.c + ${TOP}/src/class/printer/printer_device.c ${TOP}/src/class/usbtmc/usbtmc_device.c ${TOP}/src/class/vendor/vendor_device.c ${TOP}/src/class/video/video_device.c diff --git a/hw/bsp/rw61x/family.c b/hw/bsp/rw61x/family.c index 265d5fcc0..fcc7fb262 100644 --- a/hw/bsp/rw61x/family.c +++ b/hw/bsp/rw61x/family.c @@ -128,7 +128,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c index 26ad4a6aa..e5b24bf69 100644 --- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c +++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c @@ -248,7 +248,7 @@ void INT_Excep_CMT0_CMI0(void) ++system_ticks; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c index 66a319541..d5c2de05a 100644 --- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c +++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c @@ -299,7 +299,7 @@ void INT_Excep_CMT0_CMI0(void) ++system_ticks; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c index 6cbf02412..bccbac8ea 100644 --- a/hw/bsp/samd11/family.c +++ b/hw/bsp/samd11/family.c @@ -155,7 +155,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd2x_l2x/family.c b/hw/bsp/samd2x_l2x/family.c index a2dc8a8d4..737219b6c 100644 --- a/hw/bsp/samd2x_l2x/family.c +++ b/hw/bsp/samd2x_l2x/family.c @@ -361,7 +361,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index 5a7105894..c008b9719 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -210,7 +210,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.cmake b/hw/bsp/same7x/boards/same70_qmtech/board.cmake index cde4c3da6..fc2071b3a 100644 --- a/hw/bsp/same7x/boards/same70_qmtech/board.cmake +++ b/hw/bsp/same7x/boards/same70_qmtech/board.cmake @@ -1,5 +1,8 @@ -set(JLINK_DEVICE SAME70N19B) -set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld) +set(JLINK_DEVICE ATSAME70N19B) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same70n19b_flash.ld) + +# N19B and Q21B share the same vector table / startup code +set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/same7x/boards/same70_qmtech/board.mk b/hw/bsp/same7x/boards/same70_qmtech/board.mk index 09ae98860..4ad8212a8 100644 --- a/hw/bsp/same7x/boards/same70_qmtech/board.mk +++ b/hw/bsp/same7x/boards/same70_qmtech/board.mk @@ -1,3 +1,6 @@ CFLAGS += -D__SAME70N19B__ -JLINK_DEVICE = SAME70N19B +LD_FILE = $(BOARD_PATH)/same70n19b_flash.ld +STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c + +JLINK_DEVICE = ATSAME70N19B diff --git a/hw/bsp/same7x/boards/same70_xplained/board.cmake b/hw/bsp/same7x/boards/same70_xplained/board.cmake index b226b6c4f..f762464a6 100644 --- a/hw/bsp/same7x/boards/same70_xplained/board.cmake +++ b/hw/bsp/same7x/boards/same70_xplained/board.cmake @@ -1,5 +1,9 @@ -set(JLINK_DEVICE SAME70Q21B) +set(JLINK_DEVICE ATSAME70Q21B) set(LD_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/same70q21b_flash.ld) +set(LD_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf) + +set(STARTUP_FILE_GNU ${TOP}/hw/mcu/microchip/same70/same70b/gcc/gcc/startup_same70q21b.c) +set(STARTUP_FILE_IAR ${TOP}/hw/mcu/microchip/same70/same70b/iar/iar/startup_same70q21b.c) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/same7x/boards/same70_xplained/board.mk b/hw/bsp/same7x/boards/same70_xplained/board.mk index ca23a9be5..231d5d770 100644 --- a/hw/bsp/same7x/boards/same70_xplained/board.mk +++ b/hw/bsp/same7x/boards/same70_xplained/board.mk @@ -1,3 +1,6 @@ CFLAGS += -D__SAME70Q21B__ -JLINK_DEVICE = SAME70Q21B +LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld +STARTUP_FILE = $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c + +JLINK_DEVICE = ATSAME70Q21B diff --git a/hw/bsp/same7x/family.c b/hw/bsp/same7x/family.c index 6feefa3b5..61c1792d1 100644 --- a/hw/bsp/same7x/family.c +++ b/hw/bsp/same7x/family.c @@ -42,56 +42,15 @@ static inline void board_vbus_set(uint8_t rhport, bool state); void _init(void); #include "board.h" -#ifndef LED_STATE_ON - #define LED_STATE_ON 1 -#endif - -#ifndef LED_PORT_CLOCK - #define LED_PORT_CLOCK ID_PIOA -#endif - -#ifndef BUTTON_PORT_CLOCK - #define BUTTON_PORT_CLOCK ID_PIOA -#endif - -#ifndef UART_PORT_CLOCK - #define UART_PORT_CLOCK ID_USART1 -#endif - -#ifndef BOARD_USART - #define BOARD_USART USART1 -#endif - -#ifndef BOARD_UART_DESCRIPTOR - #define BOARD_UART_DESCRIPTOR edbg_com -#endif - -#ifndef BOARD_UART_BUFFER - #define BOARD_UART_BUFFER edbg_com_buffer -#endif - -#ifndef BUTTON_STATE_ACTIVE - #define BUTTON_STATE_ACTIVE 0 -#endif - -#ifndef UART_TX_FUNCTION - #define UART_TX_FUNCTION MUX_PB4D_USART1_TXD1 -#endif - -#ifndef UART_RX_FUNCTION - #define UART_RX_FUNCTION MUX_PA21A_USART1_RXD1 -#endif - #ifndef UART_BUFFER_SIZE #define UART_BUFFER_SIZE 64 #endif #define LED_STATE_OFF (1 - LED_STATE_ON) -static struct usart_async_descriptor BOARD_UART_DESCRIPTOR; -static uint8_t BOARD_UART_BUFFER[UART_BUFFER_SIZE]; +static struct usart_async_descriptor edbg_com; +static uint8_t edbg_com_buffer[UART_BUFFER_SIZE]; static volatile bool uart_busy = false; - static void tx_complete_cb(const struct usart_async_descriptor *const io_descr) { (void) io_descr; uart_busy = false; @@ -121,10 +80,10 @@ void board_init(void) { gpio_set_pin_function(UART_RX_PIN, UART_RX_FUNCTION); gpio_set_pin_function(UART_TX_PIN, UART_TX_FUNCTION); - usart_async_init(&BOARD_UART_DESCRIPTOR, BOARD_USART, BOARD_UART_BUFFER, sizeof(BOARD_UART_BUFFER), _usart_get_usart_async()); - usart_async_set_baud_rate(&BOARD_UART_DESCRIPTOR, CFG_BOARD_UART_BAUDRATE); - usart_async_register_callback(&BOARD_UART_DESCRIPTOR, USART_ASYNC_TXC_CB, tx_complete_cb); - usart_async_enable(&BOARD_UART_DESCRIPTOR); + usart_async_init(&edbg_com, BOARD_USART, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async()); + usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE); + usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_complete_cb); + usart_async_enable(&edbg_com); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer (SystemCoreClock may not be correct after init) @@ -181,10 +140,40 @@ int board_uart_write(void const *buf, int len) { while (uart_busy) {} uart_busy = true; - io_write(&BOARD_UART_DESCRIPTOR.io, buf, len); + io_write(&edbg_com.io, buf, len); return len; } +// Read 128-bit unique ID via EFC STUI/SPUI commands +// Must run from RAM since STUI remaps flash to the unique ID +__attribute__((noinline)) TU_ATTR_SECTION(.ramfunc) static void read_unique_id(uint32_t uid[4]) { + // Wait for flash to be ready + while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {} + + // Issue Start Read Unique Identifier command + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_STUI; + while (EFC->EEFC_FSR & EEFC_FSR_FRDY) {} + + // Read 128-bit unique ID from flash base address + const volatile uint32_t *flash = (const volatile uint32_t *) IFLASH_ADDR; + for (int i = 0; i < 4; i++) { + uid[i] = flash[i]; + } + + // Issue Stop Read Unique Identifier command + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SPUI; + while (!(EFC->EEFC_FSR & EEFC_FSR_FRDY)) {} +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + const size_t uid_len = 16; + if (max_len < uid_len) { + return 0; + } + read_unique_id((uint32_t *)(uintptr_t) id); + return uid_len; +} + #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; @@ -192,7 +181,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/same7x/family.cmake b/hw/bsp/same7x/family.cmake index a9c9de413..63726a8e5 100644 --- a/hw/bsp/same7x/family.cmake +++ b/hw/bsp/same7x/family.cmake @@ -13,7 +13,6 @@ set(FAMILY_MCUS SAMX7X CACHE INTERNAL "") #------------------------------------ # Startup & Linker script #------------------------------------ -set(STARTUP_FILE_GNU ${SDK_DIR}/same70b/gcc/gcc/startup_same70q21b.c) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) set(LD_FILE_Clang ${LD_FILE_GNU}) @@ -47,12 +46,9 @@ function(family_add_board BOARD_TARGET) update_board(${BOARD_TARGET}) - target_compile_options(${BOARD_TARGET} PUBLIC - -Wno-error=unused-parameter - -Wno-error=cast-align - -Wno-error=redundant-decls - -Wno-error=cast-qual - ) + if (TOOLCHAIN STREQUAL "gcc" OR TOOLCHAIN STREQUAL "clang") + set_target_properties(${BOARD_TARGET} PROPERTIES COMPILE_FLAGS -Wno-error=cast-qual) + endif () endfunction() #------------------------------------ @@ -89,9 +85,13 @@ function(family_configure_example TARGET RTOS) "LINKER:--config=${LD_FILE_IAR}" ) endif () - set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES - SKIP_LINTING ON - COMPILE_OPTIONS -w) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + # ignore hal error + set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + PROPERTIES + SKIP_LINTING ON + COMPILE_OPTIONS -w) + endif() family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) diff --git a/hw/bsp/same7x/family.mk b/hw/bsp/same7x/family.mk index c8fa74d71..19e119625 100644 --- a/hw/bsp/same7x/family.mk +++ b/hw/bsp/same7x/family.mk @@ -21,11 +21,9 @@ CFLAGS_SKIP += -Wcast-qual LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs # All source paths should be relative to the top level. -LD_FILE = $(SDK_DIR)/same70b/gcc/gcc/same70q21b_flash.ld - SRC_C += \ src/portable/microchip/samx7x/dcd_samx7x.c \ - $(SDK_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ + $(STARTUP_FILE) \ $(SDK_DIR)/same70b/gcc/system_same70q21b.c \ $(SDK_DIR)/hpl/core/hpl_init.c \ $(SDK_DIR)/hpl/usart/hpl_usart.c \ @@ -48,9 +46,6 @@ INC += \ $(TOP)/$(SDK_DIR)/hri \ $(TOP)/$(SDK_DIR)/CMSIS/Core/Include -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7 - # For flash-jlink target flash: $(BUILD)/$(PROJECT).bin edbg --verbose -t same70 -pv -f $< diff --git a/hw/bsp/samg/family.c b/hw/bsp/samg/family.c index 5c5fc3c14..b27134305 100644 --- a/hw/bsp/samg/family.c +++ b/hw/bsp/samg/family.c @@ -148,7 +148,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c index e2ba47f45..e20c0ee15 100644 --- a/hw/bsp/stm32c0/family.c +++ b/hw/bsp/stm32c0/family.c @@ -173,7 +173,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index b99b0a8cc..5a35a3e50 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -160,7 +160,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 3147061cf..78a425453 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -148,12 +148,12 @@ void board_init(void) { #ifdef USB_CONNECT_PIN void dcd_disconnect(uint8_t rhport) { (void)rhport; - HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, 1-USB_CONNECT_STATE); + HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)(1 - USB_CONNECT_STATE)); } void dcd_connect(uint8_t rhport) { (void)rhport; - HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, USB_CONNECT_STATE); + HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, (GPIO_PinState)USB_CONNECT_STATE); } #endif @@ -202,7 +202,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c index f95128040..f1fd4ddb2 100644 --- a/hw/bsp/stm32f2/family.c +++ b/hw/bsp/stm32f2/family.c @@ -35,7 +35,7 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void OTG_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } //--------------------------------------------------------------------+ @@ -145,7 +145,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c index 95bcc7882..fde1e9f6d 100644 --- a/hw/bsp/stm32f3/family.c +++ b/hw/bsp/stm32f3/family.c @@ -156,7 +156,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h deleted file mode 100644 index b892df3b6..000000000 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h deleted file mode 100644 index b892df3b6..000000000 --- a/hw/bsp/stm32f4/boards/pyboardv11/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index 16f081cfb..000000000 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake index d16db508f..f54807c2a 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake @@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F411xE + HSE_VALUE=25000000 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk index 7af7ca47c..c45aba79b 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F411xE +CFLAGS += -DSTM32F411xE -DHSE_VALUE=25000000 # GCC SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index 16f081cfb..000000000 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h deleted file mode 100644 index e24e782ea..000000000 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h deleted file mode 100644 index 7bbd6b54f..000000000 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,486 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* LAN8742A_PHY_ADDRESS Address*/ -#define LAN8742A_PHY_ADDRESS 0U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index f0e9620f2..665ea114a 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -251,7 +251,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index c3c41dc3f..f3e74ecea 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -71,6 +71,7 @@ SRC_C += \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c INC += \ + $(TOP)/hw/bsp/stm32$(ST_FAMILY) \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index d8f0da201..ce9049abe 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -312,7 +312,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index 4b175b0ec..b25897264 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -181,7 +181,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index d8afa0f95..2e13a1d4b 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -211,7 +211,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c index fdb12e44f..1e8acd502 100644 --- a/hw/bsp/stm32h5/family.c +++ b/hw/bsp/stm32h5/family.c @@ -207,7 +207,7 @@ void SysTick_Handler(void) { HAL_IncTick(); } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 44ca58dc5..d2f61a5ce 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -120,13 +120,13 @@ static inline void SystemClock_Config(void) { // From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals // are shared with other peripherals. Trace CLK = PLL1R. RCC_OscInitStruct.PLL.PLLM = 5; - RCC_OscInitStruct.PLL.PLLN = 160; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 6; // Trace clock is 400/6 = 66.67 MHz (larger than 50 MHz but work well) + RCC_OscInitStruct.PLL.PLLN = 160; // May reduce to 100/200 Mhz when tracing to avoid overflowing trace buffer + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = RCC_OscInitStruct.PLL.PLLN/10; // Trace clock is limit to 50 Mhz to meet board requirement + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; RCC_OscInitStruct.PLL.PLLFRACN = 0; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; HAL_RCC_OscConfig(&RCC_OscInitStruct); diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc index 0e5a4cc00..a2e11012f 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc +++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc @@ -193,8 +193,8 @@ Mcu.PinsNb=169 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H743XIHx -MxCube.Version=6.10.0 -MxDb.Version=DB.6.0.100 +MxCube.Version=6.12.1 +MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -880,12 +880,12 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H743XIHx -ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0 +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.2 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=false +ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=2 ProjectManager.MainLocation=Src ProjectManager.NoMain=false @@ -933,8 +933,8 @@ RCC.DIVQ1Freq_Value=200000000 RCC.DIVQ2Freq_Value=50390625 RCC.DIVQ3=7 RCC.DIVQ3Freq_Value=48000000 -RCC.DIVR1=6 -RCC.DIVR1Freq_Value=133333333.33333333 +RCC.DIVR1=8 +RCC.DIVR1Freq_Value=100000000 RCC.DIVR2Freq_Value=50390625 RCC.DIVR3Freq_Value=168000000 RCC.EnbaleCSS=true @@ -979,7 +979,7 @@ RCC.SYSCLKFreq_VALUE=400000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.Tim1OutputFreq_Value=200000000 RCC.Tim2OutputFreq_Value=200000000 -RCC.TraceFreq_Value=133333333.33333333 +RCC.TraceFreq_Value=100000000 RCC.USART16Freq_Value=100000000 RCC.USART234578Freq_Value=100000000 RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3 diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug index 0ab078319..32a8155c1 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug +++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug @@ -9,6 +9,10 @@ ********************************************************************** */ void OnProjectLoad (void) { + Project.SetTraceSource ("Trace Pins"); + Project.SetTraceTiming (100, 100, 100, 100); + Project.SetSWO (0); + Edit.SysVar (VAR_TRACE_CORE_CLOCK, 200000000); Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd"); Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd"); Project.AddSvdFile ("./STM32H743.svd"); @@ -18,12 +22,8 @@ void OnProjectLoad (void) { Project.SetTargetIF ("SWD"); Project.SetTIFSpeed ("50 MHz"); - Project.SetTraceSource ("Trace Pins"); - Project.SetTracePortWidth (4); - // timing delay for trace pins in pico seconds, default is 2 nano seconds - Project.SetTraceTiming (100, 100, 100, 100); - File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf"); + // File.Open ("../../../../../../examples/cmake-build-stm32h743eval_host1/host/cdc_msc_hid/cdc_msc_hid.elf"); } /********************************************************************* diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index a320a7e72..c94c2e755 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -139,6 +139,10 @@ void board_init(void) { #endif NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + +#elif CFG_TUSB_OS == OPT_OS_THREADX + // Disable SysTick before kernel entry; _tx_initialize_low_level() will re-configure it + SysTick->CTRL &= ~1UL; #endif GPIO_InitTypeDef GPIO_InitStruct; @@ -295,10 +299,15 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } +#elif CFG_TUSB_OS == OPT_OS_THREADX +// Keep HAL_GetTick() working for HAL functions called from board_init() +void osal_threadx_tick_cb(void) { + HAL_IncTick(); +} #endif void HardFault_Handler(void) { diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h index 16c2fd335..4b8564709 100644 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h @@ -62,7 +62,7 @@ static board_pindef_t board_pindef[] = { { // Button .port = GPIOC, .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0 }, - .active_state = 1 + .active_state = 0 }, { // UART TX .port = GPIOD, diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c index 2cc39b7ac..3bf75ba97 100644 --- a/hw/bsp/stm32h7rs/family.c +++ b/hw/bsp/stm32h7rs/family.c @@ -468,7 +468,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c index 6aeab1259..7fd076dbd 100644 --- a/hw/bsp/stm32l0/family.c +++ b/hw/bsp/stm32l0/family.c @@ -123,7 +123,8 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); } uint32_t board_button_read(void) { @@ -168,7 +169,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c index 65f6b9ab3..c87b643b8 100644 --- a/hw/bsp/stm32l4/family.c +++ b/hw/bsp/stm32l4/family.c @@ -231,7 +231,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c index c839e6b3e..4354616c3 100644 --- a/hw/bsp/stm32n6/family.c +++ b/hw/bsp/stm32n6/family.c @@ -366,7 +366,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32u0/family.c b/hw/bsp/stm32u0/family.c index 50b513d8f..0f91d1f30 100644 --- a/hw/bsp/stm32u0/family.c +++ b/hw/bsp/stm32u0/family.c @@ -174,7 +174,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index dfcf5c537..55ca25d58 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -270,7 +270,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 153d10a09..de503c072 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -174,7 +174,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c index d05415755..878355b48 100644 --- a/hw/bsp/stm32wba/family.c +++ b/hw/bsp/stm32wba/family.c @@ -175,7 +175,10 @@ void board_init(void) { #endif // USB_OTG_HS } -void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } +void board_led_write(bool state) { + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +} uint32_t board_button_read(void) { return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE; } @@ -198,7 +201,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { return system_ticks; } +uint32_t tusb_time_millis_api(void) { return system_ticks; } #endif void HardFault_Handler(void) { asm( "bkpt 1" ); } diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c index ae7f22f00..503d0a8c9 100644 --- a/hw/bsp/tm4c/family.c +++ b/hw/bsp/tm4c/family.c @@ -211,7 +211,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index 6fef53025..d0acd04cb 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -147,7 +147,7 @@ void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) { +uint32_t tusb_time_millis_api(void) { return system_ticks; } diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c index e2849fb10..5e824d5a5 100644 --- a/lib/networking/rndis_reports.c +++ b/lib/networking/rndis_reports.c @@ -44,7 +44,7 @@ static const uint8_t *const permanent_hwaddr = tud_network_mac_address; static usb_eth_stat_t usb_eth_stat = { 0, 0, 0, 0 }; static uint32_t oid_packet_filter = 0x0000000; -static rndis_state_t rndis_state; +TU_ATTR_UNUSED static rndis_state_t rndis_state; static const uint32_t OIDSupportedList[] = { diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 48dc75e50..00f466007 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -19,6 +19,7 @@ function(tinyusb_sources_get OUTPUT_VAR) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/mtp/mtp_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/printer/printer_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index be0224811..995bf8a3e 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -147,7 +147,9 @@ tu_static CFG_TUD_MEM_SECTION struct { #endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_EDPT_DEDICATED_HWFIFO // Control buffer -CFG_TUD_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_AUDIO_CTRL_BUF_SZ]; +#if CFG_TUD_AUDIO_CTRL_BUF_SZ > CFG_TUD_ENDPOINT0_BUFSIZE +tu_static CFG_TUD_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_AUDIO_CTRL_BUF_SZ]; +#endif // Aligned buffer for feedback EP #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP @@ -423,6 +425,15 @@ bool tud_audio_n_mounted(uint8_t func_id) { return audio->mounted; } +static inline uint8_t* get_ctrl_buffer(void) { + // Use EP0 buffer if it is large enough, otherwise use dedicated buffer + #if CFG_TUD_AUDIO_CTRL_BUF_SZ > CFG_TUD_ENDPOINT0_BUFSIZE + return ctrl_buf; + #else + return usbd_get_ctrl_buf(); + #endif +} + //--------------------------------------------------------------------+ // READ API //--------------------------------------------------------------------+ @@ -1296,20 +1307,20 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const if (tud_audio_n_version(func_id) == 2) { uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue); if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO20_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO20_CS_REQ_CUR) { - _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(ctrl_buf); + _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(get_ctrl_buffer()); audiod_calc_tx_packet_sz(&_audiod_fct[func_id]); } } #endif // Invoke callback - return tud_audio_set_req_entity_cb(rhport, p_request, ctrl_buf); + return tud_audio_set_req_entity_cb(rhport, p_request, get_ctrl_buffer()); } else { // Find index of audio driver structure and verify interface really exists TU_VERIFY(audiod_verify_itf_exists(itf, &func_id)); // Invoke callback - return tud_audio_set_req_itf_cb(rhport, p_request, ctrl_buf); + return tud_audio_set_req_itf_cb(rhport, p_request, get_ctrl_buffer()); } } break; @@ -1324,7 +1335,7 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const if (_audiod_fct[func_id].ep_in == ep) { uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue); if (ctrlSel == AUDIO10_EP_CTRL_SAMPLING_FREQ && p_request->bRequest == AUDIO10_CS_REQ_SET_CUR) { - _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(ctrl_buf) & 0x00FFFFFF; + _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(get_ctrl_buffer()) & 0x00FFFFFF; audiod_calc_tx_packet_sz(&_audiod_fct[func_id]); } } @@ -1332,7 +1343,7 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const #endif // Invoke callback - bool ret = tud_audio_set_req_ep_cb(rhport, p_request, ctrl_buf); + bool ret = tud_audio_set_req_ep_cb(rhport, p_request, get_ctrl_buffer()); #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP if (ret && tud_audio_n_version(func_id) == 1) { @@ -1429,7 +1440,7 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const } // If we end here, the received request is a set request - we schedule a receive for the data stage and return true here. We handle the rest later in audiod_control_complete() once the data stage was finished - TU_VERIFY(tud_control_xfer(rhport, p_request, ctrl_buf, sizeof(ctrl_buf))); + TU_VERIFY(tud_control_xfer(rhport, p_request, get_ctrl_buffer(), CFG_TUD_AUDIO_CTRL_BUF_SZ)); return true; } @@ -1695,11 +1706,8 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req return false; } - // Crop length - if (len > sizeof(ctrl_buf)) len = sizeof(ctrl_buf); - // Copy into buffer - TU_VERIFY(0 == tu_memcpy_s(ctrl_buf, sizeof(ctrl_buf), data, (size_t) len)); + TU_VERIFY(0 == tu_memcpy_s(get_ctrl_buffer(), CFG_TUD_AUDIO_CTRL_BUF_SZ, data, (size_t) len)); #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL if (tud_audio_n_version(func_id) == 2) { @@ -1708,7 +1716,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req uint8_t entityID = TU_U16_HIGH(p_request->wIndex); uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue); if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO20_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO20_CS_REQ_CUR) { - _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(ctrl_buf); + _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(get_ctrl_buffer()); audiod_calc_tx_packet_sz(&_audiod_fct[func_id]); } } @@ -1716,7 +1724,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req #endif // Schedule transmit - return tud_control_xfer(rhport, p_request, ctrl_buf, len); + return tud_control_xfer(rhport, p_request, get_ctrl_buffer(), len); } // Verify an entity with the given ID exists and returns also the corresponding driver index diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index e2819ae4b..c7547c92b 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -63,10 +63,10 @@ typedef struct { #define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, line_coding) // Skip local EP buffer if dedicated hw FIFO is supported - #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 +#if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 typedef struct { - TUD_EPBUF_DEF(epout, CFG_TUD_CDC_EP_BUFSIZE); - TUD_EPBUF_DEF(epin, CFG_TUD_CDC_EP_BUFSIZE); + TUD_EPBUF_DEF(epout, CFG_TUD_CDC_RX_EPSIZE); + TUD_EPBUF_DEF(epin, CFG_TUD_CDC_TX_EPSIZE); #if CFG_TUD_CDC_NOTIFY TUD_EPBUF_TYPE_DEF(cdc_notify_msg_t, epnotify); @@ -116,7 +116,7 @@ TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms) { // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; -static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT(); +static tud_cdc_configure_t _cdcd_cfg = CFG_TUD_CDC_CONFIGURE_DEFAULT(); TU_ATTR_ALWAYS_INLINE static inline uint8_t find_cdc_itf(uint8_t ep_addr) { for (uint8_t idx = 0; idx < CFG_TUD_CDC; idx++) { @@ -267,14 +267,13 @@ void cdcd_init(void) { uint8_t *epin_buf = _cdcd_epbuf[i].epin; #endif - tu_edpt_stream_init(&p_cdc->rx_stream, false, false, false, p_cdc->rx_ff_buf, CFG_TUD_CDC_RX_BUFSIZE, epout_buf, - CFG_TUD_CDC_EP_BUFSIZE); + tu_edpt_stream_init(&p_cdc->rx_stream, false, false, false, p_cdc->rx_ff_buf, CFG_TUD_CDC_RX_BUFSIZE, epout_buf); // TX fifo can be configured to change to overwritable if not connected (DTR bit not set). Without DTR we do not // know if data is actually polled by terminal. This way the most current data is prioritized. // Default: is overwritable tu_edpt_stream_init(&p_cdc->tx_stream, false, true, _cdcd_cfg.tx_overwritabe_if_not_connected, p_cdc->tx_ff_buf, - CFG_TUD_CDC_TX_BUFSIZE, epin_buf, CFG_TUD_CDC_EP_BUFSIZE); + CFG_TUD_CDC_TX_BUFSIZE, epin_buf); } } @@ -348,8 +347,7 @@ uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16 TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { tu_edpt_stream_t *stream_tx = &p_cdc->tx_stream; - - tu_edpt_stream_open(stream_tx, rhport, desc_ep); + tu_edpt_stream_open(stream_tx, rhport, desc_ep, CFG_TUD_CDC_TX_EPSIZE); if (_cdcd_cfg.tx_persistent) { tu_edpt_stream_write_xfer(stream_tx); // flush pending data } else { @@ -357,8 +355,8 @@ uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16 } } else { tu_edpt_stream_t *stream_rx = &p_cdc->rx_stream; - - tu_edpt_stream_open(stream_rx, rhport, desc_ep); + tu_edpt_stream_open(stream_rx, rhport, desc_ep, + CFG_TUD_CDC_RX_NEED_ZLP ? CFG_TUD_CDC_RX_EPSIZE : tu_edpt_packet_size(desc_ep)); if (!_cdcd_cfg.rx_persistent) { tu_edpt_stream_clear(stream_rx); } @@ -513,7 +511,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ } // Data sent to host, we continue to fetch from tx fifo to send. - // Note: This will cause incorrect baudrate set in line coding. Though maybe the baudrate is not really important ! + // Note: This will cause incorrect baudrate set in line coding. Though maybe the baudrate is not really important! if (ep_addr == stream_tx->ep_addr) { tud_cdc_tx_complete_cb(itf); // invoke callback to possibly refill tx fifo diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index 0809b578f..0348bd2ec 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -29,6 +29,10 @@ #include "cdc.h" +#ifdef __cplusplus + extern "C" { +#endif + //--------------------------------------------------------------------+ // Class Driver Configuration //--------------------------------------------------------------------+ @@ -37,41 +41,52 @@ #endif #ifndef CFG_TUD_CDC_TX_BUFSIZE - #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + #define CFG_TUD_CDC_TX_BUFSIZE TUD_EPSIZE_BULK_MAX #endif #ifndef CFG_TUD_CDC_RX_BUFSIZE - #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + #define CFG_TUD_CDC_RX_BUFSIZE TUD_EPSIZE_BULK_MAX #endif -#if !defined(CFG_TUD_CDC_EP_BUFSIZE) && defined(CFG_TUD_CDC_EPSIZE) - #warning CFG_TUD_CDC_EPSIZE is renamed to CFG_TUD_CDC_EP_BUFSIZE, please update to use the new name - #define CFG_TUD_CDC_EP_BUFSIZE CFG_TUD_CDC_EPSIZE +// EP_BUFSIZE is separated to RX_EPSIZE and TX_EPSIZE +#ifndef CFG_TUD_CDC_RX_EPSIZE + #ifdef CFG_TUD_CDC_EP_BUFSIZE + #define CFG_TUD_CDC_RX_EPSIZE CFG_TUD_CDC_EP_BUFSIZE + #else + #define CFG_TUD_CDC_RX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif #endif -#ifndef CFG_TUD_CDC_EP_BUFSIZE - #define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#ifndef CFG_TUD_CDC_TX_EPSIZE + #ifdef CFG_TUD_CDC_EP_BUFSIZE + #define CFG_TUD_CDC_TX_EPSIZE CFG_TUD_CDC_EP_BUFSIZE + #else + #define CFG_TUD_CDC_TX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif #endif -#ifdef __cplusplus - extern "C" { +// Enable multi-packet RX transfer with ZLP termination for better throughput. Requires host support for ZLP. +#ifndef CFG_TUD_CDC_RX_NEED_ZLP + #define CFG_TUD_CDC_RX_NEED_ZLP 0 +#endif + +#ifndef CFG_TUD_CDC_CONFIGURE_DEFAULT + #define CFG_TUD_CDC_CONFIGURE_DEFAULT() \ + { \ + .rx_persistent = false, \ + .tx_persistent = false, \ + .tx_overwritabe_if_not_connected = true, \ + } #endif //--------------------------------------------------------------------+ // Driver Configuration //--------------------------------------------------------------------+ -typedef struct TU_ATTR_PACKED { - bool rx_persistent : 1; // keep rx fifo data even with bus reset or disconnect - bool tx_persistent : 1; // keep tx fifo data even with reset or disconnect - bool tx_overwritabe_if_not_connected : 1; // if not connected, tx fifo can be overwritten +typedef struct { + bool rx_persistent; // keep rx fifo data even with bus reset or disconnect + bool tx_persistent; // keep tx fifo data even with reset or disconnect + bool tx_overwritabe_if_not_connected; // if not connected, tx fifo can be overwritten } tud_cdc_configure_t; -TU_VERIFY_STATIC(sizeof(tud_cdc_configure_t) == 1, "size is not correct"); - -#define TUD_CDC_CONFIGURE_DEFAULT() { \ - .rx_persistent = false, \ - .tx_persistent = false, \ - .tx_overwritabe_if_not_connected = true, \ -} // Configure CDC driver behavior bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg); @@ -84,13 +99,13 @@ bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg); // Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1 //--------------------------------------------------------------------+ -// Check if interface is ready +// Check if the interface is ready bool tud_cdc_n_ready(uint8_t itf); -// Check if terminal is connected to this port +// Check if the terminal is connected to this port bool tud_cdc_n_connected(uint8_t itf); -// Get current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) +// Get the current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) uint8_t tud_cdc_n_get_line_state(uint8_t itf); // Get current line encoding: bit rate, stop bits parity etc .. @@ -136,10 +151,9 @@ uint32_t tud_cdc_n_write_flush(uint8_t itf); // Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation. uint32_t tud_cdc_n_write_available(uint8_t itf); -// Clear the transmit FIFO +// Clear the TX FIFO bool tud_cdc_n_write_clear(uint8_t itf); - #if CFG_TUD_CDC_NOTIFY bool tud_cdc_n_notify_msg(uint8_t itf, cdc_notify_msg_t *msg); diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 8f6dd7200..62c313b83 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -650,10 +650,10 @@ bool cdch_init(void) { for (size_t i = 0; i < CFG_TUH_CDC; i++) { cdch_interface_t *p_cdc = &cdch_data[i]; cdch_epbuf_t *epbuf = &cdch_epbuf[i]; - TU_ASSERT(tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, - epbuf->tx, CFG_TUH_CDC_TX_EPSIZE)); + TU_ASSERT(tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, + CFG_TUH_CDC_TX_BUFSIZE, epbuf->tx)); TU_ASSERT(tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false, p_cdc->stream.rx_ff_buf, - CFG_TUH_CDC_RX_BUFSIZE, epbuf->rx, CFG_TUH_CDC_RX_EPSIZE)); + CFG_TUH_CDC_RX_BUFSIZE, epbuf->rx)); } return true; @@ -737,7 +737,7 @@ static bool open_ep_stream_pair(cdch_interface_t *p_cdc, tusb_desc_endpoint_t co TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep)); const uint8_t ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); tu_edpt_stream_t *stream = (ep_dir == TUSB_DIR_IN) ? &p_cdc->stream.rx : &p_cdc->stream.tx; - tu_edpt_stream_open(stream, p_cdc->daddr, desc_ep); + tu_edpt_stream_open(stream, p_cdc->daddr, desc_ep, tu_edpt_packet_size(desc_ep)); tu_edpt_stream_clear(stream); desc_ep = (const tusb_desc_endpoint_t *)tu_desc_next(desc_ep); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 57919c7ff..1b1709b18 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -39,22 +39,22 @@ extern "C" { // RX FIFO size #ifndef CFG_TUH_CDC_RX_BUFSIZE - #define CFG_TUH_CDC_RX_BUFSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_CDC_RX_BUFSIZE TUH_EPSIZE_BULK_MAX #endif // RX Endpoint size #ifndef CFG_TUH_CDC_RX_EPSIZE - #define CFG_TUH_CDC_RX_EPSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_CDC_RX_EPSIZE TUH_EPSIZE_BULK_MAX #endif // TX FIFO size #ifndef CFG_TUH_CDC_TX_BUFSIZE - #define CFG_TUH_CDC_TX_BUFSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_CDC_TX_BUFSIZE TUH_EPSIZE_BULK_MAX #endif // TX Endpoint size #ifndef CFG_TUH_CDC_TX_EPSIZE - #define CFG_TUH_CDC_TX_EPSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_CDC_TX_EPSIZE TUH_EPSIZE_BULK_MAX #endif //--------------------------------------------------------------------+ diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index d3cc53918..ee57621b8 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -60,7 +60,9 @@ typedef struct { static dfu_state_ctx_t _dfu_ctx; +#if CFG_TUD_DFU_XFER_BUFSIZE > CFG_TUD_ENDPOINT0_BUFSIZE TU_ATTR_ALIGNED(4) uint8_t _transfer_buf[CFG_TUD_DFU_XFER_BUFSIZE]; +#endif static void reset_state(void) { _dfu_ctx.state = DFU_IDLE; @@ -68,6 +70,15 @@ static void reset_state(void) { _dfu_ctx.flashing_in_progress = false; } +static inline uint8_t* get_xfer_buffer(void) { + // Use EP0 buffer if it is large enough, otherwise use dedicated buffer + #if CFG_TUD_DFU_XFER_BUFSIZE > CFG_TUD_ENDPOINT0_BUFSIZE + return _transfer_buf; + #else + return usbd_get_ctrl_buf(); + #endif +} + static bool reply_getstatus(uint8_t rhport, const tusb_control_request_t* request, dfu_state_t state, dfu_status_t status, uint32_t timeout); static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request); static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request); @@ -283,10 +294,10 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_UPLOAD); TU_VERIFY(request->wLength <= CFG_TUD_DFU_XFER_BUFSIZE); - const uint16_t xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, _transfer_buf, + const uint16_t xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, get_xfer_buffer(), request->wLength); - return tud_control_xfer(rhport, request, _transfer_buf, xfer_len); + return tud_control_xfer(rhport, request, get_xfer_buffer(), xfer_len); } break; @@ -306,7 +317,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control if (request->wLength > 0) { // Download with payload -> transition to DOWNLOAD SYNC _dfu_ctx.state = DFU_DNLOAD_SYNC; - return tud_control_xfer(rhport, request, _transfer_buf, request->wLength); + return tud_control_xfer(rhport, request, get_xfer_buffer(), request->wLength); } else { // Download is complete -> transition to MANIFEST SYNC _dfu_ctx.state = DFU_MANIFEST_SYNC; @@ -327,7 +338,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control default: if (stage == CONTROL_STAGE_SETUP) { - return reply_getstatus(rhport, request, _dfu_ctx.state, _dfu_ctx.status, 0); + return reply_getstatus(rhport, request, (dfu_state_t) _dfu_ctx.state, (dfu_status_t) _dfu_ctx.status, 0); } break; } @@ -376,11 +387,11 @@ static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tus timeout = 0; } - return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout); + return reply_getstatus(rhport, request, next_state, (dfu_status_t) _dfu_ctx.status, timeout); } else if (stage == CONTROL_STAGE_ACK) { if (_dfu_ctx.flashing_in_progress) { _dfu_ctx.state = DFU_DNBUSY; - tud_dfu_download_cb(_dfu_ctx.alt, _dfu_ctx.block, _transfer_buf, _dfu_ctx.length); + tud_dfu_download_cb(_dfu_ctx.alt, _dfu_ctx.block, get_xfer_buffer(), _dfu_ctx.length); } else { _dfu_ctx.state = DFU_DNLOAD_IDLE; } @@ -405,7 +416,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tus timeout = 0; } - return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout); + return reply_getstatus(rhport, request, next_state, (dfu_status_t) _dfu_ctx.status, timeout); } else if (stage == CONTROL_STAGE_ACK) { if (_dfu_ctx.flashing_in_progress) { _dfu_ctx.state = DFU_MANIFEST; diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 023a81595..de4ff5dd8 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -74,8 +74,8 @@ static midid_interface_t _midid_itf[CFG_TUD_MIDI]; #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 // Endpoint Transfer buffer: not used if dedicated hw FIFO is available typedef struct { - TUD_EPBUF_DEF(epin, CFG_TUD_MIDI_EP_BUFSIZE); - TUD_EPBUF_DEF(epout, CFG_TUD_MIDI_EP_BUFSIZE); + TUD_EPBUF_DEF(epin, CFG_TUD_MIDI_TX_EPSIZE); + TUD_EPBUF_DEF(epout, CFG_TUD_MIDI_RX_EPSIZE); } midid_epbuf_t; CFG_TUD_MEM_SECTION static midid_epbuf_t _midid_epbuf[CFG_TUD_MIDI]; @@ -168,6 +168,108 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void *buffer, ui return total_read; } +// Note: this function shares stream->buffer with tud_midi_n_stream_read(). +// Do not mix calls to both functions on the same interface. +uint32_t tud_midi_n_demux_stream_read(uint8_t itf, uint8_t *p_cable_num, void *buffer, uint32_t bufsize) { + TU_VERIFY(p_cable_num != NULL && buffer != NULL && bufsize > 0, 0); + + midid_interface_t *p_midi = &_midid_itf[itf]; + midi_driver_stream_t *stream = &p_midi->stream_read; + tu_edpt_stream_t *ep_str = &p_midi->ep_stream.rx; + + uint8_t *buf8 = (uint8_t *)buffer; + uint32_t total_read = 0; + + // Initialize to invalid cable so callers can detect "no data" even when + // the return value is 0. + *p_cable_num = 0xff; + + // If there are leftover bytes from a previous partial read, return them first + if (stream->total > 0) { + *p_cable_num = (stream->buffer[0] >> 4) & 0x0f; + const uint8_t count = (uint8_t)tu_min32((uint32_t)(stream->total - stream->index), bufsize); + TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)); + + total_read += count; + stream->index += count; + buf8 += count; + bufsize -= count; + + if (stream->total == stream->index) { + stream->index = 0; + stream->total = 0; + } + + if (bufsize == 0) { + return total_read; + } + } + + while (bufsize > 0) { + // Peek at next packet header to get cable number without consuming + uint8_t one_byte; + if (!tu_edpt_stream_peek(ep_str, &one_byte)) { + break; + } + + const uint8_t next_cable = (one_byte >> 4) & 0x0f; + + // Stop if cable changed (covers both leftover-originated reads and + // freshly consumed packets — total_read > 0 in either case) + if (total_read > 0 && next_cable != *p_cable_num) { + break; + } + *p_cable_num = next_cable; + + // Consume the packet + if (!tud_midi_n_packet_read(itf, stream->buffer)) { + break; + } + + const uint8_t code_index = stream->buffer[0] & 0x0f; + uint8_t msg_bytes; + + // MIDI 1.0 Table 4-1: Code Index Number Classifications + switch (code_index) { + case MIDI_CIN_MISC: + case MIDI_CIN_CABLE_EVENT: + // Reserved and unused, skip this packet + continue; + + case MIDI_CIN_SYSEX_END_1BYTE: + case MIDI_CIN_1BYTE_DATA: + msg_bytes = 1; + break; + + case MIDI_CIN_SYSCOM_2BYTE: + case MIDI_CIN_SYSEX_END_2BYTE: + case MIDI_CIN_PROGRAM_CHANGE: + case MIDI_CIN_CHANNEL_PRESSURE: + msg_bytes = 2; + break; + + default: + msg_bytes = 3; + break; + } + + const uint8_t count = (uint8_t)tu_min32((uint32_t)msg_bytes, bufsize); + TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1, count)); + + total_read += count; + buf8 += count; + bufsize -= count; + + if (count < msg_bytes) { + // Output buffer full, save remaining for next call + stream->total = msg_bytes; + stream->index = count; + } + } + + return total_read; +} + bool tud_midi_n_packet_read(uint8_t itf, uint8_t packet[4]) { midid_interface_t *p_midi = &_midid_itf[itf]; tu_edpt_stream_t *ep_str = &p_midi->ep_stream.rx; @@ -324,10 +426,10 @@ void midid_init(void) { #endif tu_edpt_stream_init(&p_midi->ep_stream.rx, false, false, false, p_midi->ep_stream.rx_ff_buf, - CFG_TUD_MIDI_RX_BUFSIZE, epout_buf, CFG_TUD_MIDI_EP_BUFSIZE); + CFG_TUD_MIDI_RX_BUFSIZE, epout_buf); tu_edpt_stream_init(&p_midi->ep_stream.tx, false, true, false, p_midi->ep_stream.tx_ff_buf, CFG_TUD_MIDI_TX_BUFSIZE, - epin_buf, CFG_TUD_MIDI_EP_BUFSIZE); + epin_buf); } } @@ -408,11 +510,11 @@ uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t *desc_itf, uint1 if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { tu_edpt_stream_t *stream_tx = &p_midi->ep_stream.tx; - tu_edpt_stream_open(stream_tx, rhport, desc_ep); + tu_edpt_stream_open(stream_tx, rhport, desc_ep, CFG_TUD_MIDI_TX_EPSIZE); tu_edpt_stream_clear(stream_tx); } else { tu_edpt_stream_t *stream_rx = &p_midi->ep_stream.rx; - tu_edpt_stream_open(stream_rx, rhport, desc_ep); + tu_edpt_stream_open(stream_rx, rhport, desc_ep, tu_edpt_packet_size(desc_ep)); tu_edpt_stream_clear(stream_rx); TU_ASSERT(tu_edpt_stream_read_xfer(stream_rx) > 0, 0); // prepare to receive data } diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h index ddbc2f9f0..57eabec1f 100644 --- a/src/class/midi/midi_device.h +++ b/src/class/midi/midi_device.h @@ -34,13 +34,20 @@ // Class Driver Configuration //--------------------------------------------------------------------+ -#if !defined(CFG_TUD_MIDI_EP_BUFSIZE) && defined(CFG_TUD_MIDI_EPSIZE) - #warning CFG_TUD_MIDI_EPSIZE is renamed to CFG_TUD_MIDI_EP_BUFSIZE, please update to use the new name - #define CFG_TUD_MIDI_EP_BUFSIZE CFG_TUD_MIDI_EPSIZE +#ifndef CFG_TUD_MIDI_RX_EPSIZE + #ifdef CFG_TUD_MIDI_EP_BUFSIZE + #define CFG_TUD_MIDI_RX_EPSIZE CFG_TUD_MIDI_EP_BUFSIZE + #else + #define CFG_TUD_MIDI_RX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif #endif -#ifndef CFG_TUD_MIDI_EP_BUFSIZE - #define CFG_TUD_MIDI_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#ifndef CFG_TUD_MIDI_TX_EPSIZE + #ifdef CFG_TUD_MIDI_EP_BUFSIZE + #define CFG_TUD_MIDI_TX_EPSIZE CFG_TUD_MIDI_EP_BUFSIZE + #else + #define CFG_TUD_MIDI_TX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif #endif #ifdef __cplusplus @@ -66,6 +73,13 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num); // Read byte stream (legacy) uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void *buffer, uint32_t bufsize); +// Read byte stream with cable demultiplexing: returns the cable number of the +// data that was read. Reads from a single cable per call; stops when the next +// packet belongs to a different cable so the caller can dispatch per-cable. +// Note: shares internal state with tud_midi_n_stream_read(); do not mix both +// on the same interface. +uint32_t tud_midi_n_demux_stream_read(uint8_t itf, uint8_t *p_cable_num, void *buffer, uint32_t bufsize); + // Write byte Stream (legacy) uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, const uint8_t *buffer, uint32_t bufsize); @@ -97,6 +111,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_midi_stream_read(void *buffer, } TU_ATTR_ALWAYS_INLINE static inline uint32_t +tud_midi_demux_stream_read(uint8_t *p_cable_num, void *buffer, uint32_t bufsize) { + return tud_midi_n_demux_stream_read(0, p_cable_num, buffer, bufsize); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_midi_stream_write(uint8_t cable_num, const uint8_t *buffer, uint32_t bufsize) { return tud_midi_n_stream_write(0, cable_num, buffer, bufsize); } diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 5548a0ba8..0feb5106d 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -83,8 +83,8 @@ typedef struct { }midih_interface_t; typedef struct { - TUH_EPBUF_DEF(tx, TUH_EPSIZE_BULK_MPS); - TUH_EPBUF_DEF(rx, TUH_EPSIZE_BULK_MPS); + TUH_EPBUF_DEF(tx, TUH_EPSIZE_BULK_MAX); + TUH_EPBUF_DEF(rx, TUH_EPSIZE_BULK_MAX); } midih_epbuf_t; static midih_interface_t _midi_host[CFG_TUH_MIDI]; @@ -121,9 +121,9 @@ bool midih_init(void) { for (int inst = 0; inst < CFG_TUH_MIDI; inst++) { midih_interface_t *p_midi_host = &_midi_host[inst]; tu_edpt_stream_init(&p_midi_host->ep_stream.rx, true, false, false, - p_midi_host->ep_stream.rx_ff_buf, CFG_TUH_MIDI_RX_BUFSIZE, _midi_epbuf->rx, TUH_EPSIZE_BULK_MPS); + p_midi_host->ep_stream.rx_ff_buf, CFG_TUH_MIDI_RX_BUFSIZE, _midi_epbuf[inst].rx); tu_edpt_stream_init(&p_midi_host->ep_stream.tx, true, true, false, - p_midi_host->ep_stream.tx_ff_buf, CFG_TUH_MIDI_TX_BUFSIZE, _midi_epbuf->tx, TUH_EPSIZE_BULK_MPS); + p_midi_host->ep_stream.tx_ff_buf, CFG_TUH_MIDI_TX_BUFSIZE, _midi_epbuf[inst].tx); } return true; } @@ -306,7 +306,7 @@ uint16_t midih_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_interface_ ep_stream = &p_midi->ep_stream.rx; } TU_ASSERT(tuh_edpt_open(dev_addr, p_ep), 0); - tu_edpt_stream_open(ep_stream, dev_addr, p_ep); + tu_edpt_stream_open(ep_stream, dev_addr, p_ep, tu_edpt_packet_size(p_ep)); tu_edpt_stream_clear(ep_stream); break; diff --git a/src/class/midi/midi_host.h b/src/class/midi/midi_host.h index 8a8dccab4..b9ab0130d 100644 --- a/src/class/midi/midi_host.h +++ b/src/class/midi/midi_host.h @@ -38,15 +38,15 @@ extern "C" { // Class Driver Configuration //--------------------------------------------------------------------+ #ifndef CFG_TUH_MIDI_RX_BUFSIZE - #define CFG_TUH_MIDI_RX_BUFSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_MIDI_RX_BUFSIZE TUH_EPSIZE_BULK_MAX #endif #ifndef CFG_TUH_MIDI_TX_BUFSIZE - #define CFG_TUH_MIDI_TX_BUFSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_MIDI_TX_BUFSIZE TUH_EPSIZE_BULK_MAX #endif #ifndef CFG_TUH_MIDI_EP_BUFSIZE - #define CFG_TUH_MIDI_EP_BUFSIZE TUH_EPSIZE_BULK_MPS + #define CFG_TUH_MIDI_EP_BUFSIZE TUH_EPSIZE_BULK_MAX #endif // Enable the MIDI stream read/write API. Some library can work with raw USB MIDI packet diff --git a/src/class/printer/printer.h b/src/class/printer/printer.h new file mode 100644 index 000000000..09d1a8956 --- /dev/null +++ b/src/class/printer/printer.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_PRINTER_H_ +#define TUSB_PRINTER_H_ + +#include "common/tusb_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Printer Class Specific Control Request +typedef enum { + TUSB_PRINTER_REQUEST_GET_DEVICE_ID = 0x00, ///< Get device ID + TUSB_PRINTER_REQUEST_GET_PORT_STATUS = 0x01, ///< Get port status + TUSB_PRINTER_REQUEST_SOFT_RESET = 0x02, ///< Soft reset +} tusb_printer_request_type_t; + +/// Printer Port Status (returned by GET_PORT_STATUS request) +/// USB Printer Class spec 1.1, Section 4.2 +typedef union TU_ATTR_PACKED { + uint8_t status; + struct TU_ATTR_PACKED { + uint8_t reserved0 : 3; ///< Reserved (bits 0-2) + uint8_t not_error : 1; ///< 1 = no error, 0 = error + uint8_t selected : 1; ///< 1 = selected (online), 0 = not selected + uint8_t paper_empty : 1; ///< 1 = paper empty, 0 = paper not empty + uint8_t reserved6 : 2; ///< Reserved (bits 6-7) + } status_bm; +} tusb_printer_port_status_t; + +TU_VERIFY_STATIC(sizeof(tusb_printer_port_status_t) == 1, "size is not correct"); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/class/printer/printer_device.c b/src/class/printer/printer_device.c new file mode 100644 index 000000000..d2dc9b163 --- /dev/null +++ b/src/class/printer/printer_device.c @@ -0,0 +1,329 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if (CFG_TUD_ENABLED && CFG_TUD_PRINTER) + +#include "device/usbd.h" +#include "device/usbd_pvt.h" + +#include "printer_device.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +typedef struct { + uint8_t itf_num; + + /*------------- From this point, data is not cleared by bus reset -------------*/ + + tu_edpt_stream_t rx_stream; + tu_edpt_stream_t tx_stream; + + uint8_t rx_ff_buf[CFG_TUD_PRINTER_RX_BUFSIZE]; + uint8_t tx_ff_buf[CFG_TUD_PRINTER_TX_BUFSIZE]; +} printer_interface_t; + +#define ITF_MEM_RESET_SIZE offsetof(printer_interface_t, rx_stream) + +#if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 +typedef struct { + TUD_EPBUF_DEF(epout, CFG_TUD_PRINTER_RX_EPSIZE); + TUD_EPBUF_DEF(epin, CFG_TUD_PRINTER_TX_EPSIZE); +} printer_epbuf_t; + +CFG_TUD_MEM_SECTION static printer_epbuf_t _printer_epbuf[CFG_TUD_PRINTER]; +#endif + +static printer_interface_t _printer_itf[CFG_TUD_PRINTER]; + +//--------------------------------------------------------------------+ +// INTERNAL HELPERS +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline uint8_t _find_itf(uint8_t ep_addr) { + for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) { + const printer_interface_t *p = &_printer_itf[i]; + if (ep_addr == p->rx_stream.ep_addr || ep_addr == p->tx_stream.ep_addr) { + return i; + } + } + return TUSB_INDEX_INVALID_8; +} + +//--------------------------------------------------------------------+ +// Weak stubs: invoked if no strong implementation is available +//--------------------------------------------------------------------+ +TU_ATTR_WEAK void tud_printer_rx_cb(uint8_t itf) { + (void)itf; +} + +TU_ATTR_WEAK void tud_printer_tx_complete_cb(uint8_t itf) { + (void)itf; +} + +TU_ATTR_WEAK void tud_printer_request_complete_cb(uint8_t itf, tusb_control_request_t const *request) { + (void)itf; + (void)request; +} + +TU_ATTR_WEAK uint8_t const *tud_printer_get_device_id_cb(uint8_t itf) { + (void)itf; + return NULL; +} + +TU_ATTR_WEAK uint8_t tud_printer_get_port_status_cb(uint8_t itf) { + (void)itf; + return 0x18; // not error, selected, paper not empty +} + +TU_ATTR_WEAK void tud_printer_soft_reset_cb(uint8_t itf) { + (void)itf; +} + +//--------------------------------------------------------------------+ +// READ API +//--------------------------------------------------------------------+ +uint32_t tud_printer_n_read_available(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_PRINTER, 0); + return tu_edpt_stream_read_available(&_printer_itf[itf].rx_stream); +} + +uint32_t tud_printer_n_read(uint8_t itf, void *buffer, uint32_t bufsize) { + TU_VERIFY(itf < CFG_TUD_PRINTER, 0); + return tu_edpt_stream_read(&_printer_itf[itf].rx_stream, buffer, bufsize); +} + +bool tud_printer_n_peek(uint8_t itf, uint8_t *chr) { + TU_VERIFY(itf < CFG_TUD_PRINTER); + return tu_edpt_stream_peek(&_printer_itf[itf].rx_stream, chr); +} + +void tud_printer_n_read_flush(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_PRINTER, ); + printer_interface_t *p = &_printer_itf[itf]; + tu_edpt_stream_clear(&p->rx_stream); + tu_edpt_stream_read_xfer(&p->rx_stream); +} + +//--------------------------------------------------------------------+ +// WRITE API +//--------------------------------------------------------------------+ +uint32_t tud_printer_n_write(uint8_t itf, const void *buffer, uint32_t bufsize) { + TU_VERIFY(itf < CFG_TUD_PRINTER, 0); + return tu_edpt_stream_write(&_printer_itf[itf].tx_stream, buffer, bufsize); +} + +uint32_t tud_printer_n_write_flush(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_PRINTER, 0); + return tu_edpt_stream_write_xfer(&_printer_itf[itf].tx_stream); +} + +uint32_t tud_printer_n_write_available(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_PRINTER, 0); + return tu_edpt_stream_write_available(&_printer_itf[itf].tx_stream); +} + +bool tud_printer_n_write_clear(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_PRINTER); + tu_edpt_stream_clear(&_printer_itf[itf].tx_stream); + return true; +} + +//--------------------------------------------------------------------+ +// USBD-CLASS API +//--------------------------------------------------------------------+ +void printerd_init(void) { + tu_memclr(_printer_itf, sizeof(_printer_itf)); + + for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) { + printer_interface_t *p = &_printer_itf[i]; + + #if CFG_TUD_EDPT_DEDICATED_HWFIFO + uint8_t *epout_buf = NULL; + uint8_t *epin_buf = NULL; + #else + uint8_t *epout_buf = _printer_epbuf[i].epout; + uint8_t *epin_buf = _printer_epbuf[i].epin; + #endif + + tu_edpt_stream_init(&p->rx_stream, false, false, false, + p->rx_ff_buf, CFG_TUD_PRINTER_RX_BUFSIZE, epout_buf); + + tu_edpt_stream_init(&p->tx_stream, false, true, true, + p->tx_ff_buf, CFG_TUD_PRINTER_TX_BUFSIZE, epin_buf); + } +} + +bool printerd_deinit(void) { + for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) { + printer_interface_t *p = &_printer_itf[i]; + tu_edpt_stream_deinit(&p->rx_stream); + tu_edpt_stream_deinit(&p->tx_stream); + } + return true; +} + +void printerd_reset(uint8_t rhport) { + (void)rhport; + + for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) { + printer_interface_t *p = &_printer_itf[i]; + tu_memclr(p, ITF_MEM_RESET_SIZE); + tu_edpt_stream_close(&p->rx_stream); + tu_edpt_stream_close(&p->tx_stream); + } +} + +uint16_t printerd_open(uint8_t rhport, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { + TU_VERIFY(TUSB_CLASS_PRINTER == itf_desc->bInterfaceClass, 0); + + // Find available interface slot + uint8_t const printer_id = _find_itf(0); + TU_ASSERT(printer_id < CFG_TUD_PRINTER, 0); + printer_interface_t *p = &_printer_itf[printer_id]; + + p->itf_num = itf_desc->bInterfaceNumber; + + //------------- Endpoints -------------// + const uint8_t *p_desc = (const uint8_t *)itf_desc; + const uint8_t *desc_end = p_desc + max_len; + uint16_t drv_len = sizeof(tusb_desc_interface_t); + + p_desc = tu_desc_next(itf_desc); + for (uint8_t e = 0; e < itf_desc->bNumEndpoints; e++) { + TU_VERIFY(tu_desc_in_bounds(p_desc, desc_end), 0); + const tusb_desc_endpoint_t *desc_ep = (const tusb_desc_endpoint_t *)p_desc; + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer, 0); + + TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + tu_edpt_stream_t *stream_tx = &p->tx_stream; + tu_edpt_stream_open(stream_tx, rhport, desc_ep, CFG_TUD_PRINTER_TX_EPSIZE); + tu_edpt_stream_clear(stream_tx); + } else { + tu_edpt_stream_t *stream_rx = &p->rx_stream; + tu_edpt_stream_open(stream_rx, rhport, desc_ep, tu_edpt_packet_size(desc_ep)); + tu_edpt_stream_clear(stream_rx); + TU_ASSERT(tu_edpt_stream_read_xfer(stream_rx) > 0, 0); + } + + drv_len += sizeof(tusb_desc_endpoint_t); + p_desc = tu_desc_next(p_desc); + } + + return drv_len; +} + +bool printerd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t *request) { + TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); + + // GET_DEVICE_ID: wIndex = (interface_number << 8) | alt_setting + // GET_PORT_STATUS / SOFT_RESET: wIndex = interface_number + uint8_t itf_num; + if (TUSB_PRINTER_REQUEST_GET_DEVICE_ID == request->bRequest) { + itf_num = tu_u16_high(request->wIndex); + } else { + itf_num = tu_u16_low(request->wIndex); + } + + // Find the printer instance index from the USB interface number + uint8_t itf = TUSB_INDEX_INVALID_8; + for (uint8_t i = 0; i < CFG_TUD_PRINTER; i++) { + if (_printer_itf[i].itf_num == itf_num) { + itf = i; + break; + } + } + TU_VERIFY(itf < CFG_TUD_PRINTER); + + // https://www.usb.org/sites/default/files/usbprint11a021811.pdf + if (stage == CONTROL_STAGE_SETUP) { + switch (request->bRequest) { + case TUSB_PRINTER_REQUEST_GET_DEVICE_ID: { + const uint8_t *device_id = tud_printer_get_device_id_cb(itf); + TU_VERIFY(device_id); + const uint16_t total_len = (uint16_t)((device_id[0] << 8) | device_id[1]); + return tud_control_xfer(rhport, request, (void *)(uintptr_t)device_id, total_len); + } + + case TUSB_PRINTER_REQUEST_GET_PORT_STATUS: { + static uint8_t port_status; + port_status = tud_printer_get_port_status_cb(itf); + return tud_control_xfer(rhport, request, &port_status, sizeof(port_status)); + } + + case TUSB_PRINTER_REQUEST_SOFT_RESET: + tud_printer_soft_reset_cb(itf); + tud_control_status(rhport, request); + return true; + + default: + return false; + } + } else if (stage == CONTROL_STAGE_ACK) { + tud_printer_request_complete_cb(itf, request); + } + + return true; +} + +bool printerd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { + (void)rhport; + (void)result; + + uint8_t const itf = _find_itf(ep_addr); + TU_ASSERT(itf < CFG_TUD_PRINTER); + printer_interface_t *p = &_printer_itf[itf]; + + // Received new data + if (ep_addr == p->rx_stream.ep_addr) { + tu_edpt_stream_read_xfer_complete(&p->rx_stream, xferred_bytes); + + if (!tu_edpt_stream_empty(&p->rx_stream)) { + tud_printer_rx_cb(itf); + } + + tu_edpt_stream_read_xfer(&p->rx_stream); + } + + // Data sent to host + if (ep_addr == p->tx_stream.ep_addr) { + tud_printer_tx_complete_cb(itf); + + if (0 == tu_edpt_stream_write_xfer(&p->tx_stream)) { + tu_edpt_stream_write_zlp_if_needed(&p->tx_stream, xferred_bytes); + } + } + + return true; +} + +#endif diff --git a/src/class/printer/printer_device.h b/src/class/printer/printer_device.h new file mode 100644 index 000000000..afde1f022 --- /dev/null +++ b/src/class/printer/printer_device.h @@ -0,0 +1,151 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2026 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_PRINTER_DEVICE_H_ +#define TUSB_PRINTER_DEVICE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "printer.h" + +//--------------------------------------------------------------------+ +// Configuration +//--------------------------------------------------------------------+ +#ifndef CFG_TUD_PRINTER_RX_EPSIZE + #define CFG_TUD_PRINTER_RX_EPSIZE TUD_EPSIZE_BULK_MAX +#endif + +#ifndef CFG_TUD_PRINTER_TX_EPSIZE + #define CFG_TUD_PRINTER_TX_EPSIZE TUD_EPSIZE_BULK_MAX +#endif + +//--------------------------------------------------------------------+ +// Application API (Multiple Ports) i.e. CFG_TUD_PRINTER > 1 +//--------------------------------------------------------------------+ + +// Get the number of bytes available for reading +uint32_t tud_printer_n_read_available(uint8_t itf); + +// Read received bytes +uint32_t tud_printer_n_read(uint8_t itf, void *buffer, uint32_t bufsize); + +// Get the number of bytes available for writing +uint32_t tud_printer_n_write_available(uint8_t itf); + +// Clear the received FIFO +void tud_printer_n_read_flush(uint8_t itf); + +// Get a byte from FIFO without removing it +bool tud_printer_n_peek(uint8_t itf, uint8_t *ui8); + +// Write data to host +uint32_t tud_printer_n_write(uint8_t itf, const void *buffer, uint32_t bufsize); + +// Force sending data in the TX FIFO +uint32_t tud_printer_n_write_flush(uint8_t itf); + +// Clear the transmit FIFO +bool tud_printer_n_write_clear(uint8_t itf); + +//--------------------------------------------------------------------+ +// Application API (Single Port) +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_read_available(void) { + return tud_printer_n_read_available(0); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write_available(void) { + return tud_printer_n_write_available(0); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_read(void *buffer, uint32_t bufsize) { + return tud_printer_n_read(0, buffer, bufsize); +} + +TU_ATTR_ALWAYS_INLINE static inline void tud_printer_read_flush(void) { + tud_printer_n_read_flush(0); +} + +TU_ATTR_ALWAYS_INLINE static inline bool tud_printer_peek(uint8_t *ui8) { + return tud_printer_n_peek(0, ui8); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write(const void *buffer, uint32_t bufsize) { + return tud_printer_n_write(0, buffer, bufsize); +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_printer_write_flush(void) { + return tud_printer_n_write_flush(0); +} + +TU_ATTR_ALWAYS_INLINE static inline bool tud_printer_write_clear(void) { + return tud_printer_n_write_clear(0); +} + +//--------------------------------------------------------------------+ +// Application Callback API (weak is optional) +//--------------------------------------------------------------------+ + +// Invoked when received new data +void tud_printer_rx_cb(uint8_t itf); + +// Invoked when last write transfer is completed +void tud_printer_tx_complete_cb(uint8_t itf); + +// Invoked when host requests device ID string (IEEE 1284). +// Application returns pointer to device ID buffer (must remain valid until transfer completes). +// First 2 bytes of returned buffer must contain big-endian length (including the 2 length bytes). +const uint8_t *tud_printer_get_device_id_cb(uint8_t itf); + +// Invoked when host requests port status. +uint8_t tud_printer_get_port_status_cb(uint8_t itf); + +// Invoked when host requests soft reset. +void tud_printer_soft_reset_cb(uint8_t itf); + +// Invoked when a control request is completed (GET_DEVICE_ID, GET_PORT_STATUS, etc.) +void tud_printer_request_complete_cb(uint8_t itf, tusb_control_request_t const *request); + + +//--------------------------------------------------------------------+ +// Internal Class Driver API +//--------------------------------------------------------------------+ +void printerd_init(void); +bool printerd_deinit(void); +void printerd_reset(uint8_t rhport); +uint16_t printerd_open(uint8_t rhport, const tusb_desc_interface_t *itf_desc, uint16_t max_len); +bool printerd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t *request); +bool printerd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index b917c8dc7..e1017ba48 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -49,8 +49,7 @@ typedef struct { #else uint8_t ep_in; uint8_t ep_out; - uint16_t ep_in_mps; - uint16_t ep_out_mps; + uint16_t rx_xfer_len; #endif } vendord_interface_t; @@ -62,15 +61,15 @@ typedef struct { static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR]; - // Skip local EP buffer if dedicated hw FIFO is supported or no fifo mode - #if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 || !CFG_TUD_VENDOR_TXRX_BUFFERED +// Skip local EP buffer if dedicated hw FIFO is supported or no fifo mode +#if CFG_TUD_EDPT_DEDICATED_HWFIFO == 0 || !CFG_TUD_VENDOR_TXRX_BUFFERED typedef struct { - TUD_EPBUF_DEF(epout, CFG_TUD_VENDOR_EPSIZE); - TUD_EPBUF_DEF(epin, CFG_TUD_VENDOR_EPSIZE); + TUD_EPBUF_DEF(epout, CFG_TUD_VENDOR_RX_EPSIZE); + TUD_EPBUF_DEF(epin, CFG_TUD_VENDOR_TX_EPSIZE); } vendord_epbuf_t; CFG_TUD_MEM_SECTION static vendord_epbuf_t _vendord_epbuf[CFG_TUD_VENDOR]; - #endif +#endif //--------------------------------------------------------------------+ // Weak stubs: invoked if no strong implementation is available @@ -86,9 +85,6 @@ TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t idx, uint32_t sent_bytes) { (void) sent_bytes; } -//-------------------------------------------------------------------- -// Application API -//-------------------------------------------------------------------- bool tud_vendor_n_mounted(uint8_t idx) { TU_VERIFY(idx < CFG_TUD_VENDOR); vendord_interface_t *p_itf = &_vendord_itf[idx]; @@ -128,9 +124,9 @@ void tud_vendor_n_read_flush(uint8_t idx) { tu_edpt_stream_clear(&p_itf->rx_stream); tu_edpt_stream_read_xfer(&p_itf->rx_stream); } -#endif + #endif -#if CFG_TUD_VENDOR_RX_MANUAL_XFER + #if CFG_TUD_VENDOR_RX_MANUAL_XFER bool tud_vendor_n_read_xfer(uint8_t idx) { TU_VERIFY(idx < CFG_TUD_VENDOR); vendord_interface_t *p_itf = &_vendord_itf[idx]; @@ -141,7 +137,7 @@ bool tud_vendor_n_read_xfer(uint8_t idx) { #else // Non-FIFO mode TU_VERIFY(usbd_edpt_claim(p_itf->rhport, p_itf->ep_out)); - return usbd_edpt_xfer(p_itf->rhport, p_itf->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false); + return usbd_edpt_xfer(p_itf->rhport, p_itf->ep_out, _vendord_epbuf[idx].epout, p_itf->rx_xfer_len, false); #endif } #endif @@ -160,7 +156,7 @@ uint32_t tud_vendor_n_write(uint8_t idx, const void *buffer, uint32_t bufsize) { #else // non-fifo mode: direct transfer TU_VERIFY(usbd_edpt_claim(p_itf->rhport, p_itf->ep_in), 0); - const uint32_t xact_len = tu_min32(bufsize, CFG_TUD_VENDOR_EPSIZE); + const uint32_t xact_len = tu_min32(bufsize, CFG_TUD_VENDOR_TX_EPSIZE); memcpy(_vendord_epbuf[idx].epin, buffer, xact_len); TU_ASSERT(usbd_edpt_xfer(p_itf->rhport, p_itf->ep_in, _vendord_epbuf[idx].epin, (uint16_t)xact_len, false), 0); return xact_len; @@ -177,7 +173,7 @@ uint32_t tud_vendor_n_write_available(uint8_t idx) { #else // Non-FIFO mode TU_VERIFY(p_itf->ep_in > 0, 0); // must be opened - return usbd_edpt_busy(p_itf->rhport, p_itf->ep_in) ? 0 : CFG_TUD_VENDOR_EPSIZE; + return usbd_edpt_busy(p_itf->rhport, p_itf->ep_in) ? 0 : CFG_TUD_VENDOR_TX_EPSIZE; #endif } @@ -215,12 +211,10 @@ void vendord_init(void) { #endif uint8_t *rx_ff_buf = p_itf->rx_ff_buf; - tu_edpt_stream_init(&p_itf->rx_stream, false, false, false, rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, epout_buf, - CFG_TUD_VENDOR_EPSIZE); + tu_edpt_stream_init(&p_itf->rx_stream, false, false, false, rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, epout_buf); uint8_t *tx_ff_buf = p_itf->tx_ff_buf; - tu_edpt_stream_init(&p_itf->tx_stream, false, true, false, tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, epin_buf, - CFG_TUD_VENDOR_EPSIZE); + tu_edpt_stream_init(&p_itf->tx_stream, false, true, false, tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, epin_buf); } #endif } @@ -302,30 +296,31 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t *desc_itf, uin const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); + uint16_t rx_xfer_len = CFG_TUD_VENDOR_RX_NEED_ZLP ? CFG_TUD_VENDOR_RX_EPSIZE : tu_edpt_packet_size(desc_ep); + #if CFG_TUD_VENDOR_TXRX_BUFFERED // open endpoint stream if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { tu_edpt_stream_t *tx_stream = &p_vendor->tx_stream; - tu_edpt_stream_open(tx_stream, rhport, desc_ep); + tu_edpt_stream_open(tx_stream, rhport, desc_ep, CFG_TUD_VENDOR_TX_EPSIZE); tu_edpt_stream_write_xfer(tx_stream); // flush pending data } else { tu_edpt_stream_t *rx_stream = &p_vendor->rx_stream; - tu_edpt_stream_open(rx_stream, rhport, desc_ep); + tu_edpt_stream_open(rx_stream, rhport, desc_ep, rx_xfer_len); #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0 TU_ASSERT(tu_edpt_stream_read_xfer(rx_stream) > 0, 0); // prepare for incoming data #endif } #else + p_vendor->rx_xfer_len = rx_xfer_len; // Non-FIFO mode: store endpoint info if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { p_vendor->ep_in = desc_ep->bEndpointAddress; - p_vendor->ep_in_mps = tu_edpt_packet_size(desc_ep); } else { p_vendor->ep_out = desc_ep->bEndpointAddress; - p_vendor->ep_out_mps = tu_edpt_packet_size(desc_ep); #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0 // Prepare for incoming data - TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false), 0); + TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, rx_xfer_len, false), 0); #endif } #endif @@ -367,7 +362,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint // Non-FIFO mode: invoke callback with buffer tud_vendor_rx_cb(idx, _vendord_epbuf[idx].epout, xferred_bytes); #if CFG_TUD_VENDOR_RX_MANUAL_XFER == 0 - usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, CFG_TUD_VENDOR_EPSIZE, false); + usbd_edpt_xfer(rhport, p_vendor->ep_out, _vendord_epbuf[idx].epout, p_vendor->rx_xfer_len, false); #endif } else if (ep_addr == p_vendor->ep_in) { // Send complete diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 101765bb1..cdca9fd15 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -36,18 +36,30 @@ extern "C" { //--------------------------------------------------------------------+ // Configuration //--------------------------------------------------------------------+ -#ifndef CFG_TUD_VENDOR_EPSIZE - #define CFG_TUD_VENDOR_EPSIZE 64 +#ifndef CFG_TUD_VENDOR_RX_EPSIZE + #ifdef CFG_TUD_VENDOR_EPSIZE + #define CFG_TUD_VENDOR_RX_EPSIZE CFG_TUD_VENDOR_EPSIZE + #else + #define CFG_TUD_VENDOR_RX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif +#endif + +#ifndef CFG_TUD_VENDOR_TX_EPSIZE + #ifdef CFG_TUD_VENDOR_EPSIZE + #define CFG_TUD_VENDOR_TX_EPSIZE CFG_TUD_VENDOR_EPSIZE + #else + #define CFG_TUD_VENDOR_TX_EPSIZE TUD_EPSIZE_BULK_MAX + #endif #endif // RX FIFO can be disabled by setting this value to 0 #ifndef CFG_TUD_VENDOR_RX_BUFSIZE - #define CFG_TUD_VENDOR_RX_BUFSIZE 64 + #define CFG_TUD_VENDOR_RX_BUFSIZE TUD_EPSIZE_BULK_MAX #endif // TX FIFO can be disabled by setting this value to 0 #ifndef CFG_TUD_VENDOR_TX_BUFSIZE - #define CFG_TUD_VENDOR_TX_BUFSIZE 64 + #define CFG_TUD_VENDOR_TX_BUFSIZE TUD_EPSIZE_BULK_MAX #endif // Vendor is buffered (FIFO mode) if both TX and RX buffers are configured @@ -62,6 +74,11 @@ extern "C" { #define CFG_TUD_VENDOR_RX_MANUAL_XFER 0 #endif +// Enable multi-packet RX transfer with ZLP termination for better throughput. Requires host support for ZLP. +#ifndef CFG_TUD_VENDOR_RX_NEED_ZLP + #define CFG_TUD_VENDOR_RX_NEED_ZLP 0 +#endif + //--------------------------------------------------------------------+ // Application API (Multiple Interfaces) i.e CFG_TUD_VENDOR > 1 //--------------------------------------------------------------------+ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index b2375def9..bbcfe45d5 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -70,6 +70,13 @@ typedef struct TU_ATTR_PACKED { uint8_t bEntityId; } tusb_desc_cs_video_entity_itf_t; +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t wMaxTransferSize; +} tusb_desc_cs_video_vc_ep_t; + typedef union { struct TU_ATTR_PACKED { uint8_t bLength; @@ -740,6 +747,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) /* The end of the video control interface descriptor. */ void const *end = _end_of_control_descriptor(vc); if (vc->std.bNumEndpoints != 0) { + /* Extend end to cover the standard endpoint and class-specific endpoint descriptors + * that follow wTotalLength */ + end = (uint8_t const*)end + sizeof(tusb_desc_endpoint_t) + sizeof(tusb_desc_cs_video_vc_ep_t); /* Find the notification endpoint descriptor. */ cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); TU_ASSERT(cur < end); @@ -780,6 +790,9 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t if (vc->std.bNumEndpoints != 0) { /* Support for 1 endpoint only. */ TU_VERIFY(1 == vc->std.bNumEndpoints); + /* Extend end to cover the standard endpoint and class-specific endpoint descriptors + * that follow wTotalLength */ + end = (uint8_t const*)end + sizeof(tusb_desc_endpoint_t) + sizeof(tusb_desc_cs_video_vc_ep_t); /* Find the notification endpoint descriptor. */ cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); TU_VERIFY(cur < end); diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 9f188f296..06d25d131 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -30,11 +30,6 @@ #define TU_FIFO_DBG 0 -// Suppress IAR warning -// Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement -#if defined(__ICCARM__) - #pragma diag_suppress = Pa082 -#endif #if OSAL_MUTEX_REQUIRED @@ -115,7 +110,7 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) { // Can support multiple i.e both 16 and 32-bit data access if needed //--------------------------------------------------------------------+ #if CFG_TUSB_FIFO_HWFIFO_API - #if CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE + #if CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE > 0 #define HWFIFO_ADDR_NEXT_N(_hwfifo, _const, _n) _hwfifo = (_const volatile void *)((uintptr_t)(_hwfifo) + _n) #else #define HWFIFO_ADDR_NEXT_N(_hwfifo, _const, _n) @@ -123,6 +118,9 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) { #define HWFIFO_ADDR_NEXT(_hwfifo, _const) HWFIFO_ADDR_NEXT_N(_hwfifo, _const, CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE) + // the fixed ratio works since in the only case of dynamic/multiple data_stride (rusb2): addr_stride is 0 + #define HWFIFO_ADDR_DATA_RATIO (CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE / CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE) + //------------- Write -------------// #ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE TU_ATTR_ALWAYS_INLINE static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) { @@ -240,16 +238,16 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co len -= 2; HWFIFO_ADDR_NEXT_N(hwfifo, const, 2); } - #endif + #endif - #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS + #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS // 8-bit access is allowed for odd bytes while (len > 0) { *dest++ = *((const volatile uint8_t *)hwfifo); len--; HWFIFO_ADDR_NEXT_N(hwfifo, const, 1); } - #else + #else // Read odd bytes i.e 1 byte for 16 bit or 1-3 bytes for 32 bit if (len > 0) { uint32_t tmp; @@ -257,7 +255,7 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co memcpy(dest, &tmp, len); HWFIFO_ADDR_NEXT(hwfifo, const); } - #endif + #endif #endif } #endif @@ -280,15 +278,15 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_bytes); tu_hwfifo_read(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part #else - // Write full words to linear part of buffer + // Write full words to the linear part of the buffer const uint8_t data_stride = access_mode->data_stride; const uint32_t odd_mask = data_stride - 1; uint16_t lin_even = lin_bytes & ~odd_mask; tu_hwfifo_read(hwfifo, ff_buf, lin_even, access_mode); - HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_even); + HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_even * HWFIFO_ADDR_DATA_RATIO); ff_buf += lin_even; - // There could be odd 1 byte (16bit) or 1-3 bytes (32bit) before the wrap-around boundary + // There could be an odd 1 byte (16bit) or 1-3 bytes (32bit) before the wrap-around boundary // combine it with the wrapped part to form a full word for data stride const uint8_t lin_odd = lin_bytes & odd_mask; if (lin_odd > 0) { @@ -342,7 +340,7 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t const uint32_t odd_mask = data_stride - 1; uint16_t lin_even = lin_bytes & ~odd_mask; tu_hwfifo_write(hwfifo, ff_buf, lin_even, access_mode); - HWFIFO_ADDR_NEXT_N(hwfifo, , lin_even); + HWFIFO_ADDR_NEXT_N(hwfifo, , lin_even * HWFIFO_ADDR_DATA_RATIO); ff_buf += lin_even; // There could be odd 1 byte (16bit) or 1-3 bytes (32bit) before the wrap-around boundary @@ -496,7 +494,9 @@ uint16_t tu_fifo_peek_n_access_mode(tu_fifo_t *f, void *p_buffer, uint16_t n, ui // Read n items without removing it from the FIFO, correct read pointer if overflowed uint16_t tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n) { ff_lock(f->mutex_rd); - const uint16_t ret = tu_fifo_peek_n_access_mode(f, p_buffer, n, f->wr_idx, f->rd_idx, NULL); + const uint16_t wr_idx = f->wr_idx; + const uint16_t rd_idx = f->rd_idx; + const uint16_t ret = tu_fifo_peek_n_access_mode(f, p_buffer, n, wr_idx, rd_idx, NULL); ff_unlock(f->mutex_rd); return ret; } @@ -506,7 +506,8 @@ uint16_t tu_fifo_read_n_access_mode(tu_fifo_t *f, void *buffer, uint16_t n, cons ff_lock(f->mutex_rd); // Peek the data: f->rd_idx might get modified in case of an overflow so we can not use a local variable - n = tu_fifo_peek_n_access_mode(f, buffer, n, f->wr_idx, f->rd_idx, access_mode); + const uint16_t wr_idx = f->wr_idx; + n = tu_fifo_peek_n_access_mode(f, buffer, n, wr_idx, f->rd_idx, access_mode); f->rd_idx = advance_index(f->depth, f->rd_idx, n); ff_unlock(f->mutex_rd); @@ -633,7 +634,8 @@ static bool ff_peek_local(tu_fifo_t *f, void *buf, uint16_t wr_idx, uint16_t rd_ bool tu_fifo_read(tu_fifo_t *f, void *buffer) { // Peek the data // f->rd_idx might get modified in case of an overflow so we can not use a local variable - const bool ret = ff_peek_local(f, buffer, f->wr_idx, f->rd_idx); + const uint16_t wr_idx = f->wr_idx; + const bool ret = ff_peek_local(f, buffer, wr_idx, f->rd_idx); if (ret) { ff_lock(f->mutex_rd); f->rd_idx = advance_index(f->depth, f->rd_idx, 1); @@ -645,7 +647,9 @@ bool tu_fifo_read(tu_fifo_t *f, void *buffer) { // Read one item without removing it from the FIFO, correct read index if overflowed bool tu_fifo_peek(tu_fifo_t *f, void *p_buffer) { - return ff_peek_local(f, p_buffer, f->wr_idx, f->rd_idx); + const uint16_t wr_idx = f->wr_idx; + const uint16_t rd_idx = f->rd_idx; + return ff_peek_local(f, p_buffer, wr_idx, rd_idx); } // Write one element into the buffer diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h index 86ba59059..b31a0802e 100644 --- a/src/common/tusb_fifo.h +++ b/src/common/tusb_fifo.h @@ -120,9 +120,9 @@ typedef struct { uint8_t *buffer; // buffer pointer uint16_t depth; // max items bool overwritable; // overwritable when full - // 1 byte padding here + // 1 byte padding here - volatile uint16_t wr_idx; // write index TODO maybe can drop volatile + volatile uint16_t wr_idx; // write index volatile uint16_t rd_idx; // read index #if OSAL_MUTEX_REQUIRED @@ -291,16 +291,22 @@ TU_ATTR_ALWAYS_INLINE static inline bool tu_fifo_empty(const tu_fifo_t *f) { // return number of items in fifo, capped to fifo's depth TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_count(const tu_fifo_t *f) { - return tu_min16(tu_ff_overflow_count(f->depth, f->wr_idx, f->rd_idx), f->depth); + const uint16_t wr_idx = f->wr_idx; + const uint16_t rd_idx = f->rd_idx; + return tu_min16(tu_ff_overflow_count(f->depth, wr_idx, rd_idx), f->depth); } // check if fifo is full TU_ATTR_ALWAYS_INLINE static inline bool tu_fifo_full(const tu_fifo_t *f) { - return tu_ff_overflow_count(f->depth, f->wr_idx, f->rd_idx) >= f->depth; + const uint16_t wr_idx = f->wr_idx; + const uint16_t rd_idx = f->rd_idx; + return tu_ff_overflow_count(f->depth, wr_idx, rd_idx) >= f->depth; } TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_remaining(const tu_fifo_t *f) { - return tu_ff_remaining_local(f->depth, f->wr_idx, f->rd_idx); + const uint16_t wr_idx = f->wr_idx; + const uint16_t rd_idx = f->rd_idx; + return tu_ff_remaining_local(f->depth, wr_idx, rd_idx); } #ifdef __cplusplus diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 5b9497b9a..edc7ecc3e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -71,13 +71,24 @@ #define TUP_DCD_ENDPOINT_MAX 5 #elif TU_CHECK_MCU(OPT_MCU_LPC54) + #include "fsl_device_registers.h" + // TODO USB0 has 5, USB1 has 6 #define TUP_USBIP_IP3511 + + #if !defined(LPC54114_cm4_SERIES) && !defined(LPC54114_cm0plus_SERIES) + #define TUP_USBIP_IP3516 + #define TUP_USBIP_OHCI + #define TUP_USBIP_OHCI_NXP + #define TUP_OHCI_RHPORTS 1 // 1 downstream port + #endif + #define TUP_DCD_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_LPC55) // TODO USB0 has 5, USB1 has 6 #define TUP_USBIP_IP3511 + #define TUP_USBIP_IP3516 #define TUP_USBIP_OHCI #define TUP_USBIP_OHCI_NXP #define TUP_OHCI_RHPORTS 1 // 1 downstream port @@ -172,6 +183,10 @@ #define TUP_RHPORT_HIGHSPEED 1 #define TUD_ENDPOINT_ONE_DIRECTION_ONLY + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_SAMX7X_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ) #define TUP_DCD_ENDPOINT_MAX 8 #define TUD_ENDPOINT_ONE_DIRECTION_ONLY diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index 43ce7a1df..91d213755 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef TUSB_PRIVATE_H_ -#define TUSB_PRIVATE_H_ +#ifndef TUSB_PRIVATE_H +#define TUSB_PRIVATE_H // Internal Helper used by Host and Device Stack @@ -33,9 +33,11 @@ extern "C" { #endif -//--------------------------------------------------------------------+ -// Configuration -//--------------------------------------------------------------------+ +typedef void (*tusb_defer_func_t)(uintptr_t param); + + //--------------------------------------------------------------------+ + // Configuration + //--------------------------------------------------------------------+ #define TUP_USBIP_CONTROLLER_NUM 2 extern tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM]; @@ -60,9 +62,10 @@ typedef struct { uint8_t hwid; // device: rhport, host: daddr bool is_host; // 1: host, 0: device uint8_t ep_addr; - uint16_t mps; + // 1 byte padding - uint16_t ep_bufsize; + uint16_t mps; + uint16_t xfer_len; uint8_t *ep_buf; // set to NULL to use xfer_fifo when CFG_TUD_EDPT_DEDICATED_HWFIFO = 1 tu_fifo_t ff; @@ -79,9 +82,8 @@ typedef struct { bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed); #else TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) { - (void)desc_ep; (void)speed; - return true; + return tu_edpt_packet_size(desc_ep) > 0; } #endif @@ -101,7 +103,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex); // Init an endpoint stream bool tu_edpt_stream_init(tu_edpt_stream_t *s, bool is_host, bool is_tx, bool overwritable, void *ff_buf, - uint16_t ff_bufsize, uint8_t *ep_buf, uint16_t ep_bufsize); + uint16_t ff_bufsize, uint8_t *ep_buf); // Deinit an endpoint stream TU_ATTR_ALWAYS_INLINE static inline void tu_edpt_stream_deinit(tu_edpt_stream_t *s) { @@ -118,10 +120,11 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_edpt_stream_deinit(tu_edpt_stream_t // Open an endpoint stream TU_ATTR_ALWAYS_INLINE static inline void tu_edpt_stream_open(tu_edpt_stream_t *s, uint8_t hwid, - const tusb_desc_endpoint_t *desc_ep) { + const tusb_desc_endpoint_t *desc_ep, uint16_t xfer_len) { s->hwid = hwid; s->ep_addr = desc_ep->bEndpointAddress; s->mps = tu_edpt_packet_size(desc_ep); + s->xfer_len = xfer_len; } TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_stream_is_opened(const tu_edpt_stream_t *s) { diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 7d26ac74e..a18f9feb7 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -115,6 +115,10 @@ enum { TUSB_EPSIZE_ISO_HS_MAX = 1024, }; +// Endpoint Bulk size depending on host/device max speed +#define TUD_EPSIZE_BULK_MAX (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define TUH_EPSIZE_BULK_MAX (TUH_OPT_HIGH_SPEED ? 512 : 64) + /// Isochronous Endpoint Attributes typedef enum { TUSB_ISO_EP_ATT_NO_SYNC = 0x00, @@ -341,12 +345,10 @@ typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< DEVICE Descriptor Type. uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). - uint8_t bDeviceClass ; ///< Class code (assigned by the USB-IF). uint8_t bDeviceSubClass ; ///< Subclass code (assigned by the USB-IF). uint8_t bDeviceProtocol ; ///< Protocol code (assigned by the USB-IF). uint8_t bMaxPacketSize0 ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. - uint16_t idVendor ; ///< Vendor ID (assigned by the USB-IF). uint16_t idProduct ; ///< Product ID (assigned by the manufacturer). uint16_t bcdDevice ; ///< Device release number in binary-coded decimal. diff --git a/src/device/usbd.c b/src/device/usbd.c index cca4169d7..42903576c 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -334,6 +334,19 @@ static const usbd_class_driver_t _usbd_driver[] = { .sof = NULL }, #endif + + #if CFG_TUD_PRINTER + { + .name = DRIVER_NAME("PRINTER"), + .init = printerd_init, + .deinit = printerd_deinit, + .reset = printerd_reset, + .open = printerd_open, + .control_xfer_cb = printerd_control_xfer_cb, + .xfer_cb = printerd_xfer_cb, + .sof = NULL + }, + #endif }; enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; @@ -585,7 +598,7 @@ bool tud_deinit(uint8_t rhport) { // Deinit device controller driver dcd_int_disable(rhport); dcd_disconnect(rhport); - TU_VERIFY(dcd_deinit(rhport)); + TU_ASSERT(dcd_deinit(rhport)); // Deinit class drivers for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) { @@ -823,7 +836,9 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) { TU_LOG_USBD(" %s", tu_str_std_request[p_request->bRequest]); - if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n"); + if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) { + TU_LOG_USBD("\r\n"); + } } #endif @@ -959,7 +974,25 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const //------------- Class/Interface Specific Request -------------// case TUSB_REQ_RCPT_INTERFACE: { - uint8_t const itf = tu_u16_low(p_request->wIndex); + uint8_t itf; + #if CFG_TUD_PRINTER + // Printer GET_DEVICE_ID has a weird wIndex = interface (high) | alt (low) + // attempt to interpret this as a printer request if matched + if (TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type && + TUSB_DIR_IN == p_request->bmRequestType_bit.direction && + TUSB_PRINTER_REQUEST_GET_DEVICE_ID == p_request->bRequest) { + itf = tu_u16_high(p_request->wIndex); + if (itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)) { + const usbd_class_driver_t * driver = get_driver(_usbd_dev.itf2drv[itf]); + if (driver != NULL && driver->control_xfer_cb == printerd_control_xfer_cb) { + if (invoke_class_control(rhport, driver, p_request)) { + return true; + } + } + } + } + #endif + itf = tu_u16_low(p_request->wIndex); TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); usbd_class_driver_t const * driver = get_driver(_usbd_dev.itf2drv[itf]); diff --git a/src/device/usbd.h b/src/device/usbd.h index 825fdba90..d3a6dccbb 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -297,6 +297,19 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 +//--------------------------------------------------------------------+ +// Printer Descriptor Templates +//--------------------------------------------------------------------+ + +#define TUD_PRINTER_DESC_LEN (9 + 7 + 7) // one interface, two endpoints + +#define TUD_PRINTER_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_PRINTER, 1, 2, _stridx,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 //--------------------------------------------------------------------+ // MTP Descriptor Templates diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 47d58a1f9..87593d4a7 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -63,6 +63,10 @@ CFG_TUD_MEM_SECTION static struct { TUD_EPBUF_DEF(buf, CFG_TUD_ENDPOINT0_BUFSIZE); } _ctrl_epbuf; +uint8_t* usbd_get_ctrl_buf(void) { + return _ctrl_epbuf.buf; +} + //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ @@ -93,7 +97,7 @@ static bool data_stage_xact(uint8_t rhport) { if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; - if (0u != xact_len) { + if (0u != xact_len && _ctrl_xfer.buffer != _ctrl_epbuf.buf) { TU_VERIFY(0 == tu_memcpy_s(_ctrl_epbuf.buf, CFG_TUD_ENDPOINT0_BUFSIZE, _ctrl_xfer.buffer, xact_len)); } } @@ -169,7 +173,9 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes); + if (_ctrl_xfer.buffer != _ctrl_epbuf.buf) { + memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes); + } TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2); } diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 72323ac80..5f11ea481 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -72,6 +72,8 @@ void usbd_int_set(bool enabled); void usbd_spin_lock(bool in_isr); void usbd_spin_unlock(bool in_isr); +uint8_t* usbd_get_ctrl_buf(void); + //--------------------------------------------------------------------+ // USBD Endpoint API // Note: rhport should be 0 since device stack only support 1 rhport for now diff --git a/src/host/hcd.h b/src/host/hcd.h index 36a7f5da5..47d672f9e 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -59,7 +59,7 @@ typedef enum { HCD_EVENT_XFER_COMPLETE, USBH_EVENT_FUNC_CALL, // Not an HCD event - HCD_EVENT_COUNT + HCD_EVENT_INVALID } hcd_eventid_t; typedef struct { @@ -72,7 +72,6 @@ typedef struct { struct { uint8_t hub_addr; uint8_t hub_port; - uint8_t speed; } connection; // XFER_COMPLETE diff --git a/src/host/hub.c b/src/host/hub.c index 3baaff30f..7c6735ed4 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -48,7 +48,7 @@ typedef struct { uint8_t bNbrPorts; uint8_t bPwrOn2PwrGood_2ms; // port power on to good, in 2ms unit // uint16_t wHubCharacteristics; - + bool mtt; hub_port_status_response_t port_status; } hub_interface_t; @@ -218,23 +218,37 @@ bool hub_deinit(void) { return true; } -uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - (void) rhport; - - TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass && - 0 == itf_desc->bInterfaceSubClass, 0); - TU_VERIFY(itf_desc->bInterfaceProtocol <= 1, 0); // not support multiple TT yet +uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { + (void)rhport; + TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass && 0 == itf_desc->bInterfaceSubClass, 0); - const uint16_t drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t); + const uint16_t itf_ep_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t); + uint16_t drv_len = itf_ep_len; TU_ASSERT(drv_len <= max_len, 0); + hub_interface_t *p_hub = get_hub_itf(dev_addr); + const tusb_desc_interface_t *desc_itf_use = itf_desc; // interface to use for endpoint open + + // Check device descriptor for MTT hub (bDeviceProtocol == 2) + // MTT hub has 2 alt settings: alt 0 is STT (protocol 1), alt 1 is MTT (protocol 2) + // Consume both alt settings and use alt setting 1 for endpoint + tusb_desc_device_t desc_dev; + if (tuh_descriptor_get_device_local(dev_addr, &desc_dev) && desc_dev.bDeviceProtocol == HUB_PROTOCOL_HIGH_SPEED_MTT) { + drv_len += itf_ep_len; + TU_ASSERT(drv_len <= max_len, 0); + const tusb_desc_interface_t *desc_alt1 = (const tusb_desc_interface_t *)((const uint8_t *)itf_desc + itf_ep_len); + TU_ASSERT(desc_alt1->bDescriptorType == TUSB_DESC_INTERFACE && desc_alt1->bInterfaceClass == TUSB_CLASS_HUB && + desc_alt1->bInterfaceProtocol == HUB_PROTOCOL_HIGH_SPEED_MTT, + 0); + p_hub->mtt = true; + desc_itf_use = desc_alt1; + } + // Interrupt Status endpoint - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); - TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && - TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0); + const tusb_desc_endpoint_t *desc_ep = (const tusb_desc_endpoint_t *)tu_desc_next(desc_itf_use); + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0); TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep), 0); - hub_interface_t* p_hub = get_hub_itf(dev_addr); p_hub->itf_num = itf_desc->bInterfaceNumber; p_hub->ep_in = desc_ep->bEndpointAddress; @@ -269,12 +283,27 @@ bool hub_edpt_status_xfer(uint8_t daddr) { //--------------------------------------------------------------------+ static void config_set_port_power (tuh_xfer_t* xfer); static void config_port_power_complete (tuh_xfer_t* xfer); +static void config_get_hub_descriptor(tuh_xfer_t* xfer); bool hub_set_config(uint8_t daddr, uint8_t itf_num) { hub_interface_t* p_hub = get_hub_itf(daddr); TU_ASSERT(itf_num == p_hub->itf_num); - hub_epbuf_t* p_epbuf = get_hub_epbuf(daddr); + if (p_hub->mtt) { + // Set Alternate Setting 1 for MTT hub + TU_ASSERT(tuh_interface_set(daddr, itf_num, 1, config_get_hub_descriptor, 0)); + } else { + tuh_xfer_t xfer; + xfer.daddr = daddr; + xfer.ep_addr = 0; + xfer.user_data = 0; + config_get_hub_descriptor(&xfer); + } + + return true; +} + +static void config_get_hub_descriptor(tuh_xfer_t* xfer) { // Get Hub Descriptor tusb_control_request_t const request = { .bmRequestType_bit = { @@ -288,17 +317,11 @@ bool hub_set_config(uint8_t daddr, uint8_t itf_num) { .wLength = sizeof(hub_desc_cs_t) }; - tuh_xfer_t xfer = { - .daddr = daddr, - .ep_addr = 0, - .setup = &request, - .buffer = p_epbuf->ctrl_buf, - .complete_cb = config_set_port_power, - .user_data = 0 - }; + xfer->setup = &request; + xfer->buffer = get_hub_epbuf(xfer->daddr)->ctrl_buf; + xfer->complete_cb = config_set_port_power; - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; + TU_ASSERT(tuh_control_xfer(xfer), ); } static void config_set_port_power (tuh_xfer_t* xfer) { @@ -308,7 +331,7 @@ static void config_set_port_power (tuh_xfer_t* xfer) { hub_interface_t* p_hub = get_hub_itf(daddr); hub_epbuf_t* p_epbuf = get_hub_epbuf(daddr); - // only use number of ports in hub descriptor + // only use the number of ports in the hub descriptor hub_desc_cs_t const* desc_hub = (hub_desc_cs_t const*) p_epbuf->ctrl_buf; p_hub->bNbrPorts = desc_hub->bNbrPorts; p_hub->bPwrOn2PwrGood_2ms = desc_hub->bPwrOn2PwrGood; diff --git a/src/host/hub.h b/src/host/hub.h index d9750f8a5..8a7feda70 100644 --- a/src/host/hub.h +++ b/src/host/hub.h @@ -92,6 +92,13 @@ enum { HUB_CHARS_OVER_CURRENT_INDIVIDUAL = 1, }; +// Hub Interface Protocol (USB 2.0 spec Table 11-16) +typedef enum { + HUB_PROTOCOL_FULL_SPEED = 0, // Full speed hub + HUB_PROTOCOL_HIGH_SPEED_STT = 1, // Hi-speed hub with single TT + HUB_PROTOCOL_HIGH_SPEED_MTT = 2, // Hi-speed hub with multiple TTs +} hub_protocol_t; + typedef struct TU_ATTR_PACKED{ uint8_t bLength ; ///< Size of descriptor uint8_t bDescriptorType ; ///< Other_speed_Configuration Type diff --git a/src/host/usbh.c b/src/host/usbh.c index d702e9186..75df6bf60 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -104,10 +104,9 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr) { //--------------------------------------------------------------------+ // Data Structure //--------------------------------------------------------------------+ -typedef struct { - tuh_bus_info_t bus_info; - // Device Descriptor +// Device Descriptor (without bLength and bDescriptorType header) +typedef struct TU_ATTR_PACKED { uint16_t bcdUSB; uint8_t bDeviceClass; uint8_t bDeviceSubClass; @@ -120,6 +119,13 @@ typedef struct { uint8_t iProduct; uint8_t iSerialNumber; uint8_t bNumConfigurations; +} desc_device_noheader_t; + +TU_VERIFY_STATIC( sizeof(desc_device_noheader_t) == 16u, "size is not correct"); + +typedef struct { + tuh_bus_info_t bus_info; + desc_device_noheader_t desc_device; // Device State struct TU_ATTR_PACKED { @@ -169,6 +175,12 @@ static OSAL_SPINLOCK_DEF(_usbh_spin, usbh_int_set); OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; + #if CFG_TUH_HUB +// Deferred attachment queue, only needed when using hub +OSAL_QUEUE_DEF(usbh_int_set, _usbh_daqdef, CFG_TUH_HUB, hcd_event_t); +static osal_queue_t _usbh_daq; + #endif + // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. @@ -184,11 +196,18 @@ typedef struct { } usbh_ctrl_xfer_info_t; typedef struct { + tusb_defer_func_t func; + uintptr_t arg; + uint32_t at_ms; +} usbh_call_after_t; + +typedef struct { uint8_t controller_id; // controller ID uint8_t enumerating_daddr; // device address of the device being enumerated uint8_t attach_debouncing_bm; // bitmask for roothub port attach debouncing tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer + usbh_call_after_t call_after; } usbh_data_t; static usbh_data_t _usbh_data = { @@ -311,7 +330,8 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_class_driver_t const *get_driver(uint8_ //--------------------------------------------------------------------+ // Function Inline and Prototypes //--------------------------------------------------------------------+ -static bool enum_new_device(hcd_event_t* event); +static void enum_new_device(hcd_event_t* event); +static void enum_delay_async(uintptr_t state); static void process_remove_event(hcd_event_t *event); static void remove_device_tree(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); @@ -349,6 +369,15 @@ TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const ui return ret; } +bool usbh_defer_func_ms_async(uint32_t ms, tusb_defer_func_t func, uintptr_t param) { + TU_ASSERT(_usbh_data.call_after.func == NULL); + TU_LOG_USBH("USBH schedule function after %u ms\r\n", (unsigned int)ms); + _usbh_data.call_after.func = func; + _usbh_data.call_after.arg = param; + _usbh_data.call_after.at_ms = tusb_time_millis_api() + ms; + return true; +} + TU_ATTR_ALWAYS_INLINE static inline void usbh_device_close(uint8_t rhport, uint8_t daddr) { hcd_device_close(rhport, daddr); @@ -360,6 +389,10 @@ TU_ATTR_ALWAYS_INLINE static inline void usbh_device_close(uint8_t rhport, uint8 // invalidate if enumerating if (daddr == _usbh_data.enumerating_daddr) { _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + // clear enum delay function of the device being removed + if (_usbh_data.call_after.func == enum_delay_async) { + _usbh_data.call_after.func = NULL; + } } } @@ -386,10 +419,10 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { *vid = *pid = 0; usbh_device_t const *dev = get_device(dev_addr); - TU_VERIFY(dev && dev->addressed && dev->idVendor != 0); + TU_VERIFY(dev && dev->addressed && dev->desc_device.idVendor != 0); - *vid = dev->idVendor; - *pid = dev->idProduct; + *vid = dev->desc_device.idVendor; + *pid = dev->desc_device.idProduct; return true; } @@ -400,18 +433,7 @@ bool tuh_descriptor_get_device_local(uint8_t daddr, tusb_desc_device_t* desc_dev desc_device->bLength = sizeof(tusb_desc_device_t); desc_device->bDescriptorType = TUSB_DESC_DEVICE; - desc_device->bcdUSB = dev->bcdUSB; - desc_device->bDeviceClass = dev->bDeviceClass; - desc_device->bDeviceSubClass = dev->bDeviceSubClass; - desc_device->bDeviceProtocol = dev->bDeviceProtocol; - desc_device->bMaxPacketSize0 = dev->bMaxPacketSize0; - desc_device->idVendor = dev->idVendor; - desc_device->idProduct = dev->idProduct; - desc_device->bcdDevice = dev->bcdDevice; - desc_device->iManufacturer = dev->iManufacturer; - desc_device->iProduct = dev->iProduct; - desc_device->iSerialNumber = dev->iSerialNumber; - desc_device->bNumConfigurations = dev->bNumConfigurations; + memcpy((uint8_t*) desc_device + offsetof(tusb_desc_device_t, bcdUSB), &dev->desc_device, sizeof(desc_device_noheader_t)); return true; } @@ -493,11 +515,17 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { _usbh_q = osal_queue_create(&_usbh_qdef); TU_ASSERT(_usbh_q != NULL); -#if OSAL_MUTEX_REQUIRED + #if CFG_TUH_HUB + // Deferred attachment queue + _usbh_daq = osal_queue_create(&_usbh_daqdef); + TU_ASSERT(_usbh_daq != NULL); + #endif + + #if OSAL_MUTEX_REQUIRED // Init mutex _usbh_mutex = osal_mutex_create(&_usbh_mutexdef); TU_ASSERT(_usbh_mutex); -#endif + #endif // Get application driver if available _app_driver = usbh_app_driver_get_cb(&_app_driver_count); @@ -538,7 +566,7 @@ bool tuh_deinit(uint8_t rhport) { // deinit host controller hcd_int_disable(rhport); - hcd_deinit(rhport); + TU_ASSERT(hcd_deinit(rhport)); _usbh_data.controller_id = TUSB_INDEX_INVALID_8; // remove all devices on this rhport (hub_addr = 0, hub_port = 0) @@ -558,11 +586,16 @@ bool tuh_deinit(uint8_t rhport) { osal_queue_delete(_usbh_q); _usbh_q = NULL; - #if OSAL_MUTEX_REQUIRED + #if CFG_TUH_HUB + osal_queue_delete(_usbh_daq); + _usbh_daq = NULL; + #endif + + #if OSAL_MUTEX_REQUIRED // TODO make sure there is no task waiting on this mutex osal_mutex_delete(_usbh_mutex); _usbh_mutex = NULL; - #endif + #endif } return true; @@ -570,9 +603,19 @@ bool tuh_deinit(uint8_t rhport) { bool tuh_task_event_ready(void) { if (!tuh_inited()) { - return false; // Skip if stack is not initialized + return false; // Skip if tusb stack is not initialized + } + if (!osal_queue_empty(_usbh_q)) { + return true; } - return !osal_queue_empty(_usbh_q); + + #if CFG_TUH_HUB + if (!osal_queue_empty(_usbh_daq)) { + return true; + } + #endif + + return false; } /* USB Host Driver task @@ -592,51 +635,87 @@ bool tuh_task_event_ready(void) { @endcode */ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { - (void) in_isr; // not implemented yet - // Skip if stack is not initialized if (!tuh_inited()) { return; } + (void) in_isr; // not implemented yet + // Loop until there are no more events in the queue or CFG_TUH_TASK_EVENTS_PER_RUN is reached for (unsigned epr = 0;; epr++) { -#if CFG_TUH_TASK_EVENTS_PER_RUN > 0 + #if CFG_TUH_TASK_EVENTS_PER_RUN > 0 if (epr >= CFG_TUH_TASK_EVENTS_PER_RUN) { TU_LOG_USBH("USBH event limit (" TU_XSTRING(CFG_TUH_TASK_EVENTS_PER_RUN) ") reached\r\n"); break; } -#endif + #endif + + // Process call_after_ms function if ms is reached + tusb_defer_func_t after_cb = _usbh_data.call_after.func; + if (after_cb) { + int32_t remain_ms = (int32_t)(_usbh_data.call_after.at_ms - tusb_time_millis_api()); + if (remain_ms <= 0) { + // delay expired, run callback now + TU_LOG_USBH("USBH invoke scheduled function\r\n"); + _usbh_data.call_after.func = NULL; + after_cb(_usbh_data.call_after.arg); + } + + // above after_cb() can re-schedule another function, we need to re-check and reduce timeout of + // the main event timeout to make sure we aren't blocking more than call_after remaining ms. + if (_usbh_data.call_after.func != NULL) { + remain_ms = (int32_t) (_usbh_data.call_after.at_ms - tusb_time_millis_api()); + if (remain_ms <= 0) { + timeout_ms = 0; // expired already + } else if (timeout_ms > (uint32_t)remain_ms) { + timeout_ms = (uint32_t)remain_ms; + } + } + } + hcd_event_t event; - if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; } + + #if CFG_TUH_HUB + // Get deferred device attachments if none is enumerating + bool has_deferred_attach = false; + if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) { + // zero wait to avoid blocking the main event queue + has_deferred_attach = osal_queue_receive(_usbh_daq, &event, 0); + } + + if (!has_deferred_attach) // skip event queue to process deferred attach + #endif + { + if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { + return; + } + } switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: // Should we miss the hub detach event due to high traffic, Or due to physical debouncing, some devices can - // cause multiple attaches (actually reset) without detach event. + // cause multiple attaches (actually reset) without a detached event. // Force remove currently mounted with the same bus info (rhport, hub addr, hub port) if exists process_remove_event(&event); // due to the shared control buffer, we must fully complete enumerating one device first. - // TODO better to have an separated queue for newly attached devices if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) { // New device attached and we are ready TU_LOG_USBH("[%u:] USBH Device Attach\r\n", event.rhport); _usbh_data.enumerating_daddr = 0; // enumerate new device with address 0 enum_new_device(&event); - } else { - // currently enumerating another device + } + #if CFG_TUH_HUB + else { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); - const bool is_empty = osal_queue_empty(_usbh_q); - queue_event(&event, in_isr); - if (is_empty) { - return; // Exit if this is the only event in the queue, otherwise we loop forever - } + TU_ASSERT(osal_queue_send(_usbh_daq, &event, in_isr), ); } + #endif break; case HCD_EVENT_DEVICE_REMOVE: - TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); + TU_LOG_USBH("[%u:%u:%u] USBH Device Removed\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); process_remove_event(&event); break; @@ -709,10 +788,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { break; } -#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO - // return if there is no more events, for application to run other background - if (osal_queue_empty(_usbh_q)) return; -#endif + // allow to exit tuh_task() if there is no event in the next run + timeout_ms = 0; } } @@ -770,10 +847,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { while (result == XFER_RESULT_INVALID) { // Note: this can be called within an callback ie. part of tuh_task() - // therefore event with RTOS tuh_task() still need to be invoked - if (tuh_task_event_ready()) { - tuh_task(); - } + // therefore even with RTOS tuh_task_ext() still need to be invoked + tuh_task_ext(0, false); // TODO probably some timeout to prevent hanged } @@ -1070,7 +1145,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) { } bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) { - // HACK: some device incorrectly always report 512 bulk regardless of link speed, overwrite descriptor to force 64 + // HACK: some device incorrectly always reports 512 bulk regardless of link speed, overwrite descriptor to force 64 if (desc_ep->bmAttributes.xfer == TUSB_XFER_BULK && tu_edpt_packet_size(desc_ep) > 64 && tuh_speed_get(dev_addr) == TUSB_SPEED_FULL) { TU_LOG1(" WARN: EP max packet size is 512 in fullspeed, force to 64\r\n"); @@ -1195,24 +1270,24 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->iManufacturer); - return tuh_descriptor_get_string(daddr, dev->iManufacturer, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->desc_device.iManufacturer); + return tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, language_id, buffer, len, complete_cb, user_data); } // Get product string descriptor bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->iProduct); - return tuh_descriptor_get_string(daddr, dev->iProduct, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->desc_device.iProduct); + return tuh_descriptor_get_string(daddr, dev->desc_device.iProduct, language_id, buffer, len, complete_cb, user_data); } // Get serial string descriptor bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->iSerialNumber); - return tuh_descriptor_get_string(daddr, dev->iSerialNumber, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->desc_device.iSerialNumber); + return tuh_descriptor_get_string(daddr, dev->desc_device.iSerialNumber, language_id, buffer, len, complete_cb, user_data); } // Get HID report descriptor @@ -1423,10 +1498,10 @@ enum { // USB 2.0 specs 7.1.7 for timing enum { ENUM_IDLE, ENUM_HUB_RERSET, - ENUM_HUB_GET_STATUS_AFTER_RESET, + ENUM_HUB_RESET_COMPLETE, ENUM_HUB_CLEAR_RESET, + ENUM_HUB_CLEAR_RESET_RETRY, // 2nd attempt waiting for hub reset ENUM_HUB_CLEAR_RESET_COMPLETE, - ENUM_ADDR0_DEVICE_DESC, ENUM_SET_ADDR, ENUM_GET_DEVICE_DESC, @@ -1445,138 +1520,175 @@ enum { }; static uint8_t enum_get_new_address(bool is_hub); -static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg); -static void enum_full_complete(bool success); -static void process_enumeration(tuh_xfer_t* xfer); +static bool enum_parse_configuration_desc(uint8_t dev_addr, const tusb_desc_configuration_t *desc_cfg); +static void enum_full_complete(bool success); +static void process_enumeration(tuh_xfer_t *xfer); -// start a new enumeration process -static bool enum_new_device(hcd_event_t* event) { - tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; - dev0_bus->rhport = event->rhport; - dev0_bus->hub_addr = event->connection.hub_addr; - dev0_bus->hub_port = event->connection.hub_port; +enum { + ENUM_AFTER_DEBOUNCING_DELAY, + ENUM_AFTER_RESET_ROOT_DELAY, + ENUM_AFTER_RESET_ROOT_POST_DELAY, + ENUM_AFTER_RESET_HUB_DELAY, + ENUM_AFTER_RESET_HUB_DELAY_RETRY, + ENUM_AFTER_RESET_RECOVERY_DELAY, + ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY, +}; - // wait until device connection is stable TODO non blocking - tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); +// process async delay in enumeration +static void enum_delay_async(uintptr_t state) { + tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus; + switch (state) { + case ENUM_AFTER_DEBOUNCING_DELAY: + #if CFG_TUH_HUB + if (dev0_bus->hub_addr != 0) { + // connected via hub + TU_VERIFY(dev0_bus->hub_port != 0, ); + TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, + ENUM_HUB_RERSET), ); + } else + #endif + { + // connected directly to roothub + _usbh_data.attach_debouncing_bm &= (uint8_t)~TU_BIT(dev0_bus->rhport); // clear roothub debouncing delay + if (!hcd_port_connect_status(dev0_bus->rhport)) { + TU_LOG_USBH("Device unplugged while debouncing\r\n"); + enum_full_complete(false); + return; + } + hcd_port_reset(dev0_bus->rhport); // reset port + usbh_defer_func_ms_async(ENUM_RESET_ROOT_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_ROOT_DELAY); + } + break; - if (dev0_bus->hub_addr == 0) { - // connected directly to roothub - // USB bus not active and frame number is not available yet. - // need to depend on tusb_time_millis_api() TODO non blocking + case ENUM_AFTER_RESET_ROOT_DELAY: + hcd_port_reset_end(dev0_bus->rhport); + usbh_defer_func_ms_async(ENUM_RESET_ROOT_POST_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_ROOT_POST_DELAY); + break; - _usbh_data.attach_debouncing_bm &= (uint8_t) ~TU_BIT(dev0_bus->rhport); // clear roothub debouncing delay + case ENUM_AFTER_RESET_ROOT_POST_DELAY: + if (!hcd_port_connect_status(dev0_bus->rhport)) { + // device unplugged while delaying + enum_full_complete(false); + return; + } - if (!hcd_port_connect_status(dev0_bus->rhport)) { - TU_LOG_USBH("Device unplugged while debouncing\r\n"); - enum_full_complete(false); - return true; - } + dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport); + TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]); - // reset device - hcd_port_reset(dev0_bus->rhport); - tusb_time_delay_ms_api(ENUM_RESET_ROOT_DELAY_MS); - hcd_port_reset_end(dev0_bus->rhport); - tusb_time_delay_ms_api(ENUM_RESET_ROOT_POST_DELAY_MS); + // fake transfer to kick-off the enumeration process + tuh_xfer_t xfer; + xfer.daddr = 0; + xfer.result = XFER_RESULT_SUCCESS; + xfer.user_data = ENUM_ADDR0_DEVICE_DESC; + process_enumeration(&xfer); + break; - if (!hcd_port_connect_status(dev0_bus->rhport)) { - // device unplugged while delaying - enum_full_complete(false); - return true; - } + #if CFG_TUH_HUB + case ENUM_AFTER_RESET_HUB_DELAY: + case ENUM_AFTER_RESET_HUB_DELAY_RETRY: + // get status after reset complete to check for reset change + TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, + state == ENUM_AFTER_RESET_HUB_DELAY ? ENUM_HUB_CLEAR_RESET + : ENUM_HUB_CLEAR_RESET_RETRY), ); + break; + #endif - dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport); - TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]); + case ENUM_AFTER_RESET_RECOVERY_DELAY: + // TODO probably doesn't need to open/close each enumeration + if (!usbh_edpt_control_open(0, 8)) { + TU_LOG_USBH("Failed to open dev0's control endpoint\r\n"); + enum_full_complete(false); // Stop enumeration gracefully + return; + } + // Get first 8 bytes of device descriptor for control endpoint size + TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); + TU_ASSERT(tuh_descriptor_get_device(0, _usbh_epbuf.ctrl, 8, process_enumeration, ENUM_SET_ADDR), ); + break; - // fake transfer to kick-off the enumeration process - tuh_xfer_t xfer; - xfer.daddr = 0; - xfer.result = XFER_RESULT_SUCCESS; - xfer.user_data = ENUM_ADDR0_DEVICE_DESC; - process_enumeration(&xfer); - } - #if CFG_TUH_HUB - else { - // connected via hub - TU_VERIFY(dev0_bus->hub_port != 0); - TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, - process_enumeration, ENUM_HUB_RERSET)); + case ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY: { + const uint8_t new_addr = _usbh_data.enumerating_daddr; + usbh_device_t *new_dev = get_device(new_addr); + TU_ASSERT(new_dev, ); + if (!usbh_edpt_control_open(new_addr, new_dev->desc_device.bMaxPacketSize0)) { + TU_LOG_USBH("Failed to open new device's control endpoint\r\n"); + clear_device(new_dev); + enum_full_complete(false); + return; + } + TU_LOG_USBH("Get Device Descriptor\r\n"); + TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), process_enumeration, + ENUM_GET_STRING_LANGUAGE_ID_LEN), ); + break; + } + + default: + break; } - #endif // hub +} - return true; +// start a new enumeration process +static void enum_new_device(hcd_event_t *event) { + tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus; + dev0_bus->rhport = event->rhport; + dev0_bus->hub_addr = event->connection.hub_addr; + dev0_bus->hub_port = event->connection.hub_port; + usbh_defer_func_ms_async(ENUM_DEBOUNCING_DELAY_MS, enum_delay_async, ENUM_AFTER_DEBOUNCING_DELAY); } // process device enumeration -static void process_enumeration(tuh_xfer_t* xfer) { - // Retry a few times while enumerating since device can be unstable when starting up - static uint8_t failed_count = 0; +static void process_enumeration(tuh_xfer_t *xfer) { if (XFER_RESULT_FAILED == xfer->result) { - enum { - ATTEMPT_COUNT_MAX = 3, - ATTEMPT_DELAY_MS = 100 - }; - - // retry if not reaching max attempt - failed_count++; - bool retry = (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) && (failed_count < ATTEMPT_COUNT_MAX); - if (retry) { - tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit - TU_LOG_USBH("Enumeration attempt %u/%u\r\n", failed_count+1, ATTEMPT_COUNT_MAX); - retry = tuh_control_xfer(xfer); - } - - if (!retry) { - enum_full_complete(false); // complete as failed - } + enum_full_complete(false); // failed to enum return; } - failed_count = 0; - uint8_t const daddr = xfer->daddr; - uintptr_t const state = xfer->user_data; - usbh_device_t* dev = get_device(daddr); - tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; + const uint8_t daddr = xfer->daddr; + const uintptr_t state = xfer->user_data; + usbh_device_t *dev = get_device(daddr); + tuh_bus_info_t *dev0_bus = &_usbh_data.dev0_bus; if (daddr > 0) { TU_ASSERT(dev != NULL,); } uint16_t langid = 0x0409; // default is English + bool is_enum_failed = false; switch (state) { - #if CFG_TUH_HUB + #if CFG_TUH_HUB case ENUM_HUB_RERSET: { hub_port_status_response_t port_status; hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); if (0 == port_status.status.connection) { TU_LOG_USBH("Device unplugged from hub while debouncing\r\n"); - enum_full_complete(false); - return; + is_enum_failed = true; + } else { + TU_ASSERT(hub_port_reset(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, + ENUM_HUB_RESET_COMPLETE), ); } - - TU_ASSERT(hub_port_reset(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_GET_STATUS_AFTER_RESET),); break; } - case ENUM_HUB_GET_STATUS_AFTER_RESET: { - tusb_time_delay_ms_api(ENUM_RESET_HUB_DELAY_MS); // wait for reset to take effect - - // get status to check for reset change - TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET),); + case ENUM_HUB_RESET_COMPLETE: + // wait for reset to take effect + usbh_defer_func_ms_async(ENUM_RESET_HUB_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_HUB_DELAY); break; - } - case ENUM_HUB_CLEAR_RESET: { + case ENUM_HUB_CLEAR_RESET: + case ENUM_HUB_CLEAR_RESET_RETRY: { hub_port_status_response_t port_status; hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); if (1 == port_status.change.reset) { // Acknowledge Port Reset Change - TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),); + TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, + ENUM_HUB_CLEAR_RESET_COMPLETE), ); + } else if (state == ENUM_HUB_CLEAR_RESET) { + // retry one more time if reset change not set yet + usbh_defer_func_ms_async(ENUM_RESET_HUB_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_HUB_DELAY_RETRY); } else { - // maybe retry if reset change not set but we need timeout to prevent infinite loop - // TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),); + // retry but still not set --> failed + is_enum_failed = true; } - break; } @@ -1586,70 +1698,50 @@ static void process_enumeration(tuh_xfer_t* xfer) { if (0 == port_status.status.connection) { TU_LOG_USBH("Device unplugged from hub (not addressed yet)\r\n"); - enum_full_complete(false); - return; + is_enum_failed = true; + break; } - dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : - (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; - + dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH + : (port_status.status.low_speed) ? TUSB_SPEED_LOW + : TUSB_SPEED_FULL; TU_ATTR_FALLTHROUGH; } - #endif - - case ENUM_ADDR0_DEVICE_DESC: { - tusb_time_delay_ms_api(ENUM_RESET_RECOVERY_DELAY_MS); // reset recovery - - // TODO probably doesn't need to open/close each enumeration - uint8_t const addr0 = 0; - if (!usbh_edpt_control_open(addr0, 8)) { - // Stop enumeration gracefully - enum_full_complete(false); - TU_ASSERT(false,); - } + #endif - // Get first 8 bytes of device descriptor for control endpoint size - TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8, - process_enumeration, ENUM_SET_ADDR),); + case ENUM_ADDR0_DEVICE_DESC: + usbh_defer_func_ms_async(ENUM_RESET_RECOVERY_DELAY_MS, enum_delay_async, ENUM_AFTER_RESET_RECOVERY_DELAY); break; - } case ENUM_SET_ADDR: { const tusb_desc_device_t *desc_device = (const tusb_desc_device_t *) _usbh_epbuf.ctrl; + if (!(desc_device->bDescriptorType == TUSB_DESC_DEVICE && desc_device->bMaxPacketSize0 >= 8)) { + TU_LOG_USBH("Invalid Device descriptor\r\n"); + is_enum_failed = true; + break; + } + const uint8_t new_addr = enum_get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); TU_ASSERT(new_addr != 0,); usbh_device_t* new_dev = get_device(new_addr); new_dev->bus_info = *dev0_bus; new_dev->connected = 1; - new_dev->bMaxPacketSize0 = desc_device->bMaxPacketSize0; + new_dev->desc_device.bMaxPacketSize0 = desc_device->bMaxPacketSize0; - TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC),); + TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC), ); break; } case ENUM_GET_DEVICE_DESC: { - tusb_time_delay_ms_api(ENUM_SET_ADDRESS_RECOVERY_DELAY_MS); // set address recovery - - const uint8_t new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue); - usbh_device_t* new_dev = get_device(new_addr); - TU_ASSERT(new_dev,); - new_dev->addressed = 1; + const uint8_t new_addr = (uint8_t)tu_le16toh(xfer->setup->wValue); + usbh_device_t *new_dev = get_device(new_addr); + TU_ASSERT(new_dev, ); + new_dev->addressed = 1; _usbh_data.enumerating_daddr = new_addr; usbh_device_close(dev0_bus->rhport, 0); // close dev0 - - if (!usbh_edpt_control_open(new_addr, new_dev->bMaxPacketSize0)) { // open new control endpoint - // Stop enumeration gracefully - clear_device(new_dev); - enum_full_complete(false); - TU_ASSERT(false,); - } - - TU_LOG_USBH("Get Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), - process_enumeration, ENUM_GET_STRING_LANGUAGE_ID_LEN),); + usbh_defer_func_ms_async(ENUM_SET_ADDRESS_RECOVERY_DELAY_MS, enum_delay_async, ENUM_AFTER_SET_ADDRESS_RECOVERY_DELAY); break; } @@ -1659,18 +1751,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // save the received device descriptor tusb_desc_device_t const *desc_device = (tusb_desc_device_t const *) _usbh_epbuf.ctrl; - dev->bcdUSB = desc_device->bcdUSB; - dev->bDeviceClass = desc_device->bDeviceClass; - dev->bDeviceSubClass = desc_device->bDeviceSubClass; - dev->bDeviceProtocol = desc_device->bDeviceProtocol; - dev->bMaxPacketSize0 = desc_device->bMaxPacketSize0; - dev->idVendor = desc_device->idVendor; - dev->idProduct = desc_device->idProduct; - dev->bcdDevice = desc_device->bcdDevice; - dev->iManufacturer = desc_device->iManufacturer; - dev->iProduct = desc_device->iProduct; - dev->iSerialNumber = desc_device->iSerialNumber; - dev->bNumConfigurations = desc_device->bNumConfigurations; + memcpy(&dev->desc_device, (const uint8_t*) desc_device + offsetof(tusb_desc_device_t, bcdUSB), sizeof(desc_device_noheader_t)); tuh_enum_descriptor_device_cb(daddr, desc_device); // callback tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, 2, @@ -1690,8 +1771,8 @@ static void process_enumeration(tuh_xfer_t* xfer) { if (desc_langid->bLength >= 4) { langid = tu_le16toh(desc_langid->utf16le[0]); // previous request is langid } - if (dev->iManufacturer != 0) { - tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, 2, + if (dev->desc_device.iManufacturer != 0) { + tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_MANUFACTURER); break; } @@ -1699,10 +1780,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_MANUFACTURER: { - if (dev->iManufacturer != 0) { + if (dev->desc_device.iManufacturer != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->desc_device.iManufacturer, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_STRING_PRODUCT_LEN); break; } @@ -1710,22 +1791,22 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_PRODUCT_LEN: { - if (dev->iProduct != 0) { + if (dev->desc_device.iProduct != 0) { if (state == ENUM_GET_STRING_PRODUCT_LEN) { langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through } tuh_descriptor_get_string( - daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_PRODUCT); + daddr, dev->desc_device.iProduct, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_PRODUCT); break; } TU_ATTR_FALLTHROUGH; } case ENUM_GET_STRING_PRODUCT: { - if (dev->iProduct != 0) { + if (dev->desc_device.iProduct != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->desc_device.iProduct, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_STRING_SERIAL_LEN); break; } @@ -1733,22 +1814,22 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_SERIAL_LEN: { - if (dev->iSerialNumber != 0) { + if (dev->desc_device.iSerialNumber != 0) { if (state == ENUM_GET_STRING_SERIAL_LEN) { langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through } tuh_descriptor_get_string( - daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_SERIAL); + daddr, dev->desc_device.iSerialNumber, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_SERIAL); break; } TU_ATTR_FALLTHROUGH; } case ENUM_GET_STRING_SERIAL: { - if (dev->iSerialNumber != 0) { + if (dev->desc_device.iSerialNumber != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->desc_device.iSerialNumber, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC); break; } @@ -1787,7 +1868,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { TU_ASSERT(tuh_configuration_set(daddr, config_idx+1u, process_enumeration, ENUM_CONFIG_DRIVER),); } else { config_idx++; - TU_ASSERT(config_idx < dev->bNumConfigurations,); + TU_ASSERT(config_idx < dev->desc_device.bNumConfigurations,); TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx); TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); @@ -1799,11 +1880,12 @@ static void process_enumeration(tuh_xfer_t* xfer) { TU_LOG_USBH("Device configured\r\n"); dev->configured = 1; - #if CFG_TUH_HUB + #if CFG_TUH_HUB + // get next hub status now since device can be unplugged before set_configure() is complete if (_usbh_data.dev0_bus.hub_addr != 0) { - hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); // get next hub status + hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); } - #endif + #endif // Parse configuration & set up drivers // driver_open() must not make any usb transfer @@ -1818,9 +1900,13 @@ static void process_enumeration(tuh_xfer_t* xfer) { } default: - enum_full_complete(false); // stop enumeration if unknown state + is_enum_failed = true; break; } + + if (is_enum_failed) { + enum_full_complete(false); + } } static uint8_t enum_get_new_address(bool is_hub) { @@ -1858,10 +1944,10 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len); - // parse each interfaces + // parse all interfaces while (tu_desc_in_bounds(p_desc, desc_end)) { if (0 == tu_desc_len(p_desc)) { - // A zero length descriptor indicates that the device is off spec (e.g. wrong wTotalLength). + // A zero-length descriptor indicates that the device is off spec (e.g. wrong wTotalLength). // Parsed interfaces should still be usable TU_LOG_USBH("Encountered a zero-length descriptor after %" PRIu32 " bytes\r\n", (uint32_t)p_desc - (uint32_t)desc_cfg); break; @@ -1877,7 +1963,7 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat // uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) // (desc_end-p_desc)); TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); - // Find driver for this interface + // Find a driver for this interface const uint16_t remaining_len = (uint16_t)(desc_end - p_desc); uint8_t drv_id; for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { @@ -1925,7 +2011,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { } } - // all interface are configured + // all interfaces are configured if (itf_num == CFG_TUH_INTERFACE_MAX) { enum_full_complete(true); @@ -1940,16 +2026,17 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { static void enum_full_complete(bool success) { (void)success; - // mark enumeration as complete - _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + TU_LOG_USBH("Enumeration complete: success = %u\r\n", success); -#if CFG_TUH_HUB + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; // mark enumeration as complete + _usbh_data.call_after.func = NULL; + + #if CFG_TUH_HUB // Hub status is already requested in case of successful enumeration - if (_usbh_data.dev0_bus.hub_addr != 0 && !success) { - hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); // get next hub status + if (!success && _usbh_data.dev0_bus.hub_addr != 0) { + hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); } -#endif - + #endif } #endif diff --git a/src/host/usbh.h b/src/host/usbh.h index 143d36f8c..7ddec35b7 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -41,8 +41,7 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -// Endpoint Bulk size depending on host mx speed -#define TUH_EPSIZE_BULK_MPS (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) + // forward declaration struct tuh_xfer_s; diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 57428e3c5..adb6a8c44 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -68,8 +68,12 @@ uint8_t* usbh_get_enum_buf(void); void usbh_int_set(bool enabled); +// Invoke this function later in tuh_task() by putting it into task queue void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr); +// Schedules a function to be called after certain time asynchronously +bool usbh_defer_func_ms_async(uint32_t ms, tusb_defer_func_t func, uintptr_t param); + void usbh_spin_lock(bool in_isr); void usbh_spin_unlock(bool in_isr); diff --git a/src/osal/osal.h b/src/osal/osal.h index 44521620f..4840463f3 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -65,6 +65,8 @@ typedef void (*osal_task_func_t)(void* param); #include "osal_rtx4.h" #elif CFG_TUSB_OS == OPT_OS_ZEPHYR #include "osal_zephyr.h" +#elif CFG_TUSB_OS == OPT_OS_THREADX + #include "osal_threadx.h" #elif CFG_TUSB_OS == OPT_OS_CUSTOM #include "tusb_os_custom.h" // implemented by application #else @@ -74,6 +76,8 @@ typedef void (*osal_task_func_t)(void* param); /*-------------------------------------------------------------------- OSAL Porting API Should be implemented as static inline function in osal_port.h header + uint32_t osal_time_millis(void); + void osal_spin_init(osal_spinlock_t *ctx); void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr); diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 9aeda4d01..db724179d 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -99,6 +99,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { vTaskDelay(pdMS_TO_TICKS(msec)); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return pdTICKS_TO_MS(xTaskGetTickCount()); +} + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ @@ -137,11 +141,12 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { if (in_isr) { - if (TUP_MCU_MULTIPLE_CORE == 0) { - (void) ctx; - return; // single core MCU does not need to lock in ISR - } + #if TUP_MCU_MULTIPLE_CORE *ctx = taskENTER_CRITICAL_FROM_ISR(); + #else + (void) ctx; + return; // single core MCU does not need to lock in ISR + #endif } else { taskENTER_CRITICAL(); } @@ -149,11 +154,12 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bo TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { if (in_isr) { - if (TUP_MCU_MULTIPLE_CORE == 0) { - (void) ctx; - return; // single core MCU does not need to lock in ISR - } + #if TUP_MCU_MULTIPLE_CORE taskEXIT_CRITICAL_FROM_ISR(*ctx); + #else + (void) ctx; + return; // single core MCU does not need to lock in ISR + #endif } else { taskEXIT_CRITICAL(); } diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h index 6d51f8ec3..94124ca81 100644 --- a/src/osal/osal_mynewt.h +++ b/src/osal/osal_mynewt.h @@ -40,6 +40,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { os_time_delay( os_time_ms_to_ticks32(msec) ); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return os_time_ticks_to_ms32(os_time_get()); +} + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 6ab18ace8..7bf6029d6 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -31,6 +31,8 @@ extern "C" { #endif +// osal_time_millis() is not provided, tusb_time_millis_api() must be implemented by user application + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ @@ -184,7 +186,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v (void) msec; // not used, always behave as msec = 0 qhdl->interrupt_set(false); - const bool success = tu_fifo_read_n(&qhdl->ff, data, qhdl->item_size); + const bool success = (tu_fifo_read_n(&qhdl->ff, data, qhdl->item_size) > 0); qhdl->interrupt_set(true); return success; @@ -195,7 +197,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void qhdl->interrupt_set(false); } - const bool success = tu_fifo_write_n(&qhdl->ff, data, qhdl->item_size); + const bool success = (tu_fifo_write_n(&qhdl->ff, data, qhdl->item_size) > 0); if (!in_isr) { qhdl->interrupt_set(true); diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h index 79b728e9a..6a0a21bb3 100644 --- a/src/osal/osal_pico.h +++ b/src/osal/osal_pico.h @@ -43,6 +43,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { sleep_ms(msec); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return to_ms_since_boot(get_absolute_time()); +} + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index a778f5425..f560281c5 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -42,6 +42,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { rt_thread_mdelay(msec); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return (uint32_t)((((uint64_t)rt_tick_get()) * 1000) / RT_TICK_PER_SECOND); +} + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h index 35860ddd5..e1930c96c 100644 --- a/src/osal/osal_rtx4.h +++ b/src/osal/osal_rtx4.h @@ -46,6 +46,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { os_dly_wait(lo); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return os_time_get(); +} + TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) { if (msec == OSAL_TIMEOUT_WAIT_FOREVER) { return 0xFFFF; diff --git a/src/osal/osal_threadx.h b/src/osal/osal_threadx.h new file mode 100644 index 000000000..6bcf9c5ab --- /dev/null +++ b/src/osal/osal_threadx.h @@ -0,0 +1,201 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_OSAL_THREADX_H_ +#define TUSB_OSAL_THREADX_H_ + +// ThreadX Headers +#include "tx_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) { + if ( msec == TX_WAIT_FOREVER ) { + return TX_WAIT_FOREVER; + } + if ( msec == 0 ) { + return 0; + } + + uint32_t ticks = msec * TX_TIMER_TICKS_PER_SECOND / 1000; + + // TX_TIMER_TICKS_PER_SECOND is less than 1000 and 1 tick > 1 ms + // we still need to delay at least 1 tick + if ( ticks == 0 ) { + ticks = 1; + } + + return ticks; +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return (uint32_t)((uint64_t) tx_time_get() * 1000u / TX_TIMER_TICKS_PER_SECOND); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { + tx_thread_sleep(_osal_ms2tick(msec)); +} + +//--------------------------------------------------------------------+ +// Spinlock API +//--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Spinlock API +//--------------------------------------------------------------------+ +typedef struct { + void (* interrupt_set)(bool); +} osal_spinlock_t; + +// For SMP, spinlock must be locked by hardware, cannot just use interrupt +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name = { .interrupt_set = _int_set } + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { + if (!in_isr) { + ctx->interrupt_set(false); + } +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { + if (!in_isr) { + ctx->interrupt_set(true); + } +} + + +//--------------------------------------------------------------------+ +// Binary Semaphore API (act) +//--------------------------------------------------------------------+ +// Note: semaphores are not used in tinyusb for now, and their API has not been tested + +typedef TX_SEMAPHORE osal_semaphore_def_t, * osal_semaphore_t; + +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) { + tx_semaphore_create(semdef, TX_NULL, 0); + return semdef; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t sem_hdl) { + (void) sem_hdl; + return TX_SUCCESS == tx_semaphore_delete(sem_hdl); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { + (void) in_isr; + return TX_SUCCESS == tx_semaphore_put(sem_hdl); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { + return TX_SUCCESS == tx_semaphore_get(sem_hdl, _osal_ms2tick(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { + (void) sem_hdl; +} + +//--------------------------------------------------------------------+ +// MUTEX API +//--------------------------------------------------------------------+ +typedef TX_MUTEX osal_mutex_def_t, *osal_mutex_t; + +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) { + if (TX_SUCCESS == tx_mutex_create(mdef, mdef->tx_mutex_name, TX_NO_INHERIT)) { + return mdef; + } else { + return NULL; + } +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { + return TX_SUCCESS == tx_mutex_get(mutex_hdl, _osal_ms2tick(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { + return TX_SUCCESS == tx_mutex_put(mutex_hdl); +} + +//--------------------------------------------------------------------+ +// QUEUE API +//--------------------------------------------------------------------+ + +typedef TX_QUEUE osal_queue_def_t, * osal_queue_t; + +// _int_set is not used with an RTOS _usbd_qdef + +#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \ +static _type _name##_buf[_depth]; \ +osal_queue_def_t _name = { \ + .tx_queue_name = (CHAR*)(uintptr_t)#_name, \ + .tx_queue_message_size = (sizeof(_type) + 3) / 4, \ + .tx_queue_capacity = _depth, \ + .tx_queue_start = (ULONG *) _name##_buf } + + +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { + return TX_SUCCESS == + tx_queue_create(qdef, qdef->tx_queue_name, qdef->tx_queue_message_size, qdef->tx_queue_start, qdef->tx_queue_capacity * qdef->tx_queue_message_size * 4) + ? qdef : 0; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + (void) qhdl; + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { + return 0 == tx_queue_receive(qhdl, data, _osal_ms2tick(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { + return 0 == tx_queue_send(qhdl, (VOID *)(uintptr_t) data, in_isr ? TX_NO_WAIT : TX_WAIT_FOREVER); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { + ULONG enqueued; + tx_queue_info_get(qhdl, 0, &enqueued, 0, 0, 0, 0); + return enqueued == 0; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h index 91f225f79..900ac786c 100644 --- a/src/osal/osal_zephyr.h +++ b/src/osal/osal_zephyr.h @@ -35,6 +35,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { k_msleep(msec); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t osal_time_millis(void) { + return k_uptime_get_32(); +} + //--------------------------------------------------------------------+ // Spinlock API //--------------------------------------------------------------------+ diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h index 178eec419..c22aea887 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h +++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h @@ -47,10 +47,10 @@ static const ci_hs_controller_t _ci_controller[] = #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) -#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) -#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) #endif diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 2bba32ada..9ed75ffd9 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -285,6 +285,23 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) { return true; } +bool dcd_deinit(uint8_t rhport) { + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); + + // disable all interrupt + dcd_reg->USBINTR = 0; + + // unattach from bus + dcd_reg->USBCMD &= ~USBCMD_RUN_STOP; + + // flush all endpoints + while (dcd_reg->ENDPTPRIME) {} + dcd_reg->ENDPTFLUSH = 0xFFFFFFFF; + while (dcd_reg->ENDPTFLUSH) {} + + return true; +} + void dcd_int_enable(uint8_t rhport) { CI_DCD_INT_ENABLE(rhport); } @@ -371,7 +388,7 @@ TU_ATTR_ALWAYS_INLINE static inline void ep_ctrl_mask(volatile uint32_t *epctrl, uint32_t or_mask) { uint32_t value = *epctrl; if (and_mask != 0) { - value &= (dir == TUSB_DIR_OUT) ? and_mask : (and_mask << 16u); + value &= (dir == TUSB_DIR_OUT) ? (and_mask | 0xFFFF0000u) : ((and_mask << 16u) | 0x0000FFFFu); } if (or_mask != 0) { value |= (dir == TUSB_DIR_OUT) ? or_mask : (or_mask << 16u); diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 29ce0cd7f..c0d14fe57 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -93,21 +93,25 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) { hcd_reg->USBCMD |= USBCMD_RESET; while (hcd_reg->USBCMD & USBCMD_RESET) {} - // Set mode to device, must be set immediately after reset + // Set mode to host, must be set immediately after reset #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX // LPC18XX/43XX need to set VBUS Power Select to HIGH - // RHPORT1 is fullspeed only (need external PHY for Highspeed) hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT; - if (rhport == 1) { - hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; - } #else hcd_reg->USBMODE = USBMODE_CM_HOST; #endif + #if !TUH_OPT_HIGH_SPEED + hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; + #endif + return ehci_init(rhport, (uint32_t)&hcd_reg->CAPLENGTH, (uint32_t)&hcd_reg->USBCMD); } +bool hcd_deinit(uint8_t rhport) { + return ehci_deinit(rhport); +} + void hcd_int_enable(uint8_t rhport) { CI_HCD_INT_ENABLE(rhport); } diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 9b2cf98be..03c3b91fd 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -411,17 +411,22 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) return true; } -#if 0 -static void ehci_stop(uint8_t rhport) { +bool ehci_deinit(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; + + // Disable all the interrupt + regs->inten = 0; + + // Disable schedules regs->command_bm.run_stop = 0; // USB Spec: controller has to stop within 16 uframe = 2 frames while( regs->status_bm.hc_halted == 0 ) {} + + return true; } -#endif //--------------------------------------------------------------------+ // Endpoint API diff --git a/src/portable/ehci/ehci_api.h b/src/portable/ehci/ehci_api.h index 79fbe702a..e9018639f 100644 --- a/src/portable/ehci/ehci_api.h +++ b/src/portable/ehci/ehci_api.h @@ -38,6 +38,9 @@ // Initialize EHCI driver bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg); +// De-initialize EHCI driver +bool ehci_deinit(uint8_t rhport); + #ifdef __cplusplus } #endif diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index b0a053c01..6da1e9778 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -1,133 +1,117 @@ /* -* The MIT License (MIT) -* -* Copyright (c) 2018, hathach (tinyusb.org) -* Copyright (c) 2021, HiFiPhile -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -* THE SOFTWARE. -* -* This file is part of the TinyUSB stack. -*/ + * The MIT License (MIT) + * + * Copyright (c) 2018, hathach (tinyusb.org) + * Copyright (c) 2021, HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ #include "tusb_option.h" #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X -#include "device/dcd.h" -#include "sam.h" -#include "common_usb_regs.h" -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#ifndef USE_SOF -# define USE_SOF 0 -#endif - -// Dual bank can improve performance, but need 2 times bigger packet buffer -// As SAM7x has only 4KB packet buffer, use with caution ! -// Enable in FS mode as packets are smaller -#ifndef USE_DUAL_BANK -# if TUD_OPT_HIGH_SPEED -# define USE_DUAL_BANK 0 -# else -# define USE_DUAL_BANK 1 -# endif -#endif + #include "device/dcd.h" + #include "sam.h" + #include "samx7x_common.h" + //--------------------------------------------------------------------+ + // MACRO TYPEDEF CONSTANT ENUM DECLARATION + //--------------------------------------------------------------------+ -#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])FIFO_RAM_ADDR)[(ep)]) + // Dual bank can improve performance, but need 2 times bigger packet buffer + // As SAM7x has only 4KB packet buffer, use with caution ! + // Enable in FS mode as packets are smaller + #ifndef USE_DUAL_BANK + #if TUD_OPT_HIGH_SPEED + #define USE_DUAL_BANK 0 + #else + #define USE_DUAL_BANK 1 + #endif + #endif -// DMA Channel Transfer Descriptor -typedef struct { - volatile uint32_t next_desc; - volatile uint32_t buff_addr; - volatile uint32_t chnl_ctrl; - uint32_t padding; -} dma_desc_t; + #define EP_GET_FIFO_PTR(ep, scale) \ + (((TU_XSTRCAT(TU_STRCAT(uint, scale), _t)(*)[0x8000 / ((scale) / 8)]) FIFO_RAM_ADDR)[(ep)]) // Transfer control context typedef struct { - uint8_t * buffer; - uint16_t total_len; - uint16_t queued_len; - uint16_t max_packet_size; - uint8_t interval; - tu_fifo_t * fifo; + uint8_t *buffer; + uint16_t total_len; + uint16_t queued_len; + uint16_t max_packet_size; + uint8_t interval; + tu_fifo_t *fifo; } xfer_ctl_t; static tusb_speed_t get_speed(void); -static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix); - -// DMA descriptors shouldn't be placed in ITCM ! -CFG_TUD_MEM_SECTION static dma_desc_t dma_desc[6]; +static void dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix); static xfer_ctl_t xfer_status[EP_MAX]; -static const tusb_desc_endpoint_t ep0_desc = -{ +static const tusb_desc_endpoint_t ep0_desc = { .bEndpointAddress = 0x00, .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, }; -TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size) -{ - if (SCB->CCR & SCB_CCR_DC_Msk) - { - SCB_CleanInvalidateDCache_by_Addr(addr, size); - } - else - { - __DSB(); - __ISB(); - } + #if CFG_TUD_MEM_DCACHE_ENABLE +bool dcd_dcache_clean(const void *addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return samx7x_dcache_clean(addr, data_size); } + +bool dcd_dcache_invalidate(const void *addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return samx7x_dcache_invalidate(addr, data_size); +} + +bool dcd_dcache_clean_invalidate(const void *addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return samx7x_dcache_clean_invalidate(addr, data_size); +} + #endif //------------------------------------------------------------------ // Device API //------------------------------------------------------------------ // Initialize controller to device mode -bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rh_init; +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) { + (void)rh_init; dcd_connect(rhport); return true; } // Enable device interrupt -void dcd_int_enable (uint8_t rhport) -{ - (void) rhport; - NVIC_EnableIRQ((IRQn_Type) ID_USBHS); +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + NVIC_EnableIRQ((IRQn_Type)ID_USBHS); } // Disable device interrupt -void dcd_int_disable (uint8_t rhport) -{ - (void) rhport; - NVIC_DisableIRQ((IRQn_Type) ID_USBHS); +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + NVIC_DisableIRQ((IRQn_Type)ID_USBHS); } // Receive Set Address request, mcu port must also include status IN response -void dcd_set_address (uint8_t rhport, uint8_t dev_addr) -{ - (void) dev_addr; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void)dev_addr; // DCD can only set address after status for this request is complete // do it at dcd_edpt0_status_complete() @@ -136,30 +120,26 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup (uint8_t rhport) -{ - (void) rhport; +void dcd_remote_wakeup(uint8_t rhport) { + (void)rhport; USB_REG->DEVCTRL |= DEVCTRL_RMWKUP; } // Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ - (void) rhport; +void dcd_connect(uint8_t rhport) { + (void)rhport; dcd_int_disable(rhport); // Enable the USB controller in device mode USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE; - while (!(USB_REG->SR & SR_CLKUSABLE)); -#if TUD_OPT_HIGH_SPEED + while (!(USB_REG->SR & SR_CLKUSABLE)) + ; + #if TUD_OPT_HIGH_SPEED USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF; -#else + #else USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER; -#endif + #endif // Enable the End Of Reset, Suspend & Wakeup interrupts USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES); -#if USE_SOF - USB_REG->DEVIER = DEVIER_SOFES; -#endif // Clear the End Of Reset, SOF & Wakeup interrupts USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC); // Manually set the Suspend Interrupt @@ -173,15 +153,15 @@ void dcd_connect(uint8_t rhport) } // Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ - (void) rhport; +void dcd_disconnect(uint8_t rhport) { + (void)rhport; dcd_int_disable(rhport); // Disable all endpoints USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos); // Unfreeze USB clock USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); + while (!(USB_REG->SR & SR_CLKUSABLE)) + ; // Clear all the pending interrupts USB_REG->DEVICR = DEVICR_Msk; // Disable all interrupts @@ -189,127 +169,106 @@ void dcd_disconnect(uint8_t rhport) // Detach the device USB_REG->DEVCTRL |= DEVCTRL_DETACH; // Disable the device address - USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD); + USB_REG->DEVCTRL &= ~(DEVCTRL_ADDEN | DEVCTRL_UADD); } -void dcd_sof_enable(uint8_t rhport, bool en) -{ - (void) rhport; - (void) en; - - // TODO implement later +void dcd_sof_enable(uint8_t rhport, bool en) { + (void)rhport; + if (en) { + USB_REG->DEVIER = DEVIER_SOFES; + } else { + USB_REG->DEVIDR = DEVIDR_SOFEC; + } } -static tusb_speed_t get_speed(void) -{ +static tusb_speed_t get_speed(void) { switch (USB_REG->SR & SR_SPEED) { - case SR_SPEED_FULL_SPEED: - default: - return TUSB_SPEED_FULL; - case SR_SPEED_HIGH_SPEED: - return TUSB_SPEED_HIGH; - case SR_SPEED_LOW_SPEED: - return TUSB_SPEED_LOW; + case SR_SPEED_FULL_SPEED: + default: + return TUSB_SPEED_FULL; + case SR_SPEED_HIGH_SPEED: + return TUSB_SPEED_HIGH; + case SR_SPEED_LOW_SPEED: + return TUSB_SPEED_LOW; } } -static void dcd_ep_handler(uint8_t ep_ix) -{ +static void dcd_ep_handler(uint8_t ep_ix) { uint32_t int_status = USB_REG->DEVEPTISR[ep_ix]; int_status &= USB_REG->DEVEPTIMR[ep_ix]; - uint16_t count = (USB_REG->DEVEPTISR[ep_ix] & - DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos; - xfer_ctl_t *xfer = &xfer_status[ep_ix]; + uint16_t count = (USB_REG->DEVEPTISR[ep_ix] & DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos; + xfer_ctl_t *xfer = &xfer_status[ep_ix]; - if (ep_ix == 0U) - { + if (ep_ix == 0U) { static uint8_t ctrl_dir; - if (int_status & DEVEPTISR_CTRL_RXSTPI) - { + if (int_status & DEVEPTISR_CTRL_RXSTPI) { ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos; // Setup packet should always be 8 bytes. If not, ignore it, and try again. - if (count == 8) - { - uint8_t *ptr = EP_GET_FIFO_PTR(0,8); + if (count == 8) { + uint8_t *ptr = EP_GET_FIFO_PTR(0, 8); dcd_event_setup_received(0, ptr, true); } // Ack and disable SETUP interrupt USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC; USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC; } - if (int_status & DEVEPTISR_RXOUTI) - { - uint8_t *ptr = EP_GET_FIFO_PTR(0,8); + if (int_status & DEVEPTISR_RXOUTI) { + uint8_t *ptr = EP_GET_FIFO_PTR(0, 8); - if (count && xfer->total_len) - { + if (count && xfer->total_len) { uint16_t remain = xfer->total_len - xfer->queued_len; - if (count > remain) - { + if (count > remain) { count = remain; } - if (xfer->buffer) - { + if (xfer->buffer) { memcpy(xfer->buffer + xfer->queued_len, ptr, count); - } else - { - tu_fifo_write_n(xfer->fifo, ptr, count); + } else { + tu_hwfifo_read_to_fifo(ptr, xfer->fifo, count, NULL); } xfer->queued_len = (uint16_t)(xfer->queued_len + count); } // Acknowledge the interrupt USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC; - if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) - { + if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { // RX COMPLETE dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC; // Re-enable SETUP interrupt - if (ctrl_dir == 1) - { + if (ctrl_dir == 1) { USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; } } } - if (int_status & DEVEPTISR_TXINI) - { + if (int_status & DEVEPTISR_TXINI) { // Disable the interrupt USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC; - if ((xfer->total_len != xfer->queued_len)) - { + if ((xfer->total_len != xfer->queued_len)) { // TX not complete dcd_transmit_packet(xfer, 0); - } else - { + } else { // TX complete dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true); // Re-enable SETUP interrupt - if (ctrl_dir == 0) - { + if (ctrl_dir == 0) { USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; } } } - } else - { - if (int_status & DEVEPTISR_RXOUTI) - { - if (count && xfer->total_len) - { + } else { + if (int_status & DEVEPTISR_RXOUTI) { + if (count && xfer->total_len) { uint16_t remain = xfer->total_len - xfer->queued_len; - if (count > remain) - { + if (count > remain) { count = remain; } - uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8); - if (xfer->buffer) - { + uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8); + if (xfer->buffer) { memcpy(xfer->buffer + xfer->queued_len, ptr, count); } else { - tu_fifo_write_n(xfer->fifo, ptr, count); + tu_hwfifo_read_to_fifo(ptr, xfer->fifo, count, NULL); } xfer->queued_len = (uint16_t)(xfer->queued_len + count); } @@ -317,8 +276,7 @@ static void dcd_ep_handler(uint8_t ep_ix) USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; // Acknowledge the interrupt USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC; - if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) - { + if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) { // RX COMPLETE dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt @@ -326,16 +284,13 @@ static void dcd_ep_handler(uint8_t ep_ix) // Though the host could still send, we don't know. } } - if (int_status & DEVEPTISR_TXINI) - { + if (int_status & DEVEPTISR_TXINI) { // Acknowledge the interrupt USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC; - if ((xfer->total_len != xfer->queued_len)) - { + if ((xfer->total_len != xfer->queued_len)) { // TX not complete dcd_transmit_packet(xfer, ep_ix); - } else - { + } else { // TX complete dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true); // Disable the interrupt @@ -345,45 +300,40 @@ static void dcd_ep_handler(uint8_t ep_ix) } } -static void dcd_dma_handler(uint8_t ep_ix) -{ +static void dcd_dma_handler(uint8_t ep_ix) { uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS; - if (status & DEVDMASTATUS_CHANN_ENB) - { + if (status & DEVDMASTATUS_CHANN_ENB) { return; // Ignore EOT_STA interrupt } // Disable DMA interrupt USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1); - xfer_ctl_t *xfer = &xfer_status[ep_ix]; - uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos); - if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) - { + xfer_ctl_t *xfer = &xfer_status[ep_ix]; + uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos); + if (USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) { dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true); - } else - { + } else { + dcd_dcache_invalidate(xfer->buffer, count); dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true); } } -void dcd_int_handler(uint8_t rhport) -{ - (void) rhport; +void dcd_int_handler(uint8_t rhport) { + (void)rhport; uint32_t int_status = USB_REG->DEVISR; int_status &= USB_REG->DEVIMR; // End of reset interrupt - if (int_status & DEVISR_EORST) - { + if (int_status & DEVISR_EORST) { // Unfreeze USB clock USB_REG->CTRL &= ~CTRL_FRZCLK; - while(!(USB_REG->SR & SR_CLKUSABLE)); + while (!(USB_REG->SR & SR_CLKUSABLE)) + ; // Reset all endpoints - for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) - { + for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) { USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix); - USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + ep_ix)); + USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + ep_ix)); } - dcd_edpt_open (0, &ep0_desc); + dcd_edpt_open(0, &ep0_desc); USB_REG->DEVICR = DEVICR_EORSTC; USB_REG->DEVICR = DEVICR_WAKEUPC; USB_REG->DEVICR = DEVICR_SUSPC; @@ -392,10 +342,10 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_reset(rhport, get_speed(), true); } // End of Wakeup interrupt - if (int_status & DEVISR_WAKEUP) - { + if (int_status & DEVISR_WAKEUP) { USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); + while (!(USB_REG->SR & SR_CLKUSABLE)) + ; USB_REG->DEVICR = DEVICR_WAKEUPC; USB_REG->DEVIDR = DEVIDR_WAKEUPEC; USB_REG->DEVIER = DEVIER_SUSPES; @@ -403,11 +353,11 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } // Suspend interrupt - if (int_status & DEVISR_SUSP) - { + if (int_status & DEVISR_SUSP) { // Unfreeze USB clock USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)); + while (!(USB_REG->SR & SR_CLKUSABLE)) + ; USB_REG->DEVICR = DEVICR_SUSPC; USB_REG->DEVIDR = DEVIDR_SUSPEC; USB_REG->DEVIER = DEVIER_WAKEUPES; @@ -415,29 +365,21 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } -#if USE_SOF - if(int_status & DEVISR_SOF) - { + if (int_status & DEVISR_SOF) { USB_REG->DEVICR = DEVICR_SOFC; dcd_event_bus_signal(0, DCD_EVENT_SOF, true); } -#endif // Endpoints interrupt - for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) - { - if (int_status & (DEVISR_PEP_0 << ep_ix)) - { + for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) { + if (int_status & (DEVISR_PEP_0 << ep_ix)) { dcd_ep_handler(ep_ix); } } // Endpoints DMA interrupt - for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) - { - if (EP_DMA_SUPPORT(ep_ix)) - { - if (int_status & (DEVISR_DMA_1 << (ep_ix - 1))) - { + for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) { + if (EP_DMA_SUPPORT(ep_ix)) { + if (int_status & (DEVISR_DMA_1 << (ep_ix - 1))) { dcd_dma_handler(ep_ix); } } @@ -449,35 +391,29 @@ void dcd_int_handler(uint8_t rhport) //--------------------------------------------------------------------+ // Invoked when a control transfer's status stage is complete. // May help DCD to prepare for next control transfer, this API is optional. -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) -{ - (void) rhport; +void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t *request) { + (void)rhport; if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS ) - { - uint8_t const dev_addr = (uint8_t) request->wValue; + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) { + const uint8_t dev_addr = (uint8_t)request->wValue; USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN; } } // Configure endpoint's registers according to descriptor -bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress); - uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc); - tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; - uint8_t fifoSize = 0; // FIFO size - uint16_t defaultEndpointSize = 8; // Default size of Endpoint +bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) { + (void)rhport; + const uint8_t epnum = tu_edpt_number(ep_desc->bEndpointAddress); + const uint8_t dir = tu_edpt_dir(ep_desc->bEndpointAddress); + const uint16_t epMaxPktSize = tu_edpt_packet_size(ep_desc); + const tusb_xfer_type_t eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; + uint8_t fifoSize = 0; // FIFO size + uint16_t defaultEndpointSize = 8; // Default size of Endpoint // Find upper 2 power number of epMaxPktSize - if (epMaxPktSize) - { - while (defaultEndpointSize < epMaxPktSize) - { + if (epMaxPktSize) { + while (defaultEndpointSize < epMaxPktSize) { fifoSize++; defaultEndpointSize <<= 1; } @@ -485,121 +421,94 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) xfer_status[epnum].max_packet_size = epMaxPktSize; USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum); - USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + epnum)); + USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + epnum)); - if (epnum == 0) - { + if (epnum == 0) { // Enable the control endpoint - Endpoint 0 USB_REG->DEVEPT |= DEVEPT_EPEN0; // Configure the Endpoint 0 configuration register - USB_REG->DEVEPTCFG[0] = - ( - (fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_ALLOC - ); + USB_REG->DEVEPTCFG[0] = ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) | + (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | DEVEPTCFG_ALLOC); USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS; USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK)) - { + if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK)) { // Endpoint configuration is successful USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; // Enable Endpoint 0 Interrupts USB_REG->DEVIER = DEVIER_PEP_0; return true; - } else - { + } else { // Endpoint configuration is not successful return false; } - } else - { + } else { // Enable the endpoint USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos); // Set up the maxpacket size, fifo start address fifosize // and enable the interrupt. CLear the data toggle. // AUTOSW is needed for DMA ack ! USB_REG->DEVEPTCFG[epnum] = - ( - (fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (eptype << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_AUTOSW | - ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos) - ); - if (eptype == TUSB_XFER_ISOCHRONOUS) - { + ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | (eptype << DEVEPTCFG_EPTYPE_Pos) | + (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | DEVEPTCFG_AUTOSW | ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos)); + if (eptype == TUSB_XFER_ISOCHRONOUS) { USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS; } -#if USE_DUAL_BANK - if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) - { + #if USE_DUAL_BANK + if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) { USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK; } -#endif + #endif USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC; USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS; USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK)) - { + if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK)) { USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos); return true; - } else - { + } else { // Endpoint configuration is not successful return false; } } } -void dcd_edpt_close_all (uint8_t rhport) -{ - (void) rhport; +void dcd_edpt_close_all(uint8_t rhport) { + (void)rhport; // TODO implement dcd_edpt_close_all() } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - (void) rhport; - (void) ep_addr; - (void) largest_packet_size; + (void)rhport; + (void)ep_addr; + (void)largest_packet_size; return false; } -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) { - (void) rhport; - (void) desc_ep; +bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *desc_ep) { + (void)rhport; + (void)desc_ep; return false; } -static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) -{ +static void dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix) { uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len); - if (len) - { - if (len > xfer->max_packet_size) - { + if (len) { + if (len > xfer->max_packet_size) { len = xfer->max_packet_size; } - uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8); - if(xfer->buffer) - { + uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8); + if (xfer->buffer) { memcpy(ptr, xfer->buffer + xfer->queued_len, len); - } - else - { - tu_fifo_read_n(xfer->fifo, ptr, len); + } else { + tu_hwfifo_write_from_fifo(ptr, xfer->fifo, len, NULL); } __DSB(); __ISB(); xfer->queued_len = (uint16_t)(xfer->queued_len + len); } - if (ep_ix == 0U) - { + if (ep_ix == 0U) { // Control endpoint: clear the interrupt flag to send the data USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC; - } else - { + } else { // Other endpoint types: clear the FIFO control flag to send the data USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; } @@ -607,59 +516,36 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix) } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool is_isr) -{ - (void) is_isr; - (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool is_isr) { + (void)is_isr; + (void)rhport; + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = &xfer_status[epnum]; + xfer_ctl_t *xfer = &xfer_status[epnum]; - xfer->buffer = buffer; - xfer->total_len = total_bytes; + xfer->buffer = buffer; + xfer->total_len = total_bytes; xfer->queued_len = 0; - xfer->fifo = NULL; + xfer->fifo = NULL; - if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) - { - // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the - // address to 32-byte boundaries. - CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31); + if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) { uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos; - if (dir == TUSB_DIR_OUT) - { + if (dir == TUSB_DIR_OUT) { udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; } else { udd_dma_ctrl |= DEVDMACONTROL_END_B_EN; + dcd_dcache_clean(xfer->buffer, total_bytes); } USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer; udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB; - // Disable IRQs to have a short sequence - // between read of EOT_STA and DMA enable - uint32_t irq_state = __get_PRIMASK(); - __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) - { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); - __set_PRIMASK(irq_state); - return true; - } - __set_PRIMASK(irq_state); - - // Here a ZLP has been received - // and the DMA transfer must be not started. - // It is the end of transfer - return false; - } else - { - if (dir == TUSB_DIR_OUT) - { + USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl; + USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); + } else { + if (dir == TUSB_DIR_OUT) { USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } else - { - dcd_transmit_packet(xfer,epnum); + } else { + dcd_transmit_packet(xfer, epnum); } } return true; @@ -669,112 +555,43 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t // bytes should be written and second to keep the return value free to give back a boolean // success message. If total_bytes is too big, the FIFO will copy only what is available // into the USB buffer! -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes, bool is_isr) -{ - (void) is_isr; - (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes, bool is_isr) { + (void)is_isr; + (void)rhport; + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); - xfer_ctl_t * xfer = &xfer_status[epnum]; - if(epnum == 0x80) - xfer = &xfer_status[EP_MAX]; + xfer_ctl_t *xfer = &xfer_status[epnum]; - xfer->buffer = NULL; - xfer->total_len = total_bytes; + xfer->buffer = NULL; + xfer->total_len = total_bytes; xfer->queued_len = 0; - xfer->fifo = ff; - - if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) - { - tu_fifo_buffer_info_t info; - uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB; - uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT; - if (dir == TUSB_DIR_OUT) - { - tu_fifo_get_write_info(ff, &info); - udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - } else { - tu_fifo_get_read_info(ff, &info); - if(info.wrapped.len == 0) - { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN; - } - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN; - } - - // Clean invalidate cache of linear part - CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.linear.ptr, 4), info.linear.len + 31); - - USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.linear.ptr; - if (info.wrapped.len) - { - // Clean invalidate cache of wrapped part - CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.wrapped.ptr, 4), info.wrapped.len + 31); + xfer->fifo = ff; - dma_desc[epnum - 1].next_desc = 0; - dma_desc[epnum - 1].buff_addr = (uint32_t)info.wrapped.ptr; - dma_desc[epnum - 1].chnl_ctrl = - udd_dma_ctrl_wrap | (info.wrapped.len << DEVDMACONTROL_BUFF_LENGTH_Pos); - // Clean cache of wrapped DMA descriptor - CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t)); - - udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST; - USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; - } else { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT; - } - udd_dma_ctrl_lin |= (info.linear.len << DEVDMACONTROL_BUFF_LENGTH_Pos); - // Disable IRQs to have a short sequence - // between read of EOT_STA and DMA enable - uint32_t irq_state = __get_PRIMASK(); - __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) - { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); - __set_PRIMASK(irq_state); - return true; - } - __set_PRIMASK(irq_state); - - // Here a ZLP has been received - // and the DMA transfer must be not started. - // It is the end of transfer - return false; - } else - { - if (dir == TUSB_DIR_OUT) - { - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } else - { - dcd_transmit_packet(xfer,epnum); - } + if (dir == TUSB_DIR_OUT) { + USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; + } else { + dcd_transmit_packet(xfer, epnum); } return true; } // Stall endpoint -void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + const uint8_t epnum = tu_edpt_number(ep_addr); USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS; // Re-enable SETUP interrupt - if (epnum == 0) - { + if (epnum == 0) { USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; } } // clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + const uint8_t epnum = tu_edpt_number(ep_addr); USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS; + USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS; } #endif diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/samx7x_common.h index db4a81e0e..5e3c20c0f 100644 --- a/src/portable/microchip/samx7x/common_usb_regs.h +++ b/src/portable/microchip/samx7x/samx7x_common.h @@ -1,4 +1,4 @@ - /* +/* * The MIT License (MIT) * * Copyright (c) 2019 Microchip Technology Inc. @@ -2098,7 +2098,72 @@ typedef struct #define FIFO_RAM_ADDR 0xA0100000u // Errata: The DMA feature is not available for Pipe/Endpoint 7 -#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6) +#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6 && CFG_TUD_SAMX7X_DMA_ENABLE) + +//------------- DCache -------------// +#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE + +typedef struct { + uintptr_t start; + uintptr_t end; +} mem_region_t; + +// Can be used to define additional uncached regions +#ifndef CFG_SAMX7X_MEM_UNCACHED_REGIONS +#define CFG_SAMX7X_MEM_UNCACHED_REGIONS +#endif + +static mem_region_t uncached_regions[] = { + // DTCM + {.start = 0x20000000, .end = 0x203fffff}, + CFG_SAMX7X_MEM_UNCACHED_REGIONS +}; + +TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { + if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) { + size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT; + } + return size; +} + +TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) { + if (0 == (SCB->CCR & SCB_CCR_DC_Msk)) { + return false; // D-Cache is disabled + } + for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) { + if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; } + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_clean(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool samx7x_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} + +#endif #else // TODO : SAM3U diff --git a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c new file mode 100644 index 000000000..c9810f51c --- /dev/null +++ b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c @@ -0,0 +1,821 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 HiFiPhile (Zixun LI) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(TUP_USBIP_IP3516) + +//--------------------------------------------------------------------+ +// INCLUDE +//--------------------------------------------------------------------+ +#include "common/tusb_common.h" +#include "host/hcd.h" +#include "host/usbh.h" +#include "hcd_lpc_ip3516.h" + +#if TU_CHECK_MCU(OPT_MCU_LPC55, OPT_MCU_LPC54) + #include "fsl_device_registers.h" +#else + #error "Unsupported MCUs" +#endif + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +#if TU_CHECK_MCU(OPT_MCU_LPC54) + #define ATLPTD ATL_PTD_BASE_ADDR + #define INTPTD INT_PTD_BASE_ADDR + #define ISOPTD ISO_PTD_BASE_ADDR + #define ATLPTDD ATL_PTD_DONE_MAP + #define INTPTDD INT_PTD_DONE_MAP + #define ISOPTDD ISO_PTD_DONE_MAP + #define ATLPTDS ATL_PTD_SKIP_MAP + #define INTPTDS INT_PTD_SKIP_MAP + #define ISOPTDS ISO_PTD_SKIP_MAP + #define DATAPAYLOAD DATA_PAYLOAD_BASE_ADDR + #define LASTPTD LAST_PTD_INUSE + + #define USBHSH_ATLPTD_ATL_BASE_MASK USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK + #define USBHSH_INTPTD_INT_BASE_MASK USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK + #define USBHSH_ISOPTD_ISO_BASE_MASK USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK + + #define USBHSH_DATAPAYLOAD_DAT_BASE_MASK USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK + + #define USBHSH_LASTPTD_ATL_LAST USBHSH_LAST_PTD_INUSE_ATL_LAST + #define USBHSH_LASTPTD_INT_LAST USBHSH_LAST_PTD_INUSE_INT_LAST + #define USBHSH_LASTPTD_ISO_LAST USBHSH_LAST_PTD_INUSE_ISO_LAST +#endif + +#define USBHSH_PORTSC1_W1C_MASK (USBHSH_PORTSC1_CSC_MASK | USBHSH_PORTSC1_PEDC_MASK | USBHSH_PORTSC1_OCC_MASK) + +#define IP3516_PSPD_LOW 0 +#define IP3516_PSPD_FULL 1 +#define IP3516_PSPD_HIGH 2 + +//--------------------------------------------------------------------+ +// Proprietary Transfer Descriptor +//--------------------------------------------------------------------+ + +CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(1024) static ip3516_ptd_t _ptd; + +static struct { + uint32_t uframe_number; + uint32_t uframe_length; + bool attached; // Track attachment state to avoid duplicate events, sometimes high-speed disconnection detector is not reliable +} _hcd_data; + +//--------------------------------------------------------------------+ +// Helper Functions +//--------------------------------------------------------------------+ + +static inline bool is_ptd_free(const ptd_ctrl1_t ctrl1) { + return ctrl1.mps == 0; +} + +static inline bool is_xfer_async(tusb_xfer_type_t xfer_type) { + return (xfer_type == TUSB_XFER_CONTROL || xfer_type == TUSB_XFER_BULK); +} + +static inline void ptd_clear_state(ptd_state_t *state) { + ptd_state_t local = {.value = 0}; + local.ep_type = state->ep_type; // preserve ep_type + local.token = state->token; // preserve token + local.data_toggle = state->data_toggle; // preserve data_toggle + *state = local; +} + +static inline uint8_t ptd_find_free(tusb_xfer_type_t xfer_type) { + uint8_t max_count; + intptr_t ptd_array; + + switch (xfer_type) { + case TUSB_XFER_CONTROL: + case TUSB_XFER_BULK: + max_count = IP3516_ATL_NUM; + ptd_array = (intptr_t)&_ptd.atl; + break; + + case TUSB_XFER_INTERRUPT: + max_count = IP3516_PTL_NUM; + ptd_array = (intptr_t)&_ptd.intr; + break; + + case TUSB_XFER_ISOCHRONOUS: + max_count = IP3516_PTL_NUM; + ptd_array = (intptr_t)&_ptd.iso; + break; + + default: + return TUSB_INDEX_INVALID_8; + } + + for (uint8_t i = 0; i < max_count; i++) { + // For ATL: stride is sizeof(ip3516_atl_t) = 16 bytes = 4 words + // For PTL: stride is sizeof(ip3516_ptl_t) = 32 bytes = 8 words + uint8_t stride = is_xfer_async(xfer_type) ? sizeof(ip3516_atl_t) : sizeof(ip3516_ptl_t); + ptd_ctrl1_t *ctrl1 = (ptd_ctrl1_t *)(ptd_array + i * stride); + + if (is_ptd_free(*ctrl1)) { + return i; + } + } + + return TUSB_INDEX_INVALID_8; // No free PTD found +} + +// Close all PTDs associated with a specific device address +static void close_ptds_by_device(uint8_t dev_addr, intptr_t ptd_array, uint8_t max_count, uint8_t stride, + volatile uint32_t *skip_reg) { + + uint32_t skip_mask = 0; + + for (uint8_t i = 0; i < max_count; i++) { + intptr_t ptd_ptr = ptd_array + i * stride; + ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1)); + ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2)); + + if (!is_ptd_free(*ptd_ctrl1) && ptd_ctrl2->dev_addr == dev_addr) { + *skip_reg |= (1 << i); + skip_mask |= (1 << i); + } + } + + if (skip_mask) { + // Wait 1 uframe for PTDs to be inactive (with timeout) + uint32_t start_uframe = + (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT; + uint32_t timeout = 10000; + while (((USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT) == + start_uframe && timeout > 0) { + timeout--; + } + + // Clear PTDs + for (uint8_t i = 0; i < max_count; i++) { + if (skip_mask & (1 << i)) { + intptr_t ptd_ptr = ptd_array + i * stride; + tu_memclr((void *)ptd_ptr, stride); + } + } + + // Clear skip bits + *skip_reg &= ~skip_mask; + } +} + +// Check if a PTD matches the given endpoint criteria +static bool ptd_matches(intptr_t ptd_ptr, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { + ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1)); + if (is_ptd_free(*ptd_ctrl1)) { + return false; + } + + ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2)); + if (ptd_ctrl2->dev_addr != dev_addr || ptd_ctrl2->ep_num != ep_num) { + return false; + } + + ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + bool is_control = (ptd_state->ep_type == TUSB_XFER_CONTROL); + + // For control endpoint, match both IN and OUT directions + if (is_control) { + return true; + } + + if (ep_dir == TUSB_DIR_IN && ptd_state->token == IP3516_PTD_TOKEN_IN) { + return true; + } + + if (ep_dir == TUSB_DIR_OUT && ptd_state->token == IP3516_PTD_TOKEN_OUT) { + return true; + } + + return false; +} + +// Find and close a specific PTD +static bool find_and_close_ptd(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir, intptr_t ptd_array, uint8_t max_count, + uint8_t stride, volatile uint32_t *skip_reg) { + for (uint8_t i = 0; i < max_count; i++) { + intptr_t ptd_ptr = ptd_array + i * stride; + if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) { + if (skip_reg) { + *skip_reg |= (1 << i); + + // Wait 1 uframe for PTD to be inactive (with timeout) + uint32_t start_uframe = + (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT; + uint32_t timeout = 10000; + while (((USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT) == + start_uframe && timeout > 0) { + timeout--; + } + + // Just clear state + ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1)); + ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + ptd_clear_state(ptd_state); + ptd_ctrl1->valid = 0; + + *skip_reg &= ~(1 << i); + } else { + // Clear PTD + tu_memclr((void *)ptd_ptr, stride); + } + return true; + } + } + return false; +} + +// Find an opened PTD +static intptr_t find_opened_ptd(uint8_t dev_addr, uint8_t ep_addr) { + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + + // Search in ATL + for (uint8_t i = 0; i < IP3516_ATL_NUM; i++) { + intptr_t ptd_ptr = (intptr_t)&_ptd.atl[i]; + if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) { + return ptd_ptr; + } + } + + // Search in INT + for (uint8_t i = 0; i < IP3516_PTL_NUM; i++) { + intptr_t ptd_ptr = (intptr_t)&_ptd.intr[i]; + if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) { + return ptd_ptr; + } + } + + // Search in ISO + for (uint8_t i = 0; i < IP3516_PTL_NUM; i++) { + intptr_t ptd_ptr = (intptr_t)&_ptd.iso[i]; + if (ptd_matches(ptd_ptr, dev_addr, ep_num, ep_dir)) { + return ptd_ptr; + } + } + + return 0; +} + +static bool edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen, bool is_setup) { + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + + intptr_t ptd_ptr = find_opened_ptd(dev_addr, ep_addr); + TU_ASSERT(ptd_ptr != 0); + + ptd_ctrl1_t *ptd_ctrl1 = (ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1)); + ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2)); + ptd_data_t *ptd_data = (ptd_data_t *)(ptd_ptr + offsetof(ip3516_atl_t, data)); + ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + + // Setup data buffer and length + ptd_data->data_addr = (uint32_t)(uintptr_t)buffer & IP3516_PTD_DATA_ADDR_MASK; + ptd_data->xfer_len = buflen; + + // Clear previous state + ptd_clear_state(ptd_state); + + // Set token for EP0 + if (ep_num == 0) { + if (is_setup) { + ptd_state->token = IP3516_PTD_TOKEN_SETUP; + ptd_state->data_toggle = 0; + } else { + ptd_state->token = (ep_dir == TUSB_DIR_IN) ? IP3516_PTD_TOKEN_IN : IP3516_PTD_TOKEN_OUT; + ptd_state->data_toggle = 1; + } + } + + // Interrupt split transfer needs to be relaunched manually if NAKed + if (ptd_ctrl2->split && ptd_state->ep_type == TUSB_XFER_INTERRUPT) { + ptd_ctrl2->reload = 0x0f; + ptd_state->nak_cnt = 0x0f; + } + + // Activate PTD + ptd_ctrl1->valid = 1; + ptd_state->active = 1; + + return true; +} + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) { + (void)rh_init; + (void)rhport; + + // Reset controller + USBHSH->USBCMD |= USBHSH_USBCMD_HCRESET_MASK; + while (USBHSH->USBCMD & USBHSH_USBCMD_HCRESET_MASK) {} + + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK; + + tu_memclr(&_ptd, sizeof(_ptd)); + tu_varclr(&_hcd_data); + + // Set base addresses + USBHSH->ATLPTD = (uint32_t)&_ptd.atl & USBHSH_ATLPTD_ATL_BASE_MASK; + USBHSH->INTPTD = (uint32_t)&_ptd.intr & USBHSH_INTPTD_INT_BASE_MASK; + USBHSH->ISOPTD = (uint32_t)&_ptd.iso & USBHSH_ISOPTD_ISO_BASE_MASK; + USBHSH->DATAPAYLOAD = (uint32_t)&_ptd & USBHSH_DATAPAYLOAD_DAT_BASE_MASK; + + // Turn on power switch + if (USBHSH->HCSPARAMS & USBHSH_HCSPARAMS_PPC_MASK) { + USBHSH->PORTSC1 |= USBHSH_PORTSC1_PP_MASK; + } + + // Get frame list size + uint32_t fls = (USBHSH->USBCMD & USBHSH_USBCMD_FLS_MASK) >> USBHSH_USBCMD_FLS_SHIFT; + _hcd_data.uframe_length = 8192 >> fls; + + // Clear pending interrupts + USBHSH->USBSTS = 0xFFFFFFFF; + + // Enable interrupts + USBHSH->USBINTR = USBHSH_USBINTR_ATL_IRQ_E_MASK | USBHSH_USBINTR_INT_IRQ_E_MASK | USBHSH_USBINTR_ISO_IRQ_E_MASK | + USBHSH_USBINTR_PCDE_MASK | USBHSH_USBINTR_FLRE_MASK; + + + // Enable all PTDs + USBHSH->LASTPTD = USBHSH_LASTPTD_ATL_LAST(IP3516_ATL_NUM - 1) | USBHSH_LASTPTD_INT_LAST(IP3516_PTL_NUM - 1) | + USBHSH_LASTPTD_ISO_LAST(IP3516_PTL_NUM - 1); + + // Enable controller + USBHSH->USBCMD = USBHSH_USBCMD_ATL_EN_MASK | USBHSH_USBCMD_INT_EN_MASK | USBHSH_USBCMD_ISO_EN_MASK | USBHSH_USBCMD_RS_MASK; + + return true; +} + +// Enable USB interrupt +void hcd_int_enable(uint8_t rhport) { + (void)rhport; + NVIC_EnableIRQ(USB1_IRQn); +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void)rhport; + NVIC_DisableIRQ(USB1_IRQn); +} + +bool hcd_deinit(uint8_t rhport) { + (void)rhport; + + // Disable interrupts + USBHSH->USBINTR = 0; + USBHSH->USBSTS = 0xFFFFFFFF; + + // Disable controller + USBHSH->USBCMD &= ~(USBHSH_USBCMD_ATL_EN_MASK | USBHSH_USBCMD_INT_EN_MASK | USBHSH_USBCMD_ISO_EN_MASK | USBHSH_USBCMD_RS_MASK); + + // Turn off power switch + if (USBHSH->HCSPARAMS & USBHSH_HCSPARAMS_PPC_MASK) { + USBHSH->PORTSC1 &= ~USBHSH_PORTSC1_PP_MASK; + } + + // Connect PHY to device mode + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK | USBHSH_PORTMODE_DEV_ENABLE_MASK; + + return true; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void)rhport; + uint32_t status = USBHSH->PORTSC1 & ~USBHSH_PORTSC1_W1C_MASK; + USBHSH->PORTSC1 = status | USBHSH_PORTSC1_PR_MASK; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void)rhport; + uint32_t status = USBHSH->PORTSC1 & ~USBHSH_PORTSC1_W1C_MASK; + USBHSH->PORTSC1 = status & ~USBHSH_PORTSC1_PR_MASK; + while (USBHSH->PORTSC1 & USBHSH_PORTSC1_PR_MASK) {} +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t pspd = (USBHSH->PORTSC1 & USBHSH_PORTSC1_PSPD_MASK) >> USBHSH_PORTSC1_PSPD_SHIFT; + if (pspd == IP3516_PSPD_HIGH) { + // enable phy disconnection for high speed + USBPHY->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } +#endif +} + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void)rhport; + return (USBHSH->PORTSC1 & USBHSH_PORTSC1_CCS_MASK) ? true : false; +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void)rhport; + uint32_t pspd = (USBHSH->PORTSC1 & USBHSH_PORTSC1_PSPD_MASK) >> USBHSH_PORTSC1_PSPD_SHIFT; + switch (pspd) { + case IP3516_PSPD_LOW: + return TUSB_SPEED_LOW; + case IP3516_PSPD_FULL: + return TUSB_SPEED_FULL; + case IP3516_PSPD_HIGH: + return TUSB_SPEED_HIGH; + default: + return TUSB_SPEED_INVALID; + } +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void)rhport; + uint32_t uframe = (USBHSH->FLADJ_FRINDEX & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) >> USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT; + uframe &= (_hcd_data.uframe_length - 1); + return (uframe + _hcd_data.uframe_number) >> 3; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void)rhport; + + close_ptds_by_device(dev_addr, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t), &USBHSH->ATLPTDS); + close_ptds_by_device(dev_addr, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), &USBHSH->INTPTDS); + close_ptds_by_device(dev_addr, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), &USBHSH->ISOPTDS); +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +static inline intptr_t get_ptd_from_index(tusb_xfer_type_t xfer_type, uint8_t ptd_index) { + if (is_xfer_async(xfer_type)) { + return (intptr_t)&_ptd.atl[ptd_index]; + } else { + if (xfer_type == TUSB_XFER_INTERRUPT) { + return (intptr_t)&_ptd.intr[ptd_index]; + } else { + return (intptr_t)&_ptd.iso[ptd_index]; + } + } +} + + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc) { + (void)rhport; + + const uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress); + const tusb_xfer_type_t xfer_type = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; + + tuh_bus_info_t bus_info; + tuh_bus_info_get(dev_addr, &bus_info); + + // Find a free PTD + uint8_t ptd_index = ptd_find_free(xfer_type); + TU_ASSERT(ptd_index != TUSB_INDEX_INVALID_8); + + // Configure PTD + intptr_t ptd_ptr = get_ptd_from_index(xfer_type, ptd_index); + volatile ptd_ctrl1_t *ctrl1 = (volatile ptd_ctrl1_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl1)); + volatile ptd_ctrl2_t *ctrl2 = (volatile ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2)); + volatile ptd_data_t *data = (volatile ptd_data_t *)(ptd_ptr + offsetof(ip3516_atl_t, data)); + volatile ptd_state_t *state = (volatile ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + + // Initialize PTD fields + ctrl1->mps = ep_desc->wMaxPacketSize; + ctrl1->mult = 1; + + ctrl2->dev_addr = dev_addr; + ctrl2->ep_num = ep_num; + ctrl2->speed = bus_info.speed == TUSB_SPEED_LOW ? 2 : 0; + ctrl2->hub_addr = bus_info.hub_addr; + ctrl2->hub_port = bus_info.hub_port; + ctrl2->split = (hcd_port_speed_get(rhport) == TUSB_SPEED_HIGH) && (bus_info.speed != TUSB_SPEED_HIGH) ? 1 : 0; + + data->intr = 1; + + state->ep_type = (uint32_t)xfer_type; + state->token = tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN ? IP3516_PTD_TOKEN_IN : IP3516_PTD_TOKEN_OUT; + + if (!is_xfer_async(xfer_type)) { + ip3516_ptl_t *ptd = (ip3516_ptl_t *)ptd_ptr; + + uint32_t uframe_interval; + if (bus_info.speed == TUSB_SPEED_HIGH) { + uframe_interval = 1 << (ep_desc->bInterval - 1); + } else { + uframe_interval = ep_desc->bInterval << 3; + // round down to nearest power of 2 + uframe_interval = 1 << tu_log2(uframe_interval); + } + uframe_interval = tu_min32(uframe_interval, IP3516_MAX_UFRAME); + + // uframe_active is an 8-bit mask, where each bit corresponds to a micro-frame within a 1ms frame. + // A '1' indicates the endpoint should be polled in that micro-frame. + // For example: + // Interval 1 (poll every u-frame) -> mask is 0b11111111 (0xFF) + // Interval 2 (poll every 2nd u-frame, e.g., 0, 2, 4, 6) -> mask is 0b10101010 (0xAA) + // Interval 4 (poll every 4th u-frame, e.g., 0, 4) -> mask is 0b10001000 (0x88) + // Interval 8 (poll every 8th u-frame, e.g., 0) -> mask is 0b10000000 (0x80) + switch (uframe_interval) { + case 1: + ptd->status.uframe_active = 0xFF; + break; + case 2: + ptd->status.uframe_active = 0xAA; + break; + case 4: + ptd->status.uframe_active = 0x11; + break; + case 8: + ptd->status.uframe_active = 0x01; + break; + default: + // For intervals > 8, we poll once per frame (every 8 u-frames) and use ctrl1.uframe to skip frames. + ptd->status.uframe_active = 0x01; + if (uframe_interval >= 16) { + ctrl1->uframe = tu_log2(uframe_interval) - 3; + } + break; + } + + if (ctrl2->split) { + // 11.18.1 Best Case Full-Speed Budget + // + // A microframe of time allows at most 187.5 raw bytes of signaling on a full-speed bus. + // The best case full-speed budget assumes that 188 full-speed bytes occur in each microframe. + // + // A 1 ms frame subdivided into microframes of budget time: + // + // Microframes Y_0 Y_1 Y_2 Y_3 Y_4 Y_5 Y_6 Y_7 + // Max wire time 187.5 187.5 187.5 187.5 187.5 187.5 32 + // Best case wire budget 188 188 188 188 188 188 29 + // + // 11.18.4 Host Split Transaction Scheduling Requirements + // + // 1. The host must never schedule a start-split in microframe Y_6. + // 2. For isochronous OUT full-speed transactions, for each microframe in which the transaction is + // budgeted, the host must schedule a 188 (or the remaining data size) data byte start-split transaction. + // For isochronous IN and interrupt IN/OUT full-/low-speed transactions, a single start-split must be + // scheduled in the microframe before the transaction is budgeted to start on the full-/low-speed bus. + // 3. For isochronous OUT full-speed transactions, the host must never schedule a complete-split. The + // TT response to a complete-split for an isochronous OUT is undefined. + // For interrupt IN/OUT full-/low-speed transactions, the host must schedule a complete-split + // transaction in each of the two microframes following the first microframe in which the full-/low- + // speed transaction is budgeted. An additional complete-split must also be scheduled in the third + // following microframe unless the full-/low-speed transaction was budgeted to start in microframe Y_6 + // For isochronous IN full-speed transactions, for each microframe in which the full-speed transaction + // is budgeted, a complete-split must be scheduled for each following microframe. + // Also, determine the last microframe in which a complete-split is scheduled, call it L. + // If L is less than Y_6, schedule additional complete-splits in microframe L+1 and L+2. + // If L is equal to Y_6, schedule one complete-split in microframe Y_7. + // + // TODO: Implement budget check scheduling + // Otherwise, it may cause bus contention with other split transfers + // Here we simply start interrupt transfers for Y_0 and Y1 and isochronous transfers for Y_2 + if (xfer_type == TUSB_XFER_ISOCHRONOUS) { + const uint8_t ss_slot = 2; // Start-split slot + const uint8_t slots = (ep_desc->wMaxPacketSize + 187) / 188; + const tusb_dir_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress); + if (ep_dir == TUSB_DIR_IN) { + if (ep_desc->wMaxPacketSize > 192) { + ctrl1->mps = 192; + } + ptd->status.uframe_active = 1 << ss_slot; + for (uint8_t i = 0; i < slots; i++) { + ptd->iso_in_0.uframe_complete |= 1 << (2 + ss_slot + i); + } + // Schedule additional complete-splits if needed + uint8_t last_complete = ss_slot + slots + 1; + if (last_complete < 6) { + ptd->iso_in_0.uframe_complete |= 1 << (ss_slot + last_complete + 1); + ptd->iso_in_0.uframe_complete |= 1 << (ss_slot + last_complete + 2); + } else if (last_complete == 6) { + ptd->iso_in_0.uframe_complete |= 1 << 7; + } + } else { + if (ep_desc->wMaxPacketSize > 188) { + ctrl1->mps = 188; + } + for (uint8_t i = 0; i < slots; i++) { + ptd->status.uframe_active |= 1 << (ss_slot + i); + } + } + } else { + // Start-split slot, jigging to avoid bus contention: EP odd -> Y_1, EP even -> Y_0 + const uint8_t ss_slot = ep_num & 0x01; + ptd->status.uframe_active = 1 << ss_slot; + // Complete-split slots: next 3 u-frames + ptd->iso_in_0.uframe_complete = 0x1c << ss_slot; + } + } + } + + return true; +} + +// Close an opened endpoint +bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void)rhport; + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + + // Search in ATL + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t), NULL)) { + return true; + } + + // Search in INT + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), NULL)) { + return true; + } + + // Search in ISO + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), NULL)) { + return true; + } + + return false; +} + +// Submit a transfer on an endpoint +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { + (void)rhport; + + return edpt_xfer(dev_addr, ep_addr, buffer, buflen, false); +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void)rhport; + + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + + // Search in ATL + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.atl, IP3516_ATL_NUM, sizeof(ip3516_atl_t), + &USBHSH->ATLPTDS)) { + return true; + } + + // Search in INT + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.intr, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), + &USBHSH->INTPTDS)) { + return true; + } + + // Search in ISO + if (find_and_close_ptd(dev_addr, ep_num, ep_dir, (intptr_t)&_ptd.iso, IP3516_PTL_NUM, sizeof(ip3516_ptl_t), + &USBHSH->ISOPTDS)) { + return true; + } + + return false; +} + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) { + (void)rhport; + + return edpt_xfer(dev_addr, 0x00, (uint8_t *)(uintptr_t)setup_packet, 8, true); +} + +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void)rhport; + + intptr_t ptd_ptr = find_opened_ptd(dev_addr, ep_addr); + TU_ASSERT(ptd_ptr != 0); + + ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + ptd_clear_state(ptd_state); + ptd_state->data_toggle = 0; // reset data toggle to DATA0 + + return true; +} + +//--------------------------------------------------------------------+ +// Interrupt Handler +//--------------------------------------------------------------------+ + +// Handle port status change event +static inline void handle_port_status_change(uint8_t rhport) { + const uint32_t status = USBHSH->PORTSC1; + + if (status & USBHSH_PORTSC1_CSC_MASK) { + if (status & USBHSH_PORTSC1_CCS_MASK && !_hcd_data.attached) { + _hcd_data.attached = true; + hcd_event_device_attach(rhport, true); + } else { + _hcd_data.attached = false; + hcd_event_device_remove(rhport, true); + #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + // disable phy disconnection for high speed + USBPHY->CTRL &= ~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + #endif + } + } + + USBHSH->PORTSC1 |= status & USBHSH_PORTSC1_W1C_MASK; +} + +// Handle PTD done interrupt +static inline void handle_ptd_done(uint32_t done_status, intptr_t ptd_array, bool is_async) { + uint8_t max_count = is_async ? IP3516_ATL_NUM : IP3516_PTL_NUM; + uint8_t stride = is_async ? sizeof(ip3516_atl_t) : sizeof(ip3516_ptl_t); + + for (uint8_t i = 0; i < max_count; i++) { + if (done_status & (1 << i)) { + intptr_t ptd_ptr = ptd_array + i * stride; + ptd_ctrl2_t *ptd_ctrl2 = (ptd_ctrl2_t *)(ptd_ptr + offsetof(ip3516_atl_t, ctrl2)); + ptd_state_t *ptd_state = (ptd_state_t *)(ptd_ptr + offsetof(ip3516_atl_t, state)); + + xfer_result_t result; + if (ptd_state->halt) { + result = XFER_RESULT_STALLED; + } else if (ptd_state->error || ptd_state->babble) { + result = XFER_RESULT_FAILED; + } else { + result = XFER_RESULT_SUCCESS; + } + + uint8_t ep_addr = ptd_ctrl2->ep_num | (ptd_state->token == IP3516_PTD_TOKEN_IN ? 0x80 : 0x00); + + hcd_event_xfer_complete(ptd_ctrl2->dev_addr, ep_addr, ptd_state->xferred_len, result, true); + } + } +} + +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void)in_isr; + + uint32_t int_status = USBHSH->USBSTS; + USBHSH->USBSTS = int_status; // clear interrupt status + + // Port Change Detect + if (int_status & USBHSH_USBSTS_PCD_MASK) { + handle_port_status_change(rhport); + } + + // Frame List Rollover + if (int_status & USBHSH_USBSTS_FLR_MASK) { + _hcd_data.uframe_number += _hcd_data.uframe_length; + } + + // ATL done + if (int_status & USBHSH_USBSTS_ATL_IRQ_MASK) { + uint32_t done_status = USBHSH->ATLPTDD; + handle_ptd_done(done_status, (intptr_t)&_ptd.atl, true); + USBHSH->ATLPTDD = done_status; + } + + // INT done + if (int_status & USBHSH_USBSTS_INT_IRQ_MASK) { + uint32_t done_status = USBHSH->INTPTDD; + handle_ptd_done(done_status, (intptr_t)&_ptd.intr, false); + USBHSH->INTPTDD = done_status; + } + + // ISO done + if (int_status & USBHSH_USBSTS_ISO_IRQ_MASK) { + uint32_t done_status = USBHSH->ISOPTDD; + handle_ptd_done(done_status, (intptr_t)&_ptd.iso, false); + USBHSH->ISOPTDD = done_status; + } +} + +#endif diff --git a/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h new file mode 100644 index 000000000..5214c18ae --- /dev/null +++ b/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.h @@ -0,0 +1,188 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 HiFiPhile (Zixun LI) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_HCD_IP3516_H_ +#define TUSB_HCD_IP3516_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// IP3516 CONFIGURATION & CONSTANTS +//--------------------------------------------------------------------+ + +#define IP3516_ATL_NUM 32 +#define IP3516_PTL_NUM 32 + +#define IP3516_PTD_TOKEN_OUT 0x00U +#define IP3516_PTD_TOKEN_IN 0x01U +#define IP3516_PTD_TOKEN_SETUP 0x02U + +#define IP3516_PTD_EPTYPE_OUT 0x00U +#define IP3516_PTD_EPTYPE_IN 0x01U +#define IP3516_PTD_EPTYPE_SETUP 0x02U + +#define IP3516_PTD_MAX_TRANSFER_LENGTH 0x7FFFU + +#define IP3516_PTD_DATA_ADDR_MASK 0xFFFFU + +#define IP3516_MAX_UFRAME (1UL << 8) + +#define IP3516_PERIODIC_TRANSFER_GAP (3U) +#define IP3516_ISO_MULTIPLE_TRANSFER (8U) + + +//--------------------------------------------------------------------+ +// IP3516 PTD Data Structure +//--------------------------------------------------------------------+ + +// Control Word 1 +typedef union { + uint32_t value; + struct { + uint32_t valid : 1; + uint32_t next_ptd : 5; + uint32_t : 1; + uint32_t jump : 1; + uint32_t uframe : 8; + uint32_t mps : 11; + uint32_t : 1; + uint32_t mult : 2; + uint32_t : 2; + }; +} ptd_ctrl1_t; + +TU_VERIFY_STATIC(sizeof(ptd_ctrl1_t) == 4, "size is not correct"); + +// Control Word 2 +typedef union { + uint32_t value; + struct { + uint32_t ep_num : 4; + uint32_t dev_addr : 7; + uint32_t split : 1; + uint32_t reload : 4; + uint32_t speed : 2; + uint32_t hub_port : 7; + uint32_t hub_addr : 7; + }; +} ptd_ctrl2_t; + +TU_VERIFY_STATIC(sizeof(ptd_ctrl2_t) == 4, "size is not correct"); + +// Data Word +typedef union { + uint32_t value; + struct { + uint32_t xfer_len : 15; + uint32_t intr : 1; + uint32_t data_addr : 16; + }; +} ptd_data_t; + +TU_VERIFY_STATIC(sizeof(ptd_data_t) == 4, "size is not correct"); + +// State Word +typedef union { + uint32_t value; + struct { + uint32_t xferred_len : 15; + uint32_t token : 2; + uint32_t ep_type : 2; + uint32_t nak_cnt : 4; + uint32_t err_cnt : 2; + uint32_t data_toggle : 1; + uint32_t ping : 1; + uint32_t start_complete : 1; + uint32_t error : 1; + uint32_t babble : 1; + uint32_t halt : 1; + uint32_t active : 1; + }; +} ptd_state_t; + +TU_VERIFY_STATIC(sizeof(ptd_state_t) == 4, "size is not correct"); + +// Status Word +typedef union { + uint32_t value; + struct { + uint32_t uframe_active : 8; + uint32_t iso_status0 : 3; + uint32_t iso_status1 : 3; + uint32_t iso_status2 : 3; + uint32_t iso_status3 : 3; + uint32_t iso_status4 : 3; + uint32_t iso_status5 : 3; + uint32_t iso_status6 : 3; + uint32_t iso_status7 : 3; + }; +} ptd_status_t; + +TU_VERIFY_STATIC(sizeof(ptd_status_t) == 4, "size is not correct"); + +// ATL (Asynchronous Transfer List) structure +typedef volatile struct { + ptd_ctrl1_t ctrl1; + ptd_ctrl2_t ctrl2; + ptd_data_t data; + ptd_state_t state; +} ip3516_atl_t; + +TU_VERIFY_STATIC(sizeof(ip3516_atl_t) == 16, "size is not correct"); + +// PTL (Periodic Transfer List) structure +typedef volatile struct { + ptd_ctrl1_t ctrl1; + ptd_ctrl2_t ctrl2; + ptd_data_t data; + ptd_state_t state; + ptd_status_t status; + union { + uint32_t value; + struct { + uint32_t uframe_complete : 8; + uint32_t spl_iso_in_0 : 24; + }; + } iso_in_0; + uint32_t iso_in_1; + uint32_t iso_in_2; +} ip3516_ptl_t; + +TU_VERIFY_STATIC(sizeof(ip3516_ptl_t) == 32, "size is not correct"); + +// Proprietary Transfer Descriptor +typedef struct { + ip3516_ptl_t intr[IP3516_PTL_NUM]; + ip3516_ptl_t iso[IP3516_PTL_NUM]; + ip3516_atl_t atl[IP3516_ATL_NUM]; +} ip3516_ptd_t; + +#ifdef __cplusplus +} +#endif +#endif /* TUSB_HCD_IP3516_H_ */ diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 5ca093506..4b248d9e6 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -243,7 +243,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI; - OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated. + OHCI_REG->frame_interval ^= (1ul << 31); //Must toggle when frame_interval is updated. OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power) @@ -557,6 +557,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { (void) rhport; ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr); + TU_ASSERT(p_ed); ohci_ed_word2_t td_head = p_ed->td_head; td_head.toggle = 0; // reset data toggle diff --git a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c index acdeccf6d..1813ef70b 100644 --- a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c @@ -223,9 +223,13 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { tu_memclr(&_hcd_data, sizeof(_hcd_data)); + // Clear pending interrupts + // Normally no interrupts should be pending here since we just reset the core, + // but device mode suspend needs to cleared by WKUP flag + FSDEV_REG->ISTR = 0; + // Enable interrupts for host mode - FSDEV_REG->CNTR |= USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SOFM | USB_CNTR_SUSPM | - USB_CNTR_WKUPM | USB_CNTR_ERRM | USB_CNTR_PMAOVRM; + FSDEV_REG->CNTR |= USB_CNTR_DCON | USB_CNTR_CTRM | USB_CNTR_SOFM | USB_CNTR_ERRM | USB_CNTR_PMAOVRM; // Initialize port state _hcd_data.connected = false; diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index b413121a5..9fac0bc1c 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -36,9 +36,6 @@ #include <device/dcd.h> #include "musb_def.h" -//#include "bsp/board_api.h" -extern uint32_t board_millis(void); // TODO remove - typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2e2b050bc..8685ec6dc 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -492,6 +492,12 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; } +bool dcd_deinit(uint8_t rhport) { + dcd_disconnect(rhport); + dwc2_core_deinit(rhport); + return true; +} + void dcd_int_enable(uint8_t rhport) { dwc2_dcd_int_enable(rhport); } @@ -527,34 +533,38 @@ void dcd_remote_wakeup(uint8_t rhport) { } void dcd_connect(uint8_t rhport) { - (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); #ifdef TUP_USBIP_DWC2_ESP32 - usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; - conf.pad_pull_override = 0; - conf.dp_pullup = 0; - conf.dp_pulldown = 0; - conf.dm_pullup = 0; - conf.dm_pulldown = 0; - USB_WRAP.otg_conf = conf; + // On ESP32-P4 HS PHY, do not write to USB_WRAP register which belongs to FS PHY + if (rhport == 0) { + usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; + conf.pad_pull_override = 0; + conf.dp_pullup = 0; + conf.dp_pulldown = 0; + conf.dm_pullup = 0; + conf.dm_pulldown = 0; + USB_WRAP.otg_conf = conf; + } #endif dwc2->dctl &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { - (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); #ifdef TUP_USBIP_DWC2_ESP32 - usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; - conf.pad_pull_override = 1; - conf.dp_pullup = 0; - conf.dp_pulldown = 1; - conf.dm_pullup = 0; - conf.dm_pulldown = 1; - USB_WRAP.otg_conf = conf; + // On ESP32-P4 HS PHY, do not write to USB_WRAP register which belongs to FS PHY + if (rhport == 0) { + usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; + conf.pad_pull_override = 1; + conf.dp_pullup = 0; + conf.dp_pulldown = 1; + conf.dm_pullup = 0; + conf.dm_pulldown = 1; + USB_WRAP.otg_conf = conf; + } #endif dwc2->dctl |= DCTL_SDIS; diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h index 10824ae92..fa6d10c12 100644 --- a/src/portable/synopsys/dwc2/dwc2_at32.h +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -112,6 +112,12 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_ } } +// MCU specific PHY deinit, disable PHY power +TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { + (void) hs_phy_type; + dwc2->stm32_gccfg &= ~(STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN); +} + // MCU specific PHY update, it is called AFTER init() and core reset TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { (void) dwc2; diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index df6d4a852..00842bba2 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -73,6 +73,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) // nothing to do } +// MCU specific PHY deinit, disable PHY power +static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + // nothing to do +} + // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 27dda44ee..33eabaeab 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -39,14 +39,11 @@ static void reset_core(dwc2_regs_t* dwc2) { while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) { } - // load gsnpsid (it is not readable after reset is asserted) - const uint32_t gsnpsid = dwc2->gsnpsid; - - // reset core - dwc2->grstctl |= GRSTCTL_CSRST; + const uint32_t gsnpsid = dwc2->gsnpsid; // preload gsnpsid which is not readable while resetting + dwc2->grstctl |= GRSTCTL_CSRST; // reset core if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { - // prior v4.20a: CSRST is self-clearing and the core clears this bit after all the necessary logic is reset in + // prior v4.20a: CSRST is self-clearing, and the core clears this bit after all the necessary logic is reset in // the core, which can take several clocks, depending on the current state of the core. Once this bit has been // cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). while (dwc2->grstctl & GRSTCTL_CSRST) {} @@ -88,8 +85,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) { } /* dwc2 has 2 highspeed PHYs options - * - UTMI+ is internal highspeed PHY, can be clocked at 30/60 Mhz for fullspeed or 60 Mhz for highspeed. Can be either - * 8 or 16-bit interface. + * - UTMI+ is internal highspeed PHY, can be clocked at 30 Mhz (8-bit) or 60 Mhz (16-bit). * - ULPI is external highspeed PHY, clocked at 60Mhz with 8-bit interface. * * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz @@ -247,6 +243,24 @@ bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma) { return true; } +void dwc2_core_deinit(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + // Disable global interrupt + dwc2->gahbcfg &= ~GAHBCFG_GINT; + + // Reset core: this also flushes FIFOs and clears all interrupt registers + reset_core(dwc2); + + // Stop PHY clock and gate HCLK for power saving (per databook chapter 14) + dwc2->pcgcctl |= PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK; + + // MCU-specific PHY deinit (disable PHY power) + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + const uint8_t hs_phy_type = (dwc2->gusbcfg & GUSBCFG_PHYSEL) ? GHWCFG2_HSPHY_NOT_SUPPORTED : ghwcfg2.hs_phy_type; + dwc2_phy_deinit(dwc2, hs_phy_type); +} + // void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) { // (void) in_isr; // dwc2_regs_t * const dwc2 = DWC2_REG(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 1947173b2..9f28ab2e0 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -42,6 +42,7 @@ // - _dwc2_controller[]: array of controllers // - DWC2_EP_MAX: largest EP counts of all controllers // - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset +// - dwc2_phy_deinit(dwc2, hs_phy_type): phy deinit to disable PHY power, only deinit the phy used by core // - dwc2_dcd_int_enable/dwc2_dcd_int_disable // - dwc2_remote_wakeup_delay @@ -87,6 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { // check if highspeed phy should be used bool dwc2_core_is_highspeed_phy(dwc2_regs_t* dwc2, bool prefer_hs_phy); bool dwc2_core_init(uint8_t rhport, bool is_hs_phy, bool is_dma); +void dwc2_core_deinit(uint8_t rhport); void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h index 0e3570cbb..e1cb7c769 100644 --- a/src/portable/synopsys/dwc2/dwc2_efm32.h +++ b/src/portable/synopsys/dwc2/dwc2_efm32.h @@ -72,6 +72,14 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) USB->ROUTE = USB_ROUTE_PHYPEN; } +// MCU specific PHY deinit, disable PHY power +static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + // Disable PHY pin + USB->ROUTE = 0; +} + // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index a4e0d1770..ff9f216bd 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -121,6 +121,13 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_ } +// MCU specific PHY deinit, disable PHY power +TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + (void)dwc2; + (void)hs_phy_type; + // PHY managed by ESP-IDF +} + // MCU specific PHY update, it is called AFTER init() and core reset TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 0375fffe4..ccbf93a76 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -85,6 +85,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) // nothing to do } +// MCU specific PHY deinit, disable PHY power +static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + // nothing to do +} + // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { diff --git a/src/portable/synopsys/dwc2/dwc2_nrf.h b/src/portable/synopsys/dwc2/dwc2_nrf.h index b93571f16..51f2d684f 100644 --- a/src/portable/synopsys/dwc2/dwc2_nrf.h +++ b/src/portable/synopsys/dwc2/dwc2_nrf.h @@ -52,6 +52,12 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_ (void)hs_phy_type; } +// MCU specific PHY deinit, disable PHY power +TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + (void)dwc2; + (void)hs_phy_type; +} + // MCU specific PHY update, it is called AFTER init() and core reset TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 753917a20..259ad21b9 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -264,6 +264,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { } } +// MCU specific PHY deinit, disable PHY power +static inline void dwc2_phy_deinit(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { + // Disable on-chip FS PHY + dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; + } else { + // Disable HS PHY + #ifdef USB_HS_PHYC + dwc2->stm32_gccfg &= ~STM32_GCCFG_PHYHSEN; + // Disable PLL and LDO + USB_HS_PHYC->USB_HS_PHYC_PLL &= ~USB_HS_PHYC_PLL_PLLEN; + USB_HS_PHYC->USB_HS_PHYC_LDO &= ~USB_HS_PHYC_LDO_ENABLE; + #endif + } +} + // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // used to set turnaround time for fullspeed, nothing to do in highspeed mode diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h index 63419abf7..aca3873df 100644 --- a/src/portable/synopsys/dwc2/dwc2_xmc.h +++ b/src/portable/synopsys/dwc2/dwc2_xmc.h @@ -71,6 +71,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) //USB->ROUTE = USB_ROUTE_PHYPEN; } +// MCU specific PHY deinit, disable PHY power +static inline void dwc2_phy_deinit(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + // nothing to do +} + // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 0fd60b35d..e12e44a41 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -416,11 +416,6 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; - #if CFG_TUSB_MCU == OPT_MCU_STM32N6 - // No hardware detection of Vbus B-session is available on the STM32N6 - dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL; - #endif - while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} #ifdef TUP_USBIP_DWC2_STM32 @@ -440,7 +435,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT; + dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT; // NPTX can hold at least 2 packet, change interrupt level to half-empty uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL; @@ -450,6 +445,17 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; } +bool hcd_deinit(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + // Turn off VBUS + dwc2->hprt = HPRT_W1_MASK; // clear w1c bits without side effects + // HPRT_POWER is not set -> VBUS off + + dwc2_core_deinit(rhport); + return true; +} + // Enable USB interrupt void hcd_int_enable (uint8_t rhport) { dwc2_int_set(rhport, TUSB_ROLE_HOST, true); @@ -874,7 +880,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { break; case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR: - TU_ASSERT(0, ); // maybe try to change DToggle + // handle in channel interrupt break; case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED: @@ -1014,8 +1020,11 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_DATATOGGLE_ERR) { + channel->hcintmsk &= ~HCINT_DATATOGGLE_ERR; xfer->err_count = 0; - TU_ASSERT(false); + hcsplt.split_compl = 0; // restart with start-split + channel->hcsplt = hcsplt.value; + channel_disable(dwc2, channel); } else { // nothing to do } @@ -1351,6 +1360,17 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { } // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) +// Databook Table 2-2: System Clock Speeds +// +-----------+------------------+----------+-----------+-------------------+ +// | PHY | PHY Clock (MHz) | Width | HCFG.Sel | HFIR (clk cycles) | +// +-----------+------------------+----------+-----------+-------------------+ +// | HS UTMI+ | 30 | 16-bit | 30_60 | HS:3749 FS:29999 | +// | HS UTMI+ | 60 | 8-bit | 30_60 | HS:7499 FS:59999 | +// | HS ULPI | 60 | 8-bit | 30_60 | HS:7499 FS:59999 | +// | FS (dead.) | 48 | internal | 48 | FS:47999 | +// | LS via FS | 48 (6 effective) | internal | 6 | LS:47999 | +// +-----------+------------------+----------+-----------+-------------------+ +// HFIR = (interval_us * phy_clock) - 1, where interval is 125us (HS) or 1000us (FS/LS) static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; @@ -1443,16 +1463,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // TU_LOG1_HEX(gintsts); - if (gintsts & GINTSTS_CONIDSTSCHNG) { - // Connector ID status change - dwc2->gintsts = GINTSTS_CONIDSTSCHNG; - - //if (dwc2->gotgctl) - // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS - //dwc2->gintmsk |= GINTMSK_PRTIM; - // TODO wait for SRP if OTG - } - if (gintsts & GINTSTS_SOF) { const bool more_sof = handle_sof_irq(rhport, in_isr); if (!more_sof) { diff --git a/src/tinyusb.mk b/src/tinyusb.mk index 8f9d52de9..e7d1c0b5b 100644 --- a/src/tinyusb.mk +++ b/src/tinyusb.mk @@ -15,6 +15,7 @@ TINYUSB_SRC_C += \ src/class/mtp/mtp_device.c \ src/class/net/ecm_rndis_device.c \ src/class/net/ncm_device.c \ + src/class/printer/printer_device.c \ src/class/usbtmc/usbtmc_device.c \ src/class/video/video_device.c \ src/class/vendor/vendor_device.c \ diff --git a/src/tusb.c b/src/tusb.c index 6075e9db4..5e4422e41 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -39,23 +39,38 @@ #include "host/usbh_pvt.h" #endif +// Suppress IAR warning +// Warning[Pe111]: statement is unreachable +#if defined(__ICCARM__) +#pragma diag_suppress = Pe111 +#endif + tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM] = { TUSB_ROLE_INVALID }; //-------------------------------------------------------------------- // Weak/Default API, can be overwritten by Application //-------------------------------------------------------------------- -TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) { #if CFG_TUSB_OS != OPT_OS_NONE +TU_ATTR_WEAK uint32_t tusb_time_millis_api(void) { + return osal_time_millis(); +} + +TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) { osal_task_delay(ms); +} + #else - // delay using millis() (if implemented) and/or frame number if possible +// tusb_time_millis_api() must be implemented by user application. + +TU_ATTR_WEAK void tusb_time_delay_ms_api(uint32_t ms) { + // delay using millis() const uint32_t time_ms = tusb_time_millis_api(); while ((tusb_time_millis_api() - time_ms) < ms) {} -#endif } +#endif -TU_ATTR_WEAK void* tusb_app_virt_to_phys(void *virt_addr) { +TU_ATTR_WEAK void *tusb_app_virt_to_phys(void *virt_addr) { return virt_addr; } @@ -245,6 +260,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) { bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) { const uint16_t max_packet_size = tu_edpt_packet_size(desc_ep); TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size); + TU_ASSERT(max_packet_size > 0); switch (desc_ep->bmAttributes.xfer) { case TUSB_XFER_ISOCHRONOUS: { @@ -264,7 +280,7 @@ bool tu_edpt_validate(const tusb_desc_endpoint_t *desc_ep, tusb_speed_t speed) { break; case TUSB_XFER_INTERRUPT: { - uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); + const uint16_t spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); TU_ASSERT(max_packet_size <= spec_size); break; } @@ -306,7 +322,7 @@ bool tu_bind_driver_to_ep_itf(uint8_t driver_id, uint8_t ep2drv[][2], uint8_t it //--------------------------------------------------------------------+ bool tu_edpt_stream_init(tu_edpt_stream_t *s, bool is_host, bool is_tx, bool overwritable, void *ff_buf, - uint16_t ff_bufsize, uint8_t *ep_buf, uint16_t ep_bufsize) { + uint16_t ff_bufsize, uint8_t *ep_buf) { (void) is_tx; if (ff_buf == NULL || ff_bufsize == 0) { @@ -324,7 +340,6 @@ bool tu_edpt_stream_init(tu_edpt_stream_t *s, bool is_host, bool is_tx, bool ove #endif s->ep_buf = ep_buf; - s->ep_bufsize = ep_bufsize; return true; } @@ -394,7 +409,7 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t *s) { if (s->ep_buf == NULL) { count = tu_fifo_count(&s->ff); // re-get count since fifo can be changed } else { - count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize); + count = tu_fifo_read_n(&s->ff, s->ep_buf, s->xfer_len); } if (count > 0) { @@ -441,7 +456,7 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t *s) { if (available >= s->mps) { // multiple of packet size limit by ep bufsize uint16_t count = (uint16_t) (available & ~(s->mps - 1)); - count = tu_min16(count, s->ep_bufsize); + count = tu_min16(count, s->xfer_len); TU_ASSERT(stream_xfer(s, count), 0); return count; } else { diff --git a/src/tusb.h b/src/tusb.h index 62b3b9783..c80c8433c 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -88,6 +88,10 @@ #include "class/msc/msc_device.h" #endif + #if CFG_TUD_PRINTER + #include "class/printer/printer_device.h" + #endif + #if CFG_TUD_MTP #include "class/mtp/mtp_device.h" #endif @@ -135,7 +139,7 @@ //--------------------------------------------------------------------+ -// User API +// Application API //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED || CFG_TUD_ENABLED diff --git a/src/tusb_option.h b/src/tusb_option.h index d87c2dc8b..f5879e1df 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -238,6 +238,7 @@ #define OPT_OS_RTTHREAD 6 ///< RT-Thread #define OPT_OS_RTX4 7 ///< Keil RTX 4 #define OPT_OS_ZEPHYR 8 ///< Zephyr +#define OPT_OS_THREADX 9 ///< ThreadX //--------------------------------------------------------------------+ // Mode and Speed @@ -394,6 +395,24 @@ // odd byte with byte access #endif +//------- Microchip SAMX7X -------// +// DMA mode for device +#ifndef CFG_TUD_SAMX7X_DMA_ENABLE + #ifndef CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT + #define CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT 0 + #endif + + #define CFG_TUD_SAMX7X_DMA_ENABLE CFG_TUD_SAMX7X_DMA_ENABLE_DEFAULT +#endif + +#if (CFG_TUSB_MCU == OPT_MCU_SAMX7X) + #define CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE 4 + #define CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE 4 + #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS + #define CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS + #define CFG_TUD_EDPT_DEDICATED_HWFIFO 1 +#endif + //-------------------------------------------------------------------- // RootHub Mode detection //-------------------------------------------------------------------- @@ -469,7 +488,6 @@ #define TUP_MCU_STRICT_ALIGN 0 #endif - //--------------------------------------------------------------------+ // Common Options (Default) //--------------------------------------------------------------------+ @@ -514,6 +532,10 @@ #define CFG_TUSB_OS OPT_OS_NONE #endif +#ifndef CFG_TUSB_OS_HAS_SCHEDULER + #define CFG_TUSB_OS_HAS_SCHEDULER (CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO) +#endif + #ifndef CFG_TUSB_OS_INC_PATH #ifndef CFG_TUSB_OS_INC_PATH_DEFAULT #define CFG_TUSB_OS_INC_PATH_DEFAULT @@ -654,6 +676,10 @@ #define CFG_TUD_NCM 0 #endif +#ifndef CFG_TUD_PRINTER + #define CFG_TUD_PRINTER 0 +#endif + #ifndef CFG_TUD_EDPT_DEDICATED_HWFIFO #define CFG_TUD_EDPT_DEDICATED_HWFIFO 0 #endif diff --git a/test/fuzz/device/cdc/src/tusb_config.h b/test/fuzz/device/cdc/src/tusb_config.h index 76f44619e..14b7b627d 100644 --- a/test/fuzz/device/cdc/src/tusb_config.h +++ b/test/fuzz/device/cdc/src/tusb_config.h @@ -101,8 +101,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 diff --git a/test/fuzz/device/msc/src/tusb_config.h b/test/fuzz/device/msc/src/tusb_config.h index abd8cd4ce..7a4a24fb8 100644 --- a/test/fuzz/device/msc/src/tusb_config.h +++ b/test/fuzz/device/msc/src/tusb_config.h @@ -101,8 +101,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 diff --git a/test/fuzz/device/net/src/tusb_config.h b/test/fuzz/device/net/src/tusb_config.h index 4fe98e043..de45e9ead 100644 --- a/test/fuzz/device/net/src/tusb_config.h +++ b/test/fuzz/device/net/src/tusb_config.h @@ -106,8 +106,10 @@ #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +// CDC Endpoint transfer buffer size, default to max bulk packet size (HS 512, FS 64). Larger is faster. +// Larger RX_EPSIZE requires CFG_TUD_CDC_RX_NEED_ZLP = 1 and host ZLP support +#define CFG_TUD_CDC_RX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_EPSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk index b32f8d695..329dcce11 100644 --- a/test/fuzz/rules.mk +++ b/test/fuzz/rules.mk @@ -32,6 +32,7 @@ SRC_C += \ src/class/midi/midi_device.c \ src/class/msc/msc_device.c \ src/class/mtp/mtp_device.c \ + src/class/printer/printer_device.c \ src/class/net/ecm_rndis_device.c \ src/class/net/ncm_device.c \ src/class/usbtmc/usbtmc_device.c \ diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index b84740867..7cffd2da8 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -153,19 +153,47 @@ def open_mtp_dev(uid): # MTP seems to take a while to enumerate timeout = 2 * ENUM_TIMEOUT while timeout > 0: - # run_cmd(f"gio mount -u mtp://TinyUsb_TinyUsb_Device_{uid}/") + # unmount gio/gvfs MTP mount which blocks libmtp from accessing the device + subprocess.run(f"gio mount -u mtp://TinyUsb_TinyUsb_Device_{uid}/", + shell=True, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) for raw in mtp.detect_devices(): mtp.device = mtp.mtp.LIBMTP_Open_Raw_Device(ctypes.byref(raw)) if mtp.device: sn = mtp.get_serialnumber().decode('utf-8') - #print(f'mtp serial = {sn}') if sn == uid: return mtp + mtp.disconnect() time.sleep(1) timeout -= 1 return None +def get_printer_dev(id, vendor_str, product_str, ifnum): + """Find /dev/usb/lpX by matching USB serial, vendor, product, and interface number via sysfs""" + vendor_str = vendor_str.replace(' ', '_') if vendor_str else '' + product_str = product_str.replace(' ', '_') if product_str else '' + for lp in glob.glob('/sys/class/usbmisc/lp*'): + try: + sn = open(f'{lp}/device/../serial').read().strip() + if sn == id: + return f'/dev/usb/{os.path.basename(lp)}' + except (FileNotFoundError, PermissionError, ValueError): + pass + return None + + +def open_printer_dev(id, vendor_str, product_str, ifnum): + """Wait for printer device to enumerate and return its path""" + timeout = ENUM_TIMEOUT + while timeout > 0: + lp_dev = get_printer_dev(id, vendor_str, product_str, ifnum) + if lp_dev and os.path.exists(lp_dev): + return lp_dev + time.sleep(1) + timeout -= 1 + assert False, f'Printer device not found for {id} if{ifnum:02d}' + + # ------------------------------------------------------------- # Flashing firmware # ------------------------------------------------------------- @@ -302,7 +330,7 @@ def flash_esptool(board, firmware): idf_target = json.load(f)['IDF_TARGET'] with open(f'{fw_dir}/flash_args') as f: flash_args = f.read().strip().replace('\n', ' ') - command = (f'esptool.py --chip {idf_target} -p {port} {flasher["args"]} ' + command = (f'esptool --chip {idf_target} -p {port} {flasher["args"]} ' f'--before=default_reset --after=hard_reset write_flash {flash_args}') ret = run_cmd(command, cwd=fw_dir) return ret @@ -552,6 +580,109 @@ def test_device_hid_composite_freertos(id): pass +def test_device_printer_to_cdc(board): + import threading + + uid = board['uid'] + + # Wait for CDC port and printer device + cdc_port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) + ser = open_serial_dev(cdc_port) + lp_dev = open_printer_dev(uid, 'TinyUSB', 'TinyUSB_Device', 2) + + # Test 0: Verify IEEE 1284 Device ID from sysfs + expected_id = 'MFG:TinyUSB;MDL:Printer to CDC;CMD:PS;CLS:PRINTER;' + lp_name = os.path.basename(lp_dev) + sysfs_id_path = f'/sys/class/usbmisc/{lp_name}/device/ieee1284_id' + if os.path.exists(sysfs_id_path): + with open(sysfs_id_path) as f: + ieee1284_id = f.read().strip() + if ieee1284_id: + assert ieee1284_id == expected_id, (f'IEEE 1284 ID mismatch:\n' + f' expected: {expected_id}\n got: {ieee1284_id}') + + def rand_ascii(length): + return "".join(random.choices(string.ascii_letters + string.digits, k=length)).encode("ascii") + + sizes = [32, 64, 128, 256, 512, random.randint(2000, 5000)] + + # flush any stale data + ser.reset_input_buffer() + + # Test 1: Printer -> CDC with multiple sizes, write in random 1-64 byte chunks + for size in sizes: + test_data = rand_ascii(size) + ser.reset_input_buffer() + rd = b'' + offset = 0 + with open(lp_dev, 'wb') as lp: + while offset < size: + chunk_size = min(random.randint(1, 64), size - offset) + lp.write(test_data[offset:offset + chunk_size]) + lp.flush() + rd += ser.read(chunk_size) + offset += chunk_size + # read any remaining bytes (fullspeed devices may need extra time) + while len(rd) < size: + remaining = ser.read(size - len(rd)) + if not remaining: + break + rd += remaining + assert rd == test_data, (f'Printer->CDC wrong data ({size} bytes):\n' + f' expected: {test_data[:64]}\n received: {rd[:64]}') + + # Test 2: CDC -> Printer with multiple sizes, write in random 1-64 byte chunks + # Use a thread to read from printer since /dev/usb/lp read blocks + ser.reset_input_buffer() + time.sleep(0.5) + for size in sizes: + test_data = rand_ascii(size) + rd_result = [b'', None] # [data, error] + reader_ready = threading.Event() + + def lp_reader(): + try: + rd = b'' + fd = os.open(lp_dev, os.O_RDONLY) + reader_ready.set() + try: + while len(rd) < size: + chunk = os.read(fd, min(64, size - len(rd))) + if not chunk: + break + rd += chunk + finally: + os.close(fd) + rd_result[0] = rd + except Exception as e: + rd_result[1] = e + reader_ready.set() + + reader = threading.Thread(target=lp_reader, daemon=True) + reader.start() + # wait for reader to open lp device before writing + reader_ready.wait(timeout=5) + time.sleep(0.1) + + # Write to CDC in small chunks with flush to avoid overflowing device FIFO + offset = 0 + while offset < size: + chunk_size = min(random.randint(1, 64), size - offset) + ser.write(test_data[offset:offset + chunk_size]) + ser.flush() + time.sleep(0.01) + offset += chunk_size + + reader.join(timeout=10) + assert not reader.is_alive(), f'CDC->Printer timeout ({size} bytes)' + assert rd_result[1] is None, f'CDC->Printer read error: {rd_result[1]}' + assert rd_result[0] == test_data, (f'CDC->Printer wrong data ({size} bytes):\n' + f' expected: {test_data[:64]}\n received: {rd_result[0][:64]}') + time.sleep(0.2) + + ser.close() + + def test_device_mtp(board): uid = board['uid'] @@ -623,7 +754,8 @@ device_tests = [ 'device/dfu_runtime', 'device/cdc_msc_freertos', 'device/hid_boot_interface', - # 'device/mtp' + 'device/printer_to_cdc', + 'device/mtp' ] dual_tests = [ diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 7cb561b2d..029e5ffcd 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -13,7 +13,8 @@ "flasher": { "name": "esptool", "uid": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54", - "args": "-b 1500000" + "args": "-b 1500000", + "comment": "use --force for ESP32-P4 v0.1" }, "comment": "Use TS3USB30 mux to test both device and host" }, diff --git a/tools/codespell/ignore-words.txt b/tools/codespell/ignore-words.txt index 5b6e2e98b..7ce778fab 100644 --- a/tools/codespell/ignore-words.txt +++ b/tools/codespell/ignore-words.txt @@ -7,6 +7,7 @@ hsi inout mot pris +ptd ser sie synopsys diff --git a/tools/get_deps.py b/tools/get_deps.py index 1d596469b..115120ef7 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -14,6 +14,9 @@ deps_mandatory = { 'lib/lwip': ['https://github.com/lwip-tcpip/lwip.git', '159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'all'], + 'lib/threadx': ['https://github.com/eclipse-threadx/threadx.git', + '4b6e8100d932a3a67b34c6eb17f84f3bffb9e2ae', + 'all'], 'tools/linkermap': ['https://github.com/hathach/linkermap.git', '8e1f440fa15c567aceb5aa0d14f6d18c329cc67f', 'all'], @@ -58,9 +61,21 @@ deps_optional = { 'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git', 'b41cf930e65c734d8ec6de04f1d57d46787c76ae', 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'], + 'hw/mcu/nxp/mcuxsdk-core': ['https://github.com/nxp-mcuxpresso/mcuxsdk-core', + '0c5c6b16deb211110e06bde896cdff59ab213e16', + 'imxrt lpc51 lpc55 mcx'], 'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk', 'a1bdae309a14ec95a4f64a96d3315a4f89c397c6', - 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x imxrt'], + 'kinetis_k kinetis_k32l2 kinetis_kl lpc54 rw61x'], + 'hw/mcu/nxp/mcux-devices-lpc': ['https://github.com/nxp-mcuxpresso/mcux-devices-lpc', + '8096b783ec09d0d1c8629025a5f9d8e7df26e520', + 'lpc51 lpc55'], + 'hw/mcu/nxp/mcux-devices-mcx': ['https://github.com/nxp-mcuxpresso/mcux-devices-mcx', + 'ada1c97c761123ec0c179bb9bb9f744bf9a11475', + 'mcx'], + 'hw/mcu/nxp/mcux-devices-rt': ['https://github.com/nxp-mcuxpresso/mcux-devices-rt', + 'dba2b523c9df61f3330bd186242f8210a8e47c45', + 'imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', '675543bcc9baa8170f868ab7ba316d418dbcf41f', 'rp2040'], @@ -252,7 +267,7 @@ deps_optional = { 'hpmicro'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', - 'imxrt kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx rw61x mm32 msp432e4 nrf samd2x_l2x ' + 'kinetis_k kinetis_k32l2 kinetis_kl lpc54 rw61x mm32 msp432e4 nrf samd2x_l2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' 'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u0 stm32u5 stm32wb stm32wba ' @@ -260,7 +275,7 @@ deps_optional = { 'tm4c '], 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', '6f0a58d01aa9bd2feba212097f9afe7acd991d52', - 'ra stm32n6'], + 'imxrt ra stm32n6 lpc51 lpc55 mcx'], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', 'e73e04ca63495672d955f9268e003cffe168fcd8', 'lpc55'], diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf index caddda826..035e40b94 100644 --- a/tools/iar_template.ipcf +++ b/tools/iar_template.ipcf @@ -69,6 +69,11 @@ <path>$TUSB_DIR$/src/class/net/ncm.h</path> <path>$TUSB_DIR$/src/class/net/net_device.h</path> </group> + <group name="src/class/printer"> + <path>$TUSB_DIR$/src/class/printer/printer_device.c</path> + <path>$TUSB_DIR$/src/class/printer/printer.h</path> + <path>$TUSB_DIR$/src/class/printer/printer_device.h</path> + </group> <group name="src/class/usbtmc"> <path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path> <path>$TUSB_DIR$/src/class/usbtmc/usbtmc.h</path> |