Merge branch 'master' of https://github.com/hathach/tinyusb into dwc2_dma

8 files changed, 104 insertions, 0 deletions

diff --git a/examples/build_system/make/cpu/arm1176.mk b/examples/build_system/make/cpu/arm1176jzf-s.mk
index 022ccf7ad..022ccf7ad 100644
--- a/examples/build_system/make/cpu/arm1176.mk
+++ b/examples/build_system/make/cpu/arm1176jzf-s.mk
diff --git a/examples/build_system/make/cpu/arm926ej-s.mk b/examples/build_system/make/cpu/arm926ej-s.mk
new file mode 100644
index 000000000..5b84f514f
--- /dev/null
+++ b/examples/build_system/make/cpu/arm926ej-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm926ej-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/examples/build_system/make/cpu/cortex-m7-fpsp.mk b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
new file mode 100644
index 000000000..cd42c6fb8
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m7 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+	  --target=arm-none-eabi \
+	  -mcpu=cortex-m7 \
+	  -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  CFLAGS += \
+  	--cpu cortex-m7 \
+  	--fpu VFPv5_sp \
+
+  ASFLAGS += \
+		--cpu cortex-m7 \
+		--fpu VFPv5_sp \
+
+else
+  $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/examples/build_system/make/cpu/rv32i-ilp32.mk b/examples/build_system/make/cpu/rv32i-ilp32.mk
new file mode 100644
index 000000000..af764afc5
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32i-ilp32.mk
@@ -0,0 +1,16 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32i_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32i_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  $(error not support)
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/cpu/rv32imac-ilp32.mk b/examples/build_system/make/cpu/rv32imac-ilp32.mk
new file mode 100644
index 000000000..19c322ebc
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32imac-ilp32.mk
@@ -0,0 +1,17 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32imac_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32imac_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+  $(error not support)
+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
index a78f4130d..1500a51e0 100644
--- a/examples/build_system/make/make.mk
+++ b/examples/build_system/make/make.mk
@@ -109,6 +109,10 @@ INC += \
 BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
 CFLAGS += -DBOARD_$(BOARD_UPPER)
 
+ifdef CFLAGS_CLI
+	CFLAGS += $(CFLAGS_CLI)
+endif
+
 # use max3421 as host controller
 ifeq (${MAX3421_HOST},1)
   SRC_C += src/portable/analog/max3421/hcd_max3421.c
diff --git a/examples/build_system/make/rules.mk b/examples/build_system/make/rules.mk
index 7b6b339ed..102c6db0c 100644
--- a/examples/build_system/make/rules.mk
+++ b/examples/build_system/make/rules.mk
@@ -134,6 +134,17 @@ OPENOCD_OPTION ?=
 flash-openocd: $(BUILD)/$(PROJECT).elf
 	openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
 
+# --------------- openocd-wch -----------------
+# wch-linke is not supported yet in official openOCD yet. We need to either use
+# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
+# 2. compiled from https://github.com/hathach/riscv-openocd-wch or
+#    https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+#    with  ./configure --disable-werror --enable-wlinke --enable-ch347=no
+OPENOCD_WCH ?= /home/${USER}/app/riscv-openocd-wch/src/openocd
+OPENOCD_WCH_OPTION ?=
+flash-openocd-wch: $(BUILD)/$(PROJECT).elf
+	$(OPENOCD_WCH) $(OPENOCD_WCH_OPTION) -c init -c halt -c "flash write_image $<" -c reset -c exit
+
 # --------------- dfu-util -----------------
 DFU_UTIL_OPTION ?= -a 0
 flash-dfu-util: $(BUILD)/$(PROJECT).bin
diff --git a/examples/build_system/make/toolchain/riscv_gcc.mk b/examples/build_system/make/toolchain/riscv_gcc.mk
new file mode 100644
index 000000000..843aff38c
--- /dev/null
+++ b/examples/build_system/make/toolchain/riscv_gcc.mk
@@ -0,0 +1,20 @@
+# makefile for arm gcc toolchain
+
+# Can be set by family, default to ARM GCC
+CROSS_COMPILE ?= riscv-none-embed-
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+CFLAGS += \
+  -fsingle-precision-constant \
+
+LIBS += -lgcc -lm -lnosys
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk