mcx family renamed as mcxn

MCXN and MCXA have different ARM Cortex M33 core, can't be on the same family

19 files changed, 0 insertions, 2172 deletions

diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index 6f10a7ab0..000000000
--- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "fsl_device_registers.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       3
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.cmake b/hw/bsp/mcx/boards/frdmmcxn947/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.h b/hw/bsp/mcx/boards/frdmmcxn947/board.h
deleted file mode 100644
index acb73363f..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO0
-#define LED_CLK               kCLOCK_Gpio0
-#define LED_PIN               10 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            23
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.mk b/hw/bsp/mcx/boards/frdmmcxn947/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c
deleted file mode 100644
index c33790ac5..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- -  {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-  /* Enables the clock for PORT0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
-                                   kPORT_PullDisable,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_23 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_23 (pin B7) is configured as PIO0_23 */
-    PORT_SetPinConfig(PORT0, 23U, &SW2);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h
deleted file mode 100644
index eae98bfa7..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO3
-#define LED_CLK               kCLOCK_Gpio3
-#define LED_PIN               4 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            6
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
deleted file mode 100644
index acc2f3e45..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-    /* Enables the clock for PORT3: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port3);
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
-                                                     kPORT_PullDisable,
-                                                     /* Low internal pull resistor value is selected. */
-                                                     kPORT_LowPullResistor,
-                                                     /* Fast slew rate is configured */
-                                                     kPORT_FastSlewRate,
-                                                     /* Passive input filter is disabled */
-                                                     kPORT_PassiveFilterDisable,
-                                                     /* Open drain output is disabled */
-                                                     kPORT_OpenDrainDisable,
-                                                     /* Low drive strength is configured */
-                                                     kPORT_LowDriveStrength,
-                                                     /* Pin is configured as PIO3_4 */
-                                                     kPORT_MuxAlt0,
-                                                     /* Digital input enabled */
-                                                     kPORT_InputBufferEnable,
-                                                     /* Digital input is not inverted */
-                                                     kPORT_InputNormal,
-                                                     /* Pin Control Register fields [15:0] are not locked */
-                                                     kPORT_UnlockRegister};
-    /* PORT3_4 (pin F14) is configured as PIO3_4 */
-    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript
deleted file mode 100644
index fd8bcffef..000000000
--- a/hw/bsp/mcx/debug.jlinkscript
+++ /dev/null
@@ -1,5 +0,0 @@
-int SetupTarget(void) {
-  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
-
-  return 0;
-}
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
deleted file mode 100644
index 8672ca63f..000000000
--- a/hw/bsp/mcx/family.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_lpuart.h"
-#include "board.h"
-
-#include "pin_mux.h"
-#include "clock_config.h"
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB1_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-void board_init(void)
-{
-  BOARD_InitPins();
-  BOARD_InitBootClocks();
-  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // LED
-  CLOCK_EnableClock(LED_CLK);
-  gpio_pin_config_t led_config = {
-      kGPIO_DigitalOutput,
-      0,
-  };
-  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
-  board_led_write(0);
-
-#ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
-#endif
-
-  // Button
-#ifdef BUTTON_GPIO
-  CLOCK_EnableClock(BUTTON_CLK);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
-#endif
-
-#ifdef UART_DEV
-  // UART
-//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
-
-  // Enable UART when debug log is on
-  board_uart_init_clock();
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
-  LPUART_Init(UART_DEV, &uart_config, 12000000u);
-#endif
-
-  // USB VBUS
-  /* PORT0 PIN22 configured as USB0_VBUS */
-
-#if PORT_SUPPORT_DEVICE(0)
-  // Port0 is Full Speed
-
-  CLOCK_AttachClk(kCLK_48M_to_USB0);
-  CLOCK_EnableClock(kCLOCK_Usb0Ram);
-  CLOCK_EnableClock(kCLOCK_Usb0Fs);
-  CLOCK_EnableUsbfsClock();
-#endif
-
-#if PORT_SUPPORT_DEVICE(1)
-  // Port1 is High Speed
-
-  // Power
-  SPC0->ACTIVE_VDELAY = 0x0500;
-  /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
-  SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
-  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
-                      SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
-  /* Wait until it is done */
-  while (SPC0->SC & SPC_SC_BUSY_MASK) {}
-  if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
-    SCG0->TRIM_LOCK = 0x5a5a0001U;
-    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
-    /* wait LDO ready */
-    while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
-  }
-  SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
-  SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
-  /* xtal = 20 ~ 30MHz */
-  SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
-  SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
-  while (1) {
-    if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
-      break;
-    }
-  }
-
-  // Clock
-  SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
-  CLOCK_EnableClock(kCLOCK_UsbHs);
-  CLOCK_EnableClock(kCLOCK_UsbHsPhy);
-  CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
-  CLOCK_EnableUsbhsClock();
-
-  // USB PHY
-#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
-  USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
-#endif
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  USBPHY->PWD = 0;
-
-  // TX Timing
-  uint32_t phytx = USBPHY->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
-  //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  USBPHY->TX = phytx;
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_GPIO
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-#ifdef UART_DEV
-  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
-  return len;
-#else
-  (void) buf; (void) len;
-  return 0;
-#endif
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
deleted file mode 100644
index 13d1d44ef..000000000
--- a/hw/bsp/mcx/family.cmake
+++ /dev/null
@@ -1,110 +0,0 @@
-include_guard()
-
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# toolchain set up
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # external driver
-      #lib/sct_neopixel/sct_neopixel.c
-
-      # driver
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      )
-    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    #    )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      # driver
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      )
-
-    update_board(${BOARD_TARGET})
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_sources(${BOARD_TARGET} PUBLIC
-        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
-        )
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
-    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
-    )
-  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
-
-  # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
-
-  # Flashing
-  family_flash_jlink(${TARGET})
-  #family_flash_nxplink(${TARGET})
-  #family_flash_pyocd(${TARGET})
-endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
deleted file mode 100644
index 526effdfb..000000000
--- a/hw/bsp/mcx/family.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= cortex-m33
-
-# Default to Highspeed PORT1
-PORT ?= 1
-
-CFLAGS += \
-  -flto \
-  -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
-  -DBOARD_TUD_RHPORT=$(PORT) \
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
-
-# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-	SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
-else
-  $(info "PORT0 Full Speed")
-  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-  SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
-endif
-
-SRC_C += \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
-
-SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S