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authorhathach <[email protected]>2020-11-09 01:01:05 +0700
committerhathach <[email protected]>2020-11-09 01:01:05 +0700
commit7ab3da1e0302e466447c02fa353b8659e053764f (patch)
tree0d84614d417f97d3a044ca2011d74587b874f237 /hw/bsp/samg55xplained
parent89b92b54a7b6a9e9dabb72f2b4a3b616cc9f81cc (diff)
same70 xplained uart via edbg work with board_test
Diffstat (limited to 'hw/bsp/samg55xplained')
-rw-r--r--hw/bsp/samg55xplained/samg55xplained.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c
index c9bc0656e..ed106b06b 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg55xplained/samg55xplained.c
@@ -45,7 +45,7 @@
#define UART_TX_PIN GPIO(GPIO_PORTA, 28)
#define UART_RX_PIN GPIO(GPIO_PORTA, 27)
-struct _usart_sync_device _edbg_com;
+struct _usart_sync_device edbg_com;
//------------- IMPLEMENTATION -------------//
void board_init(void)
@@ -72,10 +72,10 @@ void board_init(void)
gpio_set_pin_function(UART_RX_PIN, MUX_PA27B_FLEXCOM7_RXD);
gpio_set_pin_function(UART_TX_PIN, MUX_PA28B_FLEXCOM7_TXD);
- _usart_sync_init(&_edbg_com, FLEXCOM7);
- _usart_sync_set_baud_rate(&_edbg_com, CFG_BOARD_UART_BAUDRATE);
- _usart_sync_set_mode(&_edbg_com, USART_MODE_ASYNCHRONOUS);
- _usart_sync_enable(&_edbg_com);
+ _usart_sync_init(&edbg_com, FLEXCOM7);
+ _usart_sync_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+ _usart_sync_set_mode(&edbg_com, USART_MODE_ASYNCHRONOUS);
+ _usart_sync_enable(&edbg_com);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer (samd SystemCoreClock may not correct)
@@ -129,8 +129,8 @@ int board_uart_write(void const * buf, int len)
uint8_t const * buf8 = (uint8_t const *) buf;
for(int i=0; i<len; i++)
{
- while ( !_usart_sync_is_ready_to_send(&_edbg_com) ) {}
- _usart_sync_write_byte(&_edbg_com, buf8[i]);
+ while ( !_usart_sync_is_ready_to_send(&edbg_com) ) {}
+ _usart_sync_write_byte(&edbg_com, buf8[i]);
}
return len;
}