Merge branch 'master' into port-ft90x

author: Gordon McNab <[email protected]> 2021-12-08 08:36:43 +0000
committer: Gordon McNab <[email protected]> 2021-12-08 08:36:43 +0000
commit: 9a7db985931ae215e808d40e7bacd52535d45305 (patch)
tree: a4d75e2c3823766da53a006280c0d805630d996e /hw/bsp
parent: edf3f3501656b010ad4a9e1d0a0d62573dd0b3fb (diff)
parent: cde824f17f73b5ce4fcec8c176827297854a76c2 (diff)
132 files changed, 10505 insertions, 842 deletions
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 6a26f55b7..e208624ba 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -96,7 +96,7 @@ void board_led_task(void)
 TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 {
   (void) fhdl;
-  SEGGER_RTT_Write(0, (char*) buf, (int) count);
+  SEGGER_RTT_Write(0, (const char*) buf, (int) count);
   return count;
 }
 
@@ -126,6 +126,8 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
+  (void) buf;
+  (void) count;
   return 0;
 }
 
@@ -135,13 +137,13 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 {
   (void) fhdl;
-  return board_uart_write(buf, count);
+  return board_uart_write(buf, (int) count);
 }
 
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
-  return board_uart_read((uint8_t*) buf, count);
+  return board_uart_read((uint8_t*) buf, (int) count);
 }
 
 #endif
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 8cc50c808..f8b5c061c 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -98,6 +98,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx
   #include "msp430.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
+  #include "msp.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
   // no header needed
 
@@ -125,7 +128,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_RP2040
   #include "pico.h"
   
-#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
+#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
   #include "em_device.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
@@ -134,6 +137,15 @@
 #elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
   #include "gd32vf103.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X
+  #include "mm32_device.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_XMC4000
+  #include "xmc_device.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_TM4C123
+  #include "TM4C123.h"
+
 #else
   #error "Missing MCU header"
 #endif
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index 1d09bd3d4..b7796b9d8 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -18,6 +18,9 @@ CFLAGS += \
   -DSVC_Handler=SVCall_Handler \
   -DHWREV=$(HWREV)
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
 
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index e7c7ae364..95fe70d01 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -53,6 +53,9 @@ void UnhandledIRQ(void)
   while(1);
 }
 
+// DA146xx driver function that must be called whenever VBUS changes.
+extern void tusb_vbus_changed(bool present);
+
 void board_init(void)
 {
   // LED
@@ -65,12 +68,15 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
+  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-  NVIC_SetPriority(USB_IRQn, 2);
+#if TUSB_OPT_DEVICE_ENABLED
+  // This board is USB powered there is no need to monitor
+  // VBUS line.  Notify driver that VBUS is present.
+  tusb_vbus_changed(true);
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -81,6 +87,7 @@ void board_init(void)
 
   mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
   mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -94,8 +101,8 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
+  // button is active HIGH
+  return hal_gpio_read(BUTTON_PIN);
 }
 
 int board_uart_read(uint8_t* buf, int len)
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 85fa17152..0441c000c 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -36,6 +36,21 @@ void USB_IRQHandler(void)
   tud_int_handler(0);
 }
 
+#if TUSB_OPT_DEVICE_ENABLED
+// DA146xx driver function that must be called whenever VBUS changes
+extern void tusb_vbus_changed(bool present);
+
+// VBUS change interrupt handler
+void VBUS_IRQHandler(void)
+{
+  bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0;
+  // Clear VBUS interrupt
+  CRG_TOP->VBUS_IRQ_CLEAR_REG = 1;
+
+  tusb_vbus_changed(present);
+}
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -65,12 +80,20 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
+  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-  NVIC_SetPriority(USB_IRQn, 2);
+#if TUSB_OPT_DEVICE_ENABLED
+  // Setup interrupt for both connect and disconnect
+  CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
+                               CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
+  NVIC_SetPriority(VBUS_IRQn, 2);
+  // Trigger interrupt at the start to inform driver about VBUS state at start
+  // otherwise it could go unnoticed.
+  NVIC_SetPendingIRQ(VBUS_IRQn);
+  NVIC_EnableIRQ(VBUS_IRQn);
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -81,6 +104,7 @@ void board_init(void)
 
   mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
   mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index c624a5cf2..b325dfeb4 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
 
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 86391ab5d..6f243c6a2 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 
@@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
index 71753012b..c3c687a70 100644
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ b/hw/bsp/esp32s2/boards/CMakeLists.txt
@@ -6,9 +6,7 @@ idf_component_register(SRCS esp32s2.c
 # Apply board specific content
 include("${BOARD}/board.cmake")
 
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
   "${TOP}/src"  
 )
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
index fb9b21641..4b9000a6a 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/esp32s2/family.mk
@@ -7,14 +7,11 @@ all:
 
 build: all
 
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
 fullclean:
 	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
 	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
 
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
+clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
 	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
 
 uf2: $(BUILD)/$(PROJECT).uf2
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index 25e5e9613..12b7bfd18 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -101,9 +101,14 @@ int board_uart_read(uint8_t* buf, int len)
 int board_uart_write(void const * buf, int len)
 {
   int32_t offset = 0;
+  uint8_t const* buf8 = (uint8_t const*) buf;
   for (offset = 0; offset < len; offset++)
-    if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
-      messible_in_write(((uint8_t *)buf)[offset]);
+  {
+    if (!(messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
+    {
+      messible_in_write(buf8[offset]);
+    }
+  }
   return len;
 }
 
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
index c45095caa..924bb18e9 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
@@ -122,7 +122,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 451bc37c2..15bd50eda 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -6,10 +6,15 @@ CFLAGS += \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \
   -DCPU_MKL25Z128VLK4 \
-  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX
+  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
+  -DCFG_EXAMPLE_VIDEO_READONLY
+
+LDFLAGS += \
+  -Wl,--defsym,__stack_size__=0x400 \
+  -Wl,--defsym,__heap_size__=0
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format
 
 MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
 
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 7d3a173ed..72982ed8a 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -54,6 +54,14 @@ void USB0_IRQHandler(void)
 #define LED_PIN_FUNCTION      kPORT_MuxAsGpio
 #define LED_STATE_ON          0
 
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_PIN_PORT       PORTC
+#define BUTTON_PIN            9U
+#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
+#define BUTTON_STATE_ACTIVE   0
+
 // UART
 #define UART_PORT             UART0
 #define UART_PIN_CLOCK        kCLOCK_PortA
@@ -84,7 +92,19 @@ void board_init(void)
   PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION);
   gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
   GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
+  board_led_write(false);
+
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  // Button
+  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
+  port_pin_config_t button_port = {
+    .pullSelect = kPORT_PullUp, 
+    .mux = BUTTON_PIN_FUNCTION,
+  };
+  PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port);
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
+#endif
 
   // UART
   CLOCK_EnableClock(UART_PIN_CLOCK);
@@ -119,6 +139,9 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN);
+#endif
   return 0;
 }
 
@@ -130,7 +153,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPSCI_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index d76fb9a2a..c20732302 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -158,7 +158,7 @@ int board_uart_write(void const* buf, int len) {
 #if defined(UART_DEV)
   int txsize = len;
   while (txsize--) {
-    usart_write(UART_DEV, *(uint8_t*)buf);
+    usart_write(UART_DEV, *(uint8_t const*)buf);
     buf++;
   }
   return len;
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 9148e7f8b..49bacdf1b 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -28,14 +28,13 @@ CFLAGS += \
 	-mstrict-align \
 	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
-	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
-	-DGD32VF103 
+	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
 	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
index 507db7f00..17dc01cd9 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DCPU_MIMXRT1011DAE5A
+CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1011
 
 # For flash-jlink target
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
index 17fd25dfe..20c697ea1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DCPU_MIMXRT1015DAF5A
+CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1015
 
 # For flash-jlink target
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 77a224a5e..716681ca9 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -172,7 +172,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len);
   return len;
 }
 
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index a919d3698..d086d503f 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -28,7 +28,9 @@ LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/system_$(MCU_VARIANT).c \
 	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
 	$(MCU_DIR)/project_template/clock_config.c \
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
index a3e04cfa1..b00fc71b0 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
@@ -1,3 +1,4 @@
+CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
 LD_FILE = $(BOARD_PATH)/lpc1549.ld
 
 JLINK_DEVICE = LPC1549
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index e80a3bc51..c7dd3f8be 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -15,7 +15,7 @@ CFLAGS += \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
 
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 3fed0b45a..7aa36abc4 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -13,12 +13,14 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 4789425a3..4f1199c3a 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -210,7 +210,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
+  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
   return 0;
 }
 
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 4fc1f6222..f037a9f5b 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -265,7 +265,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
+  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index 8fcda51ee..b736eebe1 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -9,6 +9,7 @@ CFLAGS += \
   -DCORE_M0 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 0d56a33a6..62135c274 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -9,6 +9,7 @@ CFLAGS += \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index b69be39bd..34b4d6dc0 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DRTC_EV_SUPPORT=0
 
 # lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index e99df9f08..b0d885866 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DRTC_EV_SUPPORT=0
 
 # startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
new file mode 100644
index 000000000..b7663926f
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -0,0 +1,8 @@
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = stm32f411ve
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
new file mode 100644
index 000000000..d96d6e43d
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
@@ -0,0 +1,163 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001FFFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
new file mode 100644
index 000000000..cff7bc15e
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -0,0 +1,172 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+  tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+  /* Select USBCLK source */
+  //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+  RCC->CFGR &= ~(0x3 << 22);
+  RCC->CFGR |= (0x1 << 22);
+
+  /* Enable USB clock */
+  RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+void board_led_write (bool state);
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+//   usb clock	
+  USB_DeviceClockInit();
+
+  if ( SysTick_Config(SystemCoreClock / 1000) )
+  {
+    while ( 1 )
+      ;
+  }
+  NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+  // LED
+  GPIO_InitTypeDef GPIO_InitStruct;
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15);                      //Disable JTDI   AF to  AF15
+
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  board_led_write(true);
+
+  // UART
+  UART_InitTypeDef UART_InitStruct;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);    //enableUART1,GPIOAclock
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);    //
+  //UART initialset
+
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+  UART_StructInit(&UART_InitStruct);
+  UART_InitStruct.UART_BaudRate = baudrate;
+  UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+  UART_InitStruct.UART_StopBits = UART_StopBits_1;    //one stopbit
+  UART_InitStruct.UART_Parity = UART_Parity_No;    //none odd-even  verify bit
+  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;    //No hardware flow control
+  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;    // receive and sent  mode
+
+  UART_Init(UART1, &UART_InitStruct);    //initial uart 1
+  UART_Cmd(UART1, ENABLE);                    //enable uart 1
+
+  //UART1_TX   GPIOA.9
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  //UART1_RX    GPIOA.10
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+  state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_15)) : (GPIO_SetBits(GPIOA, GPIO_Pin_15));
+}
+
+uint32_t board_button_read (void)
+{
+  return 0;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+  const char *buff = buf;
+  while ( len )
+  {
+    while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+      ;    //The loop is sent until it is finished
+    UART1->TDR = (*buff & 0xFF);
+    buff++;
+    len--;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
new file mode 100644
index 000000000..1a9f51191
--- /dev/null
+++ b/hw/bsp/mm32/family.mk
@@ -0,0 +1,36 @@
+UF2_FAMILY_ID = 0x0
+SDK_DIR = hw/mcu/mindmotion/mm32sdk
+DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m3 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X 
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
+
+SRC_C += \
+	src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
+	
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
+	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM3
+
+# flash target using on-board
+flash: flash-jlink
diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
new file mode 100644
index 000000000..3130d663b
--- /dev/null
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
@@ -0,0 +1,46 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#define CLK_LED               12u
+#define GPIO_LED              GPION
+#define GPIO_LED_PIN          1u
+
+#define CLK_BUTTON            8u
+#define GPIO_BUTTON           GPIOJ
+#define GPIO_BUTTON_PIN       0u
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
new file mode 100644
index 000000000..262dc1d30
--- /dev/null
+++ b/hw/bsp/msp432e4/family.c
@@ -0,0 +1,203 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "board.h"
+#include "msp.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+void board_init(void)
+{
+  unsigned bits;
+  /* Turn off power domains that unused peripherals belong to */
+  SYSCTL->PCCAN  = 0u;
+#ifdef __MCU_HAS_LCD0__
+  SYSCTL->PCLCD  = 0u;
+#endif
+  SYSCTL->PCEMAC = 0u;
+  SYSCTL->PCEPHY = 0u;
+  SYSCTL->PCCCM  = 0u;
+
+  /* --- Setup system clock --- */
+  /* Start power-up process of the main oscillator */
+  SYSCTL->MOSCCTL = SYSCTL_MOSCCTL_OSCRNG;
+  while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)) ; /* Wait for completion */
+  SYSCTL->MISC = SYSCTL_MISC_MOSCPUPMIS; /* Clear the completion interrupt status */
+  /* Set the main oscillator to PLL reference clock */
+  SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_PLLSRC_MOSC;
+  /* PLL freq. = (MOSC freq. / 10) * 96 = 240MHz */
+  SYSCTL->PLLFREQ1 = (4 << SYSCTL_PLLFREQ1_N_S) | (1 << SYSCTL_PLLFREQ1_Q_S);
+  SYSCTL->PLLFREQ0 = (96 << SYSCTL_PLLFREQ0_MINT_S) | SYSCTL_PLLFREQ0_PLLPWR;
+  /* Set BCHT=6, BCE=0, WS=5 for 120MHz system clock */
+  SYSCTL->MEMTIM0 = SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) |
+    SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_MB1;
+  /* Wait for completion of PLL power-up process */
+  while (!(SYSCTL->RIS & SYSCTL_RIS_PLLLRIS)) ;
+  SYSCTL->MISC = SYSCTL_MISC_PLLLMIS; /* Clear the completion interrupt status */
+  /* Switch the system clock to PLL/4 */
+  SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_MEMTIMU | SYSCTL_RSCLKCFG_ACG |
+         SYSCTL_RSCLKCFG_USEPLL | SYSCTL_RSCLKCFG_PLLSRC_MOSC | (1 << SYSCTL_RSCLKCFG_PSYSDIV_S);
+
+  SystemCoreClockUpdate();
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  /* USR_LED1 ON1 */
+  bits              = TU_BIT(CLK_LED);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIO_LED->DIR     = TU_BIT(GPIO_LED_PIN);
+  GPIO_LED->DEN     = TU_BIT(GPIO_LED_PIN);
+
+  /* USR_SW1 PJ0 */
+  bits              = TU_BIT(CLK_BUTTON);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIO_BUTTON->PUR  = TU_BIT(GPIO_BUTTON_PIN);
+  GPIO_BUTTON->DEN  = TU_BIT(GPIO_BUTTON_PIN);
+
+  /* UART PA0,1 */
+  bits              = TU_BIT(0);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIOA->AFSEL      = 3u;
+  GPIOA->PCTL       = 0x11u;
+  GPIOA->DEN        = 3u;
+
+  SYSCTL->RCGCUART |= 1u << 0;
+  while (!(SYSCTL->PRUART & (1u << 0))) ;
+  UART0->CTL        = 0;
+  UART0->IBRD       = 8;  /* 8.68056 = 16MHz / (16 * 115200) */
+  UART0->FBRD       = 44; /* 0.6875 = 44/64 -> 115108bps (0.08%) */
+  UART0->LCRH       = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
+  UART0->CC         = UART_CC_CS_PIOSC; /* Set the baud clock to PIOSC */
+  UART0->CTL        = UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
+
+  /* USB PB0(ID) PB1(VBUS) PL6,7(DP,DM) */
+  bits              = TU_BIT(1) | TU_BIT(10);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIOB->AMSEL      = TU_BIT(0) | TU_BIT(1);
+  GPIOL->AMSEL      = TU_BIT(6) | TU_BIT(7);
+
+#if TUSB_OPT_HOST_ENABLED
+  /* USB PD6(EPEN) */
+  bits              = TU_BIT(3);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIOD->AFSEL      = TU_BIT(6);
+  GPIOD->PCTL       = 0x05000000u;
+  GPIOD->DEN        = TU_BIT(6);
+#endif
+
+  SYSCTL->RCGCUSB   = 1u; /* Open the clock gate for SYSCLK */
+  while (!(SYSCTL->PRUSB & (1u << 0))) ;
+  USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
+  __DMB(); /* Wait for completion of opening of the clock gate */
+
+  SYSCTL->SRUSB     = 1u;
+  for (int i = 0; i < 16; ++i) __NOP();
+  SYSCTL->SRUSB     = 0u;
+
+  USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
+  __DMB(); /* Wait for completion of opening of the clock gate */
+#if TUSB_OPT_HOST_ENABLED
+  USB0->GPCS = USB_GPCS_DEVMOD_OTG;
+  USB0->EPC  = USB_EPC_EPENDE | USB_EPC_EPEN_HIGH;
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
+  USB0->GPCS = USB_GPCS_DEVMOD_DEVVBUS;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state)
+    GPIO_LED->DATA |= TU_BIT(GPIO_LED_PIN);
+  else
+    GPIO_LED->DATA &= ~TU_BIT(GPIO_LED_PIN);
+}
+
+uint32_t board_button_read(void)
+{
+  return (GPIO_BUTTON->DATA & TU_BIT(GPIO_BUTTON_PIN)) ? 0u : 1u;
+}
+
+int board_uart_read(uint8_t * buf, int len)
+{
+  for (int i = 0; i < len; ++i) {
+    while (UART0->FR & UART_FR_RXFE) ;
+    *buf++ = UART0->DR;
+  }
+  return len;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  uint8_t const *p = (uint8_t const *)buf;
+  for (int i = 0; i < len; ++i) {
+    while (UART0->FR & UART_FR_TXFF) ;
+    UART0->DR = *p++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0u;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
new file mode 100644
index 000000000..e3cb90abc
--- /dev/null
+++ b/hw/bsp/msp432e4/family.mk
@@ -0,0 +1,41 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti
+
+CFLAGS += \
+	-flto \
+	-mthumb \
+	-mslow-flash-data \
+	-mabi=aapcs \
+	-mcpu=cortex-m4 \
+	-mfloat-abi=hard \
+	-mfpu=fpv4-sp-d16 \
+	-D__MSP432E401Y__ \
+	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=cast-qual -Wno-error=format=
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
+LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
+LDFLAGS += $(addprefix -L,$(LDINC))
+
+MCU_DIR = hw/mcu/ti/msp432e4
+
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	src/portable/mentor/musb/hcd_musb.c \
+	$(MCU_DIR)/Source/system_msp432e401y.c
+
+INC += \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR)/Include \
+	$(TOP)/$(BOARD_PATH)
+
+SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# For flash-jlink target
+JLINK_DEVICE = MSP432E401Y
+JLINK_IF     = SWD
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 04c37feeb..3e901567c 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 
@@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d1afd2587..d8283a9e6 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -14,19 +14,7 @@ CFLAGS += \
   -DCONFIG_GPIO_AS_PINRESET
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
-
-# due to tusb_hal_nrf_power_event
-GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
-ifeq ($(CMDEXE),1)
-  ifeq ($(shell if $(GCCVERSION) geq 8 echo 1), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-else
-  ifeq ($(shell expr $(GCCVERSION) \>= 8), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-endif
+CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 # All source paths should be relative to the top level.
 LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index a0a208ca7..ff1d5aa3a 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -16,24 +16,12 @@ LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/spi_i2s.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 848b19f95..4f0ebf201 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -7,6 +7,7 @@ CFLAGS += \
   -mcpu=cortex-m0 \
   -D__ARM_FEATURE_DSP=0 \
   -DUSE_ASSERT=0 \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -D__CORTEX_SC=0 \
   -DCFG_TUSB_MCU=OPT_MCU_NUC126
 
@@ -16,28 +17,13 @@ LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/clk.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/ebi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pwm.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/scuart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/spi.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/timer_pwm.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/GCC/startup_NUC126.S
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 90b3e91fb..4d7aac7f5 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -6,6 +6,7 @@ CFLAGS += \
   -mabi=aapcs-linux \
   -mcpu=cortex-m0 \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_NUC120
 
 # All source paths should be relative to the top level.
@@ -14,26 +15,11 @@ LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc120/dcd_nuc120.c \
   hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/system_NUC100Series.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2s.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/ps2.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/spi.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/GCC/startup_NUC100Series.S
diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
new file mode 100644
index 000000000..1d3565d5c
--- /dev/null
+++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
@@ -0,0 +1,38 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
new file mode 100644
index 000000000..897342479
--- /dev/null
+++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
@@ -0,0 +1 @@
+CFLAGS += -DBCM_VERSION=2711
diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
new file mode 100644
index 000000000..ba0b2700a
--- /dev/null
+++ b/hw/bsp/raspberrypi4/family.c
@@ -0,0 +1,144 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "board.h"
+
+#include "broadcom/interrupts.h"
+#include "broadcom/io.h"
+#include "broadcom/mmu.h"
+#include "broadcom/caches.h"
+#include "broadcom/vcmailbox.h"
+
+// LED
+#define LED_PIN               18
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+void board_init(void)
+{
+  setup_mmu_flat_map();
+  init_caches();
+
+  // LED
+  gpio_initOutputPinWithPullNone(LED_PIN);
+  board_led_write(true);
+
+  // Button
+  // TODO
+
+  // Uart
+  uart_init();
+
+  // Turn on USB peripheral.
+  vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
+
+  // Timer 1/1024 second tick
+  SYSTMR->CS_b.M1 = 1;
+  SYSTMR->C1 = SYSTMR->CLO + 977;
+  BP_EnableIRQ(TIMER_1_IRQn);
+
+  BP_SetPriority(USB_IRQn, 0x00);
+  BP_ClearPendingIRQ(USB_IRQn);
+  BP_EnableIRQ(USB_IRQn);
+  BP_EnableIRQs();
+}
+
+void board_led_write(bool state)
+{
+  gpio_setPinOutputBool(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  for (int i = 0; i < len; i++) {
+    const char* cbuf = buf;
+    while (!UART1->STAT_b.TX_READY) {}
+    if (cbuf[i] == '\n') {
+      UART1->IO = '\r';
+      while (!UART1->STAT_b.TX_READY) {}
+    }
+    UART1->IO = cbuf[i];
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void TIMER_1_IRQHandler(void)
+{
+  system_ticks++;
+  SYSTMR->C1 += 977;
+  SYSTMR->CS_b.M1 = 1;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  // asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
new file mode 100644
index 000000000..c65070a71
--- /dev/null
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -0,0 +1,51 @@
+MCU_DIR = hw/mcu/broadcom
+DEPS_SUBMODULES += $(MCU_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CC = clang
+
+CFLAGS += \
+	-mcpu=cortex-a72 \
+	-Wall \
+	-O0 \
+	-ffreestanding \
+	-nostdlib \
+	-nostartfiles \
+	-std=c17 \
+	-mgeneral-regs-only \
+	-DCFG_TUSB_MCU=OPT_MCU_BCM2711
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=cast-qual
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
+	$(MCU_DIR)/broadcom/interrupts.c \
+	$(MCU_DIR)/broadcom/io.c \
+	$(MCU_DIR)/broadcom/mmu.c \
+	$(MCU_DIR)/broadcom/caches.c \
+	$(MCU_DIR)/broadcom/vcmailbox.c
+
+
+CROSS_COMPILE = aarch64-none-elf-
+
+SKIP_NANOLIB = 1
+
+LD_FILE = $(MCU_DIR)/broadcom/link.ld
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
+
+SRC_S += $(MCU_DIR)/broadcom/boot.S
+
+$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) -O binary $^ $@
+
+# Copy to kernel to netboot drive or SD card
+# Change destinaation to fit your need
+flash: $(BUILD)/kernel8.img
+	$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 41960b6cd..1aa180ef8 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -70,12 +70,13 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/hid/hid_device.c
 			${TOP}/src/class/midi/midi_device.c
 			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/net_device.c
+			${TOP}/src/class/net/ecm_rndis_device.c
+			${TOP}/src/class/net/ncm_device.c
 			${TOP}/src/class/usbtmc/usbtmc_device.c
 			${TOP}/src/class/vendor/vendor_device.c
+			${TOP}/src/class/video/video_device.c
 			)
 
-
 	# Base config for host mode; wrapped by SDK's tinyusb_host
 	add_library(tinyusb_host_base INTERFACE)
 	target_sources(tinyusb_host_base INTERFACE
@@ -151,4 +152,28 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		enable_language(C CXX ASM)
 		pico_sdk_init()
 	endfunction()
+
+	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
+	function(suppress_tinyusb_warnings)
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/tusb.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/device/usbd.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-null-dereference")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+	endfunction()
 endif()
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index caf5fd6fa..633ddad16 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -228,7 +228,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const *buf, int len)
 {
-  sci0_buf[0].buf = (uint8_t*)buf;
+  sci0_buf[0].buf = (uint8_t*)(uintptr_t) buf;
   sci0_buf[0].cnt = len;
   SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
   while (SCI0.SCR.BIT.TE) ;
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 20867455e..ab86bc419 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -273,7 +273,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const *buf, int len)
 {
-  sci_buf[0].buf = (uint8_t*)buf;
+  sci_buf[0].buf = (uint8_t*)(uintptr_t) buf;
   sci_buf[0].cnt = len;
   SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
   while (SCI5.SCR.BIT.TE) ;
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 032d11b98..ae55be75b 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -11,6 +11,9 @@ CFLAGS += \
   -DOSC32K_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
index 5cd82735c..4be547a1b 100644
--- a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21J18A__
+CFLAGS += -D__SAMD21J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/samd21j18a_flash.ld
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.mk b/hw/bsp/samd21/boards/circuitplayground_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/circuitplayground_express/board.mk
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk
index ec3217f89..112fb6946 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.mk
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY
+CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/samd21g17a_flash.ld
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.mk b/hw/bsp/samd21/boards/feather_m0_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/feather_m0_express/board.mk
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/luna_d21/board.mk
index 5beb5e02d..27a634e3a 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.mk
+++ b/hw/bsp/samd21/boards/luna_d21/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld
 
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h
index b9292b9af..13b7556b0 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.h
@@ -35,7 +35,7 @@
 #define LED_PIN               17
 #define LED_STATE_ON          1
 
-// Button
+// Button: D5
 #define BUTTON_PIN            15
 #define BUTTON_STATE_ACTIVE   0
 
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.mk b/hw/bsp/samd21/boards/metro_m0_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.mk
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h
new file mode 100644
index 000000000..6f8325e49
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.h
@@ -0,0 +1,46 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED is neopixel, leave unset for now
+
+// Button is wired to reset
+
+// UART
+#define UART_RX_PIN           8
+#define UART_TX_PIN           7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd21/boards/qtpy/board.mk b/hw/bsp/samd21/boards/qtpy/board.mk
new file mode 100644
index 000000000..6cefa84c3
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.mk
@@ -0,0 +1,11 @@
+# For Adafruit QT Py board
+
+CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD21E18
+
+flash: flash-bossac
diff --git a/hw/bsp/samd21/boards/qtpy/qtpy.ld b/hw/bsp/samd21/boards/qtpy/qtpy.ld
new file mode 100644
index 000000000..f0c93340c
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/qtpy.ld
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+ENTRY(Reset_Handler)
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
index 54591b3a5..1c888da3a 100644
--- a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h
new file mode 100644
index 000000000..c8692e6bd
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.h
@@ -0,0 +1,34 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Jean Gressmann <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#pragma once
+
+// LED
+#define LED_PIN               10 // PA10
+#define LED_STATE_ON          1
+
+// UART
+#define UART_SERCOM           0
+
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk
new file mode 100644
index 000000000..803ffe892
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.mk
@@ -0,0 +1,5 @@
+CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/trinket_m0.ld
+
diff --git a/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
new file mode 100644
index 000000000..f0c93340c
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+ENTRY(Reset_Handler)
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index eb5b55863..cead582e9 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -45,6 +45,11 @@ void USB_Handler(void)
 }
 
 //--------------------------------------------------------------------+
+// UART support
+//--------------------------------------------------------------------+
+void uart_init(void);
+
+//--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
@@ -70,15 +75,23 @@ void board_init(void)
   // Update SystemCoreClock since it is hard coded with asf4 and not correct
   // Init 1ms tick timer (samd SystemCoreClock may not correct)
   SystemCoreClock = CONF_CPU_FREQUENCY;
+#if CFG_TUSB_OS  == OPT_OS_NONE
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
 
   // Led init
+#ifdef LED_PIN
   gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
   board_led_write(false);
+#endif
 
   // Button init
+#ifdef BUTTON_PIN
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
   gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
+#endif
+
+  uart_init();
 
 #if CFG_TUSB_OS  == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -119,12 +132,94 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
+  (void)state;
+#ifdef LED_PIN
   gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+#endif
 }
 
 uint32_t board_button_read(void)
 {
+#ifdef BUTTON_PIN
   return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
+#else
+  return 0;
+#endif
+}
+
+#if defined(UART_SERCOM)
+
+#define BOARD_SERCOM2(n)  SERCOM ## n
+#define BOARD_SERCOM(n) BOARD_SERCOM2(n)
+
+void uart_init(void)
+{
+#if UART_SERCOM == 0
+  gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2);
+  gpio_set_pin_function(PIN_PA07, PINMUX_PA07D_SERCOM0_PAD3);
+
+  // setup clock (48MHz)
+  _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
+  _gclk_enable_channel(SERCOM0_GCLK_ID_CORE, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+  SERCOM0->USART.CTRLA.bit.SWRST = 1; /* reset SERCOM & enable config */
+  while(SERCOM0->USART.SYNCBUSY.bit.SWRST);
+
+  SERCOM0->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+    SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+    SERCOM_USART_CTRLA_DORD | /* LSB first */
+    SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+    SERCOM_USART_CTRLA_RXPO(3) | /* pad 3 */
+    SERCOM_USART_CTRLA_TXPO(1);  /* pad 2 */
+
+  SERCOM0->USART.CTRLB.reg =
+    SERCOM_USART_CTRLB_TXEN | /* tx enabled */
+    SERCOM_USART_CTRLB_RXEN;  /* rx enabled */
+
+  SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26);
+
+  SERCOM0->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+  while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#endif
+}
+
+static inline void uart_send_buffer(uint8_t const *text, size_t len)
+{
+  for (size_t i = 0; i < len; ++i) {
+    BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = text[i];
+    while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+static inline void uart_send_str(const char* text)
+{
+  while (*text) {
+    BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = *text++;
+    while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  if (len < 0) {
+    uart_send_str(buf);
+  } else {
+    uart_send_buffer(buf, len);
+  }
+  return len;
+}
+
+#else // ! defined(UART_SERCOM)
+void uart_init(void)
+{
+
 }
 
 int board_uart_read(uint8_t* buf, int len)
@@ -138,6 +233,7 @@ int board_uart_write(void const * buf, int len)
   (void) buf; (void) len;
   return 0;
 }
+#endif
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index f1b063f2c..208f23789 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -12,6 +12,9 @@ CFLAGS += \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index 9bb5f815e..ab10ae4f8 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -35,8 +35,8 @@
 #define LED_PIN               16
 #define LED_STATE_ON          1
 
-// Button
-#define BUTTON_PIN            (32+14) // D5
+// Button: D5
+#define BUTTON_PIN            (32+14)
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index f4e260fb1..783bed82a 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -13,7 +13,8 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
-CFLAGS += -Wno-error=undef
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 16ac786d5..2d0d928ff 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -15,6 +15,8 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
   -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
 
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
new file mode 100644
index 000000000..ba7088e44
--- /dev/null
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -0,0 +1,56 @@
+DEPS_SUBMODULES += hw/mcu/microchip
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -D__SAME70N19B__ \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
+
+# suppress following warnings from mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+
+ASF_DIR = hw/mcu/microchip/same70
+
+# All source paths should be relative to the top level.
+LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
+
+SRC_C += \
+	src/portable/microchip/samx7x/dcd_samx7x.c \
+	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
+	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
+	$(ASF_DIR)/hpl/core/hpl_init.c \
+	$(ASF_DIR)/hpl/usart/hpl_usart.c \
+	$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
+	$(ASF_DIR)/hal/src/hal_usart_async.c \
+	$(ASF_DIR)/hal/src/hal_io.c \
+	$(ASF_DIR)/hal/src/hal_atomic.c \
+	$(ASF_DIR)/hal/utils/src/utils_ringbuffer.c
+
+INC += \
+  $(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(ASF_DIR) \
+	$(TOP)/$(ASF_DIR)/config \
+	$(TOP)/$(ASF_DIR)/same70b/include \
+	$(TOP)/$(ASF_DIR)/hal/include \
+	$(TOP)/$(ASF_DIR)/hal/utils/include \
+	$(TOP)/$(ASF_DIR)/hpl/core \
+	$(TOP)/$(ASF_DIR)/hpl/pio \
+	$(TOP)/$(ASF_DIR)/hpl/pmc \
+	$(TOP)/$(ASF_DIR)/hri \
+	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM7
+
+# For flash-jlink target
+JLINK_DEVICE = SAME70N19B
+
+# flash using edbg from https://github.com/ataradov/edbg
+# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
+# 	edbg -t same70 -F w0,1,1
+flash: $(BUILD)/$(PROJECT).bin
+	edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/same70_qmtech/hpl_pmc_config.h b/hw/bsp/same70_qmtech/hpl_pmc_config.h
new file mode 100644
index 000000000..387aaa5df
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_pmc_config.h
@@ -0,0 +1,1053 @@
+/* Auto-generated config file hpl_pmc_config.h */
+#ifndef HPL_PMC_CONFIG_H
+#define HPL_PMC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#define CLK_SRC_OPTION_OSC32K 0
+#define CLK_SRC_OPTION_XOSC32K 1
+#define CLK_SRC_OPTION_OSC12M 2
+#define CLK_SRC_OPTION_XOSC20M 3
+
+#define CLK_SRC_OPTION_SLCK 0
+#define CLK_SRC_OPTION_MAINCK 1
+#define CLK_SRC_OPTION_PLLACK 2
+#define CLK_SRC_OPTION_UPLLCKDIV 3
+#define CLK_SRC_OPTION_MCK 4
+
+#define CLK_SRC_OPTION_UPLLCK 3
+
+#define CONF_RC_4M 0
+#define CONF_RC_8M 1
+#define CONF_RC_12M 2
+
+#define CONF_XOSC32K_NO_BYPASS 0
+#define CONF_XOSC32K_BYPASS 1
+
+#define CONF_XOSC20M_NO_BYPASS 0
+#define CONF_XOSC20M_BYPASS 1
+
+// <e> Clock_SLCK configuration
+// <i> Indicates whether SLCK configuration is enabled or not
+// <id> enable_clk_gen_slck
+#ifndef CONF_CLK_SLCK_CONFIG
+#define CONF_CLK_SLCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SLCK source
+
+// <CLK_SRC_OPTION_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
+
+// <CLK_SRC_OPTION_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+
+// <i> This defines the clock source for SLCK
+// <id> clk_gen_slck_oscillator
+#ifndef CONF_CLK_GEN_SLCK_SRC
+#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K
+#endif
+
+// <q> Enable Clock_SLCK
+// <i> Indicates whether SLCK is enabled or disable
+// <id> clk_gen_slck_arch_enable
+#ifndef CONF_CLK_SLCK_ENABLE
+#define CONF_CLK_SLCK_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_MAINCK configuration
+// <i> Indicates whether MAINCK configuration is enabled or not
+// <id> enable_clk_gen_mainck
+#ifndef CONF_CLK_MAINCK_CONFIG
+#define CONF_CLK_MAINCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MAINCK source
+
+// <CLK_SRC_OPTION_OSC12M"> Embedded 4/8/12MHz RC Oscillator (OSC12M)
+
+// <CLK_SRC_OPTION_XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
+
+// <i> This defines the clock source for MAINCK
+// <id> clk_gen_mainck_oscillator
+#ifndef CONF_CLK_GEN_MAINCK_SRC
+#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M
+#endif
+
+// <q> Enable Clock_MAINCK
+// <i> Indicates whether MAINCK is enabled or disable
+// <id> clk_gen_mainck_arch_enable
+#ifndef CONF_CLK_MAINCK_ENABLE
+#define CONF_CLK_MAINCK_ENABLE 1
+#endif
+
+// <q> Enable Main Clock Failure Detection
+// <i> Indicates whether Main Clock Failure Detection is enabled or disable.
+// <i> The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK.
+// <id> clk_gen_cfden_enable
+#ifndef CONF_CLK_CFDEN_ENABLE
+#define CONF_CLK_CFDEN_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_MCKR configuration
+// <i> Indicates whether MCKR configuration is enabled or not
+// <id> enable_clk_gen_mckr
+#ifndef CONF_CLK_MCKR_CONFIG
+#define CONF_CLK_MCKR_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MCKR source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <i> This defines the clock source for MCKR
+// <id> clk_gen_mckr_oscillator
+#ifndef CONF_CLK_GEN_MCKR_SRC
+#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK
+#endif
+
+// <q> Enable Clock_MCKR
+// <i> Indicates whether MCKR is enabled or disable
+// <id> clk_gen_mckr_arch_enable
+#ifndef CONF_CLK_MCKR_ENABLE
+#define CONF_CLK_MCKR_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Master Clock Prescaler
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <4=> 16
+// <5=> 32
+// <6=> 64
+// <7=> 3
+// <i> Select the clock prescaler.
+// <id> mckr_presc
+#ifndef CONF_MCKR_PRESC
+#define CONF_MCKR_PRESC 0
+#endif
+
+// </h>
+// </e>// <e> Clock_MCK configuration
+// <i> Indicates whether MCK configuration is enabled or not
+// <id> enable_clk_gen_mck
+#ifndef CONF_CLK_MCK_CONFIG
+#define CONF_CLK_MCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MCK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for MCK
+// <id> clk_gen_mck_oscillator
+#ifndef CONF_CLK_GEN_MCK_SRC
+#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+//<o> Master Clock Controller Divider MCK divider
+// <0=> 1
+// <1=> 2
+// <3=> 3
+// <2=> 4
+// <i> Select the master clock divider.
+// <id> mck_div
+#ifndef CONF_MCK_DIV
+#define CONF_MCK_DIV 1
+#endif
+
+// </h>
+// </e>// <e> Clock_SYSTICK configuration
+// <i> Indicates whether SYSTICK configuration is enabled or not
+// <id> enable_clk_gen_systick
+#ifndef CONF_CLK_SYSTICK_CONFIG
+#define CONF_CLK_SYSTICK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SYSTICK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for SYSTICK
+// <id> clk_gen_systick_oscillator
+#ifndef CONF_CLK_GEN_SYSTICK_SRC
+#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Systick clock divider
+// <8=> 8
+// <i> Select systick clock divider
+// <id> systick_clock_div
+#ifndef CONF_SYSTICK_DIV
+#define CONF_SYSTICK_DIV 8
+#endif
+
+// </h>
+// </e>// <e> Clock_FCLK configuration
+// <i> Indicates whether FCLK configuration is enabled or not
+// <id> enable_clk_gen_fclk
+#ifndef CONF_CLK_FCLK_CONFIG
+#define CONF_CLK_FCLK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator FCLK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for FCLK
+// <id> clk_gen_fclk_oscillator
+#ifndef CONF_CLK_GEN_FCLK_SRC
+#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_GCLK0 configuration
+// <i> Indicates whether GCLK0 configuration is enabled or not
+// <id> enable_clk_gen_gclk0
+#ifndef CONF_CLK_GCLK0_CONFIG
+#define CONF_CLK_GCLK0_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator GCLK0 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for GCLK0
+// <id> clk_gen_gclk0_oscillator
+#ifndef CONF_CLK_GEN_GCLK0_SRC
+#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK
+#endif
+
+// <q> Enable Clock_GCLK0
+// <i> Indicates whether GCLK0 is enabled or disable
+// <id> clk_gen_gclk0_arch_enable
+#ifndef CONF_CLK_GCLK0_ENABLE
+#define CONF_CLK_GCLK0_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+// <q> Enable GCLK0 GCLKEN
+// <i> Indicates whether GCLK0 GCLKEN is enabled or disable
+// <id> gclk0_gclken_enable
+#ifndef CONF_GCLK0_GCLKEN_ENABLE
+#define CONF_GCLK0_GCLKEN_ENABLE 0
+#endif
+
+// <o> Generic Clock GCLK0 divider <1-256>
+// <i> Select the clock divider (divider = GCLKDIV + 1).
+// <id> gclk0_div
+#ifndef CONF_GCLK0_DIV
+#define CONF_GCLK0_DIV 2
+#endif
+
+// </h>
+// </e>// <e> Clock_GCLK1 configuration
+// <i> Indicates whether GCLK1 configuration is enabled or not
+// <id> enable_clk_gen_gclk1
+#ifndef CONF_CLK_GCLK1_CONFIG
+#define CONF_CLK_GCLK1_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator GCLK1 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for GCLK1
+// <id> clk_gen_gclk1_oscillator
+#ifndef CONF_CLK_GEN_GCLK1_SRC
+#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK
+#endif
+
+// <q> Enable Clock_GCLK1
+// <i> Indicates whether GCLK1 is enabled or disable
+// <id> clk_gen_gclk1_arch_enable
+#ifndef CONF_CLK_GCLK1_ENABLE
+#define CONF_CLK_GCLK1_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+// <q> Enable GCLK1 GCLKEN
+// <i> Indicates whether GCLK1 GCLKEN is enabled or disable
+// <id> gclk1_gclken_enable
+#ifndef CONF_GCLK1_GCLKEN_ENABLE
+#define CONF_GCLK1_GCLKEN_ENABLE 0
+#endif
+
+// <o> Generic Clock GCLK1 divider <1-256>
+// <i> Select the clock divider (divider = GCLKDIV + 1).
+// <id> gclk1_div
+#ifndef CONF_GCLK1_DIV
+#define CONF_GCLK1_DIV 3
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK0 configuration
+// <i> Indicates whether PCK0 configuration is enabled or not
+// <id> enable_clk_gen_pck0
+#ifndef CONF_CLK_PCK0_CONFIG
+#define CONF_CLK_PCK0_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK0 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK0
+// <id> clk_gen_pck0_oscillator
+#ifndef CONF_CLK_GEN_PCK0_SRC
+#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK0
+// <i> Indicates whether PCK0 is enabled or disable
+// <id> clk_gen_pck0_arch_enable
+#ifndef CONF_CLK_PCK0_ENABLE
+#define CONF_CLK_PCK0_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck0_presc
+#ifndef CONF_PCK0_PRESC
+#define CONF_PCK0_PRESC 1
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK1 configuration
+// <i> Indicates whether PCK1 configuration is enabled or not
+// <id> enable_clk_gen_pck1
+#ifndef CONF_CLK_PCK1_CONFIG
+#define CONF_CLK_PCK1_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK1 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK1
+// <id> clk_gen_pck1_oscillator
+#ifndef CONF_CLK_GEN_PCK1_SRC
+#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK1
+// <i> Indicates whether PCK1 is enabled or disable
+// <id> clk_gen_pck1_arch_enable
+#ifndef CONF_CLK_PCK1_ENABLE
+#define CONF_CLK_PCK1_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck1_presc
+#ifndef CONF_PCK1_PRESC
+#define CONF_PCK1_PRESC 2
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK2 configuration
+// <i> Indicates whether PCK2 configuration is enabled or not
+// <id> enable_clk_gen_pck2
+#ifndef CONF_CLK_PCK2_CONFIG
+#define CONF_CLK_PCK2_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK2 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK2
+// <id> clk_gen_pck2_oscillator
+#ifndef CONF_CLK_GEN_PCK2_SRC
+#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK2
+// <i> Indicates whether PCK2 is enabled or disable
+// <id> clk_gen_pck2_arch_enable
+#ifndef CONF_CLK_PCK2_ENABLE
+#define CONF_CLK_PCK2_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck2_presc
+#ifndef CONF_PCK2_PRESC
+#define CONF_PCK2_PRESC 3
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK3 configuration
+// <i> Indicates whether PCK3 configuration is enabled or not
+// <id> enable_clk_gen_pck3
+#ifndef CONF_CLK_PCK3_CONFIG
+#define CONF_CLK_PCK3_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK3 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK3
+// <id> clk_gen_pck3_oscillator
+#ifndef CONF_CLK_GEN_PCK3_SRC
+#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK3
+// <i> Indicates whether PCK3 is enabled or disable
+// <id> clk_gen_pck3_arch_enable
+#ifndef CONF_CLK_PCK3_ENABLE
+#define CONF_CLK_PCK3_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck3_presc
+#ifndef CONF_PCK3_PRESC
+#define CONF_PCK3_PRESC 4
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK4 configuration
+// <i> Indicates whether PCK4 configuration is enabled or not
+// <id> enable_clk_gen_pck4
+#ifndef CONF_CLK_PCK4_CONFIG
+#define CONF_CLK_PCK4_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK4 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK4
+// <id> clk_gen_pck4_oscillator
+#ifndef CONF_CLK_GEN_PCK4_SRC
+#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK4
+// <i> Indicates whether PCK4 is enabled or disable
+// <id> clk_gen_pck4_arch_enable
+#ifndef CONF_CLK_PCK4_ENABLE
+#define CONF_CLK_PCK4_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck4_presc
+#ifndef CONF_PCK4_PRESC
+#define CONF_PCK4_PRESC 5
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK5 configuration
+// <i> Indicates whether PCK5 configuration is enabled or not
+// <id> enable_clk_gen_pck5
+#ifndef CONF_CLK_PCK5_CONFIG
+#define CONF_CLK_PCK5_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK5 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK5
+// <id> clk_gen_pck5_oscillator
+#ifndef CONF_CLK_GEN_PCK5_SRC
+#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK5
+// <i> Indicates whether PCK5 is enabled or disable
+// <id> clk_gen_pck5_arch_enable
+#ifndef CONF_CLK_PCK5_ENABLE
+#define CONF_CLK_PCK5_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck5_presc
+#ifndef CONF_PCK5_PRESC
+#define CONF_PCK5_PRESC 6
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK6 configuration
+// <i> Indicates whether PCK6 configuration is enabled or not
+// <id> enable_clk_gen_pck6
+#ifndef CONF_CLK_PCK6_CONFIG
+#define CONF_CLK_PCK6_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK6 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK6
+// <id> clk_gen_pck6_oscillator
+#ifndef CONF_CLK_GEN_PCK6_SRC
+#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK6
+// <i> Indicates whether PCK6 is enabled or disable
+// <id> clk_gen_pck6_arch_enable
+#ifndef CONF_CLK_PCK6_ENABLE
+#define CONF_CLK_PCK6_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck6_presc
+#ifndef CONF_PCK6_PRESC
+#define CONF_PCK6_PRESC 7
+#endif
+
+// </h>
+// </e>// <e> Clock_USB_480M configuration
+// <i> Indicates whether USB_480M configuration is enabled or not
+// <id> enable_clk_gen_usb_480m
+#ifndef CONF_CLK_USB_480M_CONFIG
+#define CONF_CLK_USB_480M_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator USB_480M source
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <i> This defines the clock source for USB_480M
+// <id> clk_gen_usb_480m_oscillator
+#ifndef CONF_CLK_GEN_USB_480M_SRC
+#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_USB_48M configuration
+// <i> Indicates whether USB_48M configuration is enabled or not
+// <id> enable_clk_gen_usb_48m
+#ifndef CONF_CLK_USB_48M_CONFIG
+#define CONF_CLK_USB_48M_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator USB_48M source
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <i> This defines the clock source for USB_48M
+// <id> clk_gen_usb_48m_oscillator
+#ifndef CONF_CLK_GEN_USB_48M_SRC
+#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_UPLLCKDIV
+#endif
+
+// <q> Enable Clock_USB_48M
+// <i> Indicates whether USB_48M is enabled or disable
+// <id> clk_gen_usb_48m_arch_enable
+#ifndef CONF_CLK_USB_48M_ENABLE
+#define CONF_CLK_USB_48M_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// <o> USB Clock Controller Divider <1-16>
+// <i> Select the USB clock divider (divider = USBDIV + 1).
+// <id> usb_48m_div
+#ifndef CONF_USB_48M_DIV
+#define CONF_USB_48M_DIV 5
+#endif
+
+// </h>
+// </e>// <e> Clock_SLCK2 configuration
+// <i> Indicates whether SLCK2 configuration is enabled or not
+// <id> enable_clk_gen_slck2
+#ifndef CONF_CLK_SLCK2_CONFIG
+#define CONF_CLK_SLCK2_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SLCK2 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <i> This defines the clock source for SLCK2
+// <id> clk_gen_slck2_oscillator
+#ifndef CONF_CLK_GEN_SLCK2_SRC
+#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_hclk_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Processor Clock Settings
+// <y> Processor Clock source
+// <MCKR"> Master Clock Controller (PMC_MCKR)
+// <i> This defines the clock source for the HCLK (Processor clock)
+// <id> hclk_clock_source
+#ifndef CONF_HCLK_SRC
+#define CONF_HCLK_SRC MCKR
+#endif
+
+// <o> Flash Wait State
+// <0=> 1 cycle
+// <1=> 2 cycles
+// <2=> 3 cycles
+// <3=> 4 cycles
+// <4=> 5 cycles
+// <5=> 6 cycles
+// <6=> 7 cycles
+// <i> This field defines the number of wait states for read and write operations.
+// <id> efc_fws
+#ifndef CONF_EFC_WAIT_STATE
+#define CONF_EFC_WAIT_STATE 5
+#endif
+
+// </h>
+// </e>
+
+// <e> SysTick Clock
+// <id> enable_systick_clk_clock
+#ifndef CONF_SYSTICK_CLK_CONFIG
+#define CONF_SYSTICK_CLK_CONFIG 1
+#endif
+
+// <y> SysTick Clock source
+// <MCKR"> Master Clock Controller (PMC_MCKR)
+// <i> This defines the clock source for the SysTick Clock
+// <id> systick_clk_clock_source
+#ifndef CONF_SYSTICK_CLK_SRC
+#define CONF_SYSTICK_CLK_SRC MCKR
+#endif
+
+// <o> SysTick Clock Divider
+// <8=> 8
+// <i> Fixed to 8 if Systick is not using Processor clock
+// <id> systick_clk_clock_div
+#ifndef CONF_SYSTICK_CLK_DIV
+#define CONF_SYSTICK_CLK_DIV 8
+#endif
+
+// </e>
+
+// <e> OSC32K Oscillator Configuration
+// <i> Indicates whether configuration for OSC32K is enabled or not
+// <id> enable_osc32k
+#ifndef CONF_OSC32K_CONFIG
+#define CONF_OSC32K_CONFIG 1
+#endif
+
+// <h> OSC32K Oscillator Control
+// <q> OSC32K Oscillator Enable
+// <i> Indicates whether OSC32K Oscillator is enabled or not
+// <id> osc32k_arch_enable
+#ifndef CONF_OSC32K_ENABLE
+#define CONF_OSC32K_ENABLE 0
+#endif
+// </h>
+// </e>
+
+// <e> XOSC32K Oscillator Configuration
+// <i> Indicates whether configuration for XOSC32K is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 0
+#endif
+
+// <h> XOSC32K Oscillator Control
+// <y> Oscillator Bypass Select
+// <CONF_XOSC32K_NO_BYPASS"> The 32kHz crystal oscillator is not bypassed.
+// <CONF_XOSC32K_BYPASS"> The 32kHz crystal oscillator is bypassed.
+// <i> Indicates whether XOSC32K is bypassed.
+// <id> xosc32k_bypass
+#ifndef CONF_XOSC32K
+#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS
+#endif
+
+// <q> XOSC32K Oscillator Enable
+// <i> Indicates whether XOSC32K Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 0
+#endif
+// </h>
+// </e>
+
+// <e> OSC12M Oscillator Configuration
+// <i> Indicates whether configuration for OSC12M is enabled or not
+// <id> enable_osc12m
+#ifndef CONF_OSC12M_CONFIG
+#define CONF_OSC12M_CONFIG 0
+#endif
+
+// <h> OSC12M Oscillator Control
+// <q> OSC12M Oscillator Enable
+// <i> Indicates whether OSC12M Oscillator is enabled or not.
+// <id> osc12m_arch_enable
+#ifndef CONF_OSC12M_ENABLE
+#define CONF_OSC12M_ENABLE 0
+#endif
+
+// <o> OSC12M selector
+//  <0=> 4000000
+//  <1=> 8000000
+//  <2=> 12000000
+// <i> Select the frequency of embedded fast RC oscillator.
+// <id> osc12m_selector
+#ifndef CONF_OSC12M_SELECTOR
+#define CONF_OSC12M_SELECTOR 2
+#endif
+// </h>
+// </e>
+
+// <e> XOSC20M Oscillator Configuration
+// <i> Indicates whether configuration for XOSC20M is enabled or not.
+// <id> enable_xosc20m
+#ifndef CONF_XOSC20M_CONFIG
+#define CONF_XOSC20M_CONFIG 1
+#endif
+
+// <h> XOSC20M Oscillator Control
+// <o> XOSC20M selector <3000000-20000000>
+// <i> Select the frequency of crystal or ceramic resonator oscillator.
+// <id> xosc20m_selector
+#ifndef CONF_XOSC20M_SELECTOR
+#define CONF_XOSC20M_SELECTOR 12000000
+#endif
+
+// <o> Start up time for the external oscillator (ms): <0-256>
+// <i> Select start-up time.
+// <id> xosc20m_startup_time
+#ifndef CONF_XOSC20M_STARTUP_TIME
+#define CONF_XOSC20M_STARTUP_TIME 62
+#endif
+
+// <y> Oscillator Bypass Select
+// <CONF_XOSC20M_NO_BYPASS"> The external crystal oscillator is not bypassed.
+// <CONF_XOSC20M_BYPASS"> The external crystal oscillator is bypassed.
+// <i> Indicates whether XOSC20M is bypassed.
+// <id> xosc20m_bypass
+#ifndef CONF_XOSC20M
+#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS
+#endif
+
+// <q> XOSC20M Oscillator Enable
+// <i> Indicates whether XOSC20M Oscillator is enabled or not
+// <id> xosc20m_arch_enable
+#ifndef CONF_XOSC20M_ENABLE
+#define CONF_XOSC20M_ENABLE 1
+#endif
+// </h>
+// </e>
+
+// <e> PLLACK Oscillator Configuration
+// <i> Indicates whether configuration for PLLACK is enabled or not
+// <id> enable_pllack
+#ifndef CONF_PLLACK_CONFIG
+#define CONF_PLLACK_CONFIG 1
+#endif
+
+// <y> PLLACK Reference Clock Source
+// <MAINCK"> Main Clock (MAINCK)
+// <i> Select the clock source.
+// <id> pllack_ref_clock
+#ifndef CONF_PLLACK_CLK
+#define CONF_PLLACK_CLK MAINCK
+#endif
+
+// <h> PLLACK Oscillator Control
+// <q> PLLACK Oscillator Enable
+// <i> Indicates whether PLLACK Oscillator is enabled or not
+// <id> pllack_arch_enable
+#ifndef CONF_PLLACK_ENABLE
+#define CONF_PLLACK_ENABLE 1
+#endif
+
+// <o> PLLA Frontend Divider (DIVA)  <1-255>
+// <i> Select the clock divider
+// <id> pllack_div
+#ifndef CONF_PLLACK_DIV
+#define CONF_PLLACK_DIV 1
+#endif
+
+// <o> PLLACK Muliplier <1-62>
+// <i> Indicates PLLA multiplier (multiplier = MULA + 1).
+// <id> pllack_mul
+#ifndef CONF_PLLACK_MUL
+#define CONF_PLLACK_MUL 25
+#endif
+// </h>
+// </e>
+
+// <e> UPLLCK Oscillator Configuration
+// <i> Indicates whether configuration for UPLLCK is enabled or not
+// <id> enable_upllck
+#ifndef CONF_UPLLCK_CONFIG
+#define CONF_UPLLCK_CONFIG 1
+#endif
+
+// <y> UPLLCK Reference Clock Source
+// <XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
+// <i> Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M.
+// <id> upllck_ref_clock
+#ifndef CONF_UPLLCK_CLK
+#define CONF_UPLLCK_CLK XOSC20M
+#endif
+
+// <h> UPLLCK Oscillator Control
+// <q> UPLLCK Oscillator Enable
+// <i> Indicates whether UPLLCK Oscillator is enabled or not
+// <id> upllck_arch_enable
+#ifndef CONF_UPLLCK_ENABLE
+#define CONF_UPLLCK_ENABLE 1
+#endif
+// </h>
+// </e>
+
+// <e> UPLLCKDIV Oscillator Configuration
+// <i> Indicates whether configuration for UPLLCKDIV is enabled or not
+// <id> enable_upllckdiv
+#ifndef CONF_UPLLCKDIV_CONFIG
+#define CONF_UPLLCKDIV_CONFIG 1
+#endif
+
+// <y> UPLLCKDIV Reference Clock Source
+// <UPLLCK"> USB 480M Clock (UPLLCK)
+// <i> Select the clock source.
+// <id> upllckdiv_ref_clock
+#ifndef CONF_UPLLCKDIV_CLK
+#define CONF_UPLLCKDIV_CLK UPLLCK
+#endif
+
+// <h> UPLLCKDIV Oscillator Control
+// <o> UPLLCKDIV Clock Divider
+// <0=> 1
+// <1=> 2
+// <i> Select the clock divider.
+// <id> upllckdiv_div
+#ifndef CONF_UPLLCKDIV_DIV
+#define CONF_UPLLCKDIV_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> MCK/8
+// <id> enable_mck_div_8
+#ifndef CONF_MCK_DIV_8_CONFIG
+#define CONF_MCK_DIV_8_CONFIG 0
+#endif
+
+// <o> MCK/8 Source
+// <0=> Master Clock (MCK)
+// <id> mck_div_8_src
+#ifndef CONF_MCK_DIV_8_SRC
+#define CONF_MCK_DIV_8_SRC 0
+#endif
+// </e>
+
+// <e> External Clock Input Configuration
+// <id> enable_dummy_ext
+#ifndef CONF_DUMMY_EXT_CONFIG
+#define CONF_DUMMY_EXT_CONFIG 1
+#endif
+
+// <o> External Clock Input Source
+// <i> All here are dummy values
+// <i> Refer to the peripherals settings for actual input information
+// <0=> Specific clock input from specific pin
+// <id> dummy_ext_src
+#ifndef CONF_DUMMY_EXT_SRC
+#define CONF_DUMMY_EXT_SRC 0
+#endif
+// </e>
+
+// <e> External Clock Configuration
+// <id> enable_dummy_ext_clk
+#ifndef CONF_DUMMY_EXT_CLK_CONFIG
+#define CONF_DUMMY_EXT_CLK_CONFIG 1
+#endif
+
+// <o> External Clock Source
+// <i> All here are dummy values
+// <i> Refer to the peripherals settings for actual input information
+// <0=> External Clock Input
+// <id> dummy_ext_clk_src
+#ifndef CONF_DUMMY_EXT_CLK_SRC
+#define CONF_DUMMY_EXT_CLK_SRC 0
+#endif
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PMC_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/hpl_usart_config.h b/hw/bsp/same70_qmtech/hpl_usart_config.h
new file mode 100644
index 000000000..50ca3f15c
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_usart_config.h
@@ -0,0 +1,215 @@
+/* Auto-generated config file hpl_usart_config.h */
+#ifndef HPL_USART_CONFIG_H
+#define HPL_USART_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_USART_1_ENABLE
+#define CONF_USART_1_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Frame parity
+// <0x0=>Even parity
+// <0x1=>Odd parity
+// <0x2=>Parity forced to 0
+// <0x3=>Parity forced to 1
+// <0x4=>No parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_USART_1_PARITY
+#define CONF_USART_1_PARITY 0x4
+#endif
+
+// <o> Character Size
+// <0x0=>5 bits
+// <0x1=>6 bits
+// <0x2=>7 bits
+// <0x3=>8 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_USART_1_CHSIZE
+#define CONF_USART_1_CHSIZE 0x3
+#endif
+
+// <o> Stop Bit
+// <0=>1 stop bit
+// <1=>1.5 stop bits
+// <2=>2 stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_USART_1_SBMODE
+#define CONF_USART_1_SBMODE 0
+#endif
+
+// <o> Clock Output Select
+// <0=>The USART does not drive the SCK pin
+// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
+// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
+// <id> usart_clock_output_select
+#ifndef CONF_USART_1_CLKO
+#define CONF_USART_1_CLKO 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_USART_1_BAUD
+#define CONF_USART_1_BAUD 9600
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_USART_1_ADVANCED_CONFIG
+#define CONF_USART_1_ADVANCED_CONFIG 0
+#endif
+
+// <o> Channel Mode
+// <0=>Normal Mode
+// <1=>Automatic Echo
+// <2=>Local Loopback
+// <3=>Remote Loopback
+// <i> Channel mode in USART frame
+// <id> usart_channel_mode
+#ifndef CONF_USART_1_CHMODE
+#define CONF_USART_1_CHMODE 0
+#endif
+
+// <q> 9 bits character enable
+// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
+// <id> usart_9bits_enable
+#ifndef CONF_USART_1_MODE9
+#define CONF_USART_1_MODE9 0
+#endif
+
+// <o> Variable Sync
+// <0=>User defined configuration
+// <1=>sync field is updated when a character is written into US_THR
+// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
+// <id> variable_sync
+#ifndef CONF_USART_1_VAR_SYNC
+#define CONF_USART_1_VAR_SYNC 0
+#endif
+
+// <o> Oversampling Mode
+// <0=>16 Oversampling
+// <1=>8 Oversampling
+// <i> Oversampling Mode in UART mode
+// <id> usart__oversampling_mode
+#ifndef CONF_USART_1_OVER
+#define CONF_USART_1_OVER 0
+#endif
+
+// <o> Inhibit Non Ack
+// <0=>The NACK is generated
+// <1=>The NACK is not generated
+// <i> Inhibit Non Acknowledge
+// <id> usart__inack
+#ifndef CONF_USART_1_INACK
+#define CONF_USART_1_INACK 1
+#endif
+
+// <o> Disable Successive NACK
+// <0=>NACK is sent on the ISO line as soon as a parity error occurs
+// <1=>Many parity errors generate a NACK on the ISO line
+// <i> Disable Successive NACK
+// <id> usart_dsnack
+#ifndef CONF_USART_1_DSNACK
+#define CONF_USART_1_DSNACK 0
+#endif
+
+// <o> Inverted Data
+// <0=>Data isn't inverted, nomal mode
+// <1=>Data is inverted
+// <i> Inverted Data
+// <id> usart_invdata
+#ifndef CONF_USART_1_INVDATA
+#define CONF_USART_1_INVDATA 0
+#endif
+
+// <o> Maximum Number of Automatic Iteration <0-7>
+// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
+// <id> usart_max_iteration
+#ifndef CONF_USART_1_MAX_ITERATION
+#define CONF_USART_1_MAX_ITERATION 0
+#endif
+
+// <q> Receive Line Filter enable
+// <i> whether the USART filters the receive line using a three-sample filter
+// <id> usart_receive_filter_enable
+#ifndef CONF_USART_1_FILTER
+#define CONF_USART_1_FILTER 0
+#endif
+
+// <q> Manchester Encoder/Decoder Enable
+// <i> whether the USART Manchester Encoder/Decoder
+// <id> usart_manchester_filter_enable
+#ifndef CONF_USART_1_MAN
+#define CONF_USART_1_MAN 0
+#endif
+
+// <o> Manchester Synchronization Mode
+// <0=>The Manchester start bit is a 0 to 1 transition
+// <1=>The Manchester start bit is a 1 to 0 transition
+// <i> Manchester Synchronization Mode
+// <id> usart_manchester_synchronization_mode
+#ifndef CONF_USART_1_MODSYNC
+#define CONF_USART_1_MODSYNC 0
+#endif
+
+// <o> Start Frame Delimiter Selector
+// <0=>Start frame delimiter is COMMAND or DATA SYNC
+// <1=>Start frame delimiter is one bit
+// <i> Start Frame Delimiter Selector
+// <id> usart_start_frame_delimiter
+#ifndef CONF_USART_1_ONEBIT
+#define CONF_USART_1_ONEBIT 0
+#endif
+
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_USART_1_FRACTIONAL
+#define CONF_USART_1_FRACTIONAL 0x0
+#endif
+
+// <o> Data Order
+// <0=>LSB is transmitted first
+// <1=>MSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_msbf
+#ifndef CONF_USART_1_MSBF
+#define CONF_USART_1_MSBF 0
+#endif
+
+// </e>
+
+#define CONF_USART_1_MODE 0x0
+
+// Calculate BAUD register value in UART mode
+#if CONF_USART1_CK_SRC < 3
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP                                                                                           \
+	((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
+#endif
+#elif CONF_USART1_CK_SRC == 3
+// No division is active. The value written in US_BRGR has no effect.
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD 1
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP 1
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_USART_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/hpl_xdmac_config.h b/hw/bsp/same70_qmtech/hpl_xdmac_config.h
new file mode 100644
index 000000000..a3d62c6fc
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_xdmac_config.h
@@ -0,0 +1,4400 @@
+/* Auto-generated config file hpl_xdmac_config.h */
+#ifndef HPL_XDMAC_CONFIG_H
+#define HPL_XDMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> XDMAC enable
+// <i> Indicates whether xdmac is enabled or not
+// <id> xdmac_enable
+#ifndef CONF_DMA_ENABLE
+#define CONF_DMA_ENABLE 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_0
+#ifndef CONF_DMAC_BURSTSIZE_0
+#define CONF_DMAC_BURSTSIZE_0 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_0
+#ifndef CONF_DMAC_CHUNKSIZE_0
+#define CONF_DMAC_CHUNKSIZE_0 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_0
+#ifndef CONF_DMAC_SRC_INTERFACE_0
+#define CONF_DMAC_SRC_INTERFACE_0 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_0
+#ifndef CONF_DMAC_DES_INTERFACE_0
+#define CONF_DMAC_DES_INTERFACE_0 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_0
+#ifndef CONF_DMAC_TRANS_TYPE_0
+#define CONF_DMAC_TRANS_TYPE_0 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_0 == 0
+#define CONF_DMAC_TYPE_0 0
+#define CONF_DMAC_DSYNC_0 0
+#elif CONF_DMAC_TRANS_TYPE_0 == 1
+#define CONF_DMAC_TYPE_0 1
+#define CONF_DMAC_DSYNC_0 0
+#elif CONF_DMAC_TRANS_TYPE_0 == 2
+#define CONF_DMAC_TYPE_0 1
+#define CONF_DMAC_DSYNC_0 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_0 == 0xFF
+#define CONF_DMAC_SWREQ_0 1
+#else
+#define CONF_DMAC_SWREQ_0 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0)))
+#if (!CONF_DMAC_SRCINC_0)
+#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_0)
+#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_0
+#define CONF_DMAC_SRC_STRIDE_0 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_0
+#define CONF_DMAC_DES_STRIDE_0 0
+#endif
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_1
+#ifndef CONF_DMAC_BURSTSIZE_1
+#define CONF_DMAC_BURSTSIZE_1 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_1
+#ifndef CONF_DMAC_CHUNKSIZE_1
+#define CONF_DMAC_CHUNKSIZE_1 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_1
+#ifndef CONF_DMAC_SRC_INTERFACE_1
+#define CONF_DMAC_SRC_INTERFACE_1 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_1
+#ifndef CONF_DMAC_DES_INTERFACE_1
+#define CONF_DMAC_DES_INTERFACE_1 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_1
+#ifndef CONF_DMAC_TRANS_TYPE_1
+#define CONF_DMAC_TRANS_TYPE_1 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_1 == 0
+#define CONF_DMAC_TYPE_1 0
+#define CONF_DMAC_DSYNC_1 0
+#elif CONF_DMAC_TRANS_TYPE_1 == 1
+#define CONF_DMAC_TYPE_1 1
+#define CONF_DMAC_DSYNC_1 0
+#elif CONF_DMAC_TRANS_TYPE_1 == 2
+#define CONF_DMAC_TYPE_1 1
+#define CONF_DMAC_DSYNC_1 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_1 == 0xFF
+#define CONF_DMAC_SWREQ_1 1
+#else
+#define CONF_DMAC_SWREQ_1 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1)))
+#if (!CONF_DMAC_SRCINC_1)
+#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_1)
+#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_1
+#define CONF_DMAC_SRC_STRIDE_1 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_1
+#define CONF_DMAC_DES_STRIDE_1 0
+#endif
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_2
+#ifndef CONF_DMAC_BURSTSIZE_2
+#define CONF_DMAC_BURSTSIZE_2 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_2
+#ifndef CONF_DMAC_CHUNKSIZE_2
+#define CONF_DMAC_CHUNKSIZE_2 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_2
+#ifndef CONF_DMAC_SRC_INTERFACE_2
+#define CONF_DMAC_SRC_INTERFACE_2 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_2
+#ifndef CONF_DMAC_DES_INTERFACE_2
+#define CONF_DMAC_DES_INTERFACE_2 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_2
+#ifndef CONF_DMAC_TRANS_TYPE_2
+#define CONF_DMAC_TRANS_TYPE_2 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_2 == 0
+#define CONF_DMAC_TYPE_2 0
+#define CONF_DMAC_DSYNC_2 0
+#elif CONF_DMAC_TRANS_TYPE_2 == 1
+#define CONF_DMAC_TYPE_2 1
+#define CONF_DMAC_DSYNC_2 0
+#elif CONF_DMAC_TRANS_TYPE_2 == 2
+#define CONF_DMAC_TYPE_2 1
+#define CONF_DMAC_DSYNC_2 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_2 == 0xFF
+#define CONF_DMAC_SWREQ_2 1
+#else
+#define CONF_DMAC_SWREQ_2 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2)))
+#if (!CONF_DMAC_SRCINC_2)
+#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_2)
+#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_2
+#define CONF_DMAC_SRC_STRIDE_2 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_2
+#define CONF_DMAC_DES_STRIDE_2 0
+#endif
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_3
+#ifndef CONF_DMAC_BURSTSIZE_3
+#define CONF_DMAC_BURSTSIZE_3 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_3
+#ifndef CONF_DMAC_CHUNKSIZE_3
+#define CONF_DMAC_CHUNKSIZE_3 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_3
+#ifndef CONF_DMAC_SRC_INTERFACE_3
+#define CONF_DMAC_SRC_INTERFACE_3 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_3
+#ifndef CONF_DMAC_DES_INTERFACE_3
+#define CONF_DMAC_DES_INTERFACE_3 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_3
+#ifndef CONF_DMAC_TRANS_TYPE_3
+#define CONF_DMAC_TRANS_TYPE_3 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_3 == 0
+#define CONF_DMAC_TYPE_3 0
+#define CONF_DMAC_DSYNC_3 0
+#elif CONF_DMAC_TRANS_TYPE_3 == 1
+#define CONF_DMAC_TYPE_3 1
+#define CONF_DMAC_DSYNC_3 0
+#elif CONF_DMAC_TRANS_TYPE_3 == 2
+#define CONF_DMAC_TYPE_3 1
+#define CONF_DMAC_DSYNC_3 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_3 == 0xFF
+#define CONF_DMAC_SWREQ_3 1
+#else
+#define CONF_DMAC_SWREQ_3 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3)))
+#if (!CONF_DMAC_SRCINC_3)
+#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_3)
+#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_3
+#define CONF_DMAC_SRC_STRIDE_3 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_3
+#define CONF_DMAC_DES_STRIDE_3 0
+#endif
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_4
+#ifndef CONF_DMAC_BURSTSIZE_4
+#define CONF_DMAC_BURSTSIZE_4 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_4
+#ifndef CONF_DMAC_CHUNKSIZE_4
+#define CONF_DMAC_CHUNKSIZE_4 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_4
+#ifndef CONF_DMAC_SRC_INTERFACE_4
+#define CONF_DMAC_SRC_INTERFACE_4 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_4
+#ifndef CONF_DMAC_DES_INTERFACE_4
+#define CONF_DMAC_DES_INTERFACE_4 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_4
+#ifndef CONF_DMAC_TRANS_TYPE_4
+#define CONF_DMAC_TRANS_TYPE_4 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_4 == 0
+#define CONF_DMAC_TYPE_4 0
+#define CONF_DMAC_DSYNC_4 0
+#elif CONF_DMAC_TRANS_TYPE_4 == 1
+#define CONF_DMAC_TYPE_4 1
+#define CONF_DMAC_DSYNC_4 0
+#elif CONF_DMAC_TRANS_TYPE_4 == 2
+#define CONF_DMAC_TYPE_4 1
+#define CONF_DMAC_DSYNC_4 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_4 == 0xFF
+#define CONF_DMAC_SWREQ_4 1
+#else
+#define CONF_DMAC_SWREQ_4 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4)))
+#if (!CONF_DMAC_SRCINC_4)
+#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_4)
+#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_4
+#define CONF_DMAC_SRC_STRIDE_4 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_4
+#define CONF_DMAC_DES_STRIDE_4 0
+#endif
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_5
+#ifndef CONF_DMAC_BURSTSIZE_5
+#define CONF_DMAC_BURSTSIZE_5 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_5
+#ifndef CONF_DMAC_CHUNKSIZE_5
+#define CONF_DMAC_CHUNKSIZE_5 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_5
+#ifndef CONF_DMAC_SRC_INTERFACE_5
+#define CONF_DMAC_SRC_INTERFACE_5 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_5
+#ifndef CONF_DMAC_DES_INTERFACE_5
+#define CONF_DMAC_DES_INTERFACE_5 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_5
+#ifndef CONF_DMAC_TRANS_TYPE_5
+#define CONF_DMAC_TRANS_TYPE_5 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_5 == 0
+#define CONF_DMAC_TYPE_5 0
+#define CONF_DMAC_DSYNC_5 0
+#elif CONF_DMAC_TRANS_TYPE_5 == 1
+#define CONF_DMAC_TYPE_5 1
+#define CONF_DMAC_DSYNC_5 0
+#elif CONF_DMAC_TRANS_TYPE_5 == 2
+#define CONF_DMAC_TYPE_5 1
+#define CONF_DMAC_DSYNC_5 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_5 == 0xFF
+#define CONF_DMAC_SWREQ_5 1
+#else
+#define CONF_DMAC_SWREQ_5 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5)))
+#if (!CONF_DMAC_SRCINC_5)
+#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_5)
+#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_5
+#define CONF_DMAC_SRC_STRIDE_5 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_5
+#define CONF_DMAC_DES_STRIDE_5 0
+#endif
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_6
+#ifndef CONF_DMAC_BURSTSIZE_6
+#define CONF_DMAC_BURSTSIZE_6 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_6
+#ifndef CONF_DMAC_CHUNKSIZE_6
+#define CONF_DMAC_CHUNKSIZE_6 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_6
+#ifndef CONF_DMAC_SRC_INTERFACE_6
+#define CONF_DMAC_SRC_INTERFACE_6 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_6
+#ifndef CONF_DMAC_DES_INTERFACE_6
+#define CONF_DMAC_DES_INTERFACE_6 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_6
+#ifndef CONF_DMAC_TRANS_TYPE_6
+#define CONF_DMAC_TRANS_TYPE_6 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_6 == 0
+#define CONF_DMAC_TYPE_6 0
+#define CONF_DMAC_DSYNC_6 0
+#elif CONF_DMAC_TRANS_TYPE_6 == 1
+#define CONF_DMAC_TYPE_6 1
+#define CONF_DMAC_DSYNC_6 0
+#elif CONF_DMAC_TRANS_TYPE_6 == 2
+#define CONF_DMAC_TYPE_6 1
+#define CONF_DMAC_DSYNC_6 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_6 == 0xFF
+#define CONF_DMAC_SWREQ_6 1
+#else
+#define CONF_DMAC_SWREQ_6 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6)))
+#if (!CONF_DMAC_SRCINC_6)
+#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_6)
+#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_6
+#define CONF_DMAC_SRC_STRIDE_6 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_6
+#define CONF_DMAC_DES_STRIDE_6 0
+#endif
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_7
+#ifndef CONF_DMAC_BURSTSIZE_7
+#define CONF_DMAC_BURSTSIZE_7 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_7
+#ifndef CONF_DMAC_CHUNKSIZE_7
+#define CONF_DMAC_CHUNKSIZE_7 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_7
+#ifndef CONF_DMAC_SRC_INTERFACE_7
+#define CONF_DMAC_SRC_INTERFACE_7 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_7
+#ifndef CONF_DMAC_DES_INTERFACE_7
+#define CONF_DMAC_DES_INTERFACE_7 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_7
+#ifndef CONF_DMAC_TRANS_TYPE_7
+#define CONF_DMAC_TRANS_TYPE_7 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_7 == 0
+#define CONF_DMAC_TYPE_7 0
+#define CONF_DMAC_DSYNC_7 0
+#elif CONF_DMAC_TRANS_TYPE_7 == 1
+#define CONF_DMAC_TYPE_7 1
+#define CONF_DMAC_DSYNC_7 0
+#elif CONF_DMAC_TRANS_TYPE_7 == 2
+#define CONF_DMAC_TYPE_7 1
+#define CONF_DMAC_DSYNC_7 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_7 == 0xFF
+#define CONF_DMAC_SWREQ_7 1
+#else
+#define CONF_DMAC_SWREQ_7 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7)))
+#if (!CONF_DMAC_SRCINC_7)
+#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_7)
+#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_7
+#define CONF_DMAC_SRC_STRIDE_7 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_7
+#define CONF_DMAC_DES_STRIDE_7 0
+#endif
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_8
+#ifndef CONF_DMAC_BURSTSIZE_8
+#define CONF_DMAC_BURSTSIZE_8 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_8
+#ifndef CONF_DMAC_CHUNKSIZE_8
+#define CONF_DMAC_CHUNKSIZE_8 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_8
+#ifndef CONF_DMAC_SRC_INTERFACE_8
+#define CONF_DMAC_SRC_INTERFACE_8 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_8
+#ifndef CONF_DMAC_DES_INTERFACE_8
+#define CONF_DMAC_DES_INTERFACE_8 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_8
+#ifndef CONF_DMAC_TRANS_TYPE_8
+#define CONF_DMAC_TRANS_TYPE_8 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_8 == 0
+#define CONF_DMAC_TYPE_8 0
+#define CONF_DMAC_DSYNC_8 0
+#elif CONF_DMAC_TRANS_TYPE_8 == 1
+#define CONF_DMAC_TYPE_8 1
+#define CONF_DMAC_DSYNC_8 0
+#elif CONF_DMAC_TRANS_TYPE_8 == 2
+#define CONF_DMAC_TYPE_8 1
+#define CONF_DMAC_DSYNC_8 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_8 == 0xFF
+#define CONF_DMAC_SWREQ_8 1
+#else
+#define CONF_DMAC_SWREQ_8 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8)))
+#if (!CONF_DMAC_SRCINC_8)
+#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_8)
+#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_8
+#define CONF_DMAC_SRC_STRIDE_8 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_8
+#define CONF_DMAC_DES_STRIDE_8 0
+#endif
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_9
+#ifndef CONF_DMAC_BURSTSIZE_9
+#define CONF_DMAC_BURSTSIZE_9 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_9
+#ifndef CONF_DMAC_CHUNKSIZE_9
+#define CONF_DMAC_CHUNKSIZE_9 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_9
+#ifndef CONF_DMAC_SRC_INTERFACE_9
+#define CONF_DMAC_SRC_INTERFACE_9 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_9
+#ifndef CONF_DMAC_DES_INTERFACE_9
+#define CONF_DMAC_DES_INTERFACE_9 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_9
+#ifndef CONF_DMAC_TRANS_TYPE_9
+#define CONF_DMAC_TRANS_TYPE_9 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_9 == 0
+#define CONF_DMAC_TYPE_9 0
+#define CONF_DMAC_DSYNC_9 0
+#elif CONF_DMAC_TRANS_TYPE_9 == 1
+#define CONF_DMAC_TYPE_9 1
+#define CONF_DMAC_DSYNC_9 0
+#elif CONF_DMAC_TRANS_TYPE_9 == 2
+#define CONF_DMAC_TYPE_9 1
+#define CONF_DMAC_DSYNC_9 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_9 == 0xFF
+#define CONF_DMAC_SWREQ_9 1
+#else
+#define CONF_DMAC_SWREQ_9 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9)))
+#if (!CONF_DMAC_SRCINC_9)
+#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_9)
+#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_9
+#define CONF_DMAC_SRC_STRIDE_9 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_9
+#define CONF_DMAC_DES_STRIDE_9 0
+#endif
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_10
+#ifndef CONF_DMAC_BURSTSIZE_10
+#define CONF_DMAC_BURSTSIZE_10 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_10
+#ifndef CONF_DMAC_CHUNKSIZE_10
+#define CONF_DMAC_CHUNKSIZE_10 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_10
+#ifndef CONF_DMAC_SRC_INTERFACE_10
+#define CONF_DMAC_SRC_INTERFACE_10 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_10
+#ifndef CONF_DMAC_DES_INTERFACE_10
+#define CONF_DMAC_DES_INTERFACE_10 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_10
+#ifndef CONF_DMAC_TRANS_TYPE_10
+#define CONF_DMAC_TRANS_TYPE_10 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_10 == 0
+#define CONF_DMAC_TYPE_10 0
+#define CONF_DMAC_DSYNC_10 0
+#elif CONF_DMAC_TRANS_TYPE_10 == 1
+#define CONF_DMAC_TYPE_10 1
+#define CONF_DMAC_DSYNC_10 0
+#elif CONF_DMAC_TRANS_TYPE_10 == 2
+#define CONF_DMAC_TYPE_10 1
+#define CONF_DMAC_DSYNC_10 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_10 == 0xFF
+#define CONF_DMAC_SWREQ_10 1
+#else
+#define CONF_DMAC_SWREQ_10 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10)))
+#if (!CONF_DMAC_SRCINC_10)
+#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_10)
+#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_10
+#define CONF_DMAC_SRC_STRIDE_10 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_10
+#define CONF_DMAC_DES_STRIDE_10 0
+#endif
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_11
+#ifndef CONF_DMAC_BURSTSIZE_11
+#define CONF_DMAC_BURSTSIZE_11 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_11
+#ifndef CONF_DMAC_CHUNKSIZE_11
+#define CONF_DMAC_CHUNKSIZE_11 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_11
+#ifndef CONF_DMAC_SRC_INTERFACE_11
+#define CONF_DMAC_SRC_INTERFACE_11 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_11
+#ifndef CONF_DMAC_DES_INTERFACE_11
+#define CONF_DMAC_DES_INTERFACE_11 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_11
+#ifndef CONF_DMAC_TRANS_TYPE_11
+#define CONF_DMAC_TRANS_TYPE_11 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_11 == 0
+#define CONF_DMAC_TYPE_11 0
+#define CONF_DMAC_DSYNC_11 0
+#elif CONF_DMAC_TRANS_TYPE_11 == 1
+#define CONF_DMAC_TYPE_11 1
+#define CONF_DMAC_DSYNC_11 0
+#elif CONF_DMAC_TRANS_TYPE_11 == 2
+#define CONF_DMAC_TYPE_11 1
+#define CONF_DMAC_DSYNC_11 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_11 == 0xFF
+#define CONF_DMAC_SWREQ_11 1
+#else
+#define CONF_DMAC_SWREQ_11 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11)))
+#if (!CONF_DMAC_SRCINC_11)
+#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_11)
+#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_11
+#define CONF_DMAC_SRC_STRIDE_11 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_11
+#define CONF_DMAC_DES_STRIDE_11 0
+#endif
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_12
+#ifndef CONF_DMAC_BURSTSIZE_12
+#define CONF_DMAC_BURSTSIZE_12 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_12
+#ifndef CONF_DMAC_CHUNKSIZE_12
+#define CONF_DMAC_CHUNKSIZE_12 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_12
+#ifndef CONF_DMAC_SRC_INTERFACE_12
+#define CONF_DMAC_SRC_INTERFACE_12 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_12
+#ifndef CONF_DMAC_DES_INTERFACE_12
+#define CONF_DMAC_DES_INTERFACE_12 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_12
+#ifndef CONF_DMAC_TRANS_TYPE_12
+#define CONF_DMAC_TRANS_TYPE_12 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_12 == 0
+#define CONF_DMAC_TYPE_12 0
+#define CONF_DMAC_DSYNC_12 0
+#elif CONF_DMAC_TRANS_TYPE_12 == 1
+#define CONF_DMAC_TYPE_12 1
+#define CONF_DMAC_DSYNC_12 0
+#elif CONF_DMAC_TRANS_TYPE_12 == 2
+#define CONF_DMAC_TYPE_12 1
+#define CONF_DMAC_DSYNC_12 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_12 == 0xFF
+#define CONF_DMAC_SWREQ_12 1
+#else
+#define CONF_DMAC_SWREQ_12 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12)))
+#if (!CONF_DMAC_SRCINC_12)
+#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_12)
+#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_12
+#define CONF_DMAC_SRC_STRIDE_12 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_12
+#define CONF_DMAC_DES_STRIDE_12 0
+#endif
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_13
+#ifndef CONF_DMAC_BURSTSIZE_13
+#define CONF_DMAC_BURSTSIZE_13 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_13
+#ifndef CONF_DMAC_CHUNKSIZE_13
+#define CONF_DMAC_CHUNKSIZE_13 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_13
+#ifndef CONF_DMAC_SRC_INTERFACE_13
+#define CONF_DMAC_SRC_INTERFACE_13 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_13
+#ifndef CONF_DMAC_DES_INTERFACE_13
+#define CONF_DMAC_DES_INTERFACE_13 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_13
+#ifndef CONF_DMAC_TRANS_TYPE_13
+#define CONF_DMAC_TRANS_TYPE_13 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_13 == 0
+#define CONF_DMAC_TYPE_13 0
+#define CONF_DMAC_DSYNC_13 0
+#elif CONF_DMAC_TRANS_TYPE_13 == 1
+#define CONF_DMAC_TYPE_13 1
+#define CONF_DMAC_DSYNC_13 0
+#elif CONF_DMAC_TRANS_TYPE_13 == 2
+#define CONF_DMAC_TYPE_13 1
+#define CONF_DMAC_DSYNC_13 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_13 == 0xFF
+#define CONF_DMAC_SWREQ_13 1
+#else
+#define CONF_DMAC_SWREQ_13 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13)))
+#if (!CONF_DMAC_SRCINC_13)
+#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_13)
+#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_13
+#define CONF_DMAC_SRC_STRIDE_13 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_13
+#define CONF_DMAC_DES_STRIDE_13 0
+#endif
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_14
+#ifndef CONF_DMAC_BURSTSIZE_14
+#define CONF_DMAC_BURSTSIZE_14 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_14
+#ifndef CONF_DMAC_CHUNKSIZE_14
+#define CONF_DMAC_CHUNKSIZE_14 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_14
+#ifndef CONF_DMAC_SRC_INTERFACE_14
+#define CONF_DMAC_SRC_INTERFACE_14 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_14
+#ifndef CONF_DMAC_DES_INTERFACE_14
+#define CONF_DMAC_DES_INTERFACE_14 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_14
+#ifndef CONF_DMAC_TRANS_TYPE_14
+#define CONF_DMAC_TRANS_TYPE_14 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_14 == 0
+#define CONF_DMAC_TYPE_14 0
+#define CONF_DMAC_DSYNC_14 0
+#elif CONF_DMAC_TRANS_TYPE_14 == 1
+#define CONF_DMAC_TYPE_14 1
+#define CONF_DMAC_DSYNC_14 0
+#elif CONF_DMAC_TRANS_TYPE_14 == 2
+#define CONF_DMAC_TYPE_14 1
+#define CONF_DMAC_DSYNC_14 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_14 == 0xFF
+#define CONF_DMAC_SWREQ_14 1
+#else
+#define CONF_DMAC_SWREQ_14 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14)))
+#if (!CONF_DMAC_SRCINC_14)
+#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_14)
+#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_14
+#define CONF_DMAC_SRC_STRIDE_14 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_14
+#define CONF_DMAC_DES_STRIDE_14 0
+#endif
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_15
+#ifndef CONF_DMAC_BURSTSIZE_15
+#define CONF_DMAC_BURSTSIZE_15 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_15
+#ifndef CONF_DMAC_CHUNKSIZE_15
+#define CONF_DMAC_CHUNKSIZE_15 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_15
+#ifndef CONF_DMAC_SRC_INTERFACE_15
+#define CONF_DMAC_SRC_INTERFACE_15 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_15
+#ifndef CONF_DMAC_DES_INTERFACE_15
+#define CONF_DMAC_DES_INTERFACE_15 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_15
+#ifndef CONF_DMAC_TRANS_TYPE_15
+#define CONF_DMAC_TRANS_TYPE_15 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_15 == 0
+#define CONF_DMAC_TYPE_15 0
+#define CONF_DMAC_DSYNC_15 0
+#elif CONF_DMAC_TRANS_TYPE_15 == 1
+#define CONF_DMAC_TYPE_15 1
+#define CONF_DMAC_DSYNC_15 0
+#elif CONF_DMAC_TRANS_TYPE_15 == 2
+#define CONF_DMAC_TYPE_15 1
+#define CONF_DMAC_DSYNC_15 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_15 == 0xFF
+#define CONF_DMAC_SWREQ_15 1
+#else
+#define CONF_DMAC_SWREQ_15 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15)))
+#if (!CONF_DMAC_SRCINC_15)
+#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_15)
+#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_15
+#define CONF_DMAC_SRC_STRIDE_15 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_15
+#define CONF_DMAC_DES_STRIDE_15 0
+#endif
+
+// <e> Channel 16 settings
+// <id> dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_16
+#ifndef CONF_DMAC_BURSTSIZE_16
+#define CONF_DMAC_BURSTSIZE_16 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_16
+#ifndef CONF_DMAC_CHUNKSIZE_16
+#define CONF_DMAC_CHUNKSIZE_16 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_16
+#ifndef CONF_DMAC_SRC_INTERFACE_16
+#define CONF_DMAC_SRC_INTERFACE_16 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_16
+#ifndef CONF_DMAC_DES_INTERFACE_16
+#define CONF_DMAC_DES_INTERFACE_16 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_16
+#ifndef CONF_DMAC_TRANS_TYPE_16
+#define CONF_DMAC_TRANS_TYPE_16 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_16 == 0
+#define CONF_DMAC_TYPE_16 0
+#define CONF_DMAC_DSYNC_16 0
+#elif CONF_DMAC_TRANS_TYPE_16 == 1
+#define CONF_DMAC_TYPE_16 1
+#define CONF_DMAC_DSYNC_16 0
+#elif CONF_DMAC_TRANS_TYPE_16 == 2
+#define CONF_DMAC_TYPE_16 1
+#define CONF_DMAC_DSYNC_16 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_16 == 0xFF
+#define CONF_DMAC_SWREQ_16 1
+#else
+#define CONF_DMAC_SWREQ_16 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16)))
+#if (!CONF_DMAC_SRCINC_16)
+#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_16)
+#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_16
+#define CONF_DMAC_SRC_STRIDE_16 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_16
+#define CONF_DMAC_DES_STRIDE_16 0
+#endif
+
+// <e> Channel 17 settings
+// <id> dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_17
+#ifndef CONF_DMAC_BURSTSIZE_17
+#define CONF_DMAC_BURSTSIZE_17 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_17
+#ifndef CONF_DMAC_CHUNKSIZE_17
+#define CONF_DMAC_CHUNKSIZE_17 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_17
+#ifndef CONF_DMAC_SRC_INTERFACE_17
+#define CONF_DMAC_SRC_INTERFACE_17 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_17
+#ifndef CONF_DMAC_DES_INTERFACE_17
+#define CONF_DMAC_DES_INTERFACE_17 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_17
+#ifndef CONF_DMAC_TRANS_TYPE_17
+#define CONF_DMAC_TRANS_TYPE_17 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_17 == 0
+#define CONF_DMAC_TYPE_17 0
+#define CONF_DMAC_DSYNC_17 0
+#elif CONF_DMAC_TRANS_TYPE_17 == 1
+#define CONF_DMAC_TYPE_17 1
+#define CONF_DMAC_DSYNC_17 0
+#elif CONF_DMAC_TRANS_TYPE_17 == 2
+#define CONF_DMAC_TYPE_17 1
+#define CONF_DMAC_DSYNC_17 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_17 == 0xFF
+#define CONF_DMAC_SWREQ_17 1
+#else
+#define CONF_DMAC_SWREQ_17 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17)))
+#if (!CONF_DMAC_SRCINC_17)
+#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_17)
+#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_17
+#define CONF_DMAC_SRC_STRIDE_17 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_17
+#define CONF_DMAC_DES_STRIDE_17 0
+#endif
+
+// <e> Channel 18 settings
+// <id> dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_18
+#ifndef CONF_DMAC_BURSTSIZE_18
+#define CONF_DMAC_BURSTSIZE_18 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_18
+#ifndef CONF_DMAC_CHUNKSIZE_18
+#define CONF_DMAC_CHUNKSIZE_18 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_18
+#ifndef CONF_DMAC_SRC_INTERFACE_18
+#define CONF_DMAC_SRC_INTERFACE_18 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_18
+#ifndef CONF_DMAC_DES_INTERFACE_18
+#define CONF_DMAC_DES_INTERFACE_18 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_18
+#ifndef CONF_DMAC_TRANS_TYPE_18
+#define CONF_DMAC_TRANS_TYPE_18 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_18 == 0
+#define CONF_DMAC_TYPE_18 0
+#define CONF_DMAC_DSYNC_18 0
+#elif CONF_DMAC_TRANS_TYPE_18 == 1
+#define CONF_DMAC_TYPE_18 1
+#define CONF_DMAC_DSYNC_18 0
+#elif CONF_DMAC_TRANS_TYPE_18 == 2
+#define CONF_DMAC_TYPE_18 1
+#define CONF_DMAC_DSYNC_18 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_18 == 0xFF
+#define CONF_DMAC_SWREQ_18 1
+#else
+#define CONF_DMAC_SWREQ_18 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18)))
+#if (!CONF_DMAC_SRCINC_18)
+#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_18)
+#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_18
+#define CONF_DMAC_SRC_STRIDE_18 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_18
+#define CONF_DMAC_DES_STRIDE_18 0
+#endif
+
+// <e> Channel 19 settings
+// <id> dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_19
+#ifndef CONF_DMAC_BURSTSIZE_19
+#define CONF_DMAC_BURSTSIZE_19 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_19
+#ifndef CONF_DMAC_CHUNKSIZE_19
+#define CONF_DMAC_CHUNKSIZE_19 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_19
+#ifndef CONF_DMAC_SRC_INTERFACE_19
+#define CONF_DMAC_SRC_INTERFACE_19 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_19
+#ifndef CONF_DMAC_DES_INTERFACE_19
+#define CONF_DMAC_DES_INTERFACE_19 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_19
+#ifndef CONF_DMAC_TRANS_TYPE_19
+#define CONF_DMAC_TRANS_TYPE_19 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_19 == 0
+#define CONF_DMAC_TYPE_19 0
+#define CONF_DMAC_DSYNC_19 0
+#elif CONF_DMAC_TRANS_TYPE_19 == 1
+#define CONF_DMAC_TYPE_19 1
+#define CONF_DMAC_DSYNC_19 0
+#elif CONF_DMAC_TRANS_TYPE_19 == 2
+#define CONF_DMAC_TYPE_19 1
+#define CONF_DMAC_DSYNC_19 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_19 == 0xFF
+#define CONF_DMAC_SWREQ_19 1
+#else
+#define CONF_DMAC_SWREQ_19 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19)))
+#if (!CONF_DMAC_SRCINC_19)
+#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_19)
+#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_19
+#define CONF_DMAC_SRC_STRIDE_19 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_19
+#define CONF_DMAC_DES_STRIDE_19 0
+#endif
+
+// <e> Channel 20 settings
+// <id> dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_20
+#ifndef CONF_DMAC_BURSTSIZE_20
+#define CONF_DMAC_BURSTSIZE_20 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_20
+#ifndef CONF_DMAC_CHUNKSIZE_20
+#define CONF_DMAC_CHUNKSIZE_20 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_20
+#ifndef CONF_DMAC_SRC_INTERFACE_20
+#define CONF_DMAC_SRC_INTERFACE_20 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_20
+#ifndef CONF_DMAC_DES_INTERFACE_20
+#define CONF_DMAC_DES_INTERFACE_20 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_20
+#ifndef CONF_DMAC_TRANS_TYPE_20
+#define CONF_DMAC_TRANS_TYPE_20 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_20 == 0
+#define CONF_DMAC_TYPE_20 0
+#define CONF_DMAC_DSYNC_20 0
+#elif CONF_DMAC_TRANS_TYPE_20 == 1
+#define CONF_DMAC_TYPE_20 1
+#define CONF_DMAC_DSYNC_20 0
+#elif CONF_DMAC_TRANS_TYPE_20 == 2
+#define CONF_DMAC_TYPE_20 1
+#define CONF_DMAC_DSYNC_20 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_20 == 0xFF
+#define CONF_DMAC_SWREQ_20 1
+#else
+#define CONF_DMAC_SWREQ_20 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20)))
+#if (!CONF_DMAC_SRCINC_20)
+#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_20)
+#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_20
+#define CONF_DMAC_SRC_STRIDE_20 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_20
+#define CONF_DMAC_DES_STRIDE_20 0
+#endif
+
+// <e> Channel 21 settings
+// <id> dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_21
+#ifndef CONF_DMAC_BURSTSIZE_21
+#define CONF_DMAC_BURSTSIZE_21 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_21
+#ifndef CONF_DMAC_CHUNKSIZE_21
+#define CONF_DMAC_CHUNKSIZE_21 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_21
+#ifndef CONF_DMAC_SRC_INTERFACE_21
+#define CONF_DMAC_SRC_INTERFACE_21 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_21
+#ifndef CONF_DMAC_DES_INTERFACE_21
+#define CONF_DMAC_DES_INTERFACE_21 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_21
+#ifndef CONF_DMAC_TRANS_TYPE_21
+#define CONF_DMAC_TRANS_TYPE_21 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_21 == 0
+#define CONF_DMAC_TYPE_21 0
+#define CONF_DMAC_DSYNC_21 0
+#elif CONF_DMAC_TRANS_TYPE_21 == 1
+#define CONF_DMAC_TYPE_21 1
+#define CONF_DMAC_DSYNC_21 0
+#elif CONF_DMAC_TRANS_TYPE_21 == 2
+#define CONF_DMAC_TYPE_21 1
+#define CONF_DMAC_DSYNC_21 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_21 == 0xFF
+#define CONF_DMAC_SWREQ_21 1
+#else
+#define CONF_DMAC_SWREQ_21 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21)))
+#if (!CONF_DMAC_SRCINC_21)
+#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_21)
+#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_21
+#define CONF_DMAC_SRC_STRIDE_21 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_21
+#define CONF_DMAC_DES_STRIDE_21 0
+#endif
+
+// <e> Channel 22 settings
+// <id> dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_22
+#ifndef CONF_DMAC_BURSTSIZE_22
+#define CONF_DMAC_BURSTSIZE_22 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_22
+#ifndef CONF_DMAC_CHUNKSIZE_22
+#define CONF_DMAC_CHUNKSIZE_22 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_22
+#ifndef CONF_DMAC_SRC_INTERFACE_22
+#define CONF_DMAC_SRC_INTERFACE_22 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_22
+#ifndef CONF_DMAC_DES_INTERFACE_22
+#define CONF_DMAC_DES_INTERFACE_22 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_22
+#ifndef CONF_DMAC_TRANS_TYPE_22
+#define CONF_DMAC_TRANS_TYPE_22 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_22 == 0
+#define CONF_DMAC_TYPE_22 0
+#define CONF_DMAC_DSYNC_22 0
+#elif CONF_DMAC_TRANS_TYPE_22 == 1
+#define CONF_DMAC_TYPE_22 1
+#define CONF_DMAC_DSYNC_22 0
+#elif CONF_DMAC_TRANS_TYPE_22 == 2
+#define CONF_DMAC_TYPE_22 1
+#define CONF_DMAC_DSYNC_22 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_22 == 0xFF
+#define CONF_DMAC_SWREQ_22 1
+#else
+#define CONF_DMAC_SWREQ_22 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22)))
+#if (!CONF_DMAC_SRCINC_22)
+#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_22)
+#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_22
+#define CONF_DMAC_SRC_STRIDE_22 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_22
+#define CONF_DMAC_DES_STRIDE_22 0
+#endif
+
+// <e> Channel 23 settings
+// <id> dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_23
+#ifndef CONF_DMAC_BURSTSIZE_23
+#define CONF_DMAC_BURSTSIZE_23 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_23
+#ifndef CONF_DMAC_CHUNKSIZE_23
+#define CONF_DMAC_CHUNKSIZE_23 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_23
+#ifndef CONF_DMAC_SRC_INTERFACE_23
+#define CONF_DMAC_SRC_INTERFACE_23 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_23
+#ifndef CONF_DMAC_DES_INTERFACE_23
+#define CONF_DMAC_DES_INTERFACE_23 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_23
+#ifndef CONF_DMAC_TRANS_TYPE_23
+#define CONF_DMAC_TRANS_TYPE_23 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_23 == 0
+#define CONF_DMAC_TYPE_23 0
+#define CONF_DMAC_DSYNC_23 0
+#elif CONF_DMAC_TRANS_TYPE_23 == 1
+#define CONF_DMAC_TYPE_23 1
+#define CONF_DMAC_DSYNC_23 0
+#elif CONF_DMAC_TRANS_TYPE_23 == 2
+#define CONF_DMAC_TYPE_23 1
+#define CONF_DMAC_DSYNC_23 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_23 == 0xFF
+#define CONF_DMAC_SWREQ_23 1
+#else
+#define CONF_DMAC_SWREQ_23 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23)))
+#if (!CONF_DMAC_SRCINC_23)
+#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_23)
+#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_23
+#define CONF_DMAC_SRC_STRIDE_23 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_23
+#define CONF_DMAC_DES_STRIDE_23 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_XDMAC_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/peripheral_clk_config.h b/hw/bsp/same70_qmtech/peripheral_clk_config.h
new file mode 100644
index 000000000..84756f5ac
--- /dev/null
+++ b/hw/bsp/same70_qmtech/peripheral_clk_config.h
@@ -0,0 +1,126 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/**
+ * \def CONF_HCLK_FREQUENCY
+ * \brief HCLK's Clock frequency
+ */
+#ifndef CONF_HCLK_FREQUENCY
+#define CONF_HCLK_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_FCLK_FREQUENCY
+ * \brief FCLK's Clock frequency
+ */
+#ifndef CONF_FCLK_FREQUENCY
+#define CONF_FCLK_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_SLCK_FREQUENCY
+ * \brief Slow Clock frequency
+ */
+#define CONF_SLCK_FREQUENCY 0
+
+/**
+ * \def CONF_MCK_FREQUENCY
+ * \brief Master Clock frequency
+ */
+#define CONF_MCK_FREQUENCY 150000000
+
+/**
+ * \def CONF_PCK6_FREQUENCY
+ * \brief Programmable Clock Controller 6 frequency
+ */
+#define CONF_PCK6_FREQUENCY 1714285
+
+// <h> USART Clock Settings
+// <o> USART Clock source
+
+// <0=> Master Clock (MCK)
+// <1=> MCK / 8 for USART
+// <2=> Programmable Clock Controller 4 (PMC_PCK4)
+// <3=> External Clock
+// <i> This defines the clock source for the USART
+// <id> usart_clock_source
+#ifndef CONF_USART1_CK_SRC
+#define CONF_USART1_CK_SRC 0
+#endif
+
+// <o> USART External Clock Input on SCK <1-4294967295>
+// <i> Inputs the external clock frequency on SCK
+// <id> usart_clock_freq
+#ifndef CONF_USART1_SCK_FREQ
+#define CONF_USART1_SCK_FREQ 10000000
+#endif
+
+// </h>
+
+/**
+ * \def USART FREQUENCY
+ * \brief USART's Clock frequency
+ */
+#ifndef CONF_USART1_FREQUENCY
+#define CONF_USART1_FREQUENCY 150000000
+#endif
+
+#ifndef CONF_SRC_USB_480M
+#define CONF_SRC_USB_480M 0
+#endif
+
+#ifndef CONF_SRC_USB_48M
+#define CONF_SRC_USB_48M 1
+#endif
+
+// <y> USB Full/Low Speed Clock
+// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
+// <id> usb_fsls_clock_source
+// <i> 48MHz clock source for low speed and full speed.
+// <i> It must be available when low speed is supported by host driver.
+// <i> It must be available when low power mode is selected.
+#ifndef CONF_USBHS_FSLS_SRC
+#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M
+#endif
+
+// <y> USB Clock Source(Normal/Low-power Mode Selection)
+// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M)
+// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
+// <id> usb_clock_source
+// <i> Select the clock source for USB.
+// <i> In normal mode, use "USB High Speed Clock (USB_480M)".
+// <i> In low-power mode, use "USB Clock Controller (USB_48M)".
+#ifndef CONF_USBHS_SRC
+#define CONF_USBHS_SRC CONF_SRC_USB_480M
+#endif
+
+/**
+ * \def CONF_USBHS_FSLS_FREQUENCY
+ * \brief USBHS's Full/Low Speed Clock Source frequency
+ */
+#ifndef CONF_USBHS_FSLS_FREQUENCY
+#define CONF_USBHS_FSLS_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_USBHS_FREQUENCY
+ * \brief USBHS's Selected Clock Source frequency
+ */
+#ifndef CONF_USBHS_FREQUENCY
+#define CONF_USBHS_FREQUENCY 480000000
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c
new file mode 100644
index 000000000..6e6ad0602
--- /dev/null
+++ b/hw/bsp/same70_qmtech/same70_qmtech.c
@@ -0,0 +1,159 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "sam.h"
+#include "bsp/board.h"
+
+#include "peripheral_clk_config.h"
+#include "hpl/usart/hpl_usart_base.h"
+#include "hpl/pmc/hpl_pmc.h"
+#include "hal/include/hal_init.h"
+#include "hal/include/hal_usart_async.h"
+#include "hal/include/hal_gpio.h"
+
+
+// You can get the board here:
+// https://www.aliexpress.com/item/1005003173783268.html
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#define LED_PIN               GPIO(GPIO_PORTA, 15)
+
+#define BUTTON_PIN            GPIO(GPIO_PORTA, 21)
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_TX_PIN           GPIO(GPIO_PORTB, 1)
+#define UART_RX_PIN           GPIO(GPIO_PORTB, 0)
+
+static struct usart_async_descriptor edbg_com;
+static uint8_t edbg_com_buffer[64];
+static volatile bool uart_busy = false;
+
+static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
+{
+  (void) io_descr;
+  uart_busy = false;
+}
+
+//------------- IMPLEMENTATION -------------//
+void board_init(void)
+{
+  init_mcu();
+
+  /* Disable Watchdog */
+  hri_wdt_set_MR_WDDIS_bit(WDT);
+
+  // LED
+  _pmc_enable_periph_clock(ID_PIOB);
+  gpio_set_pin_level(LED_PIN, false);
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
+
+  // Button
+  _pmc_enable_periph_clock(ID_PIOA);
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
+
+  // Uart via EDBG Com
+  _pmc_enable_periph_clock(ID_USART1);
+  gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
+  gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
+
+  usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
+  usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+  usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
+  usart_async_enable(&edbg_com);
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+  // 1ms tick timer (samd SystemCoreClock may not correct)
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
+
+  // Enable USB clock
+  _pmc_enable_periph_clock(ID_USBHS);
+
+}
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USBHS_Handler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  // while until previous transfer is complete
+  while(uart_busy) {}
+  uart_busy = true;
+
+  io_write(&edbg_com.io, buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index c9bc0cea3..cb2decf50 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index aed4de68e..deff6944c 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMG
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef
+CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference
 
 ASF_DIR = hw/mcu/microchip/samg55
 
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
index 81b4ecdcb..5b9acb90b 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML21J18B__
+CFLAGS += -D__SAML21J18B__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml21
 
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk
index 0605dca19..0adfdd62c 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.mk
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML22J18A__
+CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml22
 
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
index 0605dca19..0adfdd62c 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML22J18A__
+CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml22
 
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index e0f6b2f77..bb1faeb7f 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -13,6 +13,9 @@ CFLAGS += \
   -DCONF_OSC32K_CALIB_ENABLE=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAML22
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index e8a24d1bd..f5c240ca2 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -8,7 +8,7 @@ CFLAGS += \
   -D__STARTUP_CLEAR_BSS \
   -D__START=main \
   -DEFM32GG12B810F1024GM64 \
-  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG12 
+  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG
 
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=unused-parameter
@@ -24,7 +24,7 @@ LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
 
 SRC_C += \
   $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \
-  src/portable/silabs/efm32/dcd_efm32.c
+	src/portable/synopsys/dwc2/dcd_dwc2.c
 
 SRC_S += \
   $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S
@@ -34,12 +34,8 @@ INC += \
   $(TOP)/$(SILABS_CMSIS)/Include \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = silabs
-CHIP_FAMILY = efm32
-
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4
+FREERTOS_PORT = ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index a46c42bd6..ba291e817 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -70,4 +70,5 @@ $(BUILD)/$(PROJECT).spk: $(MKSPK)
 
 # flash
 flash: $(BUILD)/$(PROJECT).spk
-	@$(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $<
+	@echo FLASH $<
+	@$(PYTHON) $(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $<
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 9e636cd76..7c0ee40b6 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F070xB
+CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 2ef0ee63c..7c72d8f4c 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F072xB
+CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index f7f8c84ee..b625c3ebd 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000
+CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 68b924432..8de3147e2 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -134,7 +134,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 08cbf5626..39831e154 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -18,7 +18,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index 9c690ca7e..db64b3a3f 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
+CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index 2b979f3d8..fa7d28399 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -21,7 +21,7 @@ CFLAGS += -Wno-error=sign-compare
 LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+  src/portable/synopsys/dwc2/dcd_dwc2.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
new file mode 100644
index 000000000..b00b5dbe0
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
@@ -0,0 +1,169 @@
+/*
+*****************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32F412ZGTx Device with
+**                1024KByte FLASH, 256KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20040000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
new file mode 100644
index 000000000..73c5f83b9
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
@@ -0,0 +1,119 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_8
+#define UART_RX_PIN           GPIO_PIN_9
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the
+   * device is clocked below the maximum system frequency, to update the
+   * voltage scaling value regarding system frequency refer to product
+   * datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLN = 200;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLLSAI output as USB clock source */
+  PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+  PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+  PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
+  PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+  PeriphClkInitStruct.PLLI2S.PLLI2SR = 7;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+   * clocks dividers */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+                                RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  // Enable clocks for LED, Button, Uart
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_USART3_CLK_ENABLE();
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
new file mode 100644
index 000000000..50973f737
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32F412Zx
+
+LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f412zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..7864f8d5f
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED         
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */ 
+/* #define HAL_CEC_MODULE_ENABLED      */ 
+/* #define HAL_CRYP_MODULE_ENABLED     */ 
+/* #define HAL_DAC_MODULE_ENABLED      */ 
+/* #define HAL_DCMI_MODULE_ENABLED     */ 
+#define HAL_DMA_MODULE_ENABLED 
+/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED 
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */  
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED     */
+#define HAL_RCC_MODULE_ENABLED      
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED   
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000U)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+  
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index cf0cb2b08..82d4957e7 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -36,6 +36,11 @@ void OTG_FS_IRQHandler(void)
   tud_int_handler(0);
 }
 
+void OTG_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -134,6 +139,8 @@ void board_init(void)
   // Enable USB OTG clock
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+//  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+
   board_vbus_sense_init();
 }
 
@@ -160,7 +167,7 @@ int board_uart_read(uint8_t* buf, int len)
 int board_uart_write(void const * buf, int len)
 {
 #ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 #else
   (void) buf; (void) len; (void) UartHandle;
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 584d69405..9811d3371 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -21,7 +21,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=cast-align
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 8f05199d0..66d9ff8fb 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -10,3 +10,6 @@ SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
 
 # flash target using on-board stlink
 flash: flash-stlink
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f723ie
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
index 093445ede..92c109a72 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
@@ -76,6 +76,8 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLQ = 9;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
+  // TODO need to enable usb clock source
+
   /* Activate the OverDrive to reach the 216 MHz Frequency */
   HAL_PWREx_EnableOverDrive();
 
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index 2400a4ba7..7710619e5 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -8,5 +8,8 @@ CFLAGS += \
 LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
 
+# For flash-jlink target
+JLINK_DEVICE = stm32f767zi
+
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 2eb737ee3..14e3b2fd9 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -284,7 +284,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index ead0c977a..8482e6dd2 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -34,7 +34,7 @@ endif
 CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
new file mode 100644
index 000000000..935d97c87
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by Ac6 System Workbench
+**
+**  Abstract    : Linker script for STM32G474RETx series
+**                512Kbytes FLASH and 160Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed �as is,� without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of Ac6 nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+CCMSRAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
new file mode 100644
index 000000000..fd9d50183
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -0,0 +1,130 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G474RE Nucleo does not has usb connection. We need to manually connect
+// - PA11 for D+, CN10.14
+// - PA12 for D-, CN10.12
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF12_LPUART1
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  // Configure the main internal regulator output voltage
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 85;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+
+#if 0 // TODO need to check if USB clock is enabled
+  /* Enable HSI48 */
+  memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /*Enable CRS Clock*/
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
new file mode 100644
index 000000000..1951fcba0
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -0,0 +1,8 @@
+CFLAGS += -DSTM32G474xx
+
+LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
new file mode 100644
index 000000000..318f50746
--- /dev/null
+++ b/hw/bsp/stm32g4/family.c
@@ -0,0 +1,186 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32g4xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_HP_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USB_LP_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USBWakeUp_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+#ifdef UART_DEV
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+//  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+//  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+//  GPIO_InitStruct.Pull = GPIO_NOPULL;
+//  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+//  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+//
+//  __HAL_RCC_USB_CLK_ENABLE();
+
+  board_vbus_sense_init();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len; (void) UartHandle;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32g4/family.mk
index 28824efdc..04222f3bb 100644
--- a/hw/bsp/stm32l476disco/board.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -1,9 +1,12 @@
-ST_FAMILY = l4
+UF2_FAMILY_ID = 0x4c71240a
+ST_FAMILY = g4
 DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -12,45 +15,30 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
-  -DSTM32L476xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
+  -DCFG_TUSB_MCU=OPT_MCU_STM32G4
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
+CFLAGS += -Wno-error=cast-align
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
-
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
+	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
-# For flash-jlink target
-JLINK_DEVICE = stm32l476vg
-
-# Path to STM32 Cube Programmer CLI, should be added into system path
-STM32Prog = STM32_Programmer_CLI
-
 # flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
+flash: flash-stlink
diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
new file mode 100644
index 000000000..ad5f7dbd4
--- /dev/null
+++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
@@ -0,0 +1,381 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_CONF_H
+#define STM32G4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+  
+#define HAL_MODULE_ENABLED  
+
+  /*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CORDIC_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_FDCAN_MODULE_ENABLED   */
+/*#define HAL_FMAC_MODULE_ENABLED   */
+/*#define HAL_HRTIM_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_OPAMP_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS     0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_EXTI_REGISTER_CALLBACKS       0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_FMAC_REGISTER_CALLBACKS       0U
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_QSPI_REGISTER_CALLBACKS       0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (24000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+/*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations in voltage and temperature.*/
+#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/    
+#endif /* LSI_VALUE */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  (32768UL)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S and SAI peripherals
+  *        This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    (12288000UL) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+
+#define  VDD_VALUE                   (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */            
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32g4xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g4xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32g4xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32g4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32g4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32g4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32g4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32g4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32g4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index 96d14a795..b768a0ee6 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -2,6 +2,7 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000
 
 # Default is Highspeed port
 PORT ?= 1
+SPEED ?= high
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
 LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index a2116d0bd..84976b4e4 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -237,7 +237,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index e35e75610..096d04d0c 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -19,18 +19,24 @@ CFLAGS += \
 	-DBOARD_DEVICE_RHPORT_NUM=$(PORT)
 
 ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-  $(info "PORT1 High Speed")
+  ifeq ($(SPEED), high)
+    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+    $(info "Using OTG_HS in HighSpeed mode")
+  else
+    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED
+    $(info "Using OTG_HS in FullSpeed mode")
+  endif
 else
-  $(info "PORT0 Full Speed")
+  $(info "Using OTG_FS")
 endif
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # All source paths should be relative to the top level.
+
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index c46887f14..e19101d64 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -13,6 +13,7 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DSTM32L053xx \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
 # mcu driver cause following warnings
diff --git a/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
index 98f468ac0..98f468ac0 100644
--- a/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
index b18846685..42c657d5e 100644
--- a/hw/bsp/stm32l476disco/stm32l476disco.c
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,21 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#ifndef BOARD_H_
+#define BOARD_H_
 
-#include "stm32l4xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
 #define LED_PORT              GPIOB
 #define LED_PIN               GPIO_PIN_2
@@ -48,15 +39,16 @@ void OTG_FS_IRQHandler(void)
 #define BUTTON_PIN            GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE   1
 
+#define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART2
+#define UART_TX_PIN           GPIO_PIN_5
+#define UART_RX_PIN           GPIO_PIN_6
 
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D-, Button
-  __HAL_RCC_GPIOB_CLK_ENABLE(); // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE(); // VBUS pin
-}
-
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
 
 /**
   * @brief  System Clock Configuration
@@ -80,7 +72,7 @@ static void all_rcc_clk_enable(void)
   * @param  None
   * @retval None
   */
-static void SystemClock_Config(void)
+static inline void board_clock_init(void)
 {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
@@ -131,112 +123,17 @@ static void SystemClock_Config(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
-void board_init(void)
+static inline void board_vbus_sense_init(void)
 {
-  SystemClock_Config();
-  all_rcc_clk_enable();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Enable USB power on Pwrctrl CR2 register */
-  HAL_PWREx_EnableVddUSB();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+  // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
+  // Disable VBUS Sense and force device mode
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
 }
 
-//--------------------------------------------------------------------+
-// board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
+#ifdef __cplusplus
+ }
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
new file mode 100644
index 000000000..e7b8557a5
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32L476xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l476vg
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
new file mode 100644
index 000000000..c1a490a70
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
@@ -0,0 +1,200 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32L4P5ZGTx Device from STM32L4PLUS series
+**                      1024Kbytes ROM
+**                      320Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + 0x0001FFFF;	/* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 320K
+  ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
new file mode 100644
index 000000000..1df389aed
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
@@ -0,0 +1,137 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOG
+#define UART_GPIO_AF          GPIO_AF8_LPUART1
+#define UART_TX_PIN           GPIO_PIN_7
+#define UART_RX_PIN           GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 48000000
+  *            PLL_M                          = 12
+  *            PLL_N                          = 60
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 2
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale1 mode
+  *            Flash Latency(WS)              = 5
+  *         The USB clock configuration from PLLSAI:
+  *            PLLSAIP                        = 8 FIXME
+  *            PLLSAIN                        = 384 FIXME
+  *            PLLSAIQ                        = 7 FIXME
+  * @param  None
+  * @retval None
+  */
+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /* Activate PLL with MSI , stabilizied via PLL by LSE */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 60;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Enable MSI Auto-calibration through LSE */
+  HAL_RCCEx_EnableMSIPLLMode();
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  // Avoid overshoot and start with HCLK 60 MHz
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  /* AHB prescaler divider at 1 as second step */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
new file mode 100644
index 000000000..8252dd838
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32L4P5xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l4p5zg
diff --git a/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
index f93a16041..f93a16041 100644
--- a/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
new file mode 100644
index 000000000..1df389aed
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
@@ -0,0 +1,137 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOG
+#define UART_GPIO_AF          GPIO_AF8_LPUART1
+#define UART_TX_PIN           GPIO_PIN_7
+#define UART_RX_PIN           GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 48000000
+  *            PLL_M                          = 12
+  *            PLL_N                          = 60
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 2
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale1 mode
+  *            Flash Latency(WS)              = 5
+  *         The USB clock configuration from PLLSAI:
+  *            PLLSAIP                        = 8 FIXME
+  *            PLLSAIN                        = 384 FIXME
+  *            PLLSAIQ                        = 7 FIXME
+  * @param  None
+  * @retval None
+  */
+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /* Activate PLL with MSI , stabilizied via PLL by LSE */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 60;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Enable MSI Auto-calibration through LSE */
+  HAL_RCCEx_EnableMSIPLLMode();
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  // Avoid overshoot and start with HCLK 60 MHz
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  /* AHB prescaler divider at 1 as second step */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
new file mode 100644
index 000000000..3d7fa227b
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DHSE_VALUE=8000000 \
+  -DSTM32L4R5xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l4r5zi
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/hw/bsp/stm32l4/family.c
index bab66b550..c15be98e5 100644
--- a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
+++ b/hw/bsp/stm32l4/family.c
@@ -26,9 +26,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
-
 #include "stm32l4xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -42,119 +42,22 @@ void OTG_FS_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UARTx                 LPUART1
-#define UART_GPIO_PORT        GPIOG
-#define UART_GPIO_AF          GPIO_AF8_LPUART1
-#define UART_TX_PIN           GPIO_PIN_7
-#define UART_RX_PIN           GPIO_PIN_8
-
 UART_HandleTypeDef UartHandle;
 
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
-  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
-  __HAL_RCC_GPIOG_CLK_ENABLE();  // Uart TX, RX
-  __HAL_RCC_LPUART1_CLK_ENABLE(); // LPUart1 module
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (MSI)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 1
-  *            APB2 Prescaler                 = 1
-  *            MSI Frequency(Hz)              = 48000000
-  *            PLL_M                          = 12
-  *            PLL_N                          = 60
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 2
-  *            VDD(V)                         = 3.3
-  *            Main regulator output voltage  = Scale1 mode
-  *            Flash Latency(WS)              = 5
-  *         The USB clock configuration from PLLSAI:
-  *            PLLSAIP                        = 8 FIXME
-  *            PLLSAIN                        = 384 FIXME
-  *            PLLSAIQ                        = 7 FIXME
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  /* Activate PLL with MSI , stabilizied via PLL by LSE */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM = 12;
-  RCC_OscInitStruct.PLL.PLLN = 60;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
-  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  // Avoid overshoot and start with HCLK 60 MHz  
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-
-  /* AHB prescaler divider at 1 as second step */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-}
-
 void board_init(void)
 {
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable voltage range 1 boost mode for frequency above 80 Mhz */
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+  board_clock_init();
 
-  /* Set tick interrupt priority, default HAL value is intentionally invalid
-     and that prevents PLL initialization in HAL_RCC_OscConfig() */
-
-  HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
-
-  SystemClock_Config();
-  all_rcc_clk_enable();
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  UART_CLK_EN();
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer
@@ -165,6 +68,15 @@ void board_init(void)
 #endif
 
   /* Enable USB power on Pwrctrl CR2 register */
+  /* Enable Power Clock*/
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+#if defined(PWR_CR5_R1MODE)
+  /* Enable voltage range 1 boost mode for frequency above 80 Mhz */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+#endif
+
+  /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
   GPIO_InitTypeDef  GPIO_InitStruct;
@@ -192,7 +104,7 @@ void board_init(void)
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance        = UARTx;
+  UartHandle.Instance        = UART_DEV;
   UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
   UartHandle.Init.StopBits   = UART_STOPBITS_1;
@@ -201,7 +113,7 @@ void board_init(void)
   UartHandle.Init.Mode       = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
-  UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  //UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
   UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 
   HAL_UART_Init(&UartHandle);
@@ -231,8 +143,7 @@ void board_init(void)
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  board_vbus_sense_init();
 }
 
 //--------------------------------------------------------------------+
@@ -257,7 +168,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/family.mk
index 12a291d0a..d6f55e5f9 100644
--- a/hw/bsp/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -4,6 +4,8 @@ DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -12,18 +14,14 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
-  -DHSE_VALUE=8000000 \
-  -DSTM32L4R5xx \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L4
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld
-
+#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -34,14 +32,11 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
 
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
-
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
index 312f86da1..312f86da1 100644
--- a/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h
+++ b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
deleted file mode 100644
index 470ef1290..000000000
--- a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l4xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_CONF_H
-#define __STM32L4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-// #define HAL_NOR_MODULE_ENABLED
-// #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
-#define HAL_GPIO_MODULE_ENABLED
-//#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-//#define HAL_LCD_MODULE_ENABLED
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SAI_MODULE_ENABLED
-//#define HAL_SD_MODULE_ENABLED
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
-  *        This internal oscillator is mainly dedicated to provide a high precision clock to
-  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
-  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
-  *        which is subject to manufacturing process variations.
-  */
-#if !defined  (HSI48_VALUE) 
- #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
-                                              The real value my vary depending on manufacturing process variations.*/
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U  /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
-  #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1 External clock source in Hz*/
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
-
-/**
-  * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
-  #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2 External clock source in Hz*/
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              0U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT               1U */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32l4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32l4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "Legacy/stm32l4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l4xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l4xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32l4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32l4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32l4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l4xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32l4xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32l4xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l4xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32l4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
new file mode 100644
index 000000000..5732056ae
--- /dev/null
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define BOARD_UART            UART0
+#define BOARD_UART_PORT       GPIOA
+
+#define BOARD_BTN_PORT        GPIOF
+#define BOARD_BTN             4
+#define BOARD_BTN_Msk         (1u<<4)
+#define BUTTON_STATE_ACTIVE   0
+
+#define LED_PORT              GPIOF
+#define LED_PIN_RED           1
+#define LED_PIN_BLUE          2
+#define LED_PIN_GREEN         3
+#define LED_STATE_ON          1
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
new file mode 100644
index 000000000..d60365d1d
--- /dev/null
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DTM4C123GH6PM
+ 
+LD_FILE = $(BOARD_PATH)/tm4c123.ld
+
+# For flash-jlink target
+JLINK_DEVICE = TM4C123GH6PM
+
+# flash using openocd
+OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg
+
+flash: flash-openocd
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
new file mode 100644
index 000000000..e2720a9ac
--- /dev/null
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
@@ -0,0 +1,65 @@
+ENTRY(Reset_Handler)
+
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000; /* required amount of stack */
+
+
+MEMORY 
+{
+    FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+SECTIONS 
+{
+    .text : 
+    {
+        . = ALIGN(4) ;
+        *(.vectors) 
+        *(.text) 
+        *(.text.*)
+        *(.init)
+        *(.fini)
+        *(.rodata)
+        *(.rodata.*)
+        . = ALIGN(4) ; 
+        __end_text = . ; 
+    } >FLASH
+    
+    .data : AT(ADDR(.text) + SIZEOF(.text))
+    {
+        . = ALIGN(4);
+        __start_data = . ; 
+        __la_data = LOADADDR(.data);
+        *(.data) 
+        *(.data.*)
+        . = ALIGN(4);
+        __end_data = . ; 
+
+    } >SRAM
+
+    .bss :
+    {
+        . = ALIGN(4) ;
+        __start_bss = . ;
+        __bss_start__ = __start_bss;
+        *(.bss)
+        *(.bss.*)
+        *(.COMMON) 
+        __end_bss = . ;
+        . = ALIGN(4);
+    }>SRAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >SRAM
+}
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
new file mode 100644
index 000000000..449781ce1
--- /dev/null
+++ b/hw/bsp/tm4c123/family.c
@@ -0,0 +1,178 @@
+#include "TM4C123.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_Handler(void)
+{
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if TUSB_OPT_DEVICE_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+static void board_uart_init (void)
+{
+  SYSCTL->RCGCUART |= (1 << 0);                // Enable the clock to UART0
+  SYSCTL->RCGCGPIO |= (1 << 0);                // Enable the clock to GPIOA
+
+  GPIOA->AFSEL |= (1 << 1) | (1 << 0);         // Enable the alternate function on pin PA0 & PA1
+  GPIOA->PCTL |= (1 << 0) | (1 << 4);          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
+  GPIOA->DEN |= (1 << 0) | (1 << 1);           // Enable the digital functionality in PA0 and PA1
+
+  // BAUDRATE = 115200, with SystemCoreClock = 50 Mhz refer manual for calculation
+  //  - BRDI = SystemCoreClock / (16* baud)
+  //  - BRDF = int(fraction*64 + 0.5)
+  UART0->CTL &= ~(1 << 0);                     // Disable UART0 by clearing UARTEN bit in the UARTCTL register
+  UART0->IBRD = 27;                            // Write the integer portion of the BRD to the UARTIRD register
+  UART0->FBRD = 8;                             // Write the fractional portion of the BRD to the UARTFBRD registerer
+
+  UART0->LCRH = (0x3 << 5);                    // 8-bit, no parity, 1 stop bit
+  UART0->CC = 0x0;                             // Configure the UART clock source as system clock
+
+  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable
+}
+
+static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk)
+{
+  /* Enable PortF Clock */
+  SYSCTL->RCGCGPIO |= (1 << 5);
+
+  /* Let the clock stabilize */
+  while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {}
+
+  /* Port Digital Enable */
+  port->DEN |= PinMsk;
+
+  /* Set direction */
+  port->DIR = dirmsk;
+}
+
+static void board_switch_init (void)
+{
+  GPIOF->DIR &= ~(1 << BOARD_BTN);
+  GPIOF->PUR |= (1 << BOARD_BTN);
+  GPIOF->DEN |= (1 << BOARD_BTN);
+}
+
+static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state)
+{
+  if ( state )
+  {
+    port->DATA |= PinMsk;
+  }
+  else
+  {
+    port->DATA &= ~(PinMsk);
+  }
+}
+
+static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk)
+{
+  return (port->DATA & pinMsk);
+}
+
+void board_init (void)
+{
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+    // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+    NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  /* Reset USB */
+  SYSCTL->SRCR2 |= (1u << 16);
+
+  for ( volatile uint8_t i = 0; i < 20; i++ ) {}
+
+  SYSCTL->SRCR2 &= ~(1u << 16);
+
+  /* Open the USB clock gate */
+  SYSCTL->RCGCUSB |= (1 << 0);
+
+  /* Power-up USB PLL */
+  SYSCTL->RCC2 &= ~(1u << 14);
+
+  /* USB IO Initialization */
+  SYSCTL->RCGCGPIO |= (1u << 3);
+
+  /* Let the clock stabilize */
+  while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {}
+
+  /* USB IOs to Analog Mode */
+  GPIOD->AFSEL &= ~((1u << 4) | (1u << 5));
+  GPIOD->DEN &= ~((1u << 4) | (1u << 5));
+  GPIOD->AMSEL |= ((1u << 4) | (1u << 5));
+
+  uint8_t leds = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
+  uint8_t dirmsk = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
+
+  /* Configure GPIO for board LED */
+  initialize_board_led(LED_PORT, leds, dirmsk);
+
+  /* Configure GPIO for board switch */
+  board_switch_init();
+
+  /* Initialize board UART */
+  board_uart_init();
+
+  TU_LOG1_INT(SystemCoreClock);
+}
+
+void board_led_write (bool state)
+{
+  WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state);
+}
+
+uint32_t board_button_read (void)
+{
+  uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
+  return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+  uint8_t const * data = buf;
+
+  for ( int i = 0; i < len; i++ )
+  {
+    while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out
+    UART0->DR = data[i];                     // Write UART0 DATA REGISTER
+  }
+
+  return len;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
+#endif
+
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
new file mode 100644
index 000000000..751076196
--- /dev/null
+++ b/hw/bsp/tm4c123/family.mk
@@ -0,0 +1,36 @@
+DEPS_SUBMODULES += hw/mcu/ti
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
+  -uvectors \
+  -DTM4C123GH6PM
+  
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
+
+MCU_DIR=hw/mcu/ti/tm4c123xx/
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/tm4c123.ld
+
+INC += \
+	$(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \
+	$(TOP)/$(MCU_DIR)/Include/TM4C123 \
+	$(TOP)/$(BOARD_PATH)
+
+SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
+	src/portable/mentor/musb/hcd_musb.c \
+	$(MCU_DIR)/Source/system_TM4C123.c \
+	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
new file mode 100644
index 000000000..3e2cb9583
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
@@ -0,0 +1,88 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PIN               P1_1
+#define LED_STATE_ON          1
+
+#define BUTTON_PIN            P1_14
+#define BUTTON_STATE_ACTIVE   0
+
+//#define UART_DEV              USART6
+//#define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
+//#define UART_GPIO_AF          GPIO_AF8_USART6
+//
+//#define UART_TX_PORT          GPIOC
+//#define UART_TX_PIN           GPIO_PIN_6
+//
+//#define UART_RX_PORT          GPIOC
+//#define UART_RX_PIN           GPIO_PIN_7
+
+static inline void board_clock_init(void)
+{
+  /* Clock configuration */
+  /* fPLL = 120MHz */
+  /* fSYS = 120MHz */
+  /* fUSBPLL = 192MHz */
+  /* fUSB = 48MHz */
+  const XMC_SCU_CLOCK_CONFIG_t clock_config =
+  {
+    .syspll_config.p_div  = 2,
+    .syspll_config.n_div  = 80,
+    .syspll_config.k_div  = 4,
+    .syspll_config.mode   = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
+    .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
+    .enable_oschp         = true,
+    .calibration_mode     = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
+    .fsys_clksrc          = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
+    .fsys_clkdiv          = 1,
+    .fcpu_clkdiv          = 1,
+    .fccu_clkdiv          = 1,
+    .fperipheral_clkdiv   = 1
+  };
+
+  /* Setup settings for USB clock */
+  XMC_SCU_CLOCK_Init(&clock_config);
+
+  XMC_SCU_CLOCK_EnableUsbPll();
+  XMC_SCU_CLOCK_StartUsbPll(2, 64);
+  XMC_SCU_CLOCK_SetUsbClockDivider(4);
+  XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_USBPLL);
+  XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB);
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
new file mode 100644
index 000000000..a2c2c5aaf
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
@@ -0,0 +1,9 @@
+MCU_VARIANT = XMC4500
+CFLAGS += \
+  -DXMC4500_F100x1024 \
+
+LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
+
+JLINK_DEVICE = XMC4500-1024
+
+flash: flash-jlink
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
new file mode 100644
index 000000000..bf6684736
--- /dev/null
+++ b/hw/bsp/xmc4000/family.c
@@ -0,0 +1,130 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "xmc_gpio.h"
+#include "xmc_scu.h"
+
+#include "bsp/board.h"
+#include "board.h"
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+  board_clock_init();
+  SystemCoreClockUpdate();
+
+  // LED
+  XMC_GPIO_CONFIG_t led_cfg;
+  led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
+  led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
+  led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM;
+  XMC_GPIO_Init(LED_PIN, &led_cfg);
+
+  // Button
+  XMC_GPIO_CONFIG_t button_cfg;
+  button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
+  XMC_GPIO_Init(BUTTON_PIN, &button_cfg);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // USB Power Enable
+  XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
+  XMC_SCU_POWER_EnableUsb();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  uint32_t is_high = state ? LED_STATE_ON : (1-LED_STATE_ON);
+
+  XMC_GPIO_SetOutputLevel(LED_PIN, is_high ? XMC_GPIO_OUTPUT_LEVEL_HIGH : XMC_GPIO_OUTPUT_LEVEL_LOW);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+#ifdef UART_DEV
+  for(int i=0;i<len;i++) {
+    buf[i] = uart_getc(uart_inst);
+  }
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  char const* bufch = (char const*) buf;
+  for(int i=0;i<len;i++) {
+    uart_putc(uart_inst, bufch[i]);
+  }
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
new file mode 100644
index 000000000..0b32bdeb5
--- /dev/null
+++ b/hw/bsp/xmc4000/family.mk
@@ -0,0 +1,40 @@
+UF2_FAMILY_ID = 0x00
+MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3
+
+DEPS_SUBMODULES += $(MCU_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_XMC4000
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+
+SKIP_NANOLIB = 1
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	$(MCU_DIR)/Newlib/syscalls.c \
+	$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/system_$(MCU_VARIANT).c \
+	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
+	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
+
+
+SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
+
+INC += \
+  $(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Include \
+	$(TOP)/$(MCU_DIR)/XMCLib/inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
author	Gordon McNab <[email protected]>	2021-12-08 08:36:43 +0000
committer	Gordon McNab <[email protected]>	2021-12-08 08:36:43 +0000
commit	9a7db985931ae215e808d40e7bacd52535d45305 (patch)
tree	a4d75e2c3823766da53a006280c0d805630d996e /hw/bsp
parent	edf3f3501656b010ad4a9e1d0a0d62573dd0b3fb (diff)
parent	cde824f17f73b5ce4fcec8c176827297854a76c2 (diff)