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authorhathach <[email protected]>2023-08-24 16:27:12 +0700
committerhathach <[email protected]>2023-08-24 16:27:12 +0700
commit3ed5d6c3724cfa9699d403a76a00f1b04672e2b5 (patch)
tree02566af73fcd2814c2371256dd247d97d0ffdbb9 /hw
parent2c237b1ae4b3ffd38fc74df29da63b01348afd1d (diff)
complete enumeration
Diffstat (limited to 'hw')
-rw-r--r--hw/bsp/nrf/family.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 45a5166a7..368763b84 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -105,6 +105,10 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
//--------------------------------------------------------------------+
// API: SPI transfer with MAX3421E, must be implemented by application
//--------------------------------------------------------------------+
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+ (void) rhport;
+ nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
+}
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
(void) rhport;
@@ -241,7 +245,6 @@ void board_init(void) {
in_config.pull = NRF_GPIO_PIN_PULLUP;
nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
- nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
#endif
}