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authorhathach <[email protected]>2024-11-20 18:03:42 +0700
committerhathach <[email protected]>2024-11-20 20:38:20 +0700
commit4da5de707b53389c8fe35f6b448f3d1bfe7c91e8 (patch)
tree74311790e7ebcec00d7c256d0ba9c95e47a5ca48 /hw
parent43a45f29cd14bad681be3bb3928ea7e0453cc886 (diff)
have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line
Diffstat (limited to 'hw')
-rw-r--r--hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 900f620fd..9f55c8d5a 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -15,6 +15,13 @@ list(APPEND compile_definitions
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
)
+if (target STREQUAL esp32p4)
+ # P4 change alignment to 64 (DCache line size) for possible DMA configuration
+ list(APPEND compile_definitions
+ CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+ )
+endif ()
+
list(APPEND srcs
# common
${tusb_src}/tusb.c
@@ -68,6 +75,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${tusb_src}
REQUIRES src
+ PRIV_REQUIRES esp_mm
)
target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})