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authorhathach <[email protected]>2026-03-02 17:51:48 +0700
committerhathach <[email protected]>2026-03-02 17:51:48 +0700
commit4df7ef54396e1695aa9504aef9dfe4263569c3f6 (patch)
treea46ba124a444a9f68671feb34c409e40a486d7ac /hw
parent0daa444a9b337262c25fe2a2b4598bd3401464e5 (diff)
fix call_after timeout adjustment with rtos
Diffstat (limited to 'hw')
-rw-r--r--hw/bsp/stm32h7/boards/stm32h743eval/board.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 0f0eb4ed3..d2f61a5ce 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -120,10 +120,10 @@ static inline void SystemClock_Config(void) {
// From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals
// are shared with other peripherals. Trace CLK = PLL1R.
RCC_OscInitStruct.PLL.PLLM = 5;
- RCC_OscInitStruct.PLL.PLLN = 160; // May reduce to 200 Mhz when tracing to avoid overflowing trace buffer
+ RCC_OscInitStruct.PLL.PLLN = 160; // May reduce to 100/200 Mhz when tracing to avoid overflowing trace buffer
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 4;
- RCC_OscInitStruct.PLL.PLLR = 16; // Trace clock is limit to 50 Mhz to meet board requirement
+ RCC_OscInitStruct.PLL.PLLR = RCC_OscInitStruct.PLL.PLLN/10; // Trace clock is limit to 50 Mhz to meet board requirement
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
RCC_OscInitStruct.PLL.PLLFRACN = 0;