diff options
| author | Zixun LI <[email protected]> | 2025-12-16 11:09:16 +0100 |
|---|---|---|
| committer | Zixun LI <[email protected]> | 2025-12-16 11:09:16 +0100 |
| commit | 5a7e5db78770d6fd37992b5812f910c3546f2a72 (patch) | |
| tree | 1878cba0dd7a239424be31039b3c4fa3795f4989 /hw | |
| parent | e00c3d1726950fda4833c265d4df0ad9b1b97c00 (diff) | |
fix riscv toolchain
Signed-off-by: Zixun LI <[email protected]>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/bsp/family_support.mk | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/hw/bsp/family_support.mk b/hw/bsp/family_support.mk index db410a657..7122a7764 100644 --- a/hw/bsp/family_support.mk +++ b/hw/bsp/family_support.mk @@ -131,8 +131,21 @@ ifdef CPU_CORE include ${TOP}/examples/build_system/make/cpu/$(CPU_CORE).mk endif -# toolchain specific -include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk +# toolchain specific - select based on CPU architecture +ifdef CPU_CORE + ifneq (,$(filter cortex% arm%,$(CPU_CORE))) + # ARM/Cortex architecture + include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk + else ifneq (,$(filter rv%,$(CPU_CORE))) + # RISC-V architecture + include ${TOP}/examples/build_system/make/toolchain/riscv_$(TOOLCHAIN).mk + else + $(error Unsupported CPU_CORE architecture: $(CPU_CORE). Must start with cortex, arm, or rv) + endif +else + # Default to ARM if CPU_CORE not specified + include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk +endif #---------------------- FreeRTOS ----------------------- FREERTOS_SRC = lib/FreeRTOS-Kernel |