diff options
| author | hathach <[email protected]> | 2018-11-21 12:24:18 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2018-11-21 12:24:18 +0700 |
| commit | 5bccb234eeef156f58da76d3276833dd54ea8dc4 (patch) | |
| tree | 06a8833cfcb3a51b06001f2b36880c1a30435a5b /hw | |
| parent | c5d9a477c0aa7fcf1fdf3cbd5526518d557e115e (diff) | |
samd21 has usb traffic
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/bsp/metro_m0_express/board_metro_m0_express.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/hw/bsp/metro_m0_express/board_metro_m0_express.c b/hw/bsp/metro_m0_express/board_metro_m0_express.c index 598d0658d..9f1ed4fe4 100644 --- a/hw/bsp/metro_m0_express/board_metro_m0_express.c +++ b/hw/bsp/metro_m0_express/board_metro_m0_express.c @@ -82,13 +82,12 @@ void board_init(void) SysTick_Config(SystemCoreClock/1000); #endif -#if 0 /* USB Clock init * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock * for low speed and full speed operation. */ - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, CONF_GCLK_USB_SRC | GCLK_PCHCTRL_CHEN); - hri_mclk_set_AHBMASK_USB_bit(MCLK); - hri_mclk_set_APBBMASK_USB_bit(MCLK); + _pm_enable_bus_clock(PM_BUS_APBB, USB); + _pm_enable_bus_clock(PM_BUS_AHB, USB); + _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); // USB Pin Init gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); @@ -98,9 +97,8 @@ void board_init(void) gpio_set_pin_level(PIN_PA25, false); gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); - gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); -#endif + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); } void board_led_control(uint32_t led_id, bool state) |