Merge branch 'refs/heads/master' into fork/BrentK-ADI/max32_port

92 files changed, 2416 insertions, 1888 deletions

diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index eee9ed9c5..a458a3fdc 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _BOARD_API_H_
-#define _BOARD_API_H_
+#ifndef BOARD_API_H_
+#define BOARD_API_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -72,6 +72,9 @@ void board_init(void);
 // Init board after tinyusb is initialized
 void board_init_after_tusb(void) TU_ATTR_WEAK;
 
+// Jump to bootloader
+void board_reset_to_bootloader(void) TU_ATTR_WEAK;
+
 // Turn LED on or off
 void board_led_write(bool state);
 
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
new file mode 100644
index 000000000..f6e47ba30
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
@@ -0,0 +1,8 @@
+set(LD_FLASH_SIZE 64K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
index 3ed2aef04..3b1187c3a 100644
--- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
@@ -6,9 +6,13 @@ extern "C" {
 #endif
 
 #define LED_PORT       GPIOA
-#define LED_PIN        GPIO_Pin_15
+#define LED_PIN        GPIO_Pin_10
 #define LED_STATE_ON   0
 
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE   0
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
new file mode 100644
index 000000000..e594f42a7
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
@@ -0,0 +1,5 @@
+CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=64K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v10x/ch32v10x_conf.h b/hw/bsp/ch32v10x/ch32v10x_conf.h
new file mode 100644
index 000000000..939c0fbde
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_conf.h
@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_CONF_H
+#define __CH32V10x_CONF_H
+
+#include "ch32v10x_adc.h"
+#include "ch32v10x_bkp.h"
+#include "ch32v10x_crc.h"
+#include "ch32v10x_dbgmcu.h"
+#include "ch32v10x_dma.h"
+#include "ch32v10x_exti.h"
+#include "ch32v10x_flash.h"
+#include "ch32v10x_gpio.h"
+#include "ch32v10x_i2c.h"
+#include "ch32v10x_iwdg.h"
+#include "ch32v10x_pwr.h"
+#include "ch32v10x_rcc.h"
+#include "ch32v10x_rtc.h"
+#include "ch32v10x_spi.h"
+#include "ch32v10x_tim.h"
+#include "ch32v10x_usart.h"
+#include "ch32v10x_wwdg.h"
+#include "ch32v10x_usb.h"
+#include "ch32v10x_usb_host.h"
+#include "ch32v10x_it.h"
+#include "ch32v10x_misc.h"
+
+#endif /* __CH32V10x_CONF_H */
diff --git a/hw/bsp/ch32v10x/ch32v10x_it.h b/hw/bsp/ch32v10x/ch32v10x_it.h
new file mode 100644
index 000000000..13afc2412
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_it.h
@@ -0,0 +1,15 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2022/08/20
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_IT_H
+#define __CH32V10x_IT_H
+
+#endif /* __CH32V10x_IT_H */
diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c
new file mode 100644
index 000000000..15f754e11
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.c
@@ -0,0 +1,148 @@
+#include <stdio.h>
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "ch32v10x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+__attribute__((interrupt)) __attribute__((used))
+void USBHD_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBWakeUp_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt)) __attribute__((used))
+void SysTick_Handler(void) {
+  SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+  SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+  system_ticks++;
+}
+
+uint32_t SysTick_Config(uint32_t ticks) {
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR = 0;
+  SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+  SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+
+  SysTick->CMPLR0 = (u8)(ticks & 0xFF);
+  SysTick->CMPLR1 = (u8)(ticks >> 8);
+  SysTick->CMPLR2 = (u8)(ticks >> 16);
+  SysTick->CMPLR3 = (u8)(ticks >> 24);
+
+  SysTick->CMPHR0 = SysTick->CMPHR1 = SysTick->CMPHR2 =   SysTick->CMPHR3 = 0;
+  SysTick->CTLR = 1;
+  return 0;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void board_init(void) {
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+  EXTEN->EXTEN_CTR |= EXTEN_USBFS_IO_EN;
+  uint8_t usb_div;
+  switch (SystemCoreClock) {
+    case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+    case 72000000: usb_div = RCC_USBCLKSource_PLLCLK_1Div5; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_USBCLKConfig(usb_div);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE);
+
+  #ifdef LED_PIN
+  GPIO_InitTypeDef led_init = {
+      .GPIO_Pin = LED_PIN,
+      .GPIO_Mode = GPIO_Mode_Out_OD,
+      .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(LED_PORT, &led_init);
+  #endif
+
+  #ifdef BUTTON_PIN
+  GPIO_InitTypeDef button_init = {
+      .GPIO_Pin = BUTTON_PIN,
+      .GPIO_Mode = GPIO_Mode_IPU,
+      .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(BUTTON_PORT, &button_init);
+  #endif
+
+  // UART TX is PA9
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+  GPIO_InitTypeDef usart_init = {
+    .GPIO_Pin = GPIO_Pin_9,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Mode = GPIO_Mode_AF_PP,
+  };
+  GPIO_Init(GPIOA, &usart_init);
+
+  USART_InitTypeDef usart = {
+    .USART_BaudRate = 115200,
+    .USART_WordLength = USART_WordLength_8b,
+    .USART_StopBits = USART_StopBits_1,
+    .USART_Parity = USART_Parity_No,
+    .USART_Mode = USART_Mode_Tx,
+    .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+  };
+  USART_Init(USART1, &usart);
+  USART_Cmd(USART1, ENABLE);
+
+  __enable_irq();
+
+  board_led_write(true);
+}
+
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  const char *bufc = (const char *) buf;
+  for (int i = 0; i < len; i++) {
+    while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+    USART_SendData(USART1, *bufc++);
+  }
+
+  return len;
+}
diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake
new file mode 100644
index 000000000..c0af0ef44
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.cmake
@@ -0,0 +1,117 @@
+include_guard()
+
+#set(UF2_FAMILY_ID 0x699b62ec)
+set(CH32_FAMILY ch32v10x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v103)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V103 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
+    ${SDK_SRC_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mcmodel=medany
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+      -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V103 ${RTOS})
+
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+
+  #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
+  #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
+endfunction()
diff --git a/hw/bsp/ch32v10x/family.mk b/hw/bsp/ch32v10x/family.mk
new file mode 100644
index 000000000..d96d5012e
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.mk
@@ -0,0 +1,53 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v10x
+SDK_DIR = hw/mcu/wch/ch32v103
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# Port0 use FSDev, Port1 use USBFS
+PORT ?= 0
+
+CFLAGS += \
+	-mcmodel=medany \
+	-ffat-lto-objects \
+	-flto \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V103
+
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
+LDFLAGS_GCC += \
+	-nostdlib -nostartfiles \
+	--specs=nosys.specs --specs=nano.specs \
+
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbfs.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v10x/linker/ch32v10x.ld b/hw/bsp/ch32v10x/linker/ch32v10x.ld
new file mode 100644
index 000000000..cd5c8dc17
--- /dev/null
+++ b/hw/bsp/ch32v10x/linker/ch32v10x.ld
@@ -0,0 +1,165 @@
+/* Define default values if not already defined */
+__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K;
+__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K;
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE
+}
+
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+SECTIONS
+{
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH
+
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH
+
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH
+
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH
+
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH
+
+	.dlalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM
+
+}
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.c b/hw/bsp/ch32v10x/system_ch32v10x.c
new file mode 100644
index 000000000..b083b83b4
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.c
@@ -0,0 +1,600 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Source File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v10x.h"
+
+/*
+ * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+ * reset the HSI is used as SYSCLK source).
+ * If none of the define below is enabled, the HSI is used as System clock source.
+ */
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+#define SYSCLK_FREQ_72MHz_HSE  72000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* ch32v10x_system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit(void)
+{
+    RCC->CTLR |= (uint32_t)0x00000001;
+    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+    SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch(tmp)
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = (pllmull >> 18) + 2;
+            if(pllsource == 0x00)
+            {
+                if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
+                {
+                    SystemCoreClock = ( HSI_VALUE ) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
+                }
+            }
+            else
+            {
+                if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+                {
+                    SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+    SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+    //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+     */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+        /* Select HSE as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 1 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#endif
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.h b/hw/bsp/ch32v10x/system_ch32v10x.h
new file mode 100644
index 000000000..d15624520
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.h
@@ -0,0 +1,29 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V10x_H
+#define __SYSTEM_CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_SYSTEM_H */
diff --git a/hw/bsp/ch32v10x/wch-riscv.cfg b/hw/bsp/ch32v10x/wch-riscv.cfg
new file mode 100644
index 000000000..aa35aa9c5
--- /dev/null
+++ b/hw/bsp/ch32v10x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk
deleted file mode 100644
index 7d7462312..000000000
--- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = D6
-
-CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
-
-LDFLAGS += \
-  -Wl,--defsym=__flash_size=64K \
-  -Wl,--defsym=__ram_size=20K \
diff --git a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
index 31b6b716e..4aae6bdc2 100644
--- a/hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
@@ -1,12 +1,15 @@
 set(MCU_VARIANT D6)
 
-set(LD_FLASH_SIZE 64K)
+# 64KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 64K)
+set(LD_FLASH_SIZE 224K)
 set(LD_RAM_SIZE 20K)
 
 # set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${CH32_FAMILY}_tinyuf2.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSE=144000000
     CFG_EXAMPLE_MSC_DUAL_READONLY
     )
 endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
new file mode 100644
index 000000000..692cf11bf
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
@@ -0,0 +1,21 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_0
+#define LED_STATE_ON   0
+
+#define UART_DEV        USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_9
+#define UART_RX_PIN     GPIO_Pin_10
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
new file mode 100644
index 000000000..bdd15f737
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+  -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 64KB zero-wait, 224KB total flash
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
new file mode 100644
index 000000000..ecb8b378f
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT D6)
+
+# 32KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 32K)
+set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 10K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSI=144000000
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
new file mode 100644
index 000000000..783831edd
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
@@ -0,0 +1,21 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_0
+#define LED_STATE_ON   0
+
+#define UART_DEV        USART2
+#define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_2
+#define UART_RX_PIN     GPIO_Pin_3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
new file mode 100644
index 000000000..f71f53478
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSI=144000000 \
+  -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 32KB zero-wait, 224KB total flash
+LDFLAGS += \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=10K \
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
index 8d3e0326e..6c7712cdd 100644
--- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
@@ -1,10 +1,13 @@
 set(MCU_VARIANT D6)
 
+# 64KB zero-wait, 224KB total flash
 set(LD_FLASH_SIZE 64K)
+#set(LD_FLASH_SIZE 224K)
 set(LD_RAM_SIZE 20K)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
+    SYSCLK_FREQ_144MHz_HSE=144000000
     CFG_EXAMPLE_MSC_DUAL_READONLY
     )
 endfunction()
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
index c8d28d90f..64eaf931e 100644
--- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
@@ -8,7 +8,11 @@ extern "C" {
 #define LED_PORT       GPIOA
 #define LED_PIN        GPIO_Pin_15
 #define LED_STATE_ON   0
-#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
+
+#define UART_DEV        USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN     GPIO_Pin_9
+#define UART_RX_PIN     GPIO_Pin_10
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
index 7d7462312..362aace47 100644
--- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
@@ -1,7 +1,11 @@
 MCU_VARIANT = D6
 
-CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+CFLAGS += \
+  -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+	-DCH32_FLASH_ENHANCE_READ_MODE=1 \
+  -DCFG_EXAMPLE_MSC_DUAL_READONLY \
 
+# 64KB zero-wait , 224KB total flash
 LDFLAGS += \
-  -Wl,--defsym=__flash_size=64K \
-  -Wl,--defsym=__ram_size=20K \
+  -Wl,--defsym=__FLASH_SIZE=224K \
+  -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/core_riscv.h b/hw/bsp/ch32v20x/core_riscv.h
deleted file mode 100644
index be1b52a6c..000000000
--- a/hw/bsp/ch32v20x/core_riscv.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : core_riscv.h
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : RISC-V Core Peripheral Access Layer Header File for CH32V20x
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __CORE_RISCV_H__
-#define __CORE_RISCV_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* IO definitions */
-#ifdef __cplusplus
-  #define     __I     volatile                /*  defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*  defines 'read only' permissions     */
-#endif
-#define       __O     volatile                /*  defines 'write only' permissions     */
-#define       __IO    volatile                /*  defines 'read / write' permissions   */
-
-/* Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef __I uint64_t vuc64;   /* Read Only */
-typedef __I uint32_t vuc32;   /* Read Only */
-typedef __I uint16_t vuc16;   /* Read Only */
-typedef __I uint8_t  vuc8;    /* Read Only */
-
-typedef const uint64_t uc64;  /* Read Only */
-typedef const uint32_t uc32;  /* Read Only */
-typedef const uint16_t uc16;  /* Read Only */
-typedef const uint8_t  uc8;   /* Read Only */
-
-typedef __I int64_t vsc64;    /* Read Only */
-typedef __I int32_t vsc32;    /* Read Only */
-typedef __I int16_t vsc16;    /* Read Only */
-typedef __I int8_t  vsc8;     /* Read Only */
-
-typedef const int64_t sc64;   /* Read Only */
-typedef const int32_t sc32;   /* Read Only */
-typedef const int16_t sc16;   /* Read Only */
-typedef const int8_t  sc8;    /* Read Only */
-
-typedef __IO uint64_t  vu64;
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t  vu16;
-typedef __IO uint8_t   vu8;
-
-typedef uint64_t  u64;
-typedef uint32_t  u32;
-typedef uint16_t  u16;
-typedef uint8_t   u8;
-
-typedef __IO int64_t  vs64;
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef int64_t  s64;
-typedef int32_t  s32;
-typedef int16_t  s16;
-typedef int8_t   s8;
-
-typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-#define   RV_STATIC_INLINE  static  inline
-
-/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
-typedef struct{
-  __I  uint32_t ISR[8];
-  __I  uint32_t IPR[8];
-  __IO uint32_t ITHRESDR;
-  __IO uint32_t RESERVED;
-  __IO uint32_t CFGR;
-  __I  uint32_t GISR;
-  __IO uint8_t VTFIDR[4];
-  uint8_t RESERVED0[12];
-  __IO uint32_t VTFADDR[4];
-  uint8_t RESERVED1[0x90];
-  __O  uint32_t IENR[8];
-  uint8_t RESERVED2[0x60];
-  __O  uint32_t IRER[8];
-  uint8_t RESERVED3[0x60];
-  __O  uint32_t IPSR[8];
-  uint8_t RESERVED4[0x60];
-  __O  uint32_t IPRR[8];
-  uint8_t RESERVED5[0x60];
-  __IO uint32_t IACTR[8];
-  uint8_t RESERVED6[0xE0];
-  __IO uint8_t IPRIOR[256];
-  uint8_t RESERVED7[0x810];
-  __IO uint32_t SCTLR;
-}PFIC_Type;
-
-/* memory mapped structure for SysTick */
-typedef struct
-{
-    __IO uint32_t CTLR;
-    __IO uint32_t SR;
-    __IO uint64_t CNT;
-    __IO uint64_t CMP;
-}SysTick_Type;
-
-#define PFIC            ((PFIC_Type *) 0xE000E000 )
-#define NVIC            PFIC
-#define NVIC_KEY1       ((uint32_t)0xFA050000)
-#define	NVIC_KEY2		((uint32_t)0xBCAF0000)
-#define	NVIC_KEY3		((uint32_t)0xBEEF0000)
-
-#define SysTick         ((SysTick_Type *) 0xE000F000)
-
-/*********************************************************************
- * @fn      __enable_irq
- *
- * @brief   Enable Global Interrupt
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq(void)
-{
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
-}
-
-/*********************************************************************
- * @fn      __disable_irq
- *
- * @brief   Disable Global Interrupt
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq(void)
-{
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
-}
-
-/*********************************************************************
- * @fn      __NOP
- *
- * @brief   nop
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP(void)
-{
-  __asm volatile ("nop");
-}
-
-/*********************************************************************
- * @fn      NVIC_EnableIRQ
- *
- * @brief   Disable Interrupt
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_DisableIRQ
- *
- * @brief   Disable Interrupt
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetStatusIRQ
- *
- * @brief   Get Interrupt Enable State
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  1 - Interrupt Pending Enable
- *          0 - Interrupt Pending Disable
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetPendingIRQ
- *
- * @brief   Get Interrupt Pending State
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  1 - Interrupt Pending Enable
- *          0 - Interrupt Pending Disable
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_SetPendingIRQ
- *
- * @brief   Set Interrupt Pending
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_ClearPendingIRQ
- *
- * @brief   Clear Interrupt Pending
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetActive
- *
- * @brief   Get Interrupt Active State
- *
- * @param   IRQn - Interrupt Numbers
- *
- * @return  1 - Interrupt Active
- *          0 - Interrupt No Active
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_SetPriority
- *
- * @brief   Set Interrupt Priority
- *
- * @param   IRQn - Interrupt Numbers
- *          priority - bit7 - Pre-emption Priority
- *                     bit[6:5] - Subpriority
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
-{
-  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
-}
-
-/*********************************************************************
- * @fn      __WFI
- *
- * @brief   Wait for Interrupt
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
-{
-  NVIC->SCTLR &= ~(1<<3);	// wfi
-  asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn      _SEV
- *
- * @brief   Set Event
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
-{
-  uint32_t t;
-
-  t = NVIC->SCTLR;
-  NVIC->SCTLR |= (1<<3)|(1<<5);
-  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
-}
-
-/*********************************************************************
- * @fn      _WFE
- *
- * @brief   Wait for Events
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
-{
-  NVIC->SCTLR |= (1<<3);
-  asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn      __WFE
- *
- * @brief   Wait for Events
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
-{
-  _SEV();
-  _WFE();
-  _WFE();
-}
-
-/*********************************************************************
- * @fn      SetVTFIRQ
- *
- * @brief   Set VTF Interrupt
- *
- * @param   addr - VTF interrupt service function base address.
- *          IRQn - Interrupt Numbers
- *          num - VTF Interrupt Numbers
- *          NewState - DISABLE or ENABLE
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
-  if(num > 3)  return ;
-
-  if (NewState != DISABLE)
-  {
-      NVIC->VTFIDR[num] = IRQn;
-      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
-  }
-  else{
-      NVIC->VTFIDR[num] = IRQn;
-      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
-  }
-}
-
-/*********************************************************************
- * @fn      NVIC_SystemReset
- *
- * @brief   Initiate a system reset request
- *
- * @return  none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
-{
-  NVIC->CFGR = NVIC_KEY3|(1<<7);
-}
-
-/*********************************************************************
- * @fn      __AMOADD_W
- *
- * @brief   Atomic Add with 32bit value
- *          Atomically ADD 32bit value with value in memory using amoadd.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be ADDed
- *
- * @return  return memory value + add value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amoadd.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOAND_W
- *
- * @brief   Atomic And with 32bit value
- *          Atomically AND 32bit value with value in memory using amoand.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be ANDed
- *
- * @return  return memory value & and value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amoand.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOMAX_W
- *
- * @brief   Atomic signed MAX with 32bit value
- *          Atomically signed max compare 32bit value with value in memory using amomax.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be compared
- *
- * @return  the bigger value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amomax.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOMAXU_W
- *
- * @brief   Atomic unsigned MAX with 32bit value
- *          Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be compared
- *
- * @return  return the bigger value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
-{
-    uint32_t result;
-
-    __asm volatile ("amomaxu.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOMIN_W
- *
- * @brief   Atomic signed MIN with 32bit value
- *          Atomically signed min compare 32bit value with value in memory using amomin.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be compared
- *
- * @return  the smaller value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amomin.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOMINU_W
- *
- * @brief   Atomic unsigned MIN with 32bit value
- *          Atomically unsigned min compare 32bit value with value in memory using amominu.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be compared
- *
- * @return  the smaller value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
-{
-    uint32_t result;
-
-    __asm volatile ("amominu.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOOR_W
- *
- * @brief   Atomic OR with 32bit value
- *          Atomically OR 32bit value with value in memory using amoor.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be ORed
- *
- * @return  return memory value | and value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amoor.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/*********************************************************************
- * @fn      __AMOSWAP_W
- *
- * @brief   Atomically swap new 32bit value into memory using amoswap.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          newval - New value to be stored into the address
- *
- * @return  return the original value in memory
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
-{
-    uint32_t result;
-
-    __asm volatile ("amoswap.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
-    return result;
-}
-
-/*********************************************************************
- * @fn      __AMOXOR_W
- *
- * @brief   Atomic XOR with 32bit value
- *          Atomically XOR 32bit value with value in memory using amoxor.d.
- *
- * @param   addr - Address pointer to data, address need to be 4byte aligned
- *          value - value to be XORed
- *
- * @return  return memory value ^ and value
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
-{
-    int32_t result;
-
-    __asm volatile ("amoxor.w %0, %2, %1" : \
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-    return *addr;
-}
-
-/* Core_Exported_Functions */
-extern uint32_t __get_MSTATUS(void);
-extern void __set_MSTATUS(uint32_t value);
-extern uint32_t __get_MISA(void);
-extern void __set_MISA(uint32_t value);
-extern uint32_t __get_MTVEC(void);
-extern void __set_MTVEC(uint32_t value);
-extern uint32_t __get_MSCRATCH(void);
-extern void __set_MSCRATCH(uint32_t value);
-extern uint32_t __get_MEPC(void);
-extern void __set_MEPC(uint32_t value);
-extern uint32_t __get_MCAUSE(void);
-extern void __set_MCAUSE(uint32_t value);
-extern uint32_t __get_MTVAL(void);
-extern void __set_MTVAL(uint32_t value);
-extern uint32_t __get_MVENDORID(void);
-extern uint32_t __get_MARCHID(void);
-extern uint32_t __get_MIMPID(void);
-extern uint32_t __get_MHARTID(void);
-extern uint32_t __get_SP(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c
index c32cfd46e..43dd7e032 100644
--- a/hw/bsp/ch32v20x/family.c
+++ b/hw/bsp/ch32v20x/family.c
@@ -1,6 +1,18 @@
 #include <stdio.h>
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
 #include "ch32v20x.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "bsp/board_api.h"
 #include "board.h"
 
@@ -50,7 +62,6 @@ void USBWakeUp_IRQHandler(void) {
 
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-
 volatile uint32_t system_ticks = 0;
 
 __attribute__((interrupt))
@@ -72,7 +83,6 @@ uint32_t SysTick_Config(uint32_t ticks) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
-
 #endif
 
 void board_init(void) {
@@ -84,28 +94,17 @@ void board_init(void) {
 
   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
 
-  uint8_t usb_div;
-  switch (SystemCoreClock) {
-    case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
-    case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
-    case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
-    default: TU_ASSERT(0,); break;
-  }
-  RCC_USBCLKConfig(usb_div);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);  // FSDEV
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
-
   GPIO_InitTypeDef GPIO_InitStructure = {
     .GPIO_Pin = LED_PIN,
     .GPIO_Mode = GPIO_Mode_Out_OD,
-    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Speed = GPIO_Speed_10MHz,
   };
   GPIO_Init(LED_PORT, &GPIO_InitStructure);
 
-  // UART TX is PA9
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+#ifdef UART_DEV
+  UART_CLOCK_EN();
   GPIO_InitTypeDef usart_init = {
-    .GPIO_Pin = GPIO_Pin_9,
+    .GPIO_Pin = UART_TX_PIN,
     .GPIO_Speed = GPIO_Speed_50MHz,
     .GPIO_Mode = GPIO_Mode_AF_PP,
   };
@@ -119,11 +118,51 @@ void board_init(void) {
     .USART_Mode = USART_Mode_Tx,
     .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
   };
-  USART_Init(USART1, &usart);
-  USART_Cmd(USART1, ENABLE);
+  USART_Init(UART_DEV, &usart);
+  USART_Cmd(UART_DEV, ENABLE);
+#endif
+
+  // USB init
+  uint8_t usb_div;
+  switch (SystemCoreClock) {
+    case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+    case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
+    case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_USBCLKConfig(usb_div);
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);  // FSDEV
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
 
   __enable_irq();
-  board_delay(2);
+}
+
+void board_reset_to_bootloader(void) {
+//   board_led_write(true);
+//
+//   __disable_irq();
+//
+// #if CFG_TUD_ENABLED
+//   tud_deinit(0);
+//   RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
+//   RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
+// #endif
+//
+//   SysTick->CTLR = 0;
+//   for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
+//     NVIC_DisableIRQ(i);
+//   }
+//
+//   __enable_irq();
+//
+//   // define function pointer to BOOT ROM address
+//   void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
+//
+//   bootloader_entry();
+//
+//   board_led_write(false);
+
+  // while(1) { }
 }
 
 void board_led_write(bool state) {
@@ -134,6 +173,17 @@ uint32_t board_button_read(void) {
   return false;
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t* ch32_uuid = ((volatile uint32_t*) 0x1FFFF7E8UL);
+  uint32_t* serial_32 = (uint32_t*) (uintptr_t) id;
+  serial_32[0] = ch32_uuid[0];
+  serial_32[1] = ch32_uuid[1];
+  serial_32[2] = ch32_uuid[2];
+
+  return 12;
+}
+
 int board_uart_read(uint8_t *buf, int len) {
   (void) buf;
   (void) len;
@@ -141,11 +191,19 @@ int board_uart_read(uint8_t *buf, int len) {
 }
 
 int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
   const char *bufc = (const char *) buf;
   for (int i = 0; i < len; i++) {
-    while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
-    USART_SendData(USART1, *bufc++);
+    while (USART_GetFlagStatus(UART_DEV, USART_FLAG_TC) == RESET);
+    USART_SendData(UART_DEV, *bufc++);
   }
+#else
+  (void) buf; (void) len;
+#endif
 
   return len;
 }
+
+//--------------------------------------------------------------------
+// Neopixel
+//--------------------------------------------------------------------
diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake
index 1d574fdf8..380ef190d 100644
--- a/hw/bsp/ch32v20x/family.cmake
+++ b/hw/bsp/ch32v20x/family.cmake
@@ -41,6 +41,7 @@ function(add_board_target BOARD_TARGET)
 
   add_library(${BOARD_TARGET} STATIC
     ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_flash.c
     ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
     ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
     ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
@@ -49,6 +50,7 @@ function(add_board_target BOARD_TARGET)
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
     ${SDK_SRC_DIR}/Peripheral/inc
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     )
@@ -70,19 +72,25 @@ function(add_board_target BOARD_TARGET)
 
   update_board(${BOARD_TARGET})
 
+  if (LD_FLASH_SIZE STREQUAL 224K)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CH32_FLASH_ENHANCE_READ_MODE=1
+      )
+  endif()
+
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     target_compile_options(${BOARD_TARGET} PUBLIC
       -mcmodel=medany
       )
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -Wl,--defsym=__flash_size=${LD_FLASH_SIZE}
-      -Wl,--defsym=__ram_size=${LD_RAM_SIZE}
       -nostartfiles
       --specs=nosys.specs --specs=nano.specs
+      -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+      -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+      "LINKER:--script=${LD_FILE_GNU}"
       )
   elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+    message(FATAL_ERROR "Clang is not supported for CH32v")
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
     target_link_options(${BOARD_TARGET} PUBLIC
       "LINKER:--config=${LD_FILE_IAR}"
@@ -129,6 +137,7 @@ function(family_configure_example TARGET RTOS)
   # Flashing
   family_add_bin_hex(${TARGET})
   family_flash_openocd_wch(${TARGET})
+  family_flash_wlink_rs(${TARGET})
 
   #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
   #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
diff --git a/hw/bsp/ch32v20x/family.mk b/hw/bsp/ch32v20x/family.mk
index 49d4d2feb..08761dc0d 100644
--- a/hw/bsp/ch32v20x/family.mk
+++ b/hw/bsp/ch32v20x/family.mk
@@ -24,6 +24,9 @@ CFLAGS += \
 	-DCH32V20x_${MCU_VARIANT} \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V20X
 
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
 ifeq ($(PORT),0)
   $(info "Using FSDEV driver")
   CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1
@@ -42,18 +45,20 @@ SRC_C += \
 	src/portable/wch/dcd_ch32_usbfs.c \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
 	$(SDK_SRC_DIR)/Core/core_riscv.c \
-	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_gpio.c \
-	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_misc.c \
-	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_rcc.c \
-	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_usart.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
 
-SRC_S += $(SDK_SRC_DIR)/Startup/startup_ch32v20x_${MCU_VARIANT}.S
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
 	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
 
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
-flash: flash-openocd-wch
+flash: flash-wlink-rs
+#flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v20x/linker/ch32v20x.ld b/hw/bsp/ch32v20x/linker/ch32v20x.ld
index cd5c8dc17..f84808b0d 100644
--- a/hw/bsp/ch32v20x/linker/ch32v20x.ld
+++ b/hw/bsp/ch32v20x/linker/ch32v20x.ld
@@ -1,17 +1,16 @@
 /* Define default values if not already defined */
-__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K;
-__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K;
+__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K;
+__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K;
+__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048;
 
 MEMORY
 {
-	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE
-	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size
 }
 
 ENTRY( _start )
 
-__stack_size = 2048;
-
 PROVIDE( _stack_size = __stack_size );
 
 SECTIONS
diff --git a/hw/bsp/ch32v20x/system_ch32v20x.c b/hw/bsp/ch32v20x/system_ch32v20x.c
index bdc0d498f..d32ee8d17 100644
--- a/hw/bsp/ch32v20x/system_ch32v20x.c
+++ b/hw/bsp/ch32v20x/system_ch32v20x.c
@@ -19,12 +19,12 @@
 * If none of the define below is enabled, the HSI is used as System clock source.
 */
 //#define SYSCLK_FREQ_HSE    HSE_VALUE
-//#define SYSCLK_FREQ_48MHz_HSE  48000000
+// #define SYSCLK_FREQ_48MHz_HSE  48000000
 //#define SYSCLK_FREQ_56MHz_HSE  56000000
-//#define SYSCLK_FREQ_72MHz_HSE  72000000
+// #define SYSCLK_FREQ_72MHz_HSE  72000000
 // #define SYSCLK_FREQ_96MHz_HSE  96000000
 //#define SYSCLK_FREQ_120MHz_HSE  120000000
-#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
 //#define SYSCLK_FREQ_HSI    HSI_VALUE
 //#define SYSCLK_FREQ_48MHz_HSI  48000000
 //#define SYSCLK_FREQ_56MHz_HSI  56000000
@@ -109,6 +109,16 @@ static void SetSysClockTo144_HSI( void );
  */
 void SystemInit (void)
 {
+  // Enable Flash enhance read mode for full 224KB
+#if defined(CH32_FLASH_ENHANCE_READ_MODE) && CH32_FLASH_ENHANCE_READ_MODE == 1
+  FLASH->KEYR = 0x45670123; // FLASH_Unlock_Fast();
+  FLASH->KEYR = 0xCDEF89AB;
+
+  FLASH->CTLR |= (1 << 24); // Enhanced Read Mode
+
+  FLASH->CTLR |= (1 << 15); // FLASH_Lock_Fast();
+#endif
+
   RCC->CTLR |= (uint32_t)0x00000001;
   RCC->CFGR0 &= (uint32_t)0xF8FF0000;
   RCC->CTLR &= (uint32_t)0xFEF6FFFF;
diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h
deleted file mode 100644
index a7ce10a00..000000000
--- a/hw/bsp/ch32v307/core_riscv.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
-* File Name          : core_riscv.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : RISC-V Core Peripheral Access Layer Header File for CH32V30x
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#ifndef __CORE_RISCV_H__
-#define __CORE_RISCV_H__
-
-/* IO definitions */
-#ifdef __cplusplus
-  #define     __I     volatile                /* defines 'read only' permissions */
-#else
-  #define     __I     volatile const          /* defines 'read only' permissions */
-#endif
-#define     __O     volatile                  /* defines 'write only' permissions */
-#define     __IO    volatile                  /* defines 'read / write' permissions */
-
-/* Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef __I uint64_t vuc64;  /* Read Only */
-typedef __I uint32_t vuc32;  /* Read Only */
-typedef __I uint16_t vuc16;  /* Read Only */
-typedef __I uint8_t vuc8;   /* Read Only */
-
-typedef const uint64_t uc64;  /* Read Only */
-typedef const uint32_t uc32;  /* Read Only */
-typedef const uint16_t uc16;  /* Read Only */
-typedef const uint8_t uc8;   /* Read Only */
-
-typedef __I int64_t vsc64;  /* Read Only */
-typedef __I int32_t vsc32;  /* Read Only */
-typedef __I int16_t vsc16;  /* Read Only */
-typedef __I int8_t vsc8;   /* Read Only */
-
-typedef const int64_t sc64;  /* Read Only */
-typedef const int32_t sc32;  /* Read Only */
-typedef const int16_t sc16;  /* Read Only */
-typedef const int8_t sc8;   /* Read Only */
-
-typedef __IO uint64_t  vu64;
-typedef __IO uint32_t  vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t  vu8;
-
-typedef uint64_t  u64;
-typedef uint32_t  u32;
-typedef uint16_t u16;
-typedef uint8_t  u8;
-
-typedef __IO int64_t  vs64;
-typedef __IO int32_t  vs32;
-typedef __IO int16_t  vs16;
-typedef __IO int8_t   vs8;
-
-typedef int64_t  s64;
-typedef int32_t  s32;
-typedef int16_t s16;
-typedef int8_t  s8;
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-#define   RV_STATIC_INLINE  static  inline
-
-/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
-typedef struct{
-  __I  uint32_t ISR[8];
-  __I  uint32_t IPR[8];
-  __IO uint32_t ITHRESDR;
-  __IO uint32_t RESERVED;
-  __IO uint32_t CFGR;
-  __I  uint32_t GISR;
-  uint8_t VTFIDR[4];
-  uint8_t RESERVED0[12];
-  __IO uint32_t VTFADDR[4];
-  uint8_t RESERVED1[0x90];
-  __O  uint32_t IENR[8];
-  uint8_t RESERVED2[0x60];
-  __O  uint32_t IRER[8];
-  uint8_t RESERVED3[0x60];
-  __O  uint32_t IPSR[8];
-  uint8_t RESERVED4[0x60];
-  __O  uint32_t IPRR[8];
-  uint8_t RESERVED5[0x60];
-  __IO uint32_t IACTR[8];
-  uint8_t RESERVED6[0xE0];
-  __IO uint8_t IPRIOR[256];
-  uint8_t RESERVED7[0x810];
-  __IO uint32_t SCTLR;
-}PFIC_Type;
-
-/* memory mapped structure for SysTick */
-typedef struct
-{
-    __IO u32 CTLR;
-    __IO u32 SR;
-    __IO u64 CNT;
-    __IO u64 CMP;
-}SysTick_Type;
-
-
-#define PFIC            ((PFIC_Type *) 0xE000E000 )
-#define NVIC            PFIC
-#define NVIC_KEY1       ((uint32_t)0xFA050000)
-#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
-#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
-
-#define SysTick         ((SysTick_Type *) 0xE000F000)
-
-
-/*********************************************************************
- * @fn      __enable_irq
- *
- * @brief   Enable Global Interrupt
- *
- * @return  none
- */
-RV_STATIC_INLINE void __enable_irq(void)
-{
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
-}
-
-/*********************************************************************
- * @fn      __disable_irq
- *
- * @brief   Disable Global Interrupt
- *
- * @return  none
- */
-RV_STATIC_INLINE void __disable_irq(void)
-{
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
-}
-
-/*********************************************************************
- * @fn      __NOP
- *
- * @brief   nop
- *
- * @return  none
- */
-RV_STATIC_INLINE void __NOP(void)
-{
-  __asm volatile ("nop");
-}
-
-/*********************************************************************
- * @fn      NVIC_EnableIRQ
- *
- * @brief   Enable Interrupt
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  none
- */
-RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_DisableIRQ
- *
- * @brief   Disable Interrupt
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  none
- */
-RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetStatusIRQ
- *
- * @brief   Get Interrupt Enable State
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  1 - Interrupt Enable
- *          0 - Interrupt Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetPendingIRQ
- *
- * @brief   Get Interrupt Pending State
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  1 - Interrupt Pending Enable
- *          0 - Interrupt Pending Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_SetPendingIRQ
- *
- * @brief   Set Interrupt Pending
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  None
- */
-RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_ClearPendingIRQ
- *
- * @brief   Clear Interrupt Pending
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  None
- */
-RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn      NVIC_GetActive
- *
- * @brief   Get Interrupt Active State
- *
- * @param   IRQn: Interrupt Numbers
- *
- * @return  1 - Interrupt Active
- *          0 - Interrupt No Active
- */
-RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn      NVIC_SetPriority
- *
- * @brief   Set Interrupt Priority
- *
- * @param   IRQn - Interrupt Numbers
- *          priority -
- *              bit7 - pre-emption priority
- *              bit6~bit4 - subpriority
- * @return  None
- */
-RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
-{
-  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
-}
-
-/*********************************************************************
- * @fn      __WFI
- *
- * @brief   Wait for Interrupt
- *
- * @return  None
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
-{
-  NVIC->SCTLR &= ~(1<<3);	// wfi
-  asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn      __WFE
- *
- * @brief   Wait for Events
- *
- * @return  None
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
-{
-  uint32_t t;
-
-  t = NVIC->SCTLR;
-  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
-  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
-  asm volatile ("wfi");
-  asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn      SetVTFIRQ
- *
- * @brief   Set VTF Interrupt
- *
- * @param   add - VTF interrupt service function base address.
- *          IRQn -Interrupt Numbers
- *          num - VTF Interrupt Numbers
- *          NewState - DISABLE or ENABLE
- * @return  None
- */
-RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
-  if(num > 3)  return ;
-
-  if (NewState != DISABLE)
-  {
-      NVIC->VTFIDR[num] = IRQn;
-      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
-  }
-  else{
-      NVIC->VTFIDR[num] = IRQn;
-      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
-  }
-}
-
-/*********************************************************************
- * @fn      NVIC_SystemReset
- *
- * @brief   Initiate a system reset request
- *
- * @return  None
- */
-RV_STATIC_INLINE void NVIC_SystemReset(void)
-{
-  NVIC->CFGR = NVIC_KEY3|(1<<7);
-}
-
-
-/* Core_Exported_Functions */
-extern uint32_t __get_FFLAGS(void);
-extern void __set_FFLAGS(uint32_t value);
-extern uint32_t __get_FRM(void);
-extern void __set_FRM(uint32_t value);
-extern uint32_t __get_FCSR(void);
-extern void __set_FCSR(uint32_t value);
-extern uint32_t __get_MSTATUS(void);
-extern void __set_MSTATUS(uint32_t value);
-extern uint32_t __get_MISA(void);
-extern void __set_MISA(uint32_t value);
-extern uint32_t __get_MIE(void);
-extern void __set_MIE(uint32_t value);
-extern uint32_t __get_MTVEC(void);
-extern void __set_MTVEC(uint32_t value);
-extern uint32_t __get_MSCRATCH(void);
-extern void __set_MSCRATCH(uint32_t value);
-extern uint32_t __get_MEPC(void);
-extern void __set_MEPC(uint32_t value);
-extern uint32_t __get_MCAUSE(void);
-extern void __set_MCAUSE(uint32_t value);
-extern uint32_t __get_MTVAL(void);
-extern void __set_MTVAL(uint32_t value);
-extern uint32_t __get_MIP(void);
-extern void __set_MIP(uint32_t value);
-extern uint32_t __get_MCYCLE(void);
-extern void __set_MCYCLE(uint32_t value);
-extern uint32_t __get_MCYCLEH(void);
-extern void __set_MCYCLEH(uint32_t value);
-extern uint32_t __get_MINSTRET(void);
-extern void __set_MINSTRET(uint32_t value);
-extern uint32_t __get_MINSTRETH(void);
-extern void __set_MINSTRETH(uint32_t value);
-extern uint32_t __get_MVENDORID(void);
-extern uint32_t __get_MARCHID(void);
-extern uint32_t __get_MIMPID(void);
-extern uint32_t __get_MHARTID(void);
-extern uint32_t __get_SP(void);
-
-
-#endif
diff --git a/hw/bsp/ch32v307/debug_uart.c b/hw/bsp/ch32v307/debug_uart.c
index fbabeeadc..2fd3a9d64 100644
--- a/hw/bsp/ch32v307/debug_uart.c
+++ b/hw/bsp/ch32v307/debug_uart.c
@@ -25,8 +25,17 @@
  */
 
 #include "debug_uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
 #include <ch32v30x.h>
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
 
 #define UART_RINGBUFFER_SIZE_TX 128
 #define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index 0846b10a9..adf2dbea5 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -25,9 +25,22 @@
  */
 
 #include "stdio.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
 #include "debug_uart.h"
 #include "ch32v30x.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "bsp/board_api.h"
 #include "board.h"
 
diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake
index af26bfc31..d603af62d 100644
--- a/hw/bsp/ch32v307/family.cmake
+++ b/hw/bsp/ch32v307/family.cmake
@@ -49,6 +49,7 @@ function(add_board_target BOARD_TARGET)
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
     ${SDK_SRC_DIR}/Peripheral/inc
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     )
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 30a070a9b..bf2732106 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -25,6 +25,9 @@ CFLAGS += \
 	-fsigned-char \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
 
+# https://github.com/openwch/ch32v307/pull/90
+CFLAGS += -Wno-error=strict-prototypes
+
 ifeq ($(SPEED),high)
   $(info "Using USBHS driver for HighSpeed mode")
   CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
@@ -51,6 +54,7 @@ SRC_S += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
 	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
 
 # For freeRTOS port source
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
deleted file mode 100644
index 667b83de3..000000000
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jerzy Kasenberg
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include <hal/hal_gpio.h>
-#include <mcu/mcu.h>
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PIN         33 // P1.1
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   (1-LED_STATE_ON)
-
-#define BUTTON_PIN      6
-
-void UnhandledIRQ(void)
-{
-  CRG_TOP->SYS_CTRL_REG = 0x80;
-  __BKPT(1);
-  while(1);
-}
-
-// DA146xx driver function that must be called whenever VBUS changes.
-extern void tusb_vbus_changed(bool present);
-
-void board_init(void)
-{
-  // LED
-  hal_gpio_init_out(LED_PIN, LED_STATE_ON);
-
-  hal_gpio_init_out(1, 0);
-  hal_gpio_init_out(2, 0);
-  hal_gpio_init_out(3, 0);
-  hal_gpio_init_out(4, 0);
-  hal_gpio_init_out(5, 0);
-
-  // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUD_ENABLED
-  // This board is USB powered there is no need to monitor
-  // VBUS line.  Notify driver that VBUS is present.
-  tusb_vbus_changed(true);
-
-  /* Setup USB IRQ */
-  NVIC_SetPriority(USB_IRQn, 2);
-  NVIC_EnableIRQ(USB_IRQn);
-
-  /* Use PLL96 / 2 clock not HCLK */
-  CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
-
-  mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-  mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active HIGH
-  return hal_gpio_read(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
-
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4d4379a6f
--- /dev/null
+++ b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "DA1469xAB.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+#define configRUN_FREERTOS_SECURE_ONLY          1
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake b/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake
new file mode 100644
index 000000000..f9ef2dc86
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.cmake
@@ -0,0 +1,4 @@
+set(JLINK_DEVICE DA14695)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h
new file mode 100644
index 000000000..5efdd43e0
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h
@@ -0,0 +1,10 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PIN         33 // P1.1
+#define LED_STATE_ON    1
+
+#define BUTTON_PIN      6
+#define BUTTON_STATE_ACTIVE 1
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk b/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk
new file mode 100644
index 000000000..1ca17ea00
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.mk
@@ -0,0 +1 @@
+JLINK_DEVICE = DA14695
diff --git a/hw/bsp/da14695_dk_usb/syscfg/syscfg.h b/hw/bsp/da1469x/boards/da14695_dk_usb/syscfg/syscfg.h
index 6cbb4319e..6cbb4319e 100644
--- a/hw/bsp/da14695_dk_usb/syscfg/syscfg.h
+++ b/hw/bsp/da1469x/boards/da14695_dk_usb/syscfg/syscfg.h
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake
new file mode 100644
index 000000000..f6408b72b
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.cmake
@@ -0,0 +1,4 @@
+set(JLINK_DEVICE DA14699)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h
new file mode 100644
index 000000000..f969acf90
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h
@@ -0,0 +1,12 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PIN         33
+#define LED_STATE_ON    1
+
+#define BUTTON_PIN      6
+#define BUTTON_STATE_ACTIVE 0
+
+#define NEED_VBUS_MONITOR
+
+#endif
diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk
new file mode 100644
index 000000000..40fe93b41
--- /dev/null
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.mk
@@ -0,0 +1,2 @@
+# For flash-jlink target
+JLINK_DEVICE = DA14699
diff --git a/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/syscfg/syscfg.h
index 6cbb4319e..6cbb4319e 100644
--- a/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h
+++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/syscfg/syscfg.h
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x/family.c
index 21bd62714..70bedf6d9 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x/family.c
@@ -25,24 +25,25 @@
  */
 
 #include "bsp/board_api.h"
+#include "board.h"
 #include <hal/hal_gpio.h>
 #include <mcu/mcu.h>
 
+#define LED_STATE_OFF   (1-LED_STATE_ON)
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-#if CFG_TUD_ENABLED
-// DA146xx driver function that must be called whenever VBUS changes
+// DA146xx driver function that must be called whenever VBUS changes.
 extern void tusb_vbus_changed(bool present);
 
+#if defined(NEED_VBUS_MONITOR) && CFG_TUD_ENABLED
 // VBUS change interrupt handler
-void VBUS_IRQHandler(void)
-{
+void VBUS_IRQHandler(void) {
   bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0;
   // Clear VBUS interrupt
   CRG_TOP->VBUS_IRQ_CLEAR_REG = 1;
@@ -54,22 +55,13 @@ void VBUS_IRQHandler(void)
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-
-#define LED_PIN         33
-#define LED_STATE_ON    1
-#define LED_STATE_OFF   0
-
-#define BUTTON_PIN      6
-
-void UnhandledIRQ(void)
-{
+void UnhandledIRQ(void) {
   CRG_TOP->SYS_CTRL_REG = 0x80;
   __BKPT(1);
-  while(1);
+  while (1);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // LED
   hal_gpio_init_out(LED_PIN, LED_STATE_ON);
 
@@ -80,12 +72,13 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP);
+  hal_gpio_init_in(BUTTON_PIN, BUTTON_STATE_ACTIVE ? HAL_GPIO_PULL_DOWN : HAL_GPIO_PULL_UP);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
 #if CFG_TUD_ENABLED
+  #ifdef NEED_VBUS_MONITOR
   // Setup interrupt for both connect and disconnect
   CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
                                CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
@@ -94,6 +87,10 @@ void board_init(void)
   // otherwise it could go unnoticed.
   NVIC_SetPendingIRQ(VBUS_IRQn);
   NVIC_EnableIRQ(VBUS_IRQn);
+  #else
+  // This board is USB powered there is no need to monitor VBUS line.  Notify driver that VBUS is present.
+  tusb_vbus_changed(true);
+  #endif
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -111,41 +108,35 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
 }
 
-uint32_t board_button_read(void)
-{
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == hal_gpio_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void)buf;
-  (void)len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void)buf;
-  (void)len;
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
 
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake
new file mode 100644
index 000000000..8c89141fe
--- /dev/null
+++ b/hw/bsp/da1469x/family.cmake
@@ -0,0 +1,141 @@
+include_guard()
+
+set(MCU_DIR ${TOP}/hw/mcu/dialog/da1469x)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(FAMILY_MCUS DA1469X CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/da1469x.ld)
+  endif ()
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/gcc_startup_da1469x.S)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${MCU_DIR}/src/system_da1469x.c
+    ${MCU_DIR}/src/da1469x_clock.c
+    ${MCU_DIR}/src/hal_gpio.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC -mthumb-interwork)
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CORE_M33
+    CFG_TUD_ENDPOINT0_SIZE=8
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    ${MCU_DIR}/include
+    ${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_DIR}/mdk
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -L${NRFX_DIR}/mdk
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+function(family_flash_jlink_dialog TARGET)
+  set(JLINKEXE JLinkExe)
+  set(JLINK_IF swd)
+
+  # mkimage from sdk
+  set(MKIMAGE $ENV{HOME}/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries/mkimage)
+
+  file(GENERATE OUTPUT $<TARGET_FILE_DIR:${TARGET}>/version.h
+    CONTENT "#define SW_VERSION \"v_1.0.0.1\"
+#define SW_VERSION_DATE \"2024-07-17 17:55\""
+    )
+
+  file(GENERATE OUTPUT $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    CONTENT "r
+halt
+loadfile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin 0x16000000
+r
+go
+exit"
+  )
+
+  add_custom_target(${TARGET}-image
+    DEPENDS ${TARGET}
+    COMMAND ${MKIMAGE} da1469x $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin $<TARGET_FILE_DIR:${TARGET}>/version.h $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin.img
+    COMMAND cp ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/product_header.dump $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin
+    COMMAND cat $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin.img >> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}-image.bin
+    )
+  add_custom_target(${TARGET}-jlink
+    DEPENDS ${TARGET}-image
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    )
+endfunction()
+
+
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_DA1469X ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink_dialog(${TARGET})
+endfunction()
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da1469x/family.mk
index 980b1a361..f35fe2cb5 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da1469x/family.mk
@@ -1,4 +1,6 @@
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+MCU_DIR = hw/mcu/dialog/da1469x
+
+include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
   -flto \
@@ -8,48 +10,52 @@ CFLAGS += \
   -mcpu=cortex-m33+nodsp \
   -mfloat-abi=hard \
   -mfpu=fpv5-sp-d16 \
-  -nostdlib \
   -DCORE_M33 \
   -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
   -DCFG_TUD_ENDPOINT0_SIZE=8\
 
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+  -nostdlib \
+  --specs=nosys.specs --specs=nano.specs
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
+LD_FILE = $(FAMILY_PATH)/linker/da1469x.ld
 
 # While this is for da1469x chip, there is chance that da1468x chip family will also work
 SRC_C += \
 	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
+	${MCU_DIR}/src/system_da1469x.c \
+	${MCU_DIR}/src/da1469x_clock.c \
+	${MCU_DIR}/src/hal_gpio.c \
 
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
+SRC_S += $(FAMILY_PATH)/gcc_startup_da1469x.S
 
 INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/${MCU_DIR}/include \
+	$(TOP)/${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 
-# For flash-jlink target
-JLINK_DEVICE = DA14695
-
 # flash using jlink but with some twists
 flash: flash-dialog
 
-flash-dialog: $(BUILD)/$(PROJECT).bin
+# SDK_BINARY_PATH is the path to the SDK binary files
+SDK_BINARY_PATH = $(HOME)/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries
+MKIMAGE = $(SDK_BINARY_PATH)/mkimage
+
+$(BUILD)/$(PROJECT)-image.bin: $(BUILD)/$(PROJECT).bin
 	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
+	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >> $(BUILD)/version.h
+	$(MKIMAGE) da1469x $^ $(BUILD)/version.h $^.img
+	cp $(TOP)/$(FAMILY_PATH)/product_header.dump $(BUILD)/$(PROJECT)-image.bin
+	cat $^.img >> $(BUILD)/$(PROJECT)-image.bin
+
+flash-dialog: $(BUILD)/$(PROJECT)-image.bin
 	@echo r > $(BUILD)/$(BOARD).jlink
 	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
+	@echo loadfile $^ 0x16000000 >> $(BUILD)/$(BOARD).jlink
 	@echo r >> $(BUILD)/$(BOARD).jlink
 	@echo go >> $(BUILD)/$(BOARD).jlink
 	@echo exit >> $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S b/hw/bsp/da1469x/gcc_startup_da1469x.S
index d47fbcd97..d47fbcd97 100644
--- a/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S
+++ b/hw/bsp/da1469x/gcc_startup_da1469x.S
diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da1469x/linker/da1469x.ld
index 8cc1d9d99..8cc1d9d99 100644
--- a/hw/bsp/da14695_dk_usb/da1469x.ld
+++ b/hw/bsp/da1469x/linker/da1469x.ld
diff --git a/hw/bsp/da14695_dk_usb/product_header.dump b/hw/bsp/da1469x/product_header.dump
index ea4842242..ea4842242 100644
--- a/hw/bsp/da14695_dk_usb/product_header.dump
+++ b/hw/bsp/da1469x/product_header.dump
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
deleted file mode 100644
index 5282f93a3..000000000
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mthumb-interwork \
-  -mabi=aapcs \
-  -mcpu=cortex-m33+nodsp \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
-  -nostdlib \
-  -DCORE_M33 \
-  -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-  -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
-	src/portable/dialog/da146xx/dcd_da146xx.c \
-	$(MCU_FAMILY_DIR)/src/system_da1469x.c \
-	$(MCU_FAMILY_DIR)/src/da1469x_clock.c \
-	$(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_FAMILY_DIR)/include \
-	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14699
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
-	@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
-	@echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
-	mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
-	cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
-	cat $^.img >> $(BUILD)/$(BOARD)-image.bin
-	@echo r > $(BUILD)/$(BOARD).jlink
-	@echo halt >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld
deleted file mode 100644
index 8cc1d9d99..000000000
--- a/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-MEMORY
-{
-    /*
-     * Flash is remapped at 0x0 by 1st stage bootloader, but this is done with
-     * an offset derived from image header thus it is safer to use remapped
-     * address space at 0x0 instead of QSPI_M address space at 0x16000000.
-     * Bootloader partition is 32K, but 9K is currently reserved for product
-     * header (8K) and image header (1K).
-     * First 512 bytes of SYSRAM are remapped at 0x0 and used as ISR vector
-     * (there's no need to reallocate ISR vector) and thus cannot be used by
-     * application.
-     */
-
-    FLASH (r)  : ORIGIN = (0x00000000), LENGTH = (1024 * 1024)
-    RAM (rw)   : ORIGIN = (0x20000000), LENGTH = (512 * 1024)
-}
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __bssnz_start__
- *   __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    __text = .;
-
-    .text :
-    {
-        __isr_vector_start = .;
-        KEEP(*(.isr_vector))
-        /* ISR vector shall have exactly 512 bytes */
-        . = __isr_vector_start + 0x200;
-        __isr_vector_end = .;
-
-        *(.text)
-        *(.text.*)
-
-        *(.libcmac.rom)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        *(.eh_frame*)
-        . = ALIGN(4);
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        . = ALIGN(4);
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-        . = ALIGN(4);
-    } > FLASH
-    __exidx_end = .;
-
-    .intvect :
-    {
-        . = ALIGN(4);
-        __intvect_start__ = .;
-        . = . + (__isr_vector_end - __isr_vector_start);
-        . = ALIGN(4);
-    } > RAM
-
-    .sleep_state (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(sleep_state)
-    } > RAM
-
-    /* This section will be zeroed by RTT package init */
-    .rtt (NOLOAD):
-    {
-        . = ALIGN(4);
-        *(.rtt)
-        . = ALIGN(4);
-    } > RAM
-
-    __text_ram_addr = LOADADDR(.text_ram);
-
-    .text_ram :
-    {
-        . = ALIGN(4);
-        __text_ram_start__ = .;
-        *(.text_ram*)
-        . = ALIGN(4);
-        __text_ram_end__ = .;
-    } > RAM AT > FLASH
-
-    __etext = LOADADDR(.data);
-
-    .data :
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        *(.preinit_array)
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        *(SORT(.init_array.*))
-        *(.init_array)
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        *(SORT(.fini_array.*))
-        *(.fini_array)
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        *(.jcr)
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-    } > RAM AT > FLASH
-
-    .bssnz :
-    {
-        . = ALIGN(4);
-        __bssnz_start__ = .;
-        *(.bss.core.nz*)
-        . = ALIGN(4);
-        __bssnz_end__ = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .cmac (NOLOAD) :
-    {
-        . = ALIGN(0x400);
-        *(.libcmac.ram)
-    } > RAM
-
-    /* Heap starts after BSS */
-    . = ALIGN(8);
-    __HeapBase = .;
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    _ram_start = ORIGIN(RAM);
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Top of head is the bottom of the stack */
-    __HeapLimit = __StackLimit;
-    end = __HeapLimit;
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
-    /* Check that intvect is at the beginning of RAM */
-    ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
diff --git a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S b/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
deleted file mode 100644
index d47fbcd97..000000000
--- a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
- #include "syscfg/syscfg.h"
-
-    .syntax unified
-    .arch   armv7-m
-
-    .section .stack
-    .align  3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xC00
-#endif
-    .equ    SYS_CTRL_REG,       0x50000024
-    .equ    CACHE_FLASH_REG,    0x100C0040
-    .equ    RESET_STAT_REG,     0x500000BC
-
-    .globl  __StackTop
-    .globl  __StackLimit
-__StackLimit:
-    .space  Stack_Size
-    .size   __StackLimit, . - __StackLimit
-__StackTop:
-    .size   __StackTop, . - __StackTop
-
-    .section .heap
-    .align  3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0
-#endif
-    .globl  __HeapBase
-    .globl  __HeapLimit
-__HeapBase:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-    .size   __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size   __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 2
-    .globl  __isr_vector
-__isr_vector:
-    .long   __StackTop
-    .long   Reset_Handler
-    /* Cortex-M33 interrupts */
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   MemoryManagement_Handler
-    .long   BusFault_Handler
-    .long   UsageFault_Handler
-    .long   SecureFault_Handler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   SVC_Handler
-    .long   DebugMonitor_Handler
-    .long   0                       /* Reserved */
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-    /* DA1469x interrupts */
-    .long   SENSOR_NODE_IRQHandler
-    .long   DMA_IRQHandler
-    .long   CHARGER_STATE_IRQHandler
-    .long   CHARGER_ERROR_IRQHandler
-    .long   CMAC2SYS_IRQHandler
-    .long   UART_IRQHandler
-    .long   UART2_IRQHandler
-    .long   UART3_IRQHandler
-    .long   I2C_IRQHandler
-    .long   I2C2_IRQHandler
-    .long   SPI_IRQHandler
-    .long   SPI2_IRQHandler
-    .long   PCM_IRQHandler
-    .long   SRC_IN_IRQHandler
-    .long   SRC_OUT_IRQHandler
-    .long   USB_IRQHandler
-    .long   TIMER_IRQHandler
-    .long   TIMER2_IRQHandler
-    .long   RTC_IRQHandler
-    .long   KEY_WKUP_GPIO_IRQHandler
-    .long   PDC_IRQHandler
-    .long   VBUS_IRQHandler
-    .long   MRM_IRQHandler
-    .long   MOTOR_CONTROLLER_IRQHandler
-    .long   TRNG_IRQHandler
-    .long   DCDC_IRQHandler
-    .long   XTAL32M_RDY_IRQHandler
-    .long   ADC_IRQHandler
-    .long   ADC2_IRQHandler
-    .long   CRYPTO_IRQHandler
-    .long   CAPTIMER1_IRQHandler
-    .long   RFDIAG_IRQHandler
-    .long   LCD_CONTROLLER_IRQHandler
-    .long   PLL_LOCK_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   TIMER4_IRQHandler
-    .long   LRA_IRQHandler
-    .long   RTC_EVENT_IRQHandler
-    .long   GPIO_P0_IRQHandler
-    .long   GPIO_P1_IRQHandler
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .long   0                       /* Reserved */
-    .size   __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
- /* Make sure interrupt vector is remapped at 0x0 */
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #8
-    strh    r2, [r1, #0]
-
-#if !MYNEWT_VAL(RAM_RESIDENT)
-/*
- * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
- * 0x16000000 but to start of an image on flash. This is calculated from product
- * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
- * retrieve proper offset value for calculations later.
- */
-    ldr     r1, =CACHE_FLASH_REG
-    ldr     r4, [r1, #0]
-    mov     r2, r4
-    mov     r3, #0xFFFF
-    bic     r4, r4, r3      /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
-    mov     r3, #0xFFF0
-    and     r2, r2, r3      /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
-    lsr     r2, r2, #2
-    orr     r4, r4, r2
-
-/* Copy ISR vector from flash to RAM */
-    ldr     r1, =__isr_vector_start     /* src ptr */
-    ldr     r2, =__isr_vector_end       /* src end */
-    ldr     r3, =__intvect_start__      /* dst ptr */
-/* Make sure we copy from QSPIC address range, not from remapped range */
-    cmp     r1, r4
-    itt     lt
-    addlt   r1, r1, r4
-    addlt   r2, r2, r4
-.loop_isr_copy:
-    cmp     r1, r2
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r3], #4
-    blt     .loop_isr_copy
-
-/* Copy QSPI code from flash to RAM */
-    ldr     r1, =__text_ram_addr        /* src ptr */
-    ldr     r2, =__text_ram_start__     /* ptr */
-    ldr     r3, =__text_ram_end__       /* dst end */
-.loop_code_text_ram_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_code_text_ram_copy
-
-/* Copy data from flash to RAM */
-    ldr     r1, =__etext                /* src ptr */
-    ldr     r2, =__data_start__         /* dst ptr */
-    ldr     r3, =__data_end__           /* dst end */
-.loop_data_copy:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt     .loop_data_copy
-#endif
-
-/* Clear BSS */
-    movs    r0, 0
-    ldr     r1, =__bss_start__
-    ldr     r2, =__bss_end__
-.loop_bss_clear:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt     .loop_bss_clear
-
-    ldr     r0, =__HeapBase
-    ldr     r1, =__HeapLimit
-/* Call static constructors */
-    bl __libc_init_array
-
-    bl      SystemInit
-    bl      main
-
-    .pool
-    .size   Reset_Handler, . - Reset_Handler
-
-/* Default interrupt handler */
-    .type   Default_Handler, %function
-Default_Handler:
-    ldr     r1, =SYS_CTRL_REG
-    ldrh    r2, [r1, #0]
-    orrs    r2, r2, #0x80   /* DEBUGGER_ENABLE */
-    strh    r2, [r1, #0]
-    b       .
-
-    .size   Default_Handler, . - Default_Handler
-
-/* Default handlers for all interrupts */
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    /* Cortex-M33 interrupts */
-    IRQ  NMI_Handler
-    IRQ  HardFault_Handler
-    IRQ  MemoryManagement_Handler
-    IRQ  BusFault_Handler
-    IRQ  UsageFault_Handler
-    IRQ  SecureFault_Handler
-    IRQ  SVC_Handler
-    IRQ  DebugMonitor_Handler
-    IRQ  PendSV_Handler
-    IRQ  SysTick_Handler
-    /* DA1469x interrupts */
-    IRQ  SENSOR_NODE_IRQHandler
-    IRQ  DMA_IRQHandler
-    IRQ  CHARGER_STATE_IRQHandler
-    IRQ  CHARGER_ERROR_IRQHandler
-    IRQ  CMAC2SYS_IRQHandler
-    IRQ  UART_IRQHandler
-    IRQ  UART2_IRQHandler
-    IRQ  UART3_IRQHandler
-    IRQ  I2C_IRQHandler
-    IRQ  I2C2_IRQHandler
-    IRQ  SPI_IRQHandler
-    IRQ  SPI2_IRQHandler
-    IRQ  PCM_IRQHandler
-    IRQ  SRC_IN_IRQHandler
-    IRQ  SRC_OUT_IRQHandler
-    IRQ  USB_IRQHandler
-    IRQ  TIMER_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC_IRQHandler
-    IRQ  KEY_WKUP_GPIO_IRQHandler
-    IRQ  PDC_IRQHandler
-    IRQ  VBUS_IRQHandler
-    IRQ  MRM_IRQHandler
-    IRQ  MOTOR_CONTROLLER_IRQHandler
-    IRQ  TRNG_IRQHandler
-    IRQ  DCDC_IRQHandler
-    IRQ  XTAL32M_RDY_IRQHandler
-    IRQ  ADC_IRQHandler
-    IRQ  ADC2_IRQHandler
-    IRQ  CRYPTO_IRQHandler
-    IRQ  CAPTIMER1_IRQHandler
-    IRQ  RFDIAG_IRQHandler
-    IRQ  LCD_CONTROLLER_IRQHandler
-    IRQ  PLL_LOCK_IRQHandler
-    IRQ  TIMER3_IRQHandler
-    IRQ  TIMER4_IRQHandler
-    IRQ  LRA_IRQHandler
-    IRQ  RTC_EVENT_IRQHandler
-    IRQ  GPIO_P0_IRQHandler
-    IRQ  GPIO_P1_IRQHandler
-    IRQ  RESERVED40_IRQHandler
-    IRQ  RESERVED41_IRQHandler
-    IRQ  RESERVED42_IRQHandler
-    IRQ  RESERVED43_IRQHandler
-    IRQ  RESERVED44_IRQHandler
-    IRQ  RESERVED45_IRQHandler
-    IRQ  RESERVED46_IRQHandler
-    IRQ  RESERVED47_IRQHandler
-
-.end
diff --git a/hw/bsp/da1469x_dk_pro/product_header.dump b/hw/bsp/da1469x_dk_pro/product_header.dump
deleted file mode 100644
index ea4842242..000000000
--- a/hw/bsp/da1469x_dk_pro/product_header.dump
+++ /dev/null
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d9443f811..03a24c95b 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -69,6 +69,10 @@ if (NOT FAMILY STREQUAL rp2040)
   endif()
 endif()
 
+if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED)
+  set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1)
+endif()
+
 set(WARNING_FLAGS_GNU
   -Wall
   -Wextra
@@ -140,7 +144,6 @@ function(family_filter RESULT DIR)
   endif()
 endfunction()
 
-
 function(family_add_subdirectory DIR)
   family_filter(SHOULD_ADD "${DIR}")
   if (SHOULD_ADD)
@@ -148,13 +151,11 @@ function(family_add_subdirectory DIR)
   endif()
 endfunction()
 
-
 function(family_get_project_name OUTPUT_NAME DIR)
   get_filename_component(SHORT_NAME ${DIR} NAME)
   set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
 endfunction()
 
-
 function(family_initialize_project PROJECT DIR)
   # set output suffix to .elf (skip espressif and rp2040)
   if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040")
@@ -168,7 +169,6 @@ function(family_initialize_project PROJECT DIR)
   endif()
 endfunction()
 
-
 #-------------------------------------------------------------
 # Common Target Configure
 # Most families use these settings except rp2040 and espressif
@@ -194,7 +194,6 @@ function(family_add_rtos TARGET RTOS)
   endif ()
 endfunction()
 
-
 # Add common configuration to example
 function(family_configure_common TARGET RTOS)
   family_add_rtos(${TARGET} ${RTOS})
@@ -205,20 +204,17 @@ function(family_configure_common TARGET RTOS)
     BOARD_${BOARD_UPPER}
   )
 
-  # run size after build
-  find_program(SIZE_EXE ${CMAKE_SIZE})
-  if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND)
-    add_custom_command(TARGET ${TARGET} POST_BUILD
-      COMMAND ${SIZE_EXE} $<TARGET_FILE:${TARGET}>
-      )
-  endif ()
-  # Add warnings flags
+  # compile define from command line
+  if(DEFINED CFLAGS_CLI)
+    target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+  endif()
+
   target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}})
 
   # Generate linker map file
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map")
-    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED)
       target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
     endif ()
  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
@@ -235,7 +231,6 @@ function(family_configure_common TARGET RTOS)
   # LOGGER option
   if (DEFINED LOGGER)
     target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
-
     # Add segger rtt to example
     if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
       if (NOT TARGET segger_rtt)
@@ -246,8 +241,15 @@ function(family_configure_common TARGET RTOS)
       target_link_libraries(${TARGET} PUBLIC segger_rtt)
     endif ()
   endif ()
-endfunction()
 
+  # run size after build
+  find_program(SIZE_EXE ${CMAKE_SIZE})
+  if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND)
+    add_custom_command(TARGET ${TARGET} POST_BUILD
+      COMMAND ${SIZE_EXE} $<TARGET_FILE:${TARGET}>
+      )
+  endif ()
+endfunction()
 
 # Add tinyusb to example
 function(family_add_tinyusb TARGET OPT_MCU RTOS)
@@ -289,7 +291,6 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
 
 endfunction()
 
-
 # Add bin/hex output
 function(family_add_bin_hex TARGET)
   add_custom_command(TARGET ${TARGET} POST_BUILD
@@ -363,7 +364,7 @@ function(family_add_default_example_warnings TARGET)
     )
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED)
       target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
     endif()
 
@@ -398,6 +399,11 @@ function(family_flash_jlink TARGET)
     set(JLINK_IF swd)
   endif ()
 
+  if (NOT DEFINED JLINK_OPTION)
+    set(JLINK_OPTION "")
+  endif ()
+  separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION})
+
   file(GENERATE
     OUTPUT $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
     CONTENT "halt
@@ -409,7 +415,8 @@ exit"
 
   add_custom_target(${TARGET}-jlink
     DEPENDS ${TARGET}
-    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.jlink
+    VERBATIM
     )
 endfunction()
 
@@ -427,6 +434,19 @@ function(family_flash_stlink TARGET)
 endfunction()
 
 
+# Add flash st-flash target
+function(family_flash_stflash TARGET)
+  if (NOT DEFINED ST_FLASH)
+    set(ST_FLASH st-flash)
+  endif ()
+
+  add_custom_target(${TARGET}-stflash
+    DEPENDS ${TARGET}
+    COMMAND ${ST_FLASH} write $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin 0x8000000
+    )
+endfunction()
+
+
 # Add flash openocd target
 function(family_flash_openocd TARGET)
   if (NOT DEFINED OPENOCD)
@@ -443,11 +463,12 @@ function(family_flash_openocd TARGET)
   # note skip verify since it has issue with rp2040
   add_custom_target(${TARGET}-openocd
     DEPENDS ${TARGET}
-    COMMAND ${OPENOCD} ${OPTION_LIST} -c "program $<TARGET_FILE:${TARGET}> reset" ${OPTION_LIST2} -c exit
+    COMMAND ${OPENOCD} ${OPTION_LIST} -c init -c halt -c "program $<TARGET_FILE:${TARGET}> reset" ${OPTION_LIST2} -c exit
     VERBATIM
     )
 endfunction()
 
+
 # Add flash openocd-wch target
 # compiled from https://github.com/hathach/riscv-openocd-wch or https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
 function(family_flash_openocd_wch TARGET)
@@ -458,6 +479,20 @@ function(family_flash_openocd_wch TARGET)
   family_flash_openocd(${TARGET})
 endfunction()
 
+
+# Add flash with https://github.com/ch32-rs/wlink
+function(family_flash_wlink_rs TARGET)
+  if (NOT DEFINED WLINK_RS)
+    set(WLINK_RS wlink)
+  endif ()
+
+  add_custom_target(${TARGET}-wlink-rs
+    DEPENDS ${TARGET}
+    COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}>
+    )
+endfunction()
+
+
 # Add flash pycod target
 function(family_flash_pyocd TARGET)
   if (NOT DEFINED PYOC)
@@ -470,6 +505,7 @@ function(family_flash_pyocd TARGET)
     )
 endfunction()
 
+
 # Flash with UF2
 function(family_flash_uf2 TARGET FAMILY_ID)
   add_custom_target(${TARGET}-uf2
@@ -478,6 +514,7 @@ function(family_flash_uf2 TARGET FAMILY_ID)
     )
 endfunction()
 
+
 # Add flash teensy_cli target
 function(family_flash_teensy TARGET)
   if (NOT DEFINED TEENSY_CLI)
@@ -490,6 +527,7 @@ function(family_flash_teensy TARGET)
     )
 endfunction()
 
+
 # Add flash using NXP's LinkServer (redserver)
 # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
 function(family_flash_nxplink TARGET)
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index c9c4918ef..2f305aa4d 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -40,6 +40,7 @@
 #include "fsl_iomuxc.h"
 #include "fsl_clock.h"
 #include "fsl_lpuart.h"
+#include "fsl_ocotp.h"
 
 #ifdef __GNUC__
 #pragma GCC diagnostic pop
@@ -186,6 +187,29 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+
+  #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
+  OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
+  #else
+  OCOTP_Init(OCOTP, 0u);
+  #endif
+
+  // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
+  // into 8 bit wide destination, avoiding punning.
+  for (int i = 0; i < 4; ++i) {
+    uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
+    for (int j = 0; j < 4; j++) {
+      id[i*4+j] = wr & 0xff;
+      wr >>= 8;
+    }
+  }
+  OCOTP_Deinit(OCOTP);
+
+  return 16;
+}
+
 int board_uart_read(uint8_t* buf, int len) {
   int count = 0;
 
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f4d7378a5..d917e9777 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -44,6 +44,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/igpio/fsl_gpio.c
     ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
     ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -75,6 +76,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/drivers/igpio
     ${SDK_DIR}/drivers/lpspi
     ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/ocotp
     )
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index bde4c4ba6..f00afb6a4 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -50,7 +50,8 @@ SRC_C += \
 	$(SDK_DIR)/drivers/common/fsl_common.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/igpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \
+	$(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \
 
 # Optional drivers: only available for some mcus: rt1160, rt1170
 ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c))
@@ -68,7 +69,8 @@ INC += \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/igpio \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(SDK_DIR)/drivers/ocotp \
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S
 
diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c
index bff7110b8..e75bc4919 100644
--- a/hw/bsp/lpc11/family.c
+++ b/hw/bsp/lpc11/family.c
@@ -90,6 +90,13 @@ void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  if ( max_len < 16 ) return 0;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  id32[0] = Chip_IAP_ReadUID();
+  return 4;
+}
+
 uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake
index f17a48dd7..818600656 100644
--- a/hw/bsp/lpc11/family.cmake
+++ b/hw/bsp/lpc11/family.cmake
@@ -30,6 +30,7 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
     ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
     ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/iap.c
     ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
     ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
     )
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
index 09713fd55..a3ec33768 100644
--- a/hw/bsp/lpc11/family.mk
+++ b/hw/bsp/lpc11/family.mk
@@ -9,13 +9,18 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+# mcu driver cause following warnings
+CFLAGS += \
+  -Wno-error=incompatible-pointer-types \
+
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc$(MCU_DRV).c \
 	$(MCU_DIR)/src/chip_$(MCU_DRV).c \
 	$(MCU_DIR)/src/clock_$(MCU_DRV).c \
+	$(MCU_DIR)/src/iap.c \
 	$(MCU_DIR)/src/iocon_$(MCU_DRV).c \
 	$(MCU_DIR)/src/sysinit_$(MCU_DRV).c
 
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
index 6f10a7ab0..d3f357576 100644
--- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -52,6 +52,7 @@
 #define configENABLE_FPU                        1
 #define configENABLE_TRUSTZONE                  0
 #define configMINIMAL_SECURE_STACK_SIZE         (1024)
+#define configRUN_FREERTOS_SECURE_ONLY          1
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index cfd5b7032..075832ea7 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -81,51 +81,85 @@ void USB1_IRQHandler(void) {
 }
 
 /****************************************************************
-name: BOARD_BootClockFROHF96M
+name: BOARD_BootClockPLL100M
 outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
 settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
 sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
 ******************************************************************/
-void BootClockFROHF96M(void) {
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on  */
-  CLOCK_SetupFROClocking(12000000U);     /*!< Set up FRO to the 12 MHz, just for sure */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
 
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
 
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
 
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
+    POWER_SetVoltageForFreq(100000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(100000000U);          /*!< Set FLASH wait states for core */
 
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 100000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
 
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*< Set SystemCoreClock variable. */
+    SystemCoreClock = 100000000U;
 }
 
 void board_init(void) {
   // Enable IOCON clock
   CLOCK_EnableClock(kCLOCK_Iocon);
 
-  // Init 96 MHz clock
-  BootClockFROHF96M();
+  // Init 100 MHz clock
+  BOARD_BootClockPLL100M();
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   // Init all GPIO ports
@@ -239,6 +273,10 @@ void board_init(void) {
 //  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
 //  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
 //  USBPHY->TX = phytx;
+
+    ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
+    ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
 #endif
 }
 
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index db8988a36..a8b4ebcc7 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -147,6 +147,13 @@ uint32_t board_button_read(void) {
   return lvl == BUTTON_STATE_ACTIVE;
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  max_len = tu_min32(max_len, sizeof(bsp_unique_id_t));
+  bsp_unique_id_t const *uid = R_BSP_UniqueIdGet();
+  memcpy(id, uid->unique_id_bytes, max_len);
+  return max_len;
+}
+
 int board_uart_read(uint8_t *buf, int len) {
   (void) buf;
   (void) len;
@@ -169,7 +176,6 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
-
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 3849894ce..733e93797 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -78,7 +78,12 @@
 // USB Host MAX3421E
 //--------------------------------------------------------------------
 
-#define MAX3421_SPI      PICO_DEFAULT_SPI_INSTANCE
+#ifdef PICO_DEFAULT_SPI
+#define MAX3421_SPI      PICO_DEFAULT_SPI // sdk v2
+#else
+#define MAX3421_SPI      PICO_DEFAULT_SPI_INSTANCE // sdk v1
+#endif
+
 #define MAX3421_SCK_PIN  PICO_DEFAULT_SPI_SCK_PIN
 #define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN
 #define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index cffb632f3..250989ce9 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -31,6 +31,7 @@
 #include "hardware/gpio.h"
 #include "hardware/sync.h"
 #include "hardware/resets.h"
+#include "hardware/clocks.h"
 #include "hardware/structs/ioqspi.h"
 #include "hardware/structs/sio.h"
 
@@ -274,7 +275,15 @@ static void max3421_init(void) {
   gpio_set_function(MAX3421_SCK_PIN, GPIO_FUNC_SPI);
   gpio_set_function(MAX3421_MOSI_PIN, GPIO_FUNC_SPI);
   gpio_set_function(MAX3421_MISO_PIN, GPIO_FUNC_SPI);
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wnull-dereference"
+#endif
   spi_set_format(MAX3421_SPI, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
 }
 
 //// API to enable/disable MAX3421 INTR pin interrupt
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index b41d7fbea..d91821ffa 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -133,7 +133,10 @@ target_sources(tinyusb_bsp INTERFACE
 target_include_directories(tinyusb_bsp INTERFACE
 	${TOP}/hw
 	)
-target_link_libraries(tinyusb_bsp	INTERFACE pico_unique_id)
+target_link_libraries(tinyusb_bsp INTERFACE
+	pico_unique_id
+	hardware_clocks
+	)
 
 # tinyusb_additions will hold our extra settings for examples
 add_library(tinyusb_additions INTERFACE)
@@ -175,6 +178,11 @@ function(family_configure_target TARGET RTOS)
 	# export RTOS_SUFFIX to parent scope
 	set(RTOS_SUFFIX ${RTOS_SUFFIX} PARENT_SCOPE)
 
+	# compile define from command line
+	if(DEFINED CFLAGS_CLI)
+		target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+	endif()
+
 	pico_add_extra_outputs(${TARGET})
 	pico_enable_stdio_uart(${TARGET} 1)
 	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_board${RTOS_SUFFIX} tinyusb_additions)
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
index 37e7e0943..999dbfe9e 100644
--- a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -58,7 +58,7 @@
 #define configCPU_CLOCK_HZ                      SystemCoreClock
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
 #define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake
new file mode 100644
index 000000000..7672ff338
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT stm32f103xe)
+set(JLINK_DEVICE stm32f103ze)
+#set(JLINK_OPTION "-USB 320000338")
+
+string(TOUPPER ${MCU_VARIANT} MCU_VARIANT_UPPER)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xE
+    HSE_VALUE=8000000U
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h
new file mode 100644
index 000000000..d31102d32
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h
@@ -0,0 +1,97 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOF
+#define LED_PIN               GPIO_PIN_6
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOG
+#define BUTTON_PIN            GPIO_PIN_8
+#define BUTTON_STATE_ACTIVE   0
+
+// USB Connect
+#define USB_CONNECT_PORT      GPIOG
+#define USB_CONNECT_PIN       GPIO_PIN_11
+#define USB_CONNECT_STATE     0
+
+// UART
+//#define UART_DEV              USART1
+//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF1_USART1
+//#define UART_TX_PIN           GPIO_PIN_9
+//#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32f1_clock_init(void)
+{
+  RCC_ClkInitTypeDef clkinitstruct = {0};
+  RCC_OscInitTypeDef oscinitstruct = {0};
+  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
+  oscinitstruct.HSEState        = RCC_HSE_ON;
+  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
+  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
+  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
+  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
+  HAL_RCC_OscConfig(&oscinitstruct);
+
+  /* USB clock selection */
+  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk
new file mode 100644
index 000000000..5b17d8036
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.mk
@@ -0,0 +1,13 @@
+MCU_VARIANT = stm32f103xe
+
+CFLAGS += -DSTM32F103xE -DHSE_VALUE=8000000U
+
+# Linker
+LD_FILE_GCC = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32F103XE_FLASH.ld
+LD_FILE_IAR = ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f103ze
+
+# flash target ROM bootloader
+flash: flash-jlink
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 70f81e7fc..600fc28c0 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -57,6 +57,19 @@ void board_init(void) {
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
 
+#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+
+#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+
+#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
+
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -107,10 +120,18 @@ void board_init(void) {
   HAL_UART_Init(&UartHandle);
 #endif
 
+#ifdef USB_CONNECT_PIN
+  GPIO_InitStruct.Pin = USB_CONNECT_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(USB_CONNECT_PORT, &GPIO_InitStruct);
+#endif
+
   // USB Pins
   // Configure USB DM and DP pins.
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -119,6 +140,18 @@ void board_init(void) {
   __HAL_RCC_USB_CLK_ENABLE();
 }
 
+#ifdef USB_CONNECT_PIN
+void dcd_disconnect(uint8_t rhport) {
+  (void)rhport;
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, 1-USB_CONNECT_STATE);
+}
+
+void dcd_connect(uint8_t rhport) {
+  (void)rhport;
+  HAL_GPIO_WritePin(USB_CONNECT_PORT, USB_CONNECT_PIN, USB_CONNECT_STATE);
+}
+#endif
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 03fbf4010..364616304 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -1,10 +1,10 @@
 ST_FAMILY = f1
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
 
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY}
+ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
 
-include $(TOP)/$(BOARD_PATH)/board.mk
+include ${TOP}/${BOARD_PATH}/board.mk
 CPU_CORE ?= cortex-m3
 
 # --------------
@@ -29,23 +29,23 @@ LDFLAGS_GCC += \
 # ------------------------
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+  ${ST_CMSIS}/Source/Templates/system_stm32${ST_FAMILY}xx.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_cortex.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_rcc.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_rcc_ex.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_gpio.c \
+  ${ST_HAL_DRIVER}/Src/stm32${ST_FAMILY}xx_hal_uart.c
 
 INC += \
-  $(TOP)/$(BOARD_PATH) \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc
+  ${TOP}/${BOARD_PATH} \
+  ${TOP}/lib/CMSIS_5/CMSIS/Core/Include \
+  ${TOP}/${ST_CMSIS}/Include \
+  ${TOP}/${ST_HAL_DRIVER}/Inc
 
 # Startup
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+SRC_S_GCC += ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s
+SRC_S_IAR += ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s
 
 # flash target ROM bootloader: flash-dfu-util
 DFU_UTIL_OPTION = -a 0 --dfuse-address 0x08000000
diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c
index e7488ba84..f94dd95cf 100644
--- a/hw/bsp/stm32f3/family.c
+++ b/hw/bsp/stm32f3/family.c
@@ -116,6 +116,19 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
 int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index e261b0467..bae7d6d5b 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -24,6 +24,7 @@ ifeq ($(PORT), 1)
     $(info "Using OTG_HS in FullSpeed mode")
   endif
 else
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
   $(info "Using OTG_FS")
 endif
 
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
index 82cb0cdb3..76133ea2d 100644
--- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -58,7 +58,7 @@
 #define configCPU_CLOCK_HZ                      SystemCoreClock
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
 #define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index b6838c619..0dafa9c0a 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -15,7 +15,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
-
+set(OPENOCD_OPTION "-f interface/stlink.cfg -f target/stm32g0x.cfg")
 
 #------------------------------------
 # BOARD_TARGET
@@ -112,6 +112,7 @@ function(family_configure_example TARGET RTOS)
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
-  family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
+  family_flash_stlink(${TARGET})
+  #family_flash_openocd(${TARGET})
 endfunction()
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
index fa3f0ac33..891ea4b79 100644
--- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -58,7 +58,7 @@
 #define configCPU_CLOCK_HZ                      SystemCoreClock
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
 #define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
diff --git a/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
index cf6e23c1b..6a9c90a4a 100644
--- a/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
@@ -58,7 +58,7 @@
 #define configCPU_CLOCK_HZ                      SystemCoreClock
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configMINIMAL_STACK_SIZE                ( 200 )
 #define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
index c8963199b..ee83bbcbc 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
@@ -54,16 +54,17 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32l0_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
 
   /* Enable HSI Oscillator to be used as System clock source
      Enable HSI48 Oscillator to be used as USB clock source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   /* Select HSI48 as USB clock source */
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
index 8d7b537d5..895bbb3ab 100644
--- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
@@ -1,5 +1,6 @@
 set(MCU_VARIANT stm32l053xx)
 set(JLINK_DEVICE stm32l053r8)
+#set(JLINK_OPTION "-USB 778921770")
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L053C8Tx_FLASH.ld)
 
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
index 0722e3102..5cda1c15a 100644
--- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
@@ -54,16 +54,17 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32l0_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
 
   /* Enable HSI Oscillator to be used as System clock source
      Enable HSI48 Oscillator to be used as USB clock source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   /* Select HSI48 as USB clock source */
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index ea7f0b73d..c8c88d687 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -126,6 +126,19 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
 int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
new file mode 100644
index 000000000..d42501948
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u545xx)
+set(JLINK_DEVICE stm32u545re)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U545xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
new file mode 100644
index 000000000..7f3bf462c
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
@@ -0,0 +1,112 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_PIN_5
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV LPUART1
+#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF8_LPUART1
+#define UART_TX_PIN GPIO_PIN_2
+#define UART_RX_PIN GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
new file mode 100644
index 000000000..072c595fb
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+  -DSTM32U545xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s
+
+MCU_VARIANT = stm32u545xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u545re
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index 922d67f83..fee56f2ba 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
+MCU_VARIANT = stm32u575xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575ai
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
index 1dd157a68..c83ec3999 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
+MCU_VARIANT = stm32u575xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
index e759cec24..4bebe3330 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -7,5 +7,6 @@ LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
 
+MCU_VARIANT = stm32u5a5xx
 # For flash-jlink target
 JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index d779b5c96..3cc7cc511 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -72,7 +72,9 @@ void board_init(void) {
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
+#ifdef GPIOF
   __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
 
@@ -140,6 +142,17 @@ void board_init(void) {
   GPIO_InitStruct.Alternate = GPIO_AF10_USB;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+#ifdef USB_DRD_FS
+  // STM32U535/STM32U545
+
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+
+  /* USB clock enable */
+  __HAL_RCC_USB_FS_CLK_ENABLE();
+
+#endif
+
 #ifdef USB_OTG_FS
   #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -170,7 +183,9 @@ void board_init(void) {
   /* USB clock enable */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
-#else
+#endif
+
+#ifdef USB_OTG_HS
   // STM59x/Ax/Fx/Gx only have 1 USB HS port
 
   #if CFG_TUSB_OS == OPT_OS_FREERTOS
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 7402540b7..f7a7aeb33 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -102,10 +102,16 @@ function(family_configure_example TARGET RTOS)
 
   # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
-    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
-    #${TOP}/src/portable/st/typec/typec_stm32.c
-    )
+  if ((${MCU_VARIANT} STREQUAL "stm32u535xx") OR (${MCU_VARIANT} STREQUAL "stm32u545xx"))
+    target_sources(${TARGET}-tinyusb PUBLIC
+      ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+      )
+  else ()
+    target_sources(${TARGET}-tinyusb PUBLIC
+      ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+      #${TOP}/src/portable/st/typec/typec_stm32.c
+      )
+  endif ()
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index be5809340..89193b99f 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -27,18 +27,28 @@ LDFLAGS_GCC += \
   --specs=nosys.specs --specs=nano.specs
 
 SRC_C += \
-	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
 
+ifeq ($(MCU_VARIANT),stm32u545xx)
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else ifeq ($(MCU_VARIANT),stm32u535xx)
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c
+endif
+
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \