Merge branch 'hathach:master' into non-blocking-host-v2

50 files changed, 988 insertions, 284 deletions

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index ad9a4f94d..699afda92 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -267,6 +267,95 @@ function(family_add_linkermap TARGET)
     VERBATIM)
 endfunction()
 
+# Add membrowse target (installed with pip install membrowse)
+function(family_add_membrowse TARGET)
+  find_program(MEMBROWSE_EXE membrowse)
+  if (MEMBROWSE_EXE STREQUAL MEMBROWSE_EXE-NOTFOUND)
+    # force anyway, bash login shell will find it from pip install path
+    set(MEMBROWSE_EXE membrowse)
+  endif ()
+
+  set(OPTION "")
+  if (DEFINED MEMBROWSE_OPTION)
+    string(APPEND OPTION " ${MEMBROWSE_OPTION}")
+  endif ()
+
+  # For Ninja generator, extract all linker scripts from Ninja commands (with INCLUDE) and pass them to membrowse.
+  if (CMAKE_GENERATOR MATCHES "Ninja")
+    set(TARGET_ELF_PATH "$<TARGET_FILE_DIR:${TARGET}>/$<TARGET_FILE_NAME:${TARGET}>")
+    set(MEMBROWSE_LD_SCRIPTS_CMD
+      "ld_scripts=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?:-Wl,--script=|-T\\s*)\\K[A-Za-z0-9_./-]+\\.ld' | xargs)\"; \
+all_ld_scripts=\"\"; \
+pending_ld_scripts=\"$ld_scripts\"; \
+while [ -n \"$pending_ld_scripts\" ]; do \
+  next_pending=\"\"; \
+  for script in $pending_ld_scripts; do \
+    case \" $all_ld_scripts \" in *\" $script \"*) continue ;; esac; \
+    all_ld_scripts=\"$all_ld_scripts $script\"; \
+    script_dir=$(dirname \"$script\"); \
+    include_scripts=$(grep -hoP '^\\s*INCLUDE\\s+[<\"]?\\K[^\">[:space:]]+\\.ld' \"$script\" 2>/dev/null | xargs); \
+    for include_script in $include_scripts; do \
+      resolved_script=\"\"; \
+      if [ -f \"$include_script\" ]; then \
+        resolved_script=\"$include_script\"; \
+      elif [ -f \"$script_dir/$include_script\" ]; then \
+        resolved_script=\"$script_dir/$include_script\"; \
+      fi; \
+      if [ -n \"$resolved_script\" ]; then \
+        case \" $all_ld_scripts $next_pending \" in *\" $resolved_script \"*) ;; *) next_pending=\"$next_pending $resolved_script\" ;; esac; \
+      fi; \
+    done; \
+  done; \
+  pending_ld_scripts=\"$(echo \"$next_pending\" | xargs)\"; \
+done; \
+ld_scripts=\"$(echo \"$all_ld_scripts\" | xargs)\"")
+    set(MEMBROWSE_LD_DEFS_CMD
+      "ld_symbols=\"$(${CMAKE_MAKE_PROGRAM} -C ${CMAKE_BINARY_DIR} -t commands ${TARGET} | grep -oP '(?<=--defsym[=,])[^[:space:]]+' | xargs)\"; \
+ld_defs=\"\"; \
+for symbol in $ld_symbols; do \
+  ld_defs=\"$ld_defs --def $symbol\"; \
+done; \
+ld_defs=\"$(echo \"$ld_defs\" | xargs)\"")
+    set(MEMBROWSE_PREPARE_CMD
+      "if [ -f \"${TARGET_ELF_PATH}\" ]; then \
+  ${MEMBROWSE_LD_SCRIPTS_CMD}; \
+  ${MEMBROWSE_LD_DEFS_CMD}; \
+  if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
+  else \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} \\\"${TARGET_ELF_PATH}\\\" \\\"$ld_scripts\\\" $ld_defs\"; \
+  fi; \
+else \
+  if [ \"$MEMBROWSE_UPLOAD\" = \"1\" ]; then \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical --upload --github --target-name ${BOARD}/${TARGET} --api-key $ENV{MEMBROWSE_API_KEY}\"; \
+  else \
+    MEMBROWSE_CMD=\"${MEMBROWSE_EXE} report ${OPTION} --identical\"; \
+  fi; \
+fi; \
+echo \"$MEMBROWSE_CMD\"")
+
+    add_custom_target(${TARGET}-membrowse
+      DEPENDS ${TARGET}
+      COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=0 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
+      VERBATIM
+      )
+    set_property(TARGET ${TARGET}-membrowse PROPERTY FOLDER ${TARGET})
+
+    add_custom_target(${TARGET}-membrowse-upload
+      COMMAND ${CMAKE_COMMAND} -E env MEMBROWSE_UPLOAD=1 bash -lc "${MEMBROWSE_PREPARE_CMD}; eval \"$MEMBROWSE_CMD\""
+      VERBATIM
+      )
+
+    if (NOT TARGET examples-membrowse-upload)
+      add_custom_target(examples-membrowse-upload)
+    endif ()
+    add_dependencies(examples-membrowse-upload ${TARGET}-membrowse-upload)
+
+    set_property(TARGET ${TARGET}-membrowse-upload PROPERTY FOLDER ${TARGET})
+  endif ()
+endfunction()
+
+
 #-------------------------------------------------------------
 # Common Target Configure
 # Most families use these settings except rp2040 and espressif
@@ -380,6 +469,7 @@ function(family_configure_common TARGET RTOS)
     # Analyze size with bloaty and linkermap
     family_add_bloaty(${TARGET})
     family_add_linkermap(${TARGET})
+    family_add_membrowse(${TARGET})
   endif ()
 
   # run size after build
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index e617ab3ca..82d0034a1 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -250,9 +250,10 @@ function(family_configure_target TARGET RTOS)
   family_flash_openocd(${TARGET})
 	family_flash_jlink(${TARGET})
 
-  # Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
+	# Generate linkermap target and post build. LINKERMAP_OPTION can be set with -D to change default options
 	family_add_bloaty(${TARGET})
   family_add_linkermap(${TARGET})
+  family_add_membrowse(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c
index 8ea8ec5a5..f95128040 100644
--- a/hw/bsp/stm32f2/family.c
+++ b/hw/bsp/stm32f2/family.c
@@ -31,7 +31,6 @@
 #include "stm32f2xx_hal.h"
 #include "bsp/board_api.h"
 #include "board.h"
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -105,9 +104,12 @@ void board_init(void) {
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+#if CFG_TUD_ENABLED
   // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = true;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
index 11e976a42..2db42b98a 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -106,14 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if  (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h
index 9583a924b..319d2336a 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.h
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -106,14 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if  (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
index 8a3fe8409..b69ebbeaf 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -107,15 +109,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
-  if  (rhport == 0) {
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
index effbf2be8..ebefeb988 100644
--- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOA,
@@ -106,15 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
index 19a029768..bcfa6059a 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
@@ -46,6 +46,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOD,
@@ -114,14 +116,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
index 61e5de70d..0faf6fe11 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
@@ -43,6 +43,8 @@
 #define PINID_UART_TX  2
 #define PINID_UART_RX  3
 
+#define VBUS_SENSE_EN  0
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOC,
@@ -106,15 +108,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
-  if  (rhport == 0) {
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport; (void) state;
 }
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
index d7b02e79d..1a289dfb5 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
@@ -44,6 +44,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOD,
@@ -111,14 +113,6 @@ static inline void board_clock_init(void) {
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  // Enable VBUS sense (B device) via pin PA9
-  if (rhport == 0) {
-    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
index d5146ae3c..0689dfe87 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
@@ -45,6 +45,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOE,
@@ -127,13 +129,6 @@ static inline void board_clock_init(void) {
   __HAL_RCC_USART2_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
index f7026ce61..be58f8ae7 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
@@ -45,6 +45,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -128,13 +130,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
index 9a348f33f..b1633b395 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
@@ -46,6 +46,8 @@
 #define PINID_UART_RX  3
 #define PINID_VBUS0_EN 4
 
+#define VBUS_SENSE_EN  1
+
 static board_pindef_t board_pindef[] = {
   { // LED
     .port = GPIOB,
@@ -117,14 +119,6 @@ static inline void board_clock_init(void)
   __HAL_RCC_USART3_CLK_ENABLE();
 }
 
-static inline void board_vbus_sense_init(uint8_t rhport) {
-  if (rhport == 0) {
-    // Enable VBUS sense (B device) via pin PA9
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  }
-}
-
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   if (rhport == 0) {
     board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN];
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 025f6a08c..f0e9620f2 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -180,11 +180,14 @@ void board_init(void) {
 #endif
 
 #if CFG_TUD_ENABLED
-  board_vbus_sense_init(BOARD_TUD_RHPORT);
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(BOARD_TUD_RHPORT, TUD_CFGID_DWC2, &cfg);
+  board_vbus_set(BOARD_TUD_RHPORT, false);
 #endif
 
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUD_RHPORT, true);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 }
 
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
index 35102c1f2..ca9641c68 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
@@ -41,7 +41,7 @@
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_HS_VBUS_SENSE     1
 
 #define PINID_LED      0
 #define PINID_BUTTON   1
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
index 2964ebada..f57ffb317 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
@@ -40,8 +40,8 @@
 #define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
 
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     0
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     1
 
 #define PINID_LED      0
 #define PINID_BUTTON   1
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index ac22c606f..d8f0da201 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -154,18 +154,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   //------------- rhport1: OTG_HS -------------//
 #ifdef USB_HS_PHYC
   // MCU with built-in HS PHY such as F723, F733, F730
@@ -178,9 +174,6 @@ void board_init(void) {
   GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
-  // Enable HS VBUS sense (B device) via pin PB13
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
   /* Configure OTG-HS ID pin */
   GPIO_InitStruct.Pin       = GPIO_PIN_13;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;
@@ -243,17 +236,16 @@ void board_init(void) {
   __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
   __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
 
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
 #endif
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
   // Turn on host vbus
 #if CFG_TUH_ENABLED
   board_vbus_set(BOARD_TUH_RHPORT, true);
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 96bfc24e1..44ca58dc5 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -44,7 +44,7 @@
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_HS_VBUS_SENSE     1
 
 // USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
 #define ULPI_PINS \
diff --git a/hw/bsp/stm32h7/boards/stm32h747disco/board.h b/hw/bsp/stm32h7/boards/stm32h747disco/board.h
index 71e8b1427..458aa48b6 100644
--- a/hw/bsp/stm32h7/boards/stm32h747disco/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h747disco/board.h
@@ -42,7 +42,7 @@
 
 // VBUS Sense detection
 #define OTG_FS_VBUS_SENSE     1
-#define OTG_HS_VBUS_SENSE     0
+#define OTG_HS_VBUS_SENSE     1
 
 // USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
 #define ULPI_PINS \
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 054d7855f..a320a7e72 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -180,18 +180,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   //------------- USB HS -------------//
 #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
   // Despite being call USB2_OTG
@@ -216,28 +212,24 @@ void board_init(void) {
   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
   __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
 
-#if OTG_HS_VBUS_SENSE
-  #error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+  #if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
+  #endif
 #endif
 
   HAL_PWREx_EnableUSBVoltageDetector();
 
   board_init2(); // optional init
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
+  // Turn on host vbus
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUH_RHPORT, 1);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 
 }
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
index 7b3456585..189c175dd 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
@@ -2,6 +2,8 @@ set(MCU_VARIANT stm32h7s3xx)
 set(JLINK_DEVICE stm32h7s3l8)
 
 set(LD_FILE_Clang ${LD_FILE_GNU})
+set(RHPORT_DEVICE 1)
+set(RHPORT_HOST 1)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
index 4fb72cce8..16c2fd335 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h
@@ -44,7 +44,7 @@
 #define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
 
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE     1
+#define OTG_FS_VBUS_SENSE     0
 #define OTG_HS_VBUS_SENSE     0
 
 #define PINID_LED      0
diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c
index 784c92465..2cc39b7ac 100644
--- a/hw/bsp/stm32h7rs/family.c
+++ b/hw/bsp/stm32h7rs/family.c
@@ -356,17 +356,14 @@ void board_init(void) {
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
+#endif // vbus sense
 
-  // Enable VBUS sense (B device) via pin PM14
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device)
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_FS_VBUS_SENSE;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
 #endif
 
   //------------- USB HS -------------//
@@ -382,33 +379,31 @@ void board_init(void) {
 
 #if OTG_HS_VBUS_SENSE
   // Configure VBUS Pin
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
-  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PM9
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+  GPIO_InitTypeDef GPIO_InitStruct2;
+  GPIO_InitStruct2.Pin = GPIO_PIN_8;
+  GPIO_InitStruct2.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct2.Pull = GPIO_NOPULL;
+  GPIO_InitStruct2.Alternate = GPIO_AF10_OTG_HS;
+  HAL_GPIO_Init(GPIOM, &GPIO_InitStruct2);
+#endif
 
 #if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
-#else
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = OTG_HS_VBUS_SENSE;
+  tud_configure(1, TUD_CFGID_DWC2, &cfg);
 #endif
 
 #endif
-#endif
 
   board_init2();
 
+  // Turn off device vbus
+#if CFG_TUD_ENABLED
+  board_vbus_set(BOARD_TUD_RHPORT, false);
+#endif
+  // Turn on host vbus
 #if CFG_TUH_ENABLED
-  board_vbus_set(BOARD_TUH_RHPORT, 1);
+  board_vbus_set(BOARD_TUH_RHPORT, true);
 #endif
 }
 
diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake
index 1fd1cb057..3b9dbf5cf 100644
--- a/hw/bsp/stm32h7rs/family.cmake
+++ b/hw/bsp/stm32h7rs/family.cmake
@@ -24,7 +24,7 @@ if (NOT DEFINED RHPORT_DEVICE)
   set(RHPORT_DEVICE 1)
 endif ()
 if (NOT DEFINED RHPORT_HOST)
-  set(RHPORT_HOST 1)
+  set(RHPORT_HOST 0)
 endif ()
 
 if (NOT DEFINED RHPORT_SPEED)
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
index 8c766d8ea..cf84d3e66 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_5
 #define UART_RX_PIN           GPIO_PIN_6
 
+#define VBUS_SENSE_EN         0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -128,15 +130,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
-  // Disable VBUS Sense and force device mode
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
index 607210cec..3b031e00f 100644
--- a/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l496nucleo/board.h
@@ -52,6 +52,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -145,12 +147,6 @@ static inline void board_clock_init(void)
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
index f522e7522..94978638e 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -129,12 +131,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
index c181f5d4a..f603ae855 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
@@ -51,6 +51,8 @@
 #define UART_TX_PIN           GPIO_PIN_7
 #define UART_RX_PIN           GPIO_PIN_8
 
+#define VBUS_SENSE_EN         1
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -129,12 +131,6 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
 }
 
-static inline void board_vbus_sense_init(void)
-{
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-}
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index e69ae8e3b..65f6b9ab3 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -170,10 +170,16 @@ void board_init(void) {
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 #endif
 
-  /* Enable USB FS Clocks */
 #if defined(USB_OTG_FS)
+  /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-  board_vbus_sense_init();
+
+  #if CFG_TUD_ENABLED
+  /* Set Vbus sense */
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+  #endif
 #else
   __HAL_RCC_USB_CLK_ENABLE();
 #endif
diff --git a/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake b/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
index e88efefb9..00efc974c 100644
--- a/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
+++ b/hw/bsp/stm32n6/boards/stm32n6570dk/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT stm32n657xx)
-set(JLINK_DEVICE stm32n6xx)
+set(JLINK_DEVICE stm32n657x0)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
 
diff --git a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
index bbcad6340..8c2ec66dc 100644
--- a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
+++ b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
@@ -44,17 +44,16 @@ extern "C" {
 #define UART_DEV USART1
 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
 
-#define BOARD_TUD_RHPORT 1
-
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 1
+#define OTG_FS_VBUS_SENSE 0
+#define OTG_HS_VBUS_SENSE 0
 
 #define PINID_LED 0
 #define PINID_BUTTON 1
 #define PINID_UART_TX 2
 #define PINID_UART_RX 3
 #define PINID_TCPP0203_EN 4
+#define PINID_PWR_USB2 8
 
 static board_pindef_t board_pindef[] = {
     {// LED
@@ -77,21 +76,22 @@ static board_pindef_t board_pindef[] = {
      .port = GPIOA,
      .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
      .active_state = 0},
-    {
-        // I2C SCL for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    { // I2C SCL for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // I2C SDA for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SDA for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // INT for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    {// INT for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
     },
+    {// PWR for USB2
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_9, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    }
 };
 
 //--------------------------------------------------------------------+
@@ -262,9 +262,12 @@ static inline void board_init2(void) {
 }
 
 void board_vbus_set(uint8_t rhport, bool state) {
-  (void) state;
-  if (rhport == 1) {
-    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  if (rhport == 0) {
+    uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
+  } else if (rhport == 1) {
+    board_pindef_t *pindef = &board_pindef[PINID_PWR_USB2];
+    HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state ? GPIO_PIN_SET : GPIO_PIN_RESET);
   }
 }
 
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
index e88efefb9..e682cabcb 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
@@ -1,8 +1,15 @@
 set(MCU_VARIANT stm32n657xx)
-set(JLINK_DEVICE stm32n6xx)
+set(JLINK_DEVICE stm32n657x0)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
 
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32N657xx
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
index 33c68f7cf..5bdbaff3c 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
@@ -44,11 +44,9 @@ extern "C" {
 #define UART_DEV USART1
 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
 
-#define BOARD_TUD_RHPORT 1
-
 // VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 1
+#define OTG_FS_VBUS_SENSE 0
+#define OTG_HS_VBUS_SENSE 0
 
 #define PINID_LED 0
 #define PINID_BUTTON 1
@@ -77,20 +75,17 @@ static board_pindef_t board_pindef[] = {
      .port = GPIOA,
      .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
      .active_state = 0},
-    {
-        // I2C SCL for TCPP0203
-        .port = GPIOB,
-        .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SCL for TCPP0203
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // I2C SDA for TCPP0203
-        .port = GPIOB,
-        .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
+    {// I2C SDA for TCPP0203
+      .port = GPIOB,
+      .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
     },
-    {
-        // INT for TCPP0203
-        .port = GPIOD,
-        .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
+    {// INT for TCPP0203
+      .port = GPIOD,
+      .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
     },
 };
 
@@ -262,9 +257,9 @@ static inline void board_init2(void) {
 }
 
 void board_vbus_set(uint8_t rhport, bool state) {
-  (void) state;
-  if (rhport == 1) {
-    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
+  if (rhport == 0) {
+    uint8_t switch_state = state ? TCPP0203_GD_PROVIDER_SWITCH_CLOSED : TCPP0203_GD_PROVIDER_SWITCH_OPEN;
+    TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, switch_state) == TCPP0203_OK, );
   }
 }
 
diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
index 05717699c..efbb82611 100644
--- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
+++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
@@ -1,9 +1,12 @@
 MCU_VARIANT = stm32n657xx
 CFLAGS += -DSTM32N657xx
-JLINK_DEVICE = stm32n6xx
+JLINK_DEVICE = stm32n657x0
 
 LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
 
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
 # flash target using on-board stlink
 flash: flash-stlink
 
diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c
index 567bb7294..c839e6b3e 100644
--- a/hw/bsp/stm32n6/family.c
+++ b/hw/bsp/stm32n6/family.c
@@ -48,7 +48,8 @@
 TU_ATTR_UNUSED static void Error_Handler(void) { }
 
 void HardFault_Handler(void);
-
+static void MPU_Config(void);
+static void SystemIsolation_Config(void);
 typedef struct {
   GPIO_TypeDef* port;
   GPIO_InitTypeDef pin_init;
@@ -87,20 +88,25 @@ static UART_HandleTypeDef UartHandle = {
 // Despite being call USB2_OTG_FS on some MCUs
 // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
 void USB2_OTG_HS_IRQHandler(void) {
-  tusb_int_handler(0, true);
+  tusb_int_handler(1, true);
 }
 
 // Despite being call USB1_OTG_HS on some MCUs
 // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
 void USB1_OTG_HS_IRQHandler(void) {
-  tusb_int_handler(1, true);
+  tusb_int_handler(0, true);
 }
 
 void board_init(void) {
-
   /* Enable BusFault and SecureFault handlers (HardFault is default) */
   SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
 
+  MPU_Config();
+  SystemIsolation_Config();
+
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
   HAL_PWREx_EnableVddA();
   HAL_PWREx_EnableVddIO2();
   HAL_PWREx_EnableVddIO3();
@@ -126,8 +132,6 @@ void board_init(void) {
   __HAL_RCC_GPIOP_CLK_ENABLE();
   __HAL_RCC_GPIOQ_CLK_ENABLE();
 
-  // HAL_ICACHE_Enable();
-
   for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
     HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
   }
@@ -155,7 +159,7 @@ void board_init(void) {
   HAL_UART_Init(&UartHandle);
 #endif
 
-
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
   __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
   __HAL_RCC_PWR_CLK_ENABLE();
   HAL_PWREx_EnableVddUSBVMEN();
@@ -196,11 +200,109 @@ void board_init(void) {
   /* Peripheral PHY clock enable */
   __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
 
-  board_init2();
+#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0
+  board_vbus_set(BOARD_TUH_RHPORT, 1);
+#endif
+#endif
+
+#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+  __HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWREx_EnableVddUSBVMEN();
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
+  HAL_PWREx_EnableVddUSB();
+
+  LL_AHB5_GRP1_ForceReset(0x00800000);
+  __HAL_RCC_USB2_OTG_HS_FORCE_RESET();
+  __HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET();
+
+  LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
+  LL_AHB5_GRP1_ReleaseReset(0x00800000);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB2_OTG_HS_CLK_ENABLE();
+
+  /* Required few clock cycles before accessing USB PHY Controller Registers */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  USB2_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
+
+  USB2_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
+                              (0x2 << 4)  |
+                              (0x1 << 2)  |
+                                0x1U;
+
+  __HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET();
+
+  /* Required few clock cycles before Releasing Reset */
+  for (volatile uint32_t i = 0; i < 10; i++) {
+      __NOP(); // No Operation instruction to create a delay
+  }
+
+  __HAL_RCC_USB2_OTG_HS_RELEASE_RESET();
+
+  /* Peripheral PHY clock enable */
+  __HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE();
 
-#if CFG_TUH_ENABLED
+#if CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1
   board_vbus_set(BOARD_TUH_RHPORT, 1);
 #endif
+#endif
+
+  board_init2();
+}
+
+static void MPU_Config(void)
+{
+  MPU_Region_InitTypeDef default_config = {0};
+  MPU_Attributes_InitTypeDef attr_config = {0};
+  uint32_t primask_bit = __get_PRIMASK();
+  __disable_irq();
+
+  /* disable the MPU */
+  HAL_MPU_Disable();
+
+  /* create an attribute configuration for the MPU */
+  attr_config.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
+  attr_config.Number = MPU_ATTRIBUTES_NUMBER0;
+
+  HAL_MPU_ConfigMemoryAttributes(&attr_config);
+
+  /* Create a non cacheable region */
+  /*Normal memory type, code execution allowed */
+  default_config.Enable = MPU_REGION_ENABLE;
+  default_config.Number = MPU_REGION_NUMBER0;
+  default_config.BaseAddress = __NON_CACHEABLE_SECTION_BEGIN;
+  default_config.LimitAddress =  __NON_CACHEABLE_SECTION_END;
+  default_config.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+  default_config.AccessPermission = MPU_REGION_ALL_RW;
+  default_config.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+  default_config.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
+  HAL_MPU_ConfigRegion(&default_config);
+
+  /* enable the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+  /* Exit critical section to lock the system and avoid any issue around MPU mechanisme */
+  __set_PRIMASK(primask_bit);
+}
+
+static void SystemIsolation_Config(void) {
+  /* set all required IPs as secure privileged */
+  __HAL_RCC_RIFSC_CLK_ENABLE();
+  RIMC_MasterConfig_t RIMC_master = {0};
+  RIMC_master.MasterCID = RIF_CID_1;
+  RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
+
+  /*RIMC configuration*/
+  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG1, &RIMC_master);
+  HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_OTG2, &RIMC_master);
+
+  /*RISUP configuration*/
+  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG1HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
+  HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_OTG2HS , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake
index 6c7aaea61..972138018 100644
--- a/hw/bsp/stm32n6/family.cmake
+++ b/hw/bsp/stm32n6/family.cmake
@@ -21,7 +21,7 @@ set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
 # Port & Speed Selection
 # ----------------------
 if (NOT DEFINED RHPORT_DEVICE)
-  set(RHPORT_DEVICE 1)
+  set(RHPORT_DEVICE 0)
 endif ()
 if (NOT DEFINED RHPORT_HOST)
   set(RHPORT_HOST 1)
@@ -68,6 +68,7 @@ function(family_add_board BOARD_TARGET)
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rif.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@@ -80,8 +81,8 @@ function(family_add_board BOARD_TARGET)
     BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
     BOARD_TUH_RHPORT=${RHPORT_HOST}
     BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
-    SEGGER_RTT_SECTION="noncacheable_buffer"
-    BUFFER_SIZE_UP=0x3000
+    SEGGER_RTT_SECTION=".noncacheable"
+    BUFFER_SIZE_UP=0x4000
     )
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk
index 45554e251..9fef533b1 100644
--- a/hw/bsp/stm32n6/family.mk
+++ b/hw/bsp/stm32n6/family.mk
@@ -12,7 +12,7 @@ CPU_CORE ?= cortex-m55
 # ----------------------
 # Port & Speed Selection
 # ----------------------
-RHPORT_DEVICE ?= 1
+RHPORT_DEVICE ?= 0
 RHPORT_HOST ?= 1
 
 ifndef RHPORT_DEVICE_SPEED
@@ -32,8 +32,8 @@ CFLAGS += \
 	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
 	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
 	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-	-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-	-DBUFFER_SIZE_UP=0x3000 \
+	-DSEGGER_RTT_SECTION="\".noncacheable\"" \
+	-DBUFFER_SIZE_UP=0x4000 \
 
 # GCC Flags
 CFLAGS_GCC += \
diff --git a/hw/bsp/stm32n6/setup_iar.mac b/hw/bsp/stm32n6/setup_iar.mac
new file mode 100644
index 000000000..b6f2bc97a
--- /dev/null
+++ b/hw/bsp/stm32n6/setup_iar.mac
@@ -0,0 +1,12 @@
+/* Called once after the target reset. */
+execUserReset()
+{
+    /* Re-load image as AIXRAM2 is erased after CPU reset */
+    __loadImage("$EXE_DIR$\\$TARGET_BNAME$.hex", 0, 0);
+
+    __restoreSoftwareBreakpoints();
+
+     #PC = __readMemory32(0x34180404, "Memory");
+
+     #SP = 0x341FFD00;
+}
diff --git a/hw/bsp/stm32n6/stm32n6.jdebug b/hw/bsp/stm32n6/stm32n6.jdebug
new file mode 100644
index 000000000..81490db5d
--- /dev/null
+++ b/hw/bsp/stm32n6/stm32n6.jdebug
@@ -0,0 +1,362 @@
+/*********************************************************************
+*                 (c) SEGGER Microcontroller GmbH                    *
+*                      The Embedded Experts                          *
+*                         www.segger.com                             *
+**********************************************************************
+
+File          :
+Created       : 31. Jan 2026 16:34
+Ozone Version : V3.40e
+*/
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  //
+  // Dialog-generated settings
+  //
+  Project.SetDevice ("STM32N657X0");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("4 MHz");
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M55F.svd");
+  //
+  // User settings
+  //
+  File.Open ("$(ProjectDir)/../../../examples/device/cdc_msc/build/stm32n6570dk/RelWithDebInfo/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*       OnStartupComplete
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//  //
+//  // Set up initial stack pointer
+//  //
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//  }
+//  //
+//  // Set up entry point PC
+//  //
+//  PC = Elf.GetEntryPointPC();
+//
+//  if (PC != 0xFFFFFFFF) {
+//    Target.SetReg("PC", PC);
+//  } else if (VectorTableAddr != 0xFFFFFFFF) {
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  } else {
+//    Util.Error("Project file error: failed to set entry point PC", 1);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  //_SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterProjectLoad
+*
+* Function description
+*   After Project load routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterProjectLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnDebugStartBreakSymbolReached
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the symbol to be breaked at during debug start. Optional.
+*
+**********************************************************************
+*/
+//void OnDebugStartBreakSymReached (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+	Debug.Download();
+  Debug.Halt();
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  //
+  // Set up initial stack pointer
+  //
+  SP = Target.ReadU32(VectorTableAddr);
+  if (SP != 0xFFFFFFFF) {
+    Target.SetReg("SP", SP);
+  }
+  //
+  // Set up entry point PC
+  //
+  PC = Elf.GetEntryPointPC();
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else {
+    Util.Error("Project script error: failed to set up entry point PC", 1);
+  }
+}
diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
index 00cb31159..49ca767fe 100644
--- a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
+++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h
@@ -67,7 +67,7 @@
 /*#define HAL_PKA_MODULE_ENABLED      */
 /*#define HAL_PSSI_MODULE_ENABLED     */
 /*#define HAL_RAMCFG_MODULE_ENABLED   */
-/*#define HAL_RIF_MODULE_ENABLED      */
+#define HAL_RIF_MODULE_ENABLED
 /*#define HAL_RNG_MODULE_ENABLED      */
 /*#define HAL_RTC_MODULE_ENABLED      */
 /*#define HAL_SAI_MODULE_ENABLED      */
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
index cf3f63ea5..c99743738 100644
--- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
@@ -55,6 +55,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -110,6 +112,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
index 0c3439b2c..eb2b63721 100644
--- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
@@ -110,6 +110,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
index b11f6a747..cce3e38b3 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -56,6 +56,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -111,6 +113,9 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
index be037b68a..b6b60f021 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -37,6 +37,8 @@ extern "C"
 {
 #endif
 
+#include "stm32u5xx_ll_tim.h"
+
 // LED GREEN
 #define LED_PORT GPIOC
 #define LED_PIN GPIO_PIN_7
@@ -55,6 +57,8 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_7
 #define UART_RX_PIN GPIO_PIN_8
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -110,6 +114,104 @@ static void SystemClock_Config(void) {
 static void SystemPower_Config(void) {
 }
 
+static inline void board_vbus_sense_init(void) {
+  /* ADC config */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+  PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  __HAL_RCC_ADC12_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  GPIO_InitStruct.Pin = GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  ADC_HandleTypeDef hadc1;
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_14B;
+  hadc1.Init.GainCompensation = 0;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  HAL_NVIC_EnableIRQ(ADC1_IRQn);
+
+  /* TIM1 init for TRGO */
+  __HAL_RCC_TIM1_CLK_ENABLE();
+  TIM_HandleTypeDef htim1;
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 159;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 999;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
+
+  HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
+  HAL_ADC_Start_IT(&hadc1);
+  HAL_TIM_Base_Start(&htim1);
+}
+
+void ADC1_IRQHandler(void) {
+  if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
+    /* Clear flag ADC group regular end of unitary conversion */
+    LL_ADC_ClearFlag_EOC(ADC1);
+    /* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
+     * with R1 = 330kOhm and R2 = 50kOhm
+     */
+    const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
+    if((ADC1->DR > threshold) && (USB_OTG_FS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
+      USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+    } else {
+      USB_OTG_FS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
+    }
+  }
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+  }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
index 0785fb36b..15106aee6 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -37,6 +37,8 @@ extern "C"
 {
 #endif
 
+#include "stm32u5xx_ll_tim.h"
+
 // LED GREEN
 #define LED_PORT GPIOC
 #define LED_PIN GPIO_PIN_7
@@ -55,11 +57,13 @@ extern "C"
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
+#define VBUS_SENSE_EN 0
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static void SystemClock_Config(void) {
+static inline void SystemClock_Config(void) {
   RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
   RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
 
@@ -128,7 +132,7 @@ static void SystemClock_Config(void) {
   }
 }
 
-static void SystemPower_Config(void) {
+static inline void SystemPower_Config(void) {
   HAL_PWREx_EnableVddIO2();
 
   /*
@@ -141,7 +145,105 @@ static void SystemPower_Config(void) {
 /* USER CODE END PWR */
 }
 
+static inline void board_vbus_sense_init(void) {
+  /* ADC config */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+  PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  __HAL_RCC_ADC12_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  GPIO_InitStruct.Pin = GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  ADC_HandleTypeDef hadc1;
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_14B;
+  hadc1.Init.GainCompensation = 0;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T1_TRGO;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+  hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+  hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_68CYCLES;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
+
+  /* TIM1 init for TRGO */
+  __HAL_RCC_TIM1_CLK_ENABLE();
+  TIM_HandleTypeDef htim1;
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 159;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 999;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK) {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) {
+    Error_Handler();
+  }
+  LL_TIM_SetTriggerOutput(htim1.Instance, LL_TIM_TRGO_UPDATE);
+
+  HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED);
+  HAL_ADC_Start_IT(&hadc1);
+  HAL_TIM_Base_Start(&htim1);
+}
 
+void ADC1_2_IRQHandler(void) {
+  if(LL_ADC_IsActiveFlag_EOC(ADC1) != 0) {
+    /* Clear flag ADC group regular end of unitary conversion */
+    LL_ADC_ClearFlag_EOC(ADC1);
+    /* ADC code = 4.5V * R2 / (R1 + R2) * (2^14) / 3.3V
+     * with R1 = 330kOhm and R2 = 50kOhm
+     */
+    const uint32_t threshold = 4500 * 50 / (50 + 330) * 16384 / 3300;
+    if((ADC1->DR > threshold) && (USB_OTG_HS->GOTGCTL & USB_OTG_GOTGCTL_BVALOEN)) {
+      USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+      USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+    } else {
+      USB_OTG_HS->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
+      USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
+    }
+  }
+  if(LL_ADC_IsActiveFlag_OVR(ADC1) != 0) {
+    /* Clear flag ADC group regular overrun */
+    LL_ADC_ClearFlag_OVR(ADC1);
+  }
+}
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 26d72d6a0..dfcf5c537 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -179,18 +179,14 @@ void board_init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-  #else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
   #endif // vbus sense
 
+#if CFG_TUD_ENABLED
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
+
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
@@ -218,13 +214,15 @@ void board_init(void) {
   /*Configuring the SYSCFG registers OTG_HS PHY*/
   HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#if CFG_TUD_ENABLED
+  tud_configure_dwc2_t cfg = CFG_TUD_CONFIGURE_DWC2_DEFAULT;
+  cfg.vbus_sensing = VBUS_SENSE_EN;
+  tud_configure(0, TUD_CFGID_DWC2, &cfg);
+#endif
 #endif // USB_OTG_FS
+
+  /* Non-standard VBus sense settings */
+  board_vbus_sense_init();
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 58dc63ae3..3d23c554d 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -45,6 +45,9 @@ function(family_add_board BOARD_TARGET)
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_adc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@@ -96,7 +99,7 @@ function(family_configure_example TARGET RTOS)
   endif ()
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
+    set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes -Wno-self-assign")
   endif ()
   set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
     SKIP_LINTING ON
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 47aed10a9..3dab8c610 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -16,6 +16,7 @@ CFLAGS_GCC += \
   -Wno-error=undef \
   -Wno-error=unused-parameter \
   -Wno-error=type-limits \
+  -Wno-self-assign \
 
 ifeq ($(TOOLCHAIN),gcc)
 CFLAGS_GCC += -Wno-error=maybe-uninitialized
@@ -35,11 +36,15 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_adc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c
 
 ifneq ($(filter stm32u545xx stm32u535xx,$(MCU_VARIANT)),)
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c \
 	src/portable/st/stm32_fsdev/fsdev_common.c
 else
 SRC_C += \
diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
index 87c3683de..5d95862f6 100644
--- a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
+++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
@@ -36,7 +36,7 @@
 
 #define HAL_MODULE_ENABLED
 
-/*#define HAL_ADC_MODULE_ENABLED */
+#define HAL_ADC_MODULE_ENABLED
 /*#define HAL_MDF_MODULE_ENABLED */
 /*#define HAL_COMP_MODULE_ENABLED */
 /*#define HAL_CORDIC_MODULE_ENABLED */
@@ -76,7 +76,7 @@
 /*#define HAL_SMBUS_MODULE_ENABLED */
 /*#define HAL_SPI_MODULE_ENABLED */
 /*#define HAL_SRAM_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
 /*#define HAL_TSC_MODULE_ENABLED */
 /*#define HAL_RAMCFG_MODULE_ENABLED */
 #define HAL_UART_MODULE_ENABLED
diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c
index 8dc6547ae..d05415755 100644
--- a/hw/bsp/stm32wba/family.c
+++ b/hw/bsp/stm32wba/family.c
@@ -172,14 +172,7 @@ void board_init(void) {
 
   // Configuring the SYSCFG registers OTG_HS PHY
   SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
-
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
-  #endif // USB_OTG_FS
+  #endif // USB_OTG_HS
 }
 
 void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); }