Merge pull request #2963 from HiFiPhile/stm32_cache

Add DWC2 cache maintenance routines for STM32

9 files changed, 165 insertions, 69 deletions

diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 5f63834d0..bf2d28e42 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -78,6 +78,10 @@ void OTG_HS_IRQHandler(void) {
 //--------------------------------------------------------------------+
 
 void board_init(void) {
+  SCB_EnableICache();
+
+  HAL_Init();
+
   board_clock_init();
 
   // Enable All GPIOs clocks
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index f8723b0c7..382b878b7 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -98,6 +98,10 @@ static void trace_etm_init(void) {
 #endif
 
 void board_init(void) {
+  SCB_EnableICache();
+
+  HAL_Init();
+
   // Implemented in board.h
   SystemClock_Config();
 
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
index f52b70408..aae820aee 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
@@ -1,9 +1,7 @@
 set(MCU_VARIANT stm32h7s3xx)
 set(JLINK_DEVICE stm32h7s3xx)
 
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld)
 set(LD_FILE_Clang ${LD_FILE_GNU})
-set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
index cf0c2ff54..47055a108 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
+++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
@@ -7,10 +7,6 @@ JLINK_DEVICE = stm32h7s3xx
 # flash target using on-board stlink
 flash: flash-stlink
 
-# Linker
-LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
-LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
-
 SRC_C += \
 	$(ST_TCPP0203)/tcpp0203.c \
 	$(ST_TCPP0203)/tcpp0203_reg.c \
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
deleted file mode 100644
index 8ffaa74a7..000000000
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
+++ /dev/null
@@ -1,55 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol NONCACHEABLEBUFFER_size   = 0x4000;
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
-define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
-define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
-
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__   = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-define symbol __region_ITCM_start__ = 0x00000000;
-define symbol __region_ITCM_end__   = 0x0000FFFF;
-define symbol __region_DTCM_start__ = 0x20000000;
-define symbol __region_DTCM_end__   = 0x2000FFFF;
-define symbol __region_SRAMAHB_start__ = 0x30000000;
-define symbol __region_SRAMAHB_end__   = 0x30007FFF;
-define symbol __region_BKPSRAM_start__ = 0x38800000;
-define symbol __region_BKPSRAM_end__   = 0x38800FFF;
-
-export symbol NONCACHEABLEBUFFER_start;
-export symbol NONCACHEABLEBUFFER_size;
-
-export symbol __ICFEDIT_region_ROM_start__;
-export symbol __ICFEDIT_region_ROM_end__;
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
-define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
-define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
-define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
-define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite };
-place in NONCACHEABLE_region { section noncacheable_buffer };
-place in DTCM_region  { block CSTACK, block HEAP };
diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c
index 4b81deea0..b506a02ab 100644
--- a/hw/bsp/stm32h7rs/family.c
+++ b/hw/bsp/stm32h7rs/family.c
@@ -123,10 +123,159 @@ void log_swo_init(void)
   #define log_swo_init()
 #endif
 
+static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit);
+static void MPU_Config(void)
+{
+  MPU_Region_InitTypeDef MPU_InitStruct = {0};
+  uint32_t index = MPU_REGION_NUMBER0;
+  uint32_t address;
+  uint32_t size;
+
+  /* Disable the MPU */
+  HAL_MPU_Disable();
+
+  /* Initialize the background region */
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+  MPU_InitStruct.Number = index;
+  MPU_InitStruct.BaseAddress = 0x0;
+  MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
+  MPU_InitStruct.SubRegionDisable = 0x87;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  index++;
+
+  /* Initialize the non cacheable region */
+#if defined ( __ICCARM__ )
+  /* get the region attribute form the icf file */
+  extern uint32_t NONCACHEABLEBUFFER_start;
+  extern uint32_t NONCACHEABLEBUFFER_size;
+
+  address = (uint32_t)&NONCACHEABLEBUFFER_start;
+  size = (uint32_t)&NONCACHEABLEBUFFER_size;
+
+#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
+  extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base;
+  extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length;
+  extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
+
+  address = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Base;
+  size  = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Length + (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
+#elif defined ( __GNUC__ )
+  extern int __NONCACHEABLEBUFFER_BEGIN;
+  extern int __NONCACHEABLEBUFFER_END;
+
+  address = (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
+  size  = (uint32_t)&__NONCACHEABLEBUFFER_END - (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
+#else
+#error "Compiler toolchain is unsupported"
+#endif
+
+  if (size != 0)
+  {
+    /* Configure the MPU attributes as Normal Non Cacheable */
+    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number = index;
+    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+    MPU_InitStruct.SubRegionDisable = 0x00;
+    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
+    MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+    index++;
+  }
+
+  /* Initialize the region corresponding to the execution area
+     (external or internal flash or external or internal RAM
+     depending on scatter file definition) */
+#if defined ( __ICCARM__ )
+  extern uint32_t __ICFEDIT_region_ROM_start__;
+  extern uint32_t __ICFEDIT_region_ROM_end__;
+  address = (uint32_t)&__ICFEDIT_region_ROM_start__;
+  size = (uint32_t)&__ICFEDIT_region_ROM_end__ - (uint32_t)&__ICFEDIT_region_ROM_start__ + 1;
+#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
+  extern uint32_t Image$$ER_ROM$$Base;
+  extern uint32_t Image$$ER_ROM$$Limit;
+  address = (uint32_t)&Image$$ER_ROM$$Base;
+  size    = (uint32_t)&Image$$ER_ROM$$Limit-(uint32_t)&Image$$ER_ROM$$Base;
+#elif defined ( __GNUC__ )
+  extern uint32_t __FLASH_BEGIN;
+  extern uint32_t __FLASH_SIZE;
+  address = (uint32_t)&__FLASH_BEGIN;
+  size  = (uint32_t)&__FLASH_SIZE;
+#else
+#error "Compiler toolchain is unsupported"
+#endif
+
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+  MPU_InitStruct.Number = index;
+  MPU_InitStruct.SubRegionDisable = 0u;
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+  MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  index++;
+
+  /* Reset unused MPU regions */
+  for(; index < __MPU_REGIONCOUNT ; index++)
+  {
+    /* All unused regions disabled */
+    MPU_InitStruct.Enable = MPU_REGION_DISABLE;
+    MPU_InitStruct.Number = index;
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  }
+
+  /* Enable the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+}
+
+/**
+  * @brief This function adjusts the MPU region Address and Size within an MPU configuration.
+  * @param Address memory address
+  * @param Size memory size
+  * @param pInit pointer to an MPU initialization structure
+  * @retval None
+  */
+static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit)
+{
+  /* Compute the MPU region size */
+  pInit->Size = ((31 - __CLZ(Size)) - 1);
+  if (Size > (1u << (pInit->Size + 1)))
+  {
+    pInit->Size++;
+  }
+  uint32_t Modulo = Address % (1 << (pInit->Size - 1));
+  if (0 != Modulo)
+  {
+    /* Align address with MPU region size considering there is no need to increase the size */
+    pInit->BaseAddress = Address - Modulo;
+  }
+  else
+  {
+    pInit->BaseAddress = Address;
+  }
+}
+
 void board_init(void) {
   HAL_Init();
 
+  MPU_Config();
+  SCB_EnableICache();
+  SCB_EnableDCache();
+
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
   // Implemented in board.h
   SystemClock_Config();
 
diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake
index e5e98f914..40230ef12 100644
--- a/hw/bsp/stm32h7rs/family.cmake
+++ b/hw/bsp/stm32h7rs/family.cmake
@@ -54,7 +54,7 @@ function(add_board_target BOARD_TARGET)
   set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
   if(NOT DEFINED LD_FILE_GNU)
-    set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.ld)
   endif()
   set(LD_FILE_Clang ${LD_FILE_GNU})
   if(NOT DEFINED LD_FILE_IAR)
@@ -87,8 +87,8 @@ function(add_board_target BOARD_TARGET)
     BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
     BOARD_TUH_RHPORT=${RHPORT_HOST}
     BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
-    SEGGER_RTT_SECTION="noncacheable_buffer"
-    BUFFER_SIZE_UP=0x3000
+    SEGGER_RTT_SECTION=\"noncacheable_buffer\"
+    BUFFER_SIZE_UP=0x300
     )
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk
index 9970059f8..fba38448d 100644
--- a/hw/bsp/stm32h7rs/family.mk
+++ b/hw/bsp/stm32h7rs/family.mk
@@ -43,8 +43,8 @@ CFLAGS += \
 	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
 	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
 	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-	-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-	-DBUFFER_SIZE_UP=0x3000 \
+	-DSEGGER_RTT_SECTION="noncacheable_buffer" \
+	-DBUFFER_SIZE_UP=0x300 \
 
 # GCC Flags
 CFLAGS_GCC += \
@@ -91,5 +91,5 @@ SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
 SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
 
 # Linker
-LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
+LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld
 LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld b/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.ld
index 3bd7f0b89..a96e1f211 100644
--- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld
+++ b/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.ld
@@ -43,7 +43,7 @@ __FLASH_SIZE   = 0x00010000;
 
 __RAM_BEGIN    = 0x24000000;
 __RAM_SIZE     = 0x4FC00;
-__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000;
+__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
 
 /* Memories definition */
 MEMORY
@@ -182,7 +182,7 @@ SECTIONS
   {
     __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
     KEEP(*(noncacheable_buffer))
-    __NONCACHEABLEBUFFER_END = .;  /* create symbol for start of section */
+    __NONCACHEABLEBUFFER_END = .;  /* create symbol for end of section */
   } > RAM_NONCACHEABLEBUFFER
 
   /* User_heap_stack section, used to check that there is enough "DTCM" Ram  type memory left */